LTC1091/LTC1092 LTC1093/LTC1094 1-, 2-, 6- and 8-Channel, 10-Bit Serial I/O Data Acquisition Systems FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ Programmable Features – Unipolar/Bipolar Conversions – Differential/Single-Ended Multiplexer Configurations Sample-and-Holds Single Supply 5V, 10V or ±5V Operation Direct 3- or 4-Wire Interface to Most MPU Serial Ports and All MPU Parallel I/O Ports Analog Inputs Common Mode to Supply Rails Resolution: 10 Bits Total Unadjusted Error (A Grade): ±1LSB Over Temp Fast Conversion Time: 20µs Low Supply Current LTC1091: 3.5mA Max, 1.5mA Typ LTC1092/LTC1093/LTC1094: 2.5mA Max, 1mA Typ U DESCRIPTIO The LTC®1091/LTC1092/LTC1093/LTC1094 10-bit data acquisition systems are designed to provide complete function, excellent accuracy and ease of use when digitizing analog data from a wide variety of signal sources and transducers. Built around a 10-bit, switched capacitor, successive approximation A/D core, these devices include software configurable analog multiplexers and bipolar and unipolar conversion modes as well as on-chip sample- and-holds. On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers. These circuits can provide a complete data acquisition system in ratiometric applications or can be used with an external reference in others. The high impedance analog inputs and the ability to operate with reduced spans (below 1V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. An efficient serial port communicates without external hardware to most MPU serial ports and all MPU parallel I/O ports allowing eight channels of data to be transmitted over as few as three wires. This, coupled with low power consumption, makes remote location possible and facilitates transmitting data through isolation barriers. Temperature drift of offset, linearity and full-scale error are all extremely low (1ppm/°C typically) allowing all grades to be specified with offset and linearity errors of ±0.5LSB maximum over temperature. In addition, the A grade devices are specified with full-scale error and total unadjusted error (including the effects of offset, linearity and full-scale errors) of ±1LSB maximum over temperature. The lower grade has a full-scale specification of ±2LSB for applications where full scale is adjustable or less critical. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATION 5V 4.7µF MPU (e.g., 8051) VCC 8 (VREF) 7 2 CLK CH0 LTC1091 6 3 DOUT CH1 5 4 DIN GND 1 ANALOG INPUT #1 0V TO 5V RANGE ANALOG INPUT #2 0V TO 5V RANGE CS P1.4 P1.3 P1.2 SERIAL DATA LINK 1091 TA01 FOR 8051 CODE SEE APPLICATIONS INFORMATION SECTION LINEARITY ERROR (LSB = 1 • VREF) 1024 1.25 VCC = 5V 1.00 0.75 0.50 0.25 0 0 1 3 4 2 REFERENCE VOLTAGE (V) 5 1091 TA02 1 LTC1091/LTC1092 LTC1093/LTC1094 W W W AXI U U ABSOLUTE RATI GS (Notes 1, 2) Supply Voltage (VCC) to GND or V – ........................ 12V Negative Supply Voltage (V –) .................... – 6V to GND Voltage Analog Reference and LTC1091/2 CS Inputs ................................. (V –) – 0.3V to (VCC + 0.3V) Digital Inputs (except LTC1091/2 CS) .. – 0.3V to 12V Digital Outputs ........................ – 0.3V to (VCC + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range LTC1091/2/3/4AC, LTC1091/2/3/4C..... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°C W U U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW CS 1 8 VCC (VREF) CH0 2 7 CLK CH1 3 6 DOUT GND 4 5 DIN TOP VIEW LTC1091ACN8 LTC1091CN8 CS 1 8 VCC +IN 2 7 CLK –IN 3 6 DOUT GND 4 5 VREF N8 PACKAGE 8-LEAD PDIP TJMAX = 110°C, θJA = 150°C/W (N) TOP VIEW TOP VIEW LTC1093ACN LTC1093CN LTC1093CSW CH0 1 20 DVCC CH1 2 19 AVCC CH2 3 18 CLK 13 DOUT CH3 4 17 CS CH0 1 16 VCC CH1 2 15 CLK CH2 3 14 CS 4 LTC1092ACN8 LTC1092CN8 N8 PACKAGE 8-LEAD PDIP TJMAX = 110°C, θJA = 150°C/W (N) CH3 ORDER PART NUMBER CH4 5 12 DIN CH4 5 16 DOUT CH5 6 11 VREF CH5 6 15 DIN COM 7 10 AGND CH6 7 14 REF + DGND 8 9 CH7 8 13 REF – COM 9 12 AGND V– N PACKAGE SW PACKAGE 16-LEAD PDIP 16-LEAD PLASTIC SO WIDE LTC1094ACN LTC1094CN 11 V – DGND 10 N PACKAGE 20-LEAD PDIP TJMAX = 110°C, θJA = 150°C/W (N) TJMAX = 110°C, θJA = 130°C/W (SW) TJMAX = 110°C, θJA = 150°C/W (N) Consult factory for Industrial and Military grade parts. PRODUCT GUIDE CONVERSION MODES PART NUMBER ±5V CAPABILITY #CHANNELS UNIPOLAR LTC1091 2 ● LTC1092 1 ● LTC1093 6 ● ● ● ● LTC1094 8 ● ● ● ● 2 BIPOLAR REDUCED SPAN CAPABILITY (SEPARATE VREF) Pin-for-Pin 10-Bit Upgrade of ADC0832 Pin-for-Pin 10-Bit Upgrade of ADC0831 ● LTC1091/LTC1092 LTC1093/LTC1094 U U U U WW RECO E DED OPERATI G CO DITIO S SYMBOL PARAMETER LTC1091A/LTC1092A/LTC1093A/LTC1094A LTC1091/LTC1092/LTC1093/LTC1094 MIN MAX CONDITIONS VCC Supply Voltage V– Negative Supply Voltage LTC1093/LTC1094, VCC = 5V fCLK Clock Frequency tCYC Total Cycle Time UNITS 4.5 10 V – 5.5 0 V VCC = 5V 0.01 0.5 LTC1091 15 CLK Cycles + 2µs LTC1092 12 CLK Cycles + 2µs LTC1093/LTC1094 18 CLK Cycles + 2µs MHz thDI Hold Time, DIN Alter SCLK↑ VCC = 5V 150 ns tsuCS Setup Time CS↓ Before CLK↑ VCC = 5V 1 µs tsuDI Setup Time DIN Stable Before CLK↑ VCC = 5V 400 ns tWHCLK CLK High Time VCC = 5V 0.8 µs tWLCLK CLK Low Time VCC = 5V 1 µs tWHCS CS High Time Between Data Transfer Cycles VCC = 5V CS Low Time During Data Transfer LTC1091 LTC1092 LTC1093/LTC1094 2 µs 15 12 18 CLK Cycles CLK Cycles CLK Cycles W U tWLCS U CONVERTER AND MULTIPLEXER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3) LTC1091A/LTC1092A LTC1093A/LTC1094A MIN TYP MAX LTC1091/LTC1092 LTC1093/LTC1094 MIN TYP MAX UNITS PARAMETER CONDITIONS Offset Error (Note 4) ● ±0.5 ±0.5 LSB Linearity Error (Notes 4, 5) ● ±0.5 ±0.5 LSB Full-Scale Error (Note 4) ● ±1.0 ±2.0 LSB Total Unadjusted Error VREF = 5.000V (Notes 4, 6) ● ±1.0 Reference Input Resistance LTC1092/LTC1093/LTC1094 VREF = 5V ● Analog and REF Input Range (Note 7) On-Channel Leakage Current (Note 8) On-Channel = 5V Off-Channel = 0V ● 1 1 µA On-Channel = 0V Off-Channel = 5V ● –1 –1 µA On-Channel = 5V Off-Channel = 0V ● –1 –1 µA On-Channel = 0V Off-Channel = 5V ● 1 1 µA Off-Channel Leakage Current (Note 8) 5 10 LSB 5 10 kΩ (V –) – 0.05V to VCC + 0.05V V 3 LTC1091/LTC1092 LTC1093/LTC1094 AC CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3) LTC1091A/LTC1092A/LTC1093A/LTC1094A LTC1091/LTC1092/LTC1093/LTC1094 MIN TYP MAX SYMBOL PARAMETER CONDITIONS tSMPL Analog Input Sample Time See Operating Sequence tCONV Conversion Time See Operating Sequence tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits ● 400 850 ns tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● 180 450 ns ten Delay Time, CLK↓ to DOUT Enabled See Test Circuits ● 160 450 ns thDO Time Output Data Remains Valid After SCLK↓ tf DOUT Fall Time See Test Circuits ● 90 300 ns tr DOUT Rise Time See Test Circuits ● 60 300 ns CIN Input Capacitance Analog Inputs On-Channel Analog Inputs Off-Channel Digital Inputs 1.5 UNITS CLK Cycles 10 CLK Cycles 150 ns 65 5 5 pF pF pF U DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3) SYMBOL PARAMETER LTC1091A/LTC1092A/LTC1093A/LTC1094A LTC1091/LTC1092/LTC1093/LTC1094 MIN TYP MAX CONDITIONS 2.0 UNITS VIH High Level Input Voltage VCC = 5.25V ● VIL Low Level Input Voltage VCC = 4.75V ● V IIH High Level Input Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● –2.5 µA VOH High Level Output Voltage VCC = 4.75V, IOUT = 10µA VCC = 4.75V, IOUT = 360µA ● 0.8 2.4 4.7 4.0 V V V VOL Low Level Output Voltage VCC = 4.75V, IOUT = 1.6mA ● 0.4 V IOZ Hi-Z Output Leakage VOUT = VCC, CS High VOUT = 0V, CS High ● ● 3 –3 µA µA ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VCC 10 mA ICC Positive Supply Current LTC1091, CS High LTC1092/LTC1093/LTC1094, CS High, REF + Open ● ● 1.5 1.0 3.5 2.5 mA mA IREF Reference Current LTC1092/LTC1093/LTC1094, VREF = 5V ● 0.5 1.0 mA V – = – 5V ● 1 50 µA I– Negative Supply Current LTC1093/LTC1094, CS High, Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND, GND and REF – wired together (unless otherwise noted). REF – is internally connected to the AGND pin on the LTC1093. DGND, AGND, REF – and V – are internally connected to the GND pin on the LTC1091/LTC1092. Note 3: VCC = 5V, VREF + = 5V, VREF – = 0V, V – = 0V for unipolar mode and – 5V for bipolar mode, CLK = 0.5MHz unless otherwise specified. Note 4: These specs apply for both unipolar (LTC1091/LTC1092/LTC1093/ LTC1094) and bipolar (LTC1093/LTC1094 only) modes. In bipolar mode, one LSB is equal to the bipolar input span (2VREF) divided by 1024. For example, when VREF = 5V, 1LSB (bipolar) = 2(5V)/1024 = 9.77mV. Note 5: Linearity error is specified between the actual end points of the A/D transfer curve. 4 Note 6: Total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below V – or one diode drop above VCC. Be careful during testing at low VCC levels (4.5V), as high level reference or analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over initial tolerance, temperature variations and loading. Note 8: Channel leakage current is measured after the channel selection. LTC1091/LTC1092 LTC1093/LTC1094 U W TYPICAL PERFOR A CE CHARACTERISTICS Change in Linearity Error vs Temperature Change in Offset Error vs Temperature VCC (VREF) = 5V fCLK = 500kHz 0.5 0.4 0.3 0.2 0.1 0 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) VCC (VREF) = 5V fCLK = 500kHz 0.5 0.4 0.3 0.2 0.1 0 –50 125 MAGNITUDE OF FULL-SCALE CHANGE (LSB) 0.6 MAGNITUDE OF LINEARITY CHANGE (LSB) MAGNITUDE OF OFFSET CHANGE (LSB) 0.6 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 1091/2/3/4 G01 2 1 6 7 8 SUPPLY VOLTAGE (V) 9 MSB-FIRST DATA 400 300 LSB-FIRST DATA 200 100 0 –50 10 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 400 MSB-FIRST DATA 300 200 1.5 1.0 0.5 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 LSB-FIRST DATA 100 0 4 6 7 8 SUPPLY VOLTAGE (V) 5 9 10 1091/2/3/4 G06 Minimum Clock Rate vs Temperature 0.3 TA = 25°C MINIMUM CLK FREQUENCY** (MHz) MAXIMUM CLK FREQUENCY* (MHz) 2.0 125 TA = 25°C 125 3.0 2.5 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 500 Maximum Clock Rate vs Supply Voltage VCC = 5V –25 1091/2/3/4 G05 3.0 MAXIMUM CLK FREQUENCY* (MHz) 0.1 600 500 Maximum Clock Rate vs Temperature –25 0.2 DOUT Delay Time vs Supply Voltage VCC = 5V 1091/2/3/4 G04 0 –50 0.3 1091/2/3/4 G03 DOUT DELAY TIME FROM SCLK↓ (ns) DOUT DELAY TIME FROM SCLK↓ (ns) LOGIC THRESHOLD (V) 3 5 0.4 0 –50 125 600 TA = 25°C VCC (VREF) = 5V fCLK = 500kHz 0.5 DOUT Delay Time vs Temperature 4 4 0.6 1091/2/3/4 G02 Digital Input Logic Threshold vs Supply Voltage 0 Change in Full-Scale Error vs Temperature 2.5 2.0 1.5 1.0 0.5 0 4 5 6 7 8 SUPPLY VOLTAGE (V) 1091/2/3/4 G07 *MAXIMUM CLK FREQUENCY REPRESENTS THE HIGHEST FREQUENCY AT WHICH CLK CAN BE OPERATED (WITH 50% DUTY CYCLE) WHILE STILL PROVIDING 100ns SETUP TIME FOR THE DEVICE RECEIVING THE DOUT DATA. 9 10 1091/2/3/4 G08 VCC = 5V 0.25 0.20 0.15 0.10 0.05 0 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 1091/2/3/4 G09 **AS THE CLK FREQUENCY IS DECREASED FROM 500kHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED. 5 LTC1091/LTC1092 LTC1093/LTC1094 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC1091/LTC1092/LTC1093/LTC1094 Maximum Clock Rate vs Source Resistance LTC1091/LTC1092/LTC1093/LTC1094 Maximum Filter Resistor vs Cycle Time 0.75 0.50 0.25 0 “+” OR “–” INPUT 100 1k RSOURCE (Ω) 10 + CFILTER ≥1µF 10k – 1k 100 10 10k 100 1000 CYCLE TIME (µs) 10 1 • VCC (VREF)] 1024 80 60 40 20 1.00 0.75 0.5 0.25 0 125 4 0.25 4 5 6 7 8 SUPPLY VOLTAGE (V) –0.50 5 4 3 2 10 1.4 1.2 1.0 0.8 1 0 10 9 fCLK = 500kHz VCC (VREF) = 5V CS = 5V 1.6 5 6 7 8 SUPPLY VOLTAGE (V) † AS THE CLK FREQUENCY AND SOURCE RESISTANCE ARE INCREASED, MAXIMUM CLK 4 †† MAXIMUM R FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 500kHz, 0Ω VALUE IS FIRST DETECTED. 9 10 1092/2/3/4 G17 1091/2/3/4 G16 6 0.5 LTC1091 Supply Current vs Temperature SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) –0.25 9 0.75 1.8 0.25 6 7 8 SUPPLY VOLTAGE (V) 1.00 1091/2/3/4 G15 fCLK = 500kHz CS = VCC (VREF) TA = 25°C 6 0 10k fCLK = 500kHz TA = 25°C 0 10 7 fCLK = 500kHz TA = 25°C 5 1k RSOURCE+ (Ω) 1.25 LTC1091 Supply Current vs Supply Voltage 0.50 4 – 1091/2/3/4 G14 LTC1091 Change in Full-Scale Error vs Supply Voltage CHANGE IN FULL-SCALE ERROR [LSB = 1 • VCC (VREF)] 1024 9 6 7 8 SUPPLY VOLTAGE (V) 5 + 1091/2/3/4 G12 fCLK = 500kHz TA = 25°C VOS = 0.85mV AT VCC (VREF) = 5V 1091/2/3/4 G13 –0.75 RSOURCE+ LTC1091 Linearity Error vs Supply Voltage 1.25 ON-CHANNEL OR OFF-CHANNEL OFFSET ERROR [LSB = INPUT CHANNEL LEAKAGE CURRENT (nA) 100 25 50 75 100 0 AMBIENT TEMPERATURE (°C) VIN LTC1091 Offset Error vs Supply Voltage LTC1091/LTC1092 Input Channel Leakage Current vs Temperature –25 1 1091/2/3/4 G11 1091/2/3/4 G10 0 –50 VCC = 5V TA = 25°C 0V TO 5V INPUT STEP 0.1 100 10000 LINEARITY ERROR [LSB = 1 • VCC (VREF)] 1024 VIN RFILTER S & H ACQUISITION TIME TO 0.1% (µs) VIN 1.00 RSOURCE 10 100k VCC = 5V TA = 25°C MAXIMUM RFILTER†† (Ω) MAXIMUM CLK FREQUENCY† (MHz) 1.25 LTC1091/LTC1092/LTC1093/LTC1094 Sample-and-Hold Acquisition Time vs Source Resistance 0.6 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 1091/2/3/4 G18 FILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN FULL-SCALE ERROR FROM ITS VALUE AT RFILTER = 0 IS FIRST DETECTED. LTC1091/LTC1092 LTC1093/LTC1094 U W LTC1092/LTC1093/LTC1094 Unadjusted Offset Error vs Reference Voltage LTC1092/LTC1093/LTC1094 Linearity Error vs Reference Voltage 1.25 VCC = 5V 9 LINEARITY ERROR (LSB = 1 • VREF) 1024 OFFSET ERROR (LSB = 1 • VREF) 1024 10 8 7 6 5 4 VOS = 1mV 3 2 1 0 0.1 VOS = 0.5mV 0.2 1 REFERENCE VOLTAGE (V) VCC = 5V 1.00 0.75 0.50 0.25 0 5 10 1 0 3 4 2 REFERENCE VOLTAGE (V) 1091/2/3/4 G19 1.25 VCC = 5V 1.00 0.75 0.50 0.25 0 1.25 OFFSET ERROR (LSB) 0.75 0.50 VREF = 4V fCLK = 500kHz 1.00 LINEARITY ERROR (LSB) 1.00 1.00 5 LTC1092/LTC1093/LTC1094 Linearity Error vs Supply Voltage VREF = 4V fCLK = 500kHz VOS = 1.25mV AT VCC = 5V 1.75 1.25 3 4 2 REFERENCE VOLTAGE (V) 1092/2/3/4 G21 1.25 NOISE = 200µVP-P 1.50 1 0 LTC1092/LTC1093/LTC1094 Offset Error vs Supply Voltage 2.00 0.75 0.50 0.25 0.75 0.50 0.25 0.25 0 0.1 0.2 1 REFERENCE VOLTAGE (V) 5 0 10 4 5 6 7 8 SUPPLY VOLTAGE (V) 1091/2/3/4 G22 0 10 VREF = 4V fCLK = 500kHz SUPPLY CURRENT (mA) –0.50 4 3 2 6 7 8 SUPPLY VOLTAGE (V) 9 10 1091/2/3/4 G25 1.0 0.8 0.6 0.4 0 5 10 VREF OPEN fCLK = 500kHz CS = 5V VCC = 5V 1.2 1 4 9 1.4 VREF OPEN fCLK = 500kHz CS = VCC TA = 25°C 5 – 0.25 6 7 8 SUPPLY VOLTAGE (V) LTC1092/LTC1093/LTC1094 Supply Current vs Temperature 6 0.50 0 5 1091/2/3/4 G24 LTC1092/LTC1093/LTC1094 Supply Current vs Supply Voltage 0.25 4 1091/2/3/4 G23 LTC1092/LTC1093/LTC1094 Change in Full-Scale Error vs Supply Voltage –0.75 9 SUPPLY CURRENT (mA) PEAK-TO-PEAK NOISE ERROR (LSB) LTC1092/LTC1093/LTC1094 Change in Full-Scale Error vs Reference Voltage 1092/2/3/4 G20 LTC1092/LTC1093/LTC1094 Noise Error vs Reference Voltage CHANGE IN FULL-SCALE ERROR (LSB) 5 CHANGE IN FULL-SCALE ERROR (LSB = 1 • VREF) 1024 TYPICAL PERFOR A CE CHARACTERISTICS 4 5 6 7 8 SUPPLY VOLTAGE (V) 9 10 1091/2/3/4 G26 0.2 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 1091/2/3/4 G27 7 LTC1091/LTC1092 LTC1093/LTC1094 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC1092/LTC1093/LTC1094 Reference Current vs Temperature 1000 0.6 INPUT CHANNEL LEAKAGE CURRENT (nA) REFERENCE CURRENT (mA) VREF = 5V 0.5 0.4 0.3 0.2 0.1 0 –50 LTC1093/LTC1094 Input Channel Leakage Current vs Temperature –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 900 GUARANTEED 800 700 600 500 400 300 ON-CHANNEL 200 OFF-CHANNEL 100 0 –50 –25 0 75 100 50 25 AMBIENT TEMPERATURE (°C) 1091/2/3/4 G28 125 1091/2/3/4 G29 U U U PI FU CTIO S LTC1091/LTC1092 CS (Pin 1): Chip Select Input. A logic low on this input enables the LTC1091/LTC1092. CH0, CH1/+ IN, – IN (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. VCC (Pin 8 )(LTC1092): Positive Supply Voltage. This pin provides power to the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. LTC1093/LTC1094 DIN (Pin 5)(LTC1091): Digital Data Input. The multiplexer address is shifted into this input. CH0 to CH5/CH0 to CH7 (Pins 1 to 6/Pins 1 to 8): Analog Inputs. The analog inputs must be free of noise with respect to AGND. VREF (Pin 5)(LTC1092): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. COM (Pin 7/Pin 9): Common. The common pin defines the zero reference point for all single-ended inputs. It must be free of noise and is usually tied to the analog ground plane. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. DGND (Pin 8/Pin 10): Digital Ground. This is the ground for the internal logic. Tie to the ground plane. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. V – (Pin 9/Pin 11): Negative Supply. Tie V – to most negative potential in the circuit. (Ground in single supply applications.) VCC(VREF)(Pin 8)(LTC1091): Positive Supply and Reference Voltage. This pin provides power and defines the span of the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane. AGND (Pin 10/Pin 12): Analog Ground. AGND should be tied directly to the analog ground plane. 8 LTC1091/LTC1092 LTC1093/LTC1094 U U U PI FU CTIO S VREF (Pin 11)(LTC1093): Reference Input. The reference input must be kept free of noise with respect to AGND. CLK (Pin 15/Pin 18): Shift Clock. This clock synchronizes the serial data transfer. REF +, REF – (Pins 13, 14 )(LTC1094): Reference Input. The reference input must be kept free of noise with respect to AGND. VCC (Pin 16)(LTC1093): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. DIN (Pin 12/Pin 15): Data Input. The A/D configuration word is shifted into this input. AVCC, DVCC (Pins 19, 20)(LTC1094): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. AVCC and DVCC should be tied together on the LTC1094. DOUT (Pin 13/Pin 16): Digital Data Output. The A/D conversion result is shifted out of this output. CS (Pin 14/Pin 17): Chip Select Input. A logic low on this input enables the LTC1093/LTC1094. W BLOCK DIAGRA (Pin numbers refer to LTC1094) DVCC 19 18 CLK AVCC 20 INPUT SHIFT REGISTER DIN 15 OUTPUT SHIFT REGISTER 16 DOUT CH0 1 SAMPLEAND-HOLD CH1 2 COMP CH2 3 CH3 4 CH4 5 10-BIT SAR ANALOG INPUT MUX 10-BIT CAPACITIVE DAC CH5 6 CH6 7 CH7 8 COM 9 10 DGND 11 V – 12 AGND 13 REF 14 – + CONTROL AND TIMING 17 CS REF 1091/2/3/4 BD 9 LTC1091/LTC1092 LTC1093/LTC1094 TEST CIRCUITS Load Circuit for tdDO, t r, t f On- and Off-Channel Leakage Current 5V 1.4V ION A ON-CHANNEL 3k IOFF DOUT A TEST POINT 100pF OFFCHANNELS POLARITY 1091/2/3/4 TC02 1091/2/3/4 TC01 Voltage Waveforms for DOUT Rise and Fall Times, t r, t f Voltage Waveforms for DOUT Delay Time, tdDO 2.4V DOUT 0.4V CLK 0.8V tr tf tdDO 1091/2/3/4 TC04 2.4V Voltage Waveforms for tdis DOUT 0.4V 2.0V 1091/2/3/4 TC03 CS Load Circuit for tdis, ten DOUT WAVEFORM 1 (SEE NOTE 1) 90% TEST POINT tdis 5V tdis WAVEFORM 2, ten 3k DOUT WAVEFORM 2 (SEE NOTE 2) 10% DOUT 100pF NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL tdis WAVEFORM 1 1091/2/3/4 TC05 NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL 1091/2/3/4 TC06 Voltage Waveforms for ten LTC1091 CS DIN CLK START 1 2 3 4 B9 DOUT 0.4V ten 10 1091/2/3/4 TC07 LTC1091/LTC1092 LTC1093/LTC1094 TEST CIRCUITS Voltage Waveforms for ten LTC1092 CS CLK 1 B9 DOUT 0.4V 1091/2/3/4 TC08 ten LTC1093/LTC1094 CS DIN START 1 CLK 3 2 4 5 6 7 DOUT 0.4V ten 1091/2/3/4 TC09 U W U UO APPLICATI B9 S I FOR ATIO The LTC1091/LTC1092/LTC1093/LTC1094 are data acquisiton components that contain the following functional blocks: 1. 10-Bit Successive Approximation A/D Converter 2. Analog Multiplexer (MUX) 3. Sample-and-Hold (S/H) 4. Synchronous, Half-Duplex Serial Interface 5. Control and Timing Logic DIGITAL CONSIDERATIONS 1. Serial Interface The LTC1091/LTC1093/LTC1094 communicate with microprocessors and other external circuitry via a synchronous, half-duplex, 4-wire serial interface while the LTC1092 uses a 3-wire interface (see Operating Sequence). The clock (CLK) synchronizes the data transfer with each bit being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems. The LTC1091/LTC1093/LTC1094 first receive input data and then transmit back the A/D conversion result (half-duplex). Because of the half-duplex operation, DIN and DOUT may be tied together allowing transmission over just three wires: CS, CLK and DATA (DIN/DOUT). Data transfer is initiated by a falling chip select (CS) signal. After CS falls, the LTC1091/LTC1093/LTC1094 looks for a start bit. After the start bit is received, a 3-bit input word (6 bits for the LTC1093/LTC1094) is shifted into the DIN input which configures the LTC1091/LTC1093/LTC1094 and starts the conversion. After one null bit, the result of the conversion is output on the DOUT line. At the end of the data exchange, CS should be brought high. This resets the LTC1091/LTC1093/LTC1094 in preparation for the next data exchange. The LTC1092 does not require a configuration input word and has no DIN pin. A falling CS initiates data transfer as shown in the LTC1092 Operating Sequence. After CS falls, 11 LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO sequence, providing easy interface to MSB- or LSB-first serial ports. The following disussion applies to the configuration of the LTC1091/LTC1093/LTC1094. CS DIN 1 DIN 2 DOUT 2 DOUT 1 The LTC1091/LTC1093/LTC1094 clock data into the DIN input on the rising edge of the clock. The input data words are defined as follows: SHIFT MUX ADDRESS IN 1 NULL BIT SHIFT A/D CONVERSION RESULT OUT 1091/2/3/4 AI01 LTC1091 DATA INPUT (DIN) WORD: the first CLK pulse enables DOUT. After one null bit, the A/D conversion result is output on the DOUT line. Bringing CS high resets the LTC1092 for the next data exchange. START SGL/ DIFF ODD/ SIGN MUX ADDRESS 2. Input Data Word MSBF MSB-FIRST/ LSB-FIRST UNIPOLAR/ BIPOLAR LTC1093/LTC1094 DATA INPUT (DIN)WORD: The LTC1092 requires no DIN word. It is permanently configured to have a single differential input and to operate in unipolar mode. The conversion result is output on the DOUT line in MSB-first sequence, followed by LSB-first START SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 MSBF UNI 1091/2/3/4 AI02 MSB-FIRST/ LSB-FIRST MUX ADDRESS LTC1091 Operating Sequence Example: Differential Inputs (CH1 +, CH0 –) MSB-First Data (MSBF = 1) tCYC CS CLK ODD/SIGN START DIN DOUT DON’T CARE SGL/ DIFF Hi-Z MSBF B9 B1 B0 Hi-Z FILLED WITH ZEROS 1091/2/3/4 AI03 tCONV tSMPL LSB-First Data (MSBF = 0) tCYC CS CLK START ODD/SIGN DIN DOUT DON’T CARE Hi-Z SGL/ DIFF MSBF B9 tSMPL 12 B1 tCONV B0 B1 B9 Hi-Z FILLED WITH ZEROS 1091/2/3/4 AI04 LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO LTC1092 Operating Sequence tCYC CS CLK DOUT Hi-Z B9 B1 tSMPL B0 B9 B1 tSMPL tCONV 1091/2/3/4 AI05 LTC1093/LTC1094 Operating Sequence Example: Differential Inputs (CH4+, CH5–), Unipolar Mode MSB-First Data (MSBF = 1) tCYC CS CLK START SEL1 UNI DIN DOUT DON’T CARE Hi-Z SGL/ ODD/ DIFF SIGN MSBF SEL0 B9 B1 Hi-Z B0 FILLED WITH ZEROS tCONV 1091/2/3/4 AI06 tSMPL LSB-First Data (MSBF = 0) tCYC CS CLK START SEL1 UNI DIN DOUT DON’T CARE Hi-Z SGL/ ODD/ SEL0 DIFF SIGN Hi-Z MSBF B9 B1 tCONV tSMPL B0 B1 B9 Hi-Z FILLED WITH ZEROS 1091/2/3/4 AI07 13 LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO Start Bit The first “logical one” clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer. The LTC1091/LTC1093/LTC1094 will ignore all leading zeros which precede this logical one. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. voltage between the two channels indicated by the + and – signs in the selected row of the following tables. In single-ended mode, all input channels are measured with respect to GND on the LTC1091 and COM on the LTC1093/LTC1094. LTC1091 Channel Selection Multiplexer (MUX) Address The bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE MUX ADDRESS SGL/ ODD/ DIFF SIGN 1 0 1 1 0 0 0 1 CHANNEL # GND 1 0 + – – + – + + – 1091-4 AI08 LTC1094 Channel Selection LTC1093 Channel Selection SGL/ DIFF 0 0 0 0 0 0 0 0 MUX ADDRESS SELECT ODD/ 0 1 SIGN 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 MUX ADDRESS SGL/ ODD/ SELECT 0 DIFF SIGN 1 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 DIFFERENTIAL CHANNEL SELECTION 0 + 1 – 2 3 + – 4 + 5 – NOT USED – + – + – + NOT USED SINGLE-ENDED CHANNEL SELECTION 0 + 1 2 3 4 5 + + COM – – – NOT USED + + + – – – NOT USED 1091-4 AI09 14 DIFFERENTIAL CHANNEL SELECTION MUX ADDRESS SGL/ ODD/ SELECT 0 DIFF SIGN 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 MUX ADDRESS SGL/ ODD/ SELECT 0 DIFF SIGN 1 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 + 1 – – 2 3 + – 4 5 + – 6 7 + – – + + – + – + SINGLE-ENDED CHANNEL SELECTION 0 + 1 2 3 4 5 6 7 + + + + + + + COM – – – – – – – – 1091-4 AI0 LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO MSB-First/LSB-First (MSBF) Unipolar Output Code (UNI = 1) The output data of the LTC1091/LTC1093/LTC1094 is programmed for MSB-first or LSB-first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on the DOUT line in MSB-first format. Logical zeros will be filled in indefinitely following the last data bit to accommodate longer word lengths required by some microprocessors. When the MSBF bit is a logical zero, LSB-first data will follow the normal MSB-first data on the DOUT line. (See operating sequence). INPUT VOLTAGE VREF – 1LSB VREF – 2LSB • • • 1LSB 0V OUTPUT CODE 1111111111 1111111110 • • • 0000000001 0000000000 INPUT VOLTAGE (VREF = 5V) 4.9951V 4.9902V • • • 0.0049V 0V 1091-4AI13 Bipolar Output Code (UNI = 0) LTC1093/LTC1094 Only OUTPUT CODE 0111111111 0111111110 • • • 0000000001 0000000000 1111111111 1111111110 • • • 1000000001 1000000000 Unipolar/Bipolar (UNI) The UNI bit of the LTC1093/LTC1094 determines whether the conversion will be unipolar or bipolar. When UNI is a logical one, a unipolar conversion will be performed on the selected input voltage. When UNI is a logical zero, a bipolar conversion will result. The input span and code assignment for each conversion type are shown in the figures below. The LTC1091/LTC1092 are permanently configured for unipolar mode. INPUT VOLTAGE VREF – 1LSB VREF – 2LSB • • • 1LSB 0V –1LSB –2LSB • • • –(VREF) + 1LSB –(VREF) INPUT VOLTAGE (VREF = 5V) 4.9902V 4.9805V • • • 0.0098V 0V –0.0098V –0.0195V • • • –4.9902V –5.000V 1091-4AI14 Unipolar Transfer Curve (UNI = 1) 1111111111 1111111110 0000000001 0000000000 VIN 0V VREF – 2LSB 1LSB VREF VREF – 1LSB 1091-4 AI11 Bipolar Transfer Curve (UNI = 0) LTC1093/LTC1094 Only 0111111111 0111111110 1LSB –VREF + 1LSB –VREF 0000000001 0000000000 VIN 1111111111 1111111110 VREF – 2LSB VREF VREF – 1LSB 1091-4 AI12 –1LSB –2LSB 1000000001 1000000000 15 LTC1091/LTC1092 LTC1093/LTC1094 U W U UO APPLICATI S I FOR ATIO 3. Accommodating Microprocessors with Different Word Lengths eliminates one 8-bit transfer and positions data right justified inside the MPU. The LTC1091/LTC1093/LTC1094 will fill zeros indefinitely after the transmitted data until CS is brought high. At that time the DOUT line is disabled. This makes interfacing easy to MPU serial ports with different transfer increments including 4 bits (e.g., COP400) and 8 bits (e.g., SPI and MICROWIRE/PLUSTM). Any word length can be accommodated by the correct positioning of the start bit in the LTC1091 input word. 4. Operation with DIN and DOUT Tied Together The LTC1091/LTC1093/LTC1094 can be operated with DIN and DOUT tied together. This eliminates one of the lines required to communicate to the MPU. Data is transmitted in both directions on a single wire. The processor pin connected to this data line should be configurable as either an input or an output. The LTC1091, for example, will take control of the data line and drive it low on the 4th falling CLK edge after the start bit is received (see Figure 2). Therefore, the processor port line must be switched to an input before this happens, to avoid a conflict. Figure 1 shows examples of LTC1091 input and output words for 4-bit and 8-bit processors. A complete data exchange can be implemented with two 4-bit MPU outputs and three inputs in 4-bit systems and one 8-bit output and two inputs in 8-bit systems. The resulting data winds up left justified in the MPU with zeros automatically filled in the unused low order bits by the LTC1091. In section 5 another example is given using the MC68HC05C4 which In the next section, an example is made of interfacing the LTC1091 with DIN and DOUT tied together to the Intel 8051 MPU. CS CLK START SGL/ ODD/ DIFF SIGN MSBF DIN Hi-Z DOUT MPU SENDS 2 DIN WORDS • • • B9 START BIT 0 0 0 1 SGL/ ODD/ MSBF DIFF SIGN B8 B7 B6 B5 B4 B3 B2 B1 B0 FILL ZEROS X = DON’T CARE X 4-BIT TRANSFERS MPU READS BACK 3 DOUT WORDS MPU SENDS 1 DIN WORD B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 START BIT 0 0 0 1 SGL/ ODD/ MSBF DIFF SIGN X 8-BIT TRANSFERS MPU READS BACK 2 DOUT WORDS 0 0 0 0 1091/2/3/4 F01 Figure 1. LTC1091 Input and Output Word Arrangements for 4-Bit and 8-Bit Serial Port Microprocessors MICROWIRE/PLUS is a trademark of National Semiconductor Corp. 16 LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO MSBF LATCHED BY LTC1091 CS 1 2 START SGL/ DIFF 3 4 CLK DATA (DIN/DOUT) ODD/ SIGN MSBF B9 B8 • • • LTC1091 CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO MPU MPU CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1091 PROCESSOR MUST RELEASE DATA LINE AFTER 4TH RISING CLK AND BEFORE THE 4TH FALLING CLK LTC1091 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK 1091/2/3/4 F02 Figure 2. LTC1091 Operation with DIN and DOUT Tied Together 5. Microprocessor Interfaces The LTC1091/LTC1092/LTC1093/LTC1094 can interface directly (without external hardware) to most popular microprocessor (MPU) synchronous serial formats (see Table 1). If an MPU without a dedicated serial port is used, then three or four of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1091/ LTC1092/LTC1093/LTC1094. Included here are one serial interface example and one example showing a parallel port programmed to form the serial interface. Table 1. Microprocessors with Hardware Serial Interfaces Compatible with the LTC1091/LTC1092/LTC1093/LTC1094 PART NUMBER TYPE OF INTERFACE Motorola MC6805S2, S3 MC68HC11 MC68HC05 SPI SPI SPI CDP68HC05 SPI RCA Hitachi HD6305 HD63705 HD6301 HD63701 HD6303 HD64180 SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous CSI/O National Semiconductor COP400 Family COP800 Family NS8050U HPC16000 Family MICROWIRETM MICROWIRE/PLUS MICROWIRE/PLUS MICROWIRE/PLUS Texas Instruments TMS7002 TMS7042 TMS70C02 TMS70C42 TMS32011* TMS32020 Serial Port Serial Port Serial Port Serial Port Serial Port Serial Port *Requires external hardware MICROWIRE is a trademark of National Semiconductor Corp. 17 LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO Motorola SPI (MC68HC05C4, MC68HC11) The MC68HC05C4 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSB first and in 8-bit increments. With two 8-bit transfers, the A/D result is read into the MPU. The first 8-bit transfer sends the DIN word to the LTC1091 and clocks B9 and B8 of the A/D conversion result into the processor. The second 8-bit transfer clocks the remaining bits, B7 through B0, into the MPU. ANDing the first MPU received byte with 03 Hex clears the six most significant bits. Notice how the position of the start bit in the first MPU transmit word is used to position the A/D result right justified in two memory locations. Data Exchange Between LTC1091 and MC68HC05C4 START BIT MPU TRANSMIT WORD 0 BYTE 2 (DUMMY) BYTE 1 SGL/ ODD/ MSBF X DIFF SIGN 1 X X X X X X X X X X X = DON’T CARE CS START SGL/ ODD/ DIFF SIGN MSBF DIN DON’T CARE CLK DOUT B9 B8 B7 B6 B5 BYTE 1 MPU RECEIVED WORD ? ? ? ? ? 0 B9 ANALOG INPUTS CLK SCK DIN MOSI DOUT MISO LTC1091 B8 B7 B6 0 0 0 0 0 B9 B5 B7 B6 B5 B4 B3 B2 B1 B0 B2 B1 BYTE 1 B0 1091/2/3/4 AI15 BCLRn LDA STA Bit 0 Port C Goes Low (CS Goes Low) Load LTC1090 DIN Word into Acc Load LTC1090 DIN Word into SPI from Acc Transfer Begins Test Status of SPIF Loop to Previous Instruction If Not Done with Transfer Load contents of SPI Data Register into Acc (DOUT MSBs) Start Next SPI Cycle Clear 6 MSBs of First DOUT Word Store in Memory Location A (MSBs) Test Status of SPIF Loop to Previous Instruction If Not Done with Transfer Set B0 of Port C (CS Goes High) Load contents of SPI Data Register into Acc (DOUT LSBs) Store in Memory location A + 1 (LSBs) STA AND STA TST BPL BYTE 2 BSETn LDA STA 18 B3 START LDA LSB LOCATION A + 1 B4 COMMENTS 1091-4 AI16 B8 B0 MNEMONIC TST BPL MSB 0 B1 LABEL MC68HC05C4 DOUT from LTC1091 Stored in MC68HC05C4 RAM LOCATION A B2 2ND TRANSFER Hardware and Software Interface to Motorola MC68HC05C4 Processor CO B3 BYTE 2 1ST TRANSFER CS B4 LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO Interfacing to the Parallel Port of the Intel 8051 Family LABEL MOV SETB CLR MOV LOOP 1 RLC CLR MOV SETB DJNZ MOV CLR MOV LOOP MOV RLC SETB CLR DJNZ MOV MOV SETB CLR CLR RLC MOV RRC RRC MOV SETB The Intel 8051 has been chosen to demonstrate the interface between the LTC1091 and parallel port microprocessors. Normally, the CS, SCLK and DIN signals would be generated on three port lines and the DOUT signal read on a 4th port line. This works very well. However, we will demonstrate here an interface with the DIN and DOUT of the LTC1091 tied together as described in section 4. This saves one wire. The 8051 first sends the start bit and MUX address to the LTC1091 over the data line connected to P1.2. Then P1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 10-bit A/D result over the same data line. ANALOG INPUTS LTC1091 CS P1.4 CLK P1.3 DOUT P1.2 DIN 8051 MUX ADDRESS A/D RESULT MNEMONIC OPERAND 1091-4 AI17 DOUT from LTC1091 Stored in 8051 RAM COMMENTS A, #FFH P1.4 P1.4 R4, #04 A P1.3 P1.2, C P1.3 R4, LOOP 1 P1, #04 P1.3 R4, #09 C, P1.2 A P1.3 P1.3 R4, LOOP R2, A C, P1.2 P1.3 P1.3 A A C, P1.2 A A R3, A P1.4 DIN Word for LTC1091 Make Sure CS Is High CS Goes Low Load Counter Rotate DIN Bit into Carry SCLK Goes Low Output DIN Bit to LTC1091 SCLK Goes High Next Bit Bit 2 Becomes an Input SCLK Goes Low Load Counter Read Data Bit into Carry Rotate Data Bit into Acc SCLK Goes High SCLK Goes Low Next Bit Store MSBs in R2 Read Data Bit into Carry SCLK Goes High SCLK Goes Low Clear Acc Rotate Data Bit from Carry to Acc Read Data Bit into Carry Rotate Right into Acc Rotate Right into Acc Store LSBs in R3 CS Goes High MSB R2 B9 B8 B7 B6 B5 B4 B3 B2 0 0 0 0 0 0 LSB R3 B1 B0 MSBF BIT LATCHED INTO LTC1091 CS 1 2 START SGL/ DIFF 3 4 CLK DATA (DIN/DOUT) ODD/ SIGN 8051 P1.2 OUTPUTS DATA TO LTC1091 8051 P1.2 RECONFIGURED AS AN INPUT AFTER THE 4TH RISING CLK AND BEFORE THE 4TH FALLING CLK MSBF B9 B8 B7 B6 B5 B4 LTC1091 SENDS A/D RESULT BACK TO 8051 P1.2 B3 B2 B1 B0 1091/2/3/4 AI18 LTC1091 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK 19 LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO 2 1 0 OUTPUT PORT SERIAL DATA MPU 3-WIRE SERIAL INTERFACE TO OTHER PERIPHERALS OR LTC1094s 3 3 3 3 CS LTC1094 CS LTC1094 CS LTC1094 8 CHANNELS 8 CHANNELS 8 CHANNELS LTC1091-4 F03 Figure 3. Several LTC1094s Sharing One 3-Wire Serial Interface Sharing the Serial Interface The LTC1094 can share the same 2- or 3-wire serial interface with other peripheral components or other LTC1094s (see Figure 3). In this case, the CS signals decide which LTC1094 is being addressed by the MPU. ANALOG CONSIDERATIONS 1. Grounding The LTC1091/LTC1092/LTC1093/LTC1094 should be used with an analog ground plane and single point grounding techniques. The AGND pin (GND on the LTC1091/LTC1092) should be tied directly to this ground plane. The DGND pin of the LTC1093/LTC1094 can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself. The VCC pin should be bypassed to the ground plane with a 4.7µF tantalum with leads as short as possible. AVCC and DVCC should be tied together on the LTC1094. The V – pin (LTC1093/LTC1094) should be bypassed with a 0.1µF ceramic disk. For single supply applications, V – can be tied to the ground plane. It is also recommended that the REF – pin and the COM pin be tied directly to the ground plane. All analog inputs should be referenced directly to the single point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. 20 Figure 4 shows an example of an ideal LTC1091 ground plane design for a 2-sided board. Of course, this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. 2. Bypassing For good performance, VCC must be free of noise and ripple. Any changes in the VCC voltage with respect to analog ground during a conversion cycle can induce errors or noise in the output code. Because the VCC (VREF) pin of the LTC1091 defines the voltage span of the A/D converter, its bypassing is especially important. VCC noise and ripple can be kept below 1mV by bypassing the VCC pin directly to the analog ground plane with a 4.7µF tantalum with leads as short as possible. AVCC and DVCC should be tied together on the LTC1094. Figures 5 and 6 show the effects of good and poor VCC bypassing. 4.7µF TANTALUM VCC S 1 8 2 7 3 6 4 5 S LTC1091-4 F04 Figure 4. Example Ground Plane for the LTC1091 LTC1091/LTC1092 LTC1093/LTC1094 U W U UO APPLICATI S I FOR ATIO 3. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1091/ LTC1092/LTC1093/LTC1094 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to ensure that the transients caused by the current spikes settle completely before the conversion begins. 0.5mV/DIV 10µs/DIV 1091-4 F05 Figure 5. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors Source Resistance The analog inputs of the LTC1091/LTC1092/LTC1093/ LTC1094 look like a 60pF capacitor (CIN) in series with a 500Ω resistor (RON) as shown in Figure 7. CIN gets switched between the selected “+” and “–” inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time. 0.5mV/DIV “+” Input Settling 10µs/DIV 1091-4 F06 This input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figure 8). The sample phase is the 1 1/2 CLK cycles before the conversion starts. The voltage on the “+” input must settle completely within this sample time. Minimizing RSOURCE+ and C1 will improve the input settling time. If large “+” input source resistance must be used, the sample time can be increased by using a slower CLK frequency. With the minimum possible sample time of 3µs, RSOURCE+ < 2k and C1 < 20pF will provide adequate settling. Figure 6. Good VCC Bypassing Keeps Noise and Ripple on VCC Below 1mV VIN + VIN – RSOURCE + RSOURCE – “+” INPUT C1 LTC1091 3RD CLK↑ RON = 500Ω “–” INPUT 4TH CLK↓ C2 CIN = 60pF LTC091-4 F07 Figure 7. Analog Input Equivalent Circuit 21 LTC1091/LTC1092 LTC1093/LTC1094 U W U UO APPLICATI S I FOR ATIO “–” Input Settling Input Op Amps At the end of the sample phase the input capacitor switches to the “–” input and the conversion starts (see Figure 8). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “–” input voltage settle completely during the first CLK cycle of the conversion time and be free of noise. Minimizing RSOURCE– and C2 will improve settling time. If large “–” input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. At the maximum CLK rate of 500kHz, RSOURCE– < 1kΩ and C2 < 20pF will provide adequate settling. When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 8). Again, the “+” and “–” input sampling times can be extended as previously described to accommodate slower op amps. Most op amps, including the LT1006 and LT1013 single supply op amps, can be made to settle well even with the minimum settling windows of 3µs (“+” input) and 2µs (“–” input) which occur at the maximum clock rate of 500kHz. Figures 9 and 10 show examples of adequate and poor op amp settling. SAMPLE HOLD “+” INPUT MUST SETTLE DURING THIS TIME CS tSMPL tCONV MSBF DON‘T CARE CLK DIN START SGL/DIFF DOUT B9 1ST BIT TEST “–” INPUT MUST SETTLE DURING THIS TIME “+” INPUT “–” INPUT 1091-4 F08 Figure 8. “+” and “–” Input Settling Windows 22 LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO resistor must be used, errors can be eliminated by increasing the cycle time as shown in the typical curve of Maximum Filter Resistor vs Cycle Time. Input Leakage Current 5mV/DIV 1µs/DIV 1091-4 F09 Figure 9. Adequate Settling of Op Amp Driving Analog Input Input leakage currents can also create errors if the source resistance gets too large. For instance, the maximum input leakage specification of 1µA (at 125°C) flowing through a source resistance of 1kΩ will cause a voltage drop of 1mV or 0.2LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see the typical curve of Input Channel Leakage Current vs Temperature). 4. Sample-and-Hold Single-Ended Inputs 5mV/DIV 20µs/DIV 1091-4 F10 Figure 10. Poor Op Amp Settling Can Cause A/D Errors The LTC1091/LTC1093/LTC1094 provide a built-in sampleand-hold (S&H) function for all signals acquired in the singleended mode. This sample-and-hold allows conversion of rapidly varying signals (see typical curve of S&H Acquisition Time vs Source Resistance). The input voltage is sampled during the tSMPL time as shown in Figure 8. The sampling interval begins as the bit preceding the MSBF bit is shifted in and continues until the falling CLK edge after the MSBF bit is received. On this falling edge, the S&H goes into hold mode and the conversion begins. RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 11. For large values of CF (e.g., 1µF), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = (60pF)(VIN/tCYC) and is roughly proportional to VIN. When running at the minimum cycle time of 32µs, the input current equals 9µA at VIN = 5V. In this case, a filter resistor of 50Ω will cause 0.1LSB of full-scale error. If a larger filter RFILTER IDC VIN “+” CFILTER LTC1091 “–” 1091-4 F11 Figure 11. RC Input Filtering 23 LTC1091/LTC1092 LTC1093/LTC1094 U W U UO APPLICATI S I FOR ATIO Differential Inputs With differential inputs, the A/D no longer converts just a single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 10 CLK cycles. Therefore, a change in the “–” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “–” input this error would be: VERROR(MAX) = (VPEAK)(2π) • f(“–”)(10/fCLK) Where f(“–”) is the frequency of the “–” input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. In most cases VERROR will not be significant. For a 60Hz signal on the “–” input to generate a 0.25LSB error (1.25mV) with the converter running at CLK = 500kHz, its peak value would have to be 150mV. 2. Transients on the reference inputs caused by the capacitive switching currents must settle completely during each bit test (each CLK cycle). Figures 13 and 14 show examples of both adequate and poor settling. Using a slower CLK will allow more time for the reference to settle. However, even at the maximum CLK rate of 500kHz most references and op amps can be made to settle within the 2µs bit time. 3. It is recommended that the REF – input of the LTC1094 be tied directly to the analog ground plane. If REF – is biased at a voltage other than ground, the voltage must not change during a conversion cycle. This voltage must also be free of noise and ripple with respect to analog ground. REF+ 14 ROUT 10k TYP 5pF TO 30pF VREF 13 (AGND) 5. Reference Inputs The voltage between the reference inputs of the LTC1091/LTC1092/LTC1093/LTC1094 defines the voltage span of the A/D converter. The reference inputs look primarily like a 10k resistor but will have transient capacitive switching currents due to the switched capacitor conversion technique (see Figure 12). During each bit test of the conversion (every CLK cycle), a capacitive current spike will be generated on the reference pins by the A/D. These current spikes settle quickly and do not cause a problem. However, if slow settling circuitry is used to drive the reference inputs, care must be taken to ensure that transients caused by these current spikes settle completely during each bit test of the conversion. LTC1091/2/3/4 EVERY CLK CYCLE RON 1091-4 F12 Figure 12. Reference Input Equivalent Circuit 0.5mV/DIV 1µs/DIV 1091-4 F13 When driving the reference inputs, three things should be kept in mind: 1. The source resistance (ROUT) driving the reference inputs should be low (less than 1Ω) to prevent DC drops caused by the 1mA maximum reference current (IREF). 24 Figure 13. Adequate Reference Settling LTC1091/LTC1092 LTC1093/LTC1094 W U U UO APPLICATI S I FOR ATIO 5V reference becomes 0.5LSB with a 1V reference and 2.5LSBs with a 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the “–” input to the LTC1092/LTC1093/ LTC1094. 0.5mV/DIV Noise with Reduced VREF 1µs/DIV 1091-4 F14 Figure 14. Poor Reference Settling Can Cause A/D Errors 6. Reduced Reference Operation The minimum reference voltage of the LTC1091 is limited to 4.5V because the VCC supply and reference are internally tied together. However, the LTC1092/LTC1093/LTC1094 can operate with reference voltages below 1V. The effective resolution of the LTC1092/LTC1093/LTC1094 can be increased by reducing the input span of the converter. The parts exhibit good linearity and gain over a wide range of reference voltages (see typical curves of Linearity and Full-Scale Error vs Reference Voltage). However, care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low VREF values: 1. Offset 2. Noise 3. Conversion speed (CLK frequency) Offset with Reduced VREF The offset of the LTC1092/LTC1093/LTC1094 has a larger effect on the output code when the A/D is operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 0.5mV which is 0.1LSB with a The total input-referred noise of the LTC1092/LTC1093/ LTC1094 can be reduced to approximately 200µV peak-topeak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Noise Error vs Reference Voltage shows the LSB contribution of this 200µV of noise. For operation with a 5V reference, the 200µV noise is only 0.04LSB peak-to-peak. In this case, the LTC1092/LTC1093/ LTC1094 noise will contribute virtually no uncertainty to the output code. However, for reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1V reference, this same 200µV noise is 0.2LSB peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 0.2LSB. If the reference is further reduced to 200mV, the 200µV noise becomes equal to one LSB and a stable code may be difficult to achieve. In this case averaging readings may be necessary. This noise data was taken in a very clean setup. Any setupinduced noise (noise or ripple on VCC, VREF, VIN or V –) will add to the internal noise. The lower the reference voltage to be used, the more critical it becomes to have a clean, noise-free setup. Conversion Speed with Reduced VREF With reduced reference voltages, the LSB step size is reduced and the LTC1092/LTC1093/LTC1094 internal comparator overdrive is reduced. Therefore, it may be necessary to reduce the maximum CLK frequency when low values of VREF are used. 25 LTC1091/LTC1092 LTC1093/LTC1094 UO TYPICAL APPLICATI S 0°C to 500°C Furnace Exhaust Gas Temperature Monitor with Low Supply Detection 9V VIN 2 J TYPE 8 GND 4 + 56k 4 LT1025A J LT1021-5 0.1µF VIN – 2 6 VOUT + 10µF 20k 1N4148 COMMON 5 LTC1091A 3 7 + 6 LTC1052 1µF 2 CS 47Ω 8 – 4 1 0.1µF 0.1µF 1k 0.1% 0.33µF 3.4k 1% 26 178k 0.1% 1µF 10k VCC CH0 CLK CH1 DOUT GND DIN TO MCU 1091 TA03 LTC1091/LTC1092 LTC1093/LTC1094 UO TYPICAL APPLICATI S 0°C to 100°C 0.25°C Accurate Thermistor Based Temperature Measurement System 5V 4.7µF 2N3904 10k ±10% 15k ±10% LTC1094 YSI 44201 0°C TO 100°C 5k AT 25°C 20°C TO –40°C YSI 44201 * 2954Ω 5000Ω CH0 DVCC CH1 AVCC CH2 CLK CH3 CS CH4 DOUT CH5 DIN CH6 REF + CH7 REF – COM AGND + LT1006 – V– DGND 4562Ω TO MCU 1491Ω 1091-4 TA04 *YSI 44007, 44034 OR EQUIVALENT – 55°C to 125°C Thermometer Using Current Output Silicon Sensors 4.7µF 5V 9V VOUT 10µF LT1019-2.5 3Ω LM134 OR OTHER 1µA/°K SENSOR 226Ω LTC1092 CS 11.5k VCC + – SCLK GND VREF TO MCU DOUT 1091 TA05 27 LTC1091/LTC1092 LTC1093/LTC1094 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.100 (2.54) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 28 0.130 ± 0.005 (3.302 ± 0.127) 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1098 LTC1091/LTC1092 LTC1093/LTC1094 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.770* (19.558) MAX 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.020 (0.508) MIN 0.065 (1.651) TYP 0.125 (3.175) MIN 0.100 (2.54) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 0.018 ± 0.003 (0.457 ± 0.076) N16 1098 29 LTC1091/LTC1092 LTC1093/LTC1094 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package 20-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.040* (26.416) MAX 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 +0.889 8.255 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.020 (0.508) MIN 0.065 (1.651) TYP 0.125 (3.175) MIN 0.005 (0.127) MIN *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 30 0.100 (2.54) BSC 0.018 ± 0.003 (0.457 ± 0.076) N20 1098 LTC1091/LTC1092 LTC1093/LTC1094 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 16-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.398 – 0.413* (10.109 – 10.490) 16 15 14 13 12 11 10 9 0.394 – 0.419 (10.007 – 10.643) NOTE 1 1 0.291 – 0.299** (7.391 – 7.595) 2 3 4 5 6 7 0.093 – 0.104 (2.362 – 2.642) 0.010 – 0.029 × 45° (0.254 – 0.737) 8 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) BSC 0.004 – 0.012 (0.102 – 0.305) 0.014 – 0.019 (0.356 – 0.482) TYP NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS S16 (WIDE) 1098 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. 31 LTC1091/LTC1092 LTC1093/LTC1094 U TYPICAL APPLICATION Micropower, 500V Optoisolated, Multichannel, 10-Bit Data Acquisition System Is Accessed Once Every Two Seconds 4N28s 10k 9V 5V 10k 2N3906 LT1021-5 10k 2N3906 51k C1 150Ω 1Ω 5V 10k + 10µF* LTC1094 8 ANALOG INPUTS 0V TO 5V RANGE 5V CH0 DVCC CH1 AVCC CH2 CLK CH3 CS CH4 DOUT CH5 DIN CH6 REF+ CH7 REF – COM AGND 5.1k ×3 10k C0 150Ω 51k TO 68HC05** 5V 10k MOSI 150Ω 51k TO ADDITIONAL LTC1094s 5.1k 51k 300Ω V– DGND SCK 150Ω 51k 4N28 10k MISO 2N3904 *SOLID TANTALUM **MC68HC05 CODE AVAILABLE FROM LINEAR TECHNOLOGY 4N28 ISOLATION BARRIER 5V LT1091-4 TA06 NC RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1090 10-Bit, 8-Channel ADC Serial I/O, 1.5mA Supply Current LTC1291/LTC1292 12-BIT, 2-Channel and Differential ADCs Pin Compatible Upgrades to LTC1091/LTC1092 LTC1293/LTC1294 12-Bit, 6- and 8-Channel ADCs Pin Compatible Upgrades to LTC1093/LTC1094 32 Linear Technology Corporation 1091fa LT/TP 1099 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1988