Features • Low Voltage and Standard Voltage Operation • • • • • • • • • • • • • – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 2.5 (VCC = 2.5V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V) Internally Organized 2048 x 8 (16K) 2-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 KHz (1.8V, 2.5V, 2.7V) and 400 KHz (5V) Compatibility Write Protect Pin for Hardware Data Protection Cascadable Feature Allows for Extended Densities 16-Byte Page Write Mode Partial Page Writes Are Allowed Self-Timed Write Cycle (10 ms max) High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: >3,000V Automotive Grade and Extended Temperature Devices Available 8-Pin JEDEC SOIC and 8-Pin PDIP Packages 2-Wire Serial EEPROM 16K (2048 x 8) AT24C164 Description The AT24C164 provides 16,384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 2048 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C164 is available in space saving 8-pin PDIP and 8-pin SOIC packages and is accessed via a 2-wire serial interface. In addition, this device is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions. Pin Configurations Pin Name Function A0 to A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect 2-Wire, 16K Serial EEPROM 8-Pin PDIP A0 A1 A2 GND 1 2 3 4 8 7 6 5 8-Pin SOIC VCC WP SCL SDA A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Rev. 0105D–07/98 1 Absolute Maximum Ratings* Operating Temperature .................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage........................................... 6.25V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Block Diagram WP Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE SELECT (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that may be hardwired or actively driven to VDD or VSS. These inputs allow the selection for 2 AT24C164 one of eight possible devices sharing a common bus. The AT24C164 can be made compatible with the AT24C16 by tying A2, A1 and A0 to VSS. Device addressing is discussed in detail in the device addressing section. WRITE PROTECT (WP): The write protect input, when tied low to GND, allows normal write operations. Memory Organization The AT24C164 is internally organized with 256 pages of 8 bytes each. Random word addressing requires an 11 bit data word address. AT24C164 Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V. Symbol Test Condition CI/O CIN Note: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter VCC1 Supply Voltage VCC2 Max Units 1.8 5.5 V Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 2.7 5.5 V VCC4 Supply Voltage 4.5 5.5 V ICC Standby Current VCC = 5.0V READ at 100 KHz 0.4 1.0 mA ICC Standby Current VCC = 5.0V WRITE at 100 KHz 2.0 3.0 mA ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 µA ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 1.4 4.0 µA ISB3 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA ISB4 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA VIL Input Low Level(1) -0.6 VCC x 0.3 V VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V Note: Test Condition Min Typ 1. VIL min and VIH max are reference only and are not tested. 3 AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). 2.7-, 2.5-, 1.8-volt Symbol Parameter fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low tHIGH Clock Pulse Width High Min Max 5.0-volt Min 100 Max Units 400 KHz 4.7 1.2 µs 4.0 0.6 µs (1) tI Noise Suppression Time tAA Clock Low to Data Out Valid 0.1 tBUF Time the bus must be free before a new transmission can start(1) 4.7 1.2 µs tHD.STA Start Hold Time 4.0 0.6 µs tSU.STA Start Set-up Time 4.7 0.6 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Set-up Time 200 100 ns tR Inputs Rise Time(1) 1.0 0.3 µs tF Inputs Fall Time(1) 300 300 ns tSU.STO Stop Set-up Time 4.7 0.6 µs tDH Data Out Hold Time 100 50 ns tWR Write Cycle Time Endurance(1) 5.0V, 25°C, Page Mode Notes: 100 4.5 0.1 10 1M 50 ns 0.9 µs 10 1M ms Write cycles 1. This parameter is characterized and is not 100% tested. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). 4 AT24C164 ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C164 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, the AT24C164 can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high. AT24C164 Bus Timing SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O (1) Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 5 Data Validity Start and Stop Definition Output Acknowledge 6 AT24C164 AT24C164 Device Addressing The AT24C164 requires an 8-bit device address word following a start condition to enable the chip for read or write operations (refer to Figure 1). The most significant bit must be a one followed by the A2, A1 and A0 device select bits (the A1 bit must be the compliment of the A1 input pin signal). The next 3 bits are used for memory block addressing and select one of the eight 256 x 8 memory blocks. These bits should be considered the three most significant bits of the data word address. The eighth bit of the device address is the read/write select bit. A read operation is selected if this bit is high or a write operation is selected if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2). PAGE WRITE: The AT24C164 is capable of a 16-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3). The data word address lower 4 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than sixteen data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6). 7 Figure 1. Device Address Figure 2. Byte Write Figure 3. Page Write Figure 4. Current Address Read Figure 5. Random Read 8 AT24C164 AT24C164 Figure 6. Sequential Read 9 Ordering Information tWR (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (KHz) 10 3000 18 3000 10 10 10 Ordering Code Package 400 AT24C164-10PC AT24C164-10SC 8P3 8S1 Commercial (0°C to 70°C) 18 400 AT24C164-10PI AT24C164-10SI 8P3 8S1 Industrial (-40°C to 85°C) 1500 4 100 AT24C164-10PC-2.7 AT24C164-10SC-2.7 8P3 8S1 Commercial (0°C to 70°C) 1500 4 100 AT24C164-10PI-2.7 AT24C164-10SI-2.7 8P3 8S1 Industrial (-40°C to 85°C) 1000 4 100 AT24C164-10PC-2.5 AT24C164-10SC-2.5 8P3 8S1 Commercial (0°C to 70°C) 1000 4 100 AT24C164-10PI-2.5 AT24C164-10SI-2.5 8P3 8S1 Industrial (-40°C to 85°C) 800 4 100 AT24C164-10PC-1.8 AT24C164-10SC-1.8 8P3 8S1 Commercial (0°C to 70°C) 800 4 100 AT24C164-10PI-1.8 AT24C164-10SI-1.8 8P3 8S1 Industrial (-40°C to 85°C) Package Type 8P3 8 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8 Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options Blank Standard Operation (4.5V to 5.5V) -2.7 Low-Voltage (2.7V to 5.5V) -2.5 Low-Voltage (2.5V to 5.5V) -1.8 Low-Voltage (1.8V to 5.5V) 10 AT24C164 Operation Range AT24C164 Packaging Information 8P3, 8-Lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) 8S1, 8-Lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA .400 (10.16) .355 (9.02) .020 (.508) .013 (.330) PIN 1 .280 (7.11) .240 (6.10) .300 (7.62) REF .210 (5.33) MAX .037 (.940) .027 (.690) .244 (6.20) .228 (5.79) .050 (1.27) BSC .100 (2.54) BSC .196 (4.98) .189 (4.80) SEATING PLANE .068 (1.73) .053 (1.35) .015 (.380) MIN .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .022 (.559) .014 (.356) .010 (.254) .004 (.102) .325 (8.26) .300 (7.62) .012 (.305) .008 (.203) .157 (3.99) .150 (3.81) PIN 1 0 REF 15 .430 (10.9) MAX 0 REF 8 .010 (.254) .007 (.203) .050 (1.27) .016 (.406) 11