Product Folder Order Now Support & Community Tools & Software Technical Documents OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 1 Features 3 Description • • The OPAx192-Q1 family (OPA192-Q1, OPA2192-Q1, and OPA4192-Q1) is a new generation of 36-V, etrim operational amplifiers. The OPAx192-Q1 family of operational amplifiers use e-trim™, a method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding. 1 • • • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified with the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device Human Body Model (HBM) Electrostatic Discharge (ESD) Classification Level 3A – Device Charged Device Model (CDM) ESD Classification Level C3 Low Offset Voltage: ±5 µV Low Offset Voltage Drift: ±0.2 µV/°C Low Noise: 5.5 nV/√Hz at 1 kHz High Common-Mode Rejection: 140 dB Low Bias Current: ±5 pA Rail-to-Rail Input and Output Wide Bandwidth: 10 MHz GBW High Slew Rate: 20 V/µs Low Quiescent Current: 1 mA per Amplifier Wide Supply: ±2.25 V to ±18 V, 4.5 V to 36 V EMI/RFI Filtered Inputs Differential Input Voltage Range to Supply Rail High Capacitive Load Drive Capability: 1 nF Industry-Standard Packages: – Single Channel in Very Small VSSOP-8 – Dual Channel in VSSOP-8 – Quad Channel in SOIC -14 2 Applications Unique features such as differential input-voltage range to the supply rail, high output current (±65 mA), high capacitive load drive of up to 1 nF, and high slew rate (20 V/µs) make the OPAx192-Q1 a robust, high-performance operational amplifier for highvoltage industrial applications. The OPAx192-Q1 family of op amps is available in standard packages and is specified from –40°C to +125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) OPA192-Q1 VSSOP (8) 3.00 mm × 3.00 mm OPA2192-Q1 VSSOP (8) 3.00 mm × 3.00 mm OPA4192-Q1 SOIC (14) 8.65 mm × 3.90 mm (1) For all available packages, see the package option addendum at the end of the data sheet. OPAx192-Q1 Maintains Ultra-Low Input Offset Voltage Over Temperature Motor Control for Automotive Traction Inverter On Board Charger Precision Current Sensing 100 66 Typical Units Shown 75 50 VOS ( V) • • • • These devices offer outstanding dc precision and ac performance, including rail-to-rail input/output, low offset (±5 µV, typical), low offset drift (±0.2 µV/°C, typical), and 10-MHz bandwidth. 25 0 ±25 ±50 ±75 ±100 ±75 ±50 ±25 0 25 50 75 Temperature (ƒC) 100 125 150 C001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. ADVANCE INFORMATION OPAx192-Q1 36-V, Precision, Rail-to-Rail Input/Output, Low-Offset Voltage, Low-Input Bias Current Op Amp With e-trim™ OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 8.1 8.2 8.3 8.4 1 1 1 2 3 5 9 ADVANCE INFORMATION Absolute Maximum Ratings ..................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information: OPA192-Q1 ............................ 6 Thermal Information: OPA2192-Q1 .......................... 6 Thermal Information: OPA4192-Q1 .......................... 6 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) ................................................................... 7 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)............................................................... 9 6.9 Typical Characteristics ............................................ 11 6.10 Typical Characteristics .......................................... 12 Parameter Measurement Information ................ 20 8 Detailed Description ............................................ 23 23 23 24 30 Application and Implementation ........................ 31 9.1 Application Information............................................ 31 9.2 Typical Applications ................................................ 31 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 Power-Supply Recommendations ..................... 35 11 Layout................................................................... 35 11.1 Layout Guidelines ................................................. 35 11.2 Layout Example .................................................... 36 12 Device and Documentation Support ................. 37 12.1 12.2 12.3 12.4 12.5 12.6 12.7 7.1 Input Offset Voltage Drift......................................... 20 Device Support...................................................... Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 37 37 37 37 37 38 38 13 Mechanical, Packaging, and Orderable Information ........................................................... 38 4 Revision History 2 DATE REVISION NOTES May 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 5 Pin Configuration and Functions ADVANCE INFORMATION OPA192-Q1 DGK Package 8-Pin VSSOP Top View NC – No internal connection. Pin Functions: OPA192-Q1 PIN NAME I/O NO. DESCRIPTION +IN 3 I Noninverting input –IN 2 I Inverting input NC 1, 5, 8 — No internal connection (can be left floating) OUT 6 O Output V+ 7 — Positive (highest) power supply V– 4 — Negative (lowest) power supply Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 3 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com OPA2192-Q1 DGK Package 8-Pin VSSOP Top View OPA4192-Q1 D Package 14-Pin SOIC Top View ADVANCE INFORMATION Pin Functions: OPA2192-Q1 and OPA4192-Q1 PIN OPA2192-Q1 OPA4192-Q1 DGK (VSSOP) D (SOIC) +IN A 3 3 I Noninverting input, channel A +IN B 5 5 I Noninverting input, channel B +IN C — 10 I Noninverting input, channel C +IN D — 12 I Noninverting input, channel D –IN A 2 2 I Inverting input, channel A –IN B 6 6 I Inverting input, channel B –IN C — 9 I Inverting input,,channel C –IN D — 13 I Inverting input, channel D OUT A 1 1 O Output, channel A OUT B 7 7 O Output, channel B OUT C — 8 O Output, channel C OUT D — 14 O Output, channel D V+ 8 4 — Positive (highest) power supply V– 4 11 — Negative (lowest) power supply NAME 4 Submit Documentation Feedback I/O DESCRIPTION Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN Supply voltage, VS = (V+) – (V–) Common-mode Voltage UNIT ±20 (40, single-supply) V (V–) – 0.5 (V+) + 0.5 Differential Current ±10 Output short circuit (2) Class 1 Operating range (2) –55 150 Junction 150 Storage, Tstg (1) mA Continuous Latch-up per JESD78D Temperature V (V+) – (V–) + 0.2 –65 °C 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Short-circuit to ground, one amplifier per package. 6.2 ESD Ratings VALUE UNIT OPA192-Q1 V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±4000 Charged device model (CDM), per AEC Q100-011 ±500 Human body model (HBM), per AEC Q100-002 (1) ±4000 Charged device model (CDM), per AEC Q100-011 ±500 Human body model (HBM), per AEC Q100-002 (1) ±4000 Charged device model (CDM), per AEC Q100-011 ±500 V OPA2192-Q1 V(ESD) Electrostatic discharge V OPA4192-Q1 V(ESD) (1) Electrostatic discharge V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage, VS = (V+) – (V–) Specified temperature Copyright © 2017, Texas Instruments Incorporated NOM MAX UNIT 4.5 (±2.25) 36 (±18) V –40 +125 °C Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 5 ADVANCE INFORMATION Signal input pins MAX OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com 6.4 Thermal Information: OPA192-Q1 OPA192-Q1 THERMAL METRIC (1) DGK (VSSOP) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 180.4 °C/W RθJC(top) RθJB Junction-to-case (top) thermal resistance 67.9 °C/W Junction-to-board thermal resistance 102.1 °C/W ψJT Junction-to-top characterization parameter 10.4 °C/W ψJB Junction-to-board characterization parameter 100.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Thermal Information: OPA2192-Q1 OPA2192-Q1 THERMAL METRIC (1) DGK (VSSOP) UNIT 8 PINS ADVANCE INFORMATION RθJA Junction-to-ambient thermal resistance 158 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.6 °C/W RθJB Junction-to-board thermal resistance 78.7 °C/W ψJT Junction-to-top characterization parameter 3.9 °C/W ψJB Junction-to-board characterization parameter 77.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.6 Thermal Information: OPA4192-Q1 OPA4192-Q1 THERMAL METRIC (1) D (SOIC) UNIT 14 PINS RθJA Junction-to-ambient thermal resistance 86.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 46.3 °C/W RθJB Junction-to-board thermal resistance 41.0 °C/W ψJT Junction-to-top characterization parameter 11.3 °C/W ψJB Junction-to-board characterization parameter 40.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±5 ±25 ±8 ±50 ±10 ±75 ±10 ±40 TA = 0°C to 85°C ±25 ±150 TA = –40°C to 125°C ±50 ±250 TA = 0°C to 85°C ±0.1 ±0.5 ±0.15 ±0.8 TA = 0°C to 85°C ±0.1 ±0.8 TA = –40°C to 125°C ±0.2 ±1.0 ±0.3 ±1.0 µV/V ±5 ±20 pA ±5 nA ±20 pA ±2 nA OFFSET VOLTAGE TA = 0°C to 85°C VOS Input offset voltage TA = –40°C to 125°C VCM = (V+) – 1.5 V D packages only dVOS/dT Input offset voltage drift DBV, DGK, and PW packages only PSRR Power-supply rejection ratio TA = –40°C to 125°C TA = –40°C to 125°C µV µV/°C IB IOS Input bias current Input offset current TA = –40°C to 125°C ±2 TA = –40°C to 125°C ADVANCE INFORMATION INPUT BIAS CURRENT NOISE En Input voltage noise (V–) – 0.1 V < VCM < (V+) – 3 V f = 0.1 Hz to 10 Hz 1.30 (V+) – 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz 4 (V–) – 0.1 V < VCM < (V+) – 3 V en Input voltage noise density (V+) – 1.5 V < VCM < (V+) + 0.1 V f = 100 Hz µVPP 10.5 f = 1 kHz 5.5 f = 100 Hz 32 f = 1 kHz nV/√Hz 12.5 NOISE (continued) in Input current noise density f = 1 kHz 1.5 fA/√Hz INPUT VOLTAGE VCM Common-mode voltage range (V–) – 0.1 (V–) – 0.1 V < VCM < (V+) – 3 V CMRR Common-mode rejection ratio (V+) – 1.5 V < VCM < (V+) TA = –40°C to 125°C 120 140 114 126 100 120 86 100 TA = –40°C to 125°C (V+) – 3 V < VCM < (V+) – 1.5 V (V+) + 0.1 V dB See Typical Characteristics INPUT IMPEDANCE ZID Differential ZIC Common-mode 100 || 1.6 1 || 6.4 MΩ || pF 1013Ω || pF OPEN-LOOP GAIN (V–) + 0.6 V < VO < (V+) – 0.6 V, RLOAD = 2 kΩ AOL Open-loop voltage gain (V–) + 0.3 V < VO < (V+) – 0.3 V, RLOAD = 10 kΩ Copyright © 2017, Texas Instruments Incorporated TA = –40°C to 125°C TA = –40°C to 125°C 120 134 114 126 126 140 120 134 Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 dB 7 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued) at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FREQUENCY RESPONSE GBW Unity gain bandwidth SR Slew rate G = 1, 10-V step To 0.01% ts Settling time To 0.001% Overload recovery time VIN × G = VS THD+N Total harmonic distortion + noise G = 1, f = 1 kHz, VO = 3.5 VRMS Crosstalk MHz 20 V/µs V S = ±18 V, G = 1, 10-V step 1.4 V S = ±18 V, G = 1, 5-V step 0.9 V S = ±18 V, G = 1, 10-V step 2.1 V S = ±18 V, G = 1, 5-V step tOR 10 µs 1.8 200 ns 0.00008% OPA2192-Q1 and OPA4192-Q1, at dc 150 OPA2192-Q1 and OPA4192-Q1, f = 100 kHz 130 dB OUTPUT ADVANCE INFORMATION No load Positive rail Voltage output swing from rail VO Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance 15 95 110 RLOAD = 2 kΩ 430 500 5 15 RLOAD = 10 kΩ 95 110 RLOAD = 2 kΩ 430 500 No load Negative rail ISC 5 RLOAD = 10 kΩ ±65 mV mA See Typical Characteristics f = 1 MHz, IO = 0 A; see Figure 31 375 Ω POWER SUPPLY IQ Quiescent current per amplifier IO = 0 A 1 TA = –40°C to 125°C, IO = 0 A 1.2 1.5 mA TEMPERATURE Thermal protection (1) (1) 8 140 °C For a detailed description of thermal protection, see Thermal Protection . Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX ±5 ±25 ±8 ±50 ±10 ±75 UNIT OFFSET VOLTAGE TA = 0°C to 85°C TA = –40°C to 125°C VOS Input offset voltage (V+) – 3.5 V < VCM < (V+) – 1.5 V VCM = (V+) – 1.5 V dVOS/dT PSRR Input offset voltage drift Power-supply rejection ratio See Common-Mode Voltage Range ±10 ±40 TA = 0°C to 85°C ±25 ±150 TA = –40°C to 125°C ±50 ±250 ±0.1 ±0.5 TA = –40°C to 125°C ±0.15 ±0.8 TA = 0°C to 85°C VCM = (V+) – 3 V DBV, DGK, and PW packages only TA = –40°C to 125°C ±0.1 ±0.8 ±0.2 ±1.1 VCM = (V+) – 1.5 V, TA = –40°C to 125°C ±0.5 ±3 VCM = (V+) – 3 V D packages only µV TA = 0°C to 85°C TA = –40°C to 125°C, VCM = VS / 2 – 0.75 V ±1 µV µV/°C µV/V ADVANCE INFORMATION VCM = (V+) – 3 V INPUT BIAS CURRENT IB IOS Input bias current Input offset current ±5 TA = –40°C to 125°C ±2 TA = –40°C to 125°C ±20 pA ±5 nA ±20 pA ±2 nA NOISE En Input voltage noise (V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz (V–) – 0.1 V < VCM < (V+) – 3 V en Input voltage noise density (V+) – 1.5 V < VCM < (V+) + 0.1 V in 1.30 (V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz Input current noise density µVPP 4 f = 100 Hz 10.5 f = 1 kHz 5.5 f = 100 Hz 32 f = 1 kHz 12.5 f = 1 kHz 1.5 nV/√Hz fA/√Hz INPUT VOLTAGE VCM Common-mode voltage range (V–) – 0.1 (V–) – 0.1 V < VCM < (V+) – 3 V CMRR Common-mode rejection ratio (V+) – 1.5 V < VCM < (V+) TA = –40°C to 125°C 94 110 90 104 100 120 84 100 TA = –40°C to 125°C (V+) – 3 V < VCM < (V+) – 1.5 V (V+) + 0.1 V dB See Typical Characteristics INPUT IMPEDANCE ZID Differential ZIC Common-mode 100 || 1.6 1 || 6.4 MΩ || pF 1013Ω || pF OPEN-LOOP GAIN (V–) + 0.6 V < VO < (V+) – 0.6 V, RLOAD = 2 kΩ AOL Open-loop voltage gain (V–) + 0.3 V < VO < (V+) – 0.3 V, RLOAD = 10 kΩ Copyright © 2017, Texas Instruments Incorporated TA = –40°C to 125°C TA = –40°C to 125°C 110 120 100 114 110 126 110 120 Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 dB 9 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued) at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FREQUENCY RESPONSE GBW Unity gain bandwidth SR Slew rate G = 1, 10-V step ts Settling time To 0.01% tOR Overload recovery time Crosstalk 10 MHz 20 V/µs 1 µs VIN× G = VS 200 ns OPA2192-Q1 and OPA4192-Q1, at dc 150 OPA2192-Q1 and OPA4192-Q1, f = 100 kHz 130 VS = ±3 V, G = 1, 5-V step dB OUTPUT No load Positive rail Voltage output swing from rail VO ADVANCE INFORMATION Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance 15 95 110 RLOAD = 2 kΩ 430 500 5 15 RLOAD = 10 kΩ 95 110 RLOAD = 2 kΩ 430 500 No load Negative rail ISC 5 RLOAD = 10 kΩ ±65 mV mA See Typical Characteristics f = 1 MHz, IO = 0 A; see Figure 31 375 Ω POWER SUPPLY IQ Quiescent current per amplifier IO = 0 A 1 TA = –40°C to 125°C 1.2 1.5 mA TEMPERATURE Thermal protection (1) (1) 10 140 °C For a detailed description of thermal protection, see Thermal Protection . Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 6.9 Typical Characteristics Table 1. Table of Graphs FIGURE Offset Voltage Production Distribution Figure 1 to Figure 6 Offset Voltage Drift Distribution Figure 7 to Figure 10 Offset Voltage vs Temperature Figure 11 Offset Voltage vs Common-Mode Voltage Figure 12 to Figure 14 Offset Voltage vs Power Supply Figure 15 Open-Loop Gain and Phase vs Frequency Figure 16 Closed-Loop Gain and Phase vs Frequency Figure 17 Input Bias Current vs Common-Mode Voltage Figure 18 Input Bias Current vs Temperature Figure 19 Output Voltage Swing vs Output Current (maximum supply) Figure 20 CMRR and PSRR vs Frequency Figure 21 CMRR vs Temperature Figure 22 PSRR vs Temperature Figure 23 0.1-Hz to 10-Hz Noise Figure 24 Input Voltage Noise Spectral Density vs Frequency Figure 25 THD+N Ratio vs Frequency Figure 26 THD+N vs Output Amplitude Figure 27 Quiescent Current vs Supply Voltage Figure 28 Quiescent Current vs Temperature Figure 29 Open Loop Gain vs Temperature Figure 30 Open Loop Output Impedance vs Frequency Small Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 31 Figure 32, Figure 33 No Phase Reversal Figure 34 Positive Overload Recovery Figure 35 Negative Overload Recovery ADVANCE INFORMATION DESCRIPTION Figure 36 Small-Signal Step Response (100 mV) Large-Signal Step Response Figure 37, Figure 38 Figure 39 Settling Time Figure 40 to Figure 43 Short-Circuit Current vs Temperature Figure 44 Maximum Output Voltage vs Frequency Figure 45 Propagation Delay Rising Edge Figure 46 Propagation Delay Falling Edge Figure 47 Crosstalk vs Frequency Figure 48 Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 11 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com 6.10 Typical Characteristics at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 50 22 18 40 16 Amplifiers (%) Percentage of Amplifiers (%) Distribution Taken From 190 Amplifiers Distribution Taken From 4715 Amplifiers 20 14 12 10 8 30 20 6 10 4 75 50 25 0 -25 -50 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 0 -75 2 Offset Voltage (µV) Offset Voltage ( V) C013 C032 TA = 125°C Distribution Taken From 190 Amplifiers 70 Distribution Taken From 190 Amplifiers 70 60 50 50 Amplifiers (%) 60 40 30 40 30 20 20 10 10 0 0 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 Offset Voltage (µV) Offset Voltage (µV) TA = 85°C Figure 3. Offset Voltage Production Distribution at 85°C Figure 4. Offset Voltage Production Distribution at 0°C 50 50 40 35 35 25 75 50 25 0 0 5 0 -25 5 -50 10 -75 15 10 Offset Voltage (µV) Offset Voltage (µV) TA = –25°C TA = –40° C Submit Documentation Feedback 75 20 15 50 20 30 25 25 0 30 -75 Amplifiers (%) 40 Figure 5. Offset Voltage Production Distribution at –25°C 12 Distribution Taken From 190 Amplifiers 45 -50 Distribution Taken From 190 Amplifiers 45 Amplifiers (%) TA = 0°C -25 Amplifiers (%) Figure 2. Offset Voltage Production Distribution at 125°C -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 ADVANCE INFORMATION Figure 1. Offset Voltage Production Distribution at 25°C Figure 6. Offset Voltage Production Distribution at –40°C Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 50 70 Distribution Taken From 75 Amplifiers Distribution Taken From 120 Amplifiers 60 40 Amplifiers (%) Amplifiers (%) 50 40 30 20 30 20 10 Offset Voltage Drift (µV/ƒC) 1.1 0.9 0.7 0.5 0.3 0.1 -0.1 -0.3 -0.5 Offset Voltage Drift (µV/ƒC) Figure 7. Offset Voltage Drift Distribution from –40°C to +125°C ADVANCE INFORMATION OPA192-Q1IDBV, OPA192-Q1IDGK, OPA2192-Q1IDGK, OPA4192-Q1IPW SOT and VSSOP, TA = –40°C to +125°C OPA192-Q1ID and OPA2192-Q1ID SOIC, TA = –40°C to +125°C Figure 8. Offset Voltage Drift Distribution from –40°C to +125°C 30 70 Distribution Taken From 75 Amplifiers Distribution Taken From 120 Amplifiers 60 25 50 20 Amplifiers (%) Amplifiers (%) -0.7 -1.1 0.8 0.6 0.7 0.4 0.5 0.2 0.3 0 0.1 -0.2 -0.1 -0.4 -0.3 -0.6 -0.5 -0.8 0 -0.7 0 -0.9 10 40 30 15 10 20 5 Offset Voltage Drift (µV/ƒC) 0.8 0.7 0.5 0.6 0.4 0.3 0.1 0.2 0 -0.2 -0.1 -0.3 -0.5 -0.4 -0.6 -0.8 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.4 -0.3 0 -0.5 0 -0.7 10 Offset Voltage Drift (µV/ƒC) OPA192-Q1IDBV, OPA192-Q1IDGK, OPA2192-Q1IDGK, OPA4192-Q1IPW SOT and VSSOP, TA = 0°C to 85°C OPA192-Q1ID and OPA2192-Q1ID SOIC, TA = 0°C to 85°C Figure 9. Offset Voltage Drift Distribution from 0°C to 85°C Figure 10. Offset Voltage Drift Distribution from 0°C to 85°C 100 50 190 Typical Units Shown 5 Typical Units Shown 75 25 25 VOS ( V) VOS ( V) 50 0 ±25 0 VCM = -18.1 V ±50 ±25 ±75 ±100 ±75 ±50 ±25 ±50 0 25 50 75 100 125 Temperature (ƒC) Figure 11. Offset Voltage vs Temperature Copyright © 2017, Texas Instruments Incorporated 150 ±20 ±15 ±10 ±5 0 5 10 15 VCM (V) C001 20 C001 Figure 12. Offset Voltage vs Common-Mode Voltage Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 13 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 200 100 5 Typical Units Shown 5 Typical Units Shown 150 75 VCM = +18.1 V 100 VCM = -18.1 V 25 50 VOS(μV) VOS ( V) 50 0 ±25 0 ±50 P-Channel N-Channel ±50 ±75 VCM = +2.35 V VCM = -2.35 V ±100 ±150 Transition ±100 12.5 13.5 14.5 15.5 16.5 17.5 VCM (V) Transition P-Channel ±200 ±2.5 ±2.0 ±1.5 ±1.0 ±0.5 0.0 0.5 18.5 N-Channel 1.0 1.5 2.0 2.5 VCM (V) C001 VS = ±2.25 V Figure 14. Offset Voltage vs Common-Mode Voltage 180 140.0 10 Typical Units Shown 40 120.0 30 10 Gain (dB) VOS(μV) Open-loop Gain 100.0 20 0 ±10 135 80.0 Phase 60.0 90 40.0 Phase (ƒ) ADVANCE INFORMATION Figure 13. Offset Voltage vs Common-Mode Voltage 50 ±20 ±30 20.0 ±40 0.0 ±50 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 45 ±20.0 1 VSUPPLY (V) 10 VS = ±2.25 V to ±18 V 1k 10k 100k Frequency (Hz) 1M 0 10M 100M CLOAD = 15 pF Figure 15. Offset Voltage vs Power Supply 60.0 Figure 16. Open-Loop Gain and Phase vs Frequency 20 G = -100 G = +1 G = -1 G = -10 15 Input Bias Current (pA) 40.0 Gain (dB) 100 20.0 0.0 IB- 10 5 0 IB+ ±5 ±10 ±15 ±20.0 1000 10k 100k 1M Frequency (Hz) ±20 ±18.0 10M Figure 17. Closed-Loop Gain and Phase vs Frequency 14 Submit Documentation Feedback ±9.0 0.0 VCM (V) C003 9.0 18.0 C001 Figure 18. Input Bias Current vs Common-Mode Voltage Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 6000 (V-) + 5 IB+ IB Ios Input Bias Current (pA) 5000 (V-) + 4 +125°C 4000 (V-) + 3 Vout (V) 3000 2000 (V-) + 2 -40°C (V-) + 1 1000 (V-) Ios 0 (V-) - 1 ±1000 ±50 ±25 0 25 50 75 100 125 150 Temperature (ƒC) 0 175 Common-Mode Rejection Ratio (µV/V) Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) 30 40 50 60 70 80 C001 Figure 20. Output Voltage Swing vs Output Current (Maximum Supply) 160.0 140.0 120.0 100.0 80.0 60.0 +PSRR CMRR 20.0 20 Iout (mA) Figure 19. Input Bias Current vs Temperature 40.0 10 C001 -PSRR ADVANCE INFORMATION ±75 10 8 6 4 VS = ±2.25 V, VCM = V+ - 3 V 2 0 ±2 VS = ±18 V, VCM = 0 V ±4 ±6 ±8 ±10 0.0 1 10 100 1k 10k 100k Frequency (Hz) 1M ±75 ±50 ±25 0 25 50 75 100 125 Temperature (ƒC) C012 Figure 21. CMRR and PSRR vs Frequency 150 C001 Figure 22. CMRR vs Temperature 0.8 0.6 0.4 400 nV/div Power-Supply Rejection Ratio (µV/V) 1 0.2 0 -0.2 -0.4 -0.6 -0.8 Peak-to-Peak Noise = VRMS × 6.6 = 1.30 Vpp -1 ±75 ±50 ±25 0 25 50 75 100 Temperature (ƒC) Figure 23. PSRR vs Temperature Copyright © 2017, Texas Instruments Incorporated 125 Time (1 s/div) 150 C001 C001 Figure 24. 0.1-Hz to 10-Hz Noise Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 15 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) Total Harmonic Distortion + Noise (%) Voltage Noise Density (nV/rtHz) VCM = V+ - 100 mV N-Channel Input 100 10 VCM = 0 V P-Channel Input 1 10 100 1k G = +1 V/V, RL = 2 kΩ G = -1 V/V, RL = 10 kΩ 0.01 10k 0.001 -100 0.0001 -120 -140 10 100k Frequency (Hz) 100 -80 0.001 -100 -120 1.1 IQ (mA) Total Harmonic Distortion + Noise (%) 0.01 1.2 Total Harmonic Distortion + Noise (dB) ADVANCE INFORMATION -60 0.1 1.0 0.9 -140 1 BW = 80 kHz Figure 26. THD+N Ratio vs Frequency 0.1 G = +1 V/V, RL = 10 kΩ G = +1 V/V, RL = 2 kΩ G = -1 V/V, RL = 10 kΩ G = -1 V/V, RL = 2 kΩ 10k Frequency (Hz) Figure 25. Input Voltage Noise Spectral Density vs Frequency 0.00001 0.01 1k C002 VOUT = 3.5 VRMS 0.0001 -80 G = -1 V/V, RL = 2 kΩ 0.00001 1 0.1 -60 G = +1 V/V, RL = 10 kΩ Total Harmonic Distortion + Noise (dB) 0.1 1000 0.8 10 0 4 8 12 Output Amplitude (VRMS) 16 20 24 28 32 36 Supply Voltage (V) C001 f = 1 kHz, BW = 80 kHz Figure 27. THD+N vs Output Amplitude Figure 28. Quiescent Current vs Supply Voltage 3.0 1.2 Vs = 4.5 V Vs = 36 V 2.0 1.1 AOL (µV/V) IQ (mA) 1.0 Vs = ±18 V 1 Vs = ±2.25 V 0.0 ±1.0 0.9 ±2.0 ±3.0 0.8 ±75 ±50 ±25 0 25 50 75 100 125 Temperature (ƒC) 150 C001 ±75 ±50 ±25 0 25 50 75 100 125 150 Temperature (ƒC) RL = 10 kΩ Figure 29. Quiescent Current vs Temperature 16 Submit Documentation Feedback Figure 30. Open-Loop Gain vs Temperature Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 50 10k 45 + 18 V 100 - + 35 1k Overshoot (%) Output Impedance ( ) 40 + - 30 R ISO OP A192-Q1 V IN CL -18 V 25 20 R ISO = 0 0Ω 15 R ISO = 25 25 Ω 10 R ISO = 50 Ω50 5 0 10 1 10 100 1k 10k 100k 1M Frequency (Hz) 10p 10M 100p 1n Capacitive Load (F) C016 RI = 1 kΩ RF = 1 kΩ G = –1 Figure 32. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 31. Open-Loop Output Impedance vs Frequency ADVANCE INFORMATION 0 50 - - RISO OPA192-Q1 + 35 VIN + CL + + - 37 VPP -18 V Sine Wave (±18.5V) -18 V - 30 VOUT OPA192-Q1 RL 5 V/div Overshoot (%) 40 VIN + 18 V + 18 V 45 25 20 15 VOUT RISO = 0 Ω0 RISO = 25 25 Ω RISO = 50 50 Ω 10 5 0 10p 100p 1n Time (200 μs/div) Capacitive Load (F) G=1 Figure 33. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 34. No Phase Reversal + 18 V VOUT + V IN - - + OP A192-Q1 V OUT + V IN - V OUT OP A192-Q1 VOUT + -18 V 5 V/div 5 V/div + 18 V - - 18 V VIN VIN Time (200 ns/div) RI = 1 kΩ RF = 10 kΩ Time (200 ns/div) G = –10 Figure 35. Positive Overload Recovery Copyright © 2017, Texas Instruments Incorporated RI = 1 kΩ G = –10 RF = 10 kΩ Figure 36. Negative Overload Recovery Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 17 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) + 18 V - + OP A192-Q1 + - 20 mV/div 20 mV/div V IN + 18 V - CL - 18 V OPA192-Q1 + + VIN RL -18 V CL - Time (120 ns/div) Time (100 ns/div) CL = 10 pF RL = 1 kΩ G=1 CL = 10 pF G = –1 Figure 38. Small-Signal Step Response (100 mV) Figure 37. Small-Signal Step Response (100 mV) Output Delta from Final Value (mV) 2 V/div ADVANCE INFORMATION 4 + 18 V - + OP A192-Q1 + V IN - CL -18 V 3 2 1 0 -1 0.01% Settling = ±1 mV -2 -3 Step Applied at t = 0 -4 0 Time (300 ns/div) RL = 1 kΩ CL = 10 pF 0.25 0.5 0.75 G = –1 1 1.25 1.5 1.75 2 Time (μs) G=1 Figure 40. Settling Time (10-V Positive Step) Figure 39. Large-Signal Step Response 4 Output Delta from Final Value (mV) Output Delta from Final Value (mV) 4 3 2 1 0 0.01% Settling = ±500 μV -1 -2 -3 Step Applied at t = 0 3 2 1 0 -1 0.01% Settling = ±1 mV -2 -3 Step Applied at t = 0 -4 -4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.2 0.4 0.6 0.8 G=1 1.2 1.4 1.6 1.8 2 G=1 Figure 41. Settling Time (5-V Positive Step) 18 1 Time (μs) Time (μs) Submit Documentation Feedback Figure 42. Settling Time (10-V Negative Step) Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 Typical Characteristics (continued) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 80 ISC, Source 3 2 ISC, Sink 60 1 ISC (mA) Output Delta from Final Value (mV) 4 0 0.01% Settling = ±500 μV -1 -2 40 20 -3 Step Applied at t = 0 -4 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 ±75 ±50 ±25 0 Time (μs) 25 50 75 100 125 150 Temperature (ƒC) C001 G=1 Figure 43. Settling Time (5-V Negative Step) Maximum output voltage without slew-rate induced distortion. VS = ±15 V Overdrive = 100 mV Output Voltage (5 V/div) Output Voltage (VPP) 25 20 15 VS = ±5 V 10 VS = ±2.25 V 5 tpLH = 0.97 s VOUT Voltage 0 10k 100k 1M Time (200 ns/div) 10M Frequency (Hz) ADVANCE INFORMATION 30 Figure 44. Short-Circuit Current vs Temperature C025 C033 Figure 45. Maximum Output Voltage vs Frequency Figure 46. Propagation Delay Rising Edge -100 VOUT Voltage Crosstalk (db) Output Voltage (1 V/div) -80 tpLH = 1.1 s Overdrive = 100 mV -120 -140 -160 -180 1k Time (200 ns/div) 10k Figure 47. Propagation Delay Falling Edge Copyright © 2017, Texas Instruments Incorporated 100k 1M Frequency (Hz) C026 Figure 48. Crosstalk vs Frequency Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 19 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com 7 Parameter Measurement Information 7.1 Input Offset Voltage Drift The OPAx192-Q1 family of operational amplifiers is manufactured using TI’s e-trim technology. Each amplifier input offset voltage and input offset voltage drift is trimmed in production, thereby minimizing errors associated with input offset voltage and input offset voltage drift. The e-trim technology is a TI proprietary method of trimming internal device parameters during either wafer probing or final testing. When trimming input offset voltage drift the systematic or linear drift error on each device is trimmed to zero. This results in the remaining errors associated with input offset drift are minimal and are the result from only nonlinear error sources. Figure 49 illustrates this concept. Input Offset Voltage VOS Before e-trim VOS After e-trim Linear component of drift Linear component of drift Figure 49. Input Offset Before and After Drift Trim A common method of specifying input offset voltage drift is the box method. The box method estimates a maximum input offset drift by bounding the offset voltage versus temperature curve with a box and using the corners of this bounding box to determine the drift. The slope of the line connecting the diagonal corners of the box corresponds to the input offset voltage drift. Figure 50 shows the box method concept. The box method works particularly well when the input offset drift is dominated by the linear component of drift, but because the OPAx192-Q1 family uses TI’s e-trim technology to remove the linear component input offset voltage drift, the box method is not a particularly useful method of accurately performing an error analysis. Figure 50 shows 30 typical units of the OPAx192-Q1 with the box method superimposed for illustrative purposes. The boundaries of the box are determined by the specified temperature range along the x-axis and the maximum specified input offset voltage across that same temperature range along the y-axis. Using the box method predicts an input offset voltage drift of 0.9 µV/°C. As shown in Figure 50, the slopes of the actual input offset voltage versus temperature are much less than that predicted by the box method. The box method predicts a negative value for the maximum input offset voltage drift and is not recommended when performing an error analysis. Offset Voltage vs Temperature 100 75 50 Offset Voltage (PV) ADVANCE INFORMATION Temperature 25 0 -25 -50 -75 -100 -50 -25 0 25 50 75 Temperature (qC) 100 125 150 Figure 50. The Box Method 20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 Input Offset Voltage Drift (continued) Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along the input offset voltage versus temperature curve. The results for the OPAx192-Q1 family are shown in Figure 51 and Figure 52. 1.1 SOIC 0.6 Input Offset Voltage Drift ( V/ƒC) +3 1 +1 0.4 0.2 0 -0.2 -0.4 -1 -0.6 -3 1 -0.8 -1 SOT and VSSOP 0.9 +3 1 0.7 +1 0.5 0.3 0.1 -0.1 -0.3 -0.5 -1 -0.7 -0.9 -3 1 -1.1 ±75 ±50 ±25 0 25 50 75 100 125 Temperature (ƒC) 150 ±75 ±50 ±25 0 Figure 51. Input Offset Voltage Drift vs Temperature (OPA192-Q1ID and OPA2192-Q1ID) 25 50 75 100 125 Temperature (ƒC) C001 150 C001 Figure 52. Input Offset Voltage Drift vs Temperature (OPA192-Q1IDBV, OPA192-Q1IDGK, OPA2192-Q1IDGK, and OPA4192-Q1IPW) As shown in Figure 51, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C to +125°C. When performing an error analysis over the full specified temperature range, use the typical and maximum values for input offset voltage drift as described in the Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) and Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) tables. If a reduced temperature range is applicable, use the information shown in Figure 51 or Figure 52 when performing an error analysis. To determine the change in input offset voltage, use Equation 1: ΔVOS = ΔT × dVOS / dT where • • • ΔVOS = Change in input offset voltage ΔT = Change in temperature dVOS / dT = Input offset voltage drift (1) For example, determine the amount of OPA192-Q1ID input offset voltage change over the temperature range of 25°C to 75°C for 1 σ (68%) of the units. As shown in Figure 51, the input offset drift is typically 0.15 µV/°C. This input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.15 µV/°C = 7.5 µV . For 3 σ (99.7%) of the units, Figure 51 shows a typical input offset drift of 0.4 µV/°C. This input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.4 µV/°C = 20 µV. Figure 53 shows six typical units. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 21 ADVANCE INFORMATION Input Offset Voltage Drift ( V/ƒC) 1 0.8 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com Input Offset Voltage Drift (continued) 75 6 Typical Units Shown 50 31 VOS ( V) 25 0 ±25 -3 1 ±50 ±75 ±75 ±50 ±25 0 25 50 75 Temperature (ƒC) 100 125 150 C001 Figure 53. Input Offset Voltage Drift vs Temperature for Six Typical Units ADVANCE INFORMATION 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 8 Detailed Description 8.1 Overview The OPAx192-Q1 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are set, further communication to the trim structure is permanently disabled. The Functional Block Diagram shows the simplified diagram of the OPAx192-Q1 with e-trim. Unlike previous e-trim op amps, the OPAx192-Q1 uses a patented two-temperature trim architecture to achieve a very low offset voltage of 25 µV (maximum) and low voltage offset drift of 0.5 µV/°C (maximum) over the full specified temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial sensors, filters, and high-voltage data acquisition. 8.2 Functional Block Diagram ADVANCE INFORMATION OPAx192-Q1 NCH Input Stage IN+ 36-V Differential Front End Slew Boost IN High Capacitive Load Compensation Output Stage VOUT PCH Input Stage ± e-trim Package Level Trim Copyright © 2017, Texas Instruments Incorporated Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 23 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com 8.3 Feature Description 8.3.1 Input Protection Circuitry The OPAx192-Q1 uses a unique input architecture to eliminate the need for input protection diodes but still provides robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure 54 can be activated by fast transient step responses and can introduce signal distortion and settling time delays because of alternate current paths, as shown in Figure 55. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling time, as shown in Figure 56. V+ V+ VIN+ VIN+ VOUT 36 V VOUT OPAx192-Q1 ~0.7 V VIN VIN V ADVANCE INFORMATION OPA192-Q1 Provides Full 36-V Differential Input Range V Conventional Input Protection Limits Differential Input Range Copyright © 2017, Texas Instruments Incorporated Figure 54. OPAx192-Q1 Input Protection Does Not Limit Differential Input Capability Vn = +10 V RFILT +10 V 1 Ron_mux Sn 1 D +10 V CFILT 2 ~±9.3 V CS CD Vn+1 = ±10 V RFILT ±10 V Vin± 2 Ron_mux Sn+1 ~0.7 V CS CFILT Vout Idiode_transient ±10 V Input Low Pass Filter Vin+ Buffer Amplifier Simplified Mux Model Figure 55. Back-to-Back Diodes Create Settling Issues Output Delta From Final Value (mV) 100 Standard Input Diode Structure Extends Settling Time 80 60 40 0.1% Settling = ±10 mV 20 0 –20 OPA192-Q1 Input Structure Offers Fast Settling –40 –60 –80 –100 0 5 10 15 20 25 30 35 Time (µs) 40 45 50 55 60 C040 Figure 56. OPAx192-Q1 Protection Circuit Maintains Fast-Settling Transient Response 24 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 Feature Description (continued) The OPAx192-Q1 family of operational amplifiers provides a true high-impedance differential input capability for high-voltage applications. This patented input protection architecture does not introduce additional signal distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications. The OPAx192-Q1 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping input signals such as multiplexed data-acquisition systems; see Figure 66. The OPAx192-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx192-Q1 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 57 shows the results of this testing on the OPAx192-Q1. Table 2 shows the EMIRR IN+ values for the OPAx192-Q1 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be found in the application report EMI Rejection Ratio of Operational Amplifiers, SBOA128, available for download from www.ti.com. 160.0 140.0 PRF = -10 dBm VSUPPLY = ±18 V VCM = 0 V EMIRR IN+ (dB) 120.0 100.0 80.0 60.0 40.0 20.0 0.0 10M 100M 1G Frequency (Hz) 10G C017 Figure 57. EMIRR Testing Table 2. OPAx192-Q1 EMIRR IN+ For Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 44.1 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 52.8 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 61.0 dB 2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 69.5 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.7 dB 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 105.5 dB 5 GHz Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 25 ADVANCE INFORMATION 8.3.2 EMI Rejection OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com 8.3.3 Phase Reversal Protection The OPAx192-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The OPAx192-Q1 is a rail-to-rail input op amp; therefore, the commonmode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. This performance is shown in Figure 58. VIN + 18 V VOUT OPA192-Q1 + - 37 VPP -18 V Sine Wave (±18.5V) 5 V/div + VOUT Figure 58. No Phase Reversal 8.3.4 Thermal Protection TA = 65°C PD = 0.81W JA = 116°C/W TJ = 116°C/W × 0.81W + 65°C TJ = 159°C (expected) +30 V VOUT The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the OPAx192-Q1 is 150°C. Exceeding this temperature causes damage to the device. The OPAx192-Q1 has a thermal protection feature that prevents damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above 140°C. Figure 59 shows an application example for the OPAx192-Q1 that has significant self heating (159°C) because of the power dissipation (0.81 W). Thermal calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 59 shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. 3V Normal Operation 0V Output High-Z 150°C OPAx192-Q1 IOUT = 30 mA + ± VIN 3V + RL 3V 100 Ÿ ± 140ºC Temperature ADVANCE INFORMATION Time (200 μs/div) Copyright © 2017, Texas Instruments Incorporated Figure 59. Thermal Protection 8.3.5 Capacitive Load and Stability The OPAx192-Q1 features a patented output stage capable of driving large capacitive loads, and in a unity-gain configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 60 and Figure 61. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier is stable in operation. 26 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 50 + 18 V 45 45 - + 18 V 40 + OP A192-Q1 + V IN - 30 40 R ISO Overshoot (%) 35 Overshoot (%) - CL -18 V 25 RISO OPA192-Q1 + 35 VIN + RL 30 25 20 20 R ISO = 0 0Ω 15 R ISO = 25 25 Ω 15 10 R ISO = 50 Ω50 10 RISO = 0 Ω0 RISO = 25 25 Ω RISO = 50 50 Ω 5 5 0 0 10p 100p 1n CL -18 V - 10p 100p 1n Capacitive Load (F) Capacitive Load (F) Figure 60. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 61. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10 Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 62. This resistor significantly reduces ringing and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the OPAx192-Q1 well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 62 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin, and results using the OPAx192-Q1 are summarized in Table 3. For additional information on techniques to optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation, and test results. +Vs Vout Riso + Vin Cload + ± -Vs Figure 62. Extending Capacitive Load Drive with the OPAx192-Q1 Table 3. OPAx192-Q1 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and Measured Results PARAMETER VALUE Capacitive Load 100 pF 1000 pF 0.01 µF 0.1 µF 1 µF Phase Margin 45° 60° 45° 60° 45° 60° 45° 60° 45° 60° RISO (Ω) 47 360 24 100 20 51 6.2 15.8 2 4.7 Measured Overshoot (%) 23.2 8.6 10.4 22.5 9.0 22.1 8.7 23.1 8.6 21 8.6 Calculated PM 45.1° 58.1° 45.8° 59.7° 46.1° 60.1° 45.2° 60.2° 47.2° 60.2° For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using an Isolation Resistor . Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 27 ADVANCE INFORMATION 50 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com 8.3.6 Common-Mode Voltage Range The OPAx192-Q1 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 63. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can vary modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD performance may be degraded compared to operation outside this region. +Vsupply IS1 VINPCH1 NCH4 NCH3 PCH2 VIN+ FUSE BANK VOS TRIM VOS DRIFT TRIM -Vsupply Figure 63. Rail-to-Rail Input Stage To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when possible. The OPAx192-Q1 uses a precision trim for both the N-channel and P-channel regions. This technique enables significantly lower levels of offset than previous-generation devices, causing variance in the transition region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in Figure 64. P-Channel Region Transition Region N-Channel Region P-Channel Region 200 200 100 100 Input Offset Voltage ( V) Input Offset Voltage ( V) ADVANCE INFORMATION e-TrimTM 0 ±100 OPA192 e-Trim Input Offset Voltage vs Vcm ±200 Transition Region N-Channel Region 0 ±100 ±200 Input Offset Voltage vs Vcm without e-Trim Input ±300 ±15.0 ±14.0 « 11.0 12.0 13.0 Common-Mode Voltage (V) 14.0 15.0 ±300 ±15.0 ±14.0 « 11.0 12.0 13.0 Common-Mode Voltage (V) 14.0 15.0 Figure 64. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers 28 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 8.3.7 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. Figure 65 shows an illustration of the ESD circuits contained in the OPAx192-Q1 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. TVS ADVANCE INFORMATION + ± RF +VS OPAx192-Q1 VDD R1 RS IN± 100 Ÿ IN+ 100 Ÿ ± + Power Supply ESD Cell VIN RL + ± VSS + ± ±VS TVS Copyright © 2017, Texas Instruments Incorporated Figure 65. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 29 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level. Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events. 8.3.8 Overload Recovery Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the OPAx192-Q1 is approximately 200 ns. ADVANCE INFORMATION 8.4 Device Functional Modes The OPAx192-Q1 has a single functional mode and is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power supply voltage for the OPAx192-Q1 is 36 V (±18 V). 30 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The OPAx192-Q1 family offers outstanding dc precision and ac performance. These devices operate up to 36-V supply rails and offer true rail-to-rail input and output, ultra-low offset voltage and offset voltage drift, as well as 10-MHz bandwidth and high capacitive load drive. These features make the OPAx192-Q1 a robust, highperformance operational amplifier for high-voltage industrial applications. 9.2 Typical Applications Figure 66 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the OPAx192-Q1 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864. 1 2 Very Low Output Impedance Input-Filter Bandwidth High-Impedance Inputs No Differential Input Clamps Fast Settling-Time Requirements 4 Attenuate High-Voltage Input Signal Fast-Settling Time Requirements Stability of the Input Driver Attenuate ADC Kickback Noise VREF Output: Value and Accuracy Low Temp and Long-Term Drift Voltage Reference CH0+ OPAx192-Q1 ±20-V, 10-kHz Sine Wave 3 + RC Filter Buffer RC Filter Reference Driver + CH0- OPAx192-Q1 Gain Network OPAx192-Q1 Gain Network + 4:2 Mux REFP + OPAx192-Q1 CH3+ OPAx192-Q1 + + Antialiasing Filter SAR ADC + VINM OPAx192-Q1 CH3- n 16 Bits 400 kSPS High-Voltage Level Translation VCM High-Voltage Multiplexed Input CONV Gain Network ±20-V, 10-kHz Sine Wave VINP OPAx192-Q1 Gain Network REF3240 Voltage Divider OPA350 VCM Generation Circuit Counter n Shmidtt Trigger Delay Digital Counter For Multiplexer 5 Fast logic transition Copyright © 2017, Texas Instruments Incorporated Figure 66. OPAx192-Q1 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for HighVoltage Inputs With Lowest Distortion Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 31 ADVANCE INFORMATION 9.2.1 16-Bit Precision Multiplexed Data-Acquisition System OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com Typical Applications (continued) 9.2.1.1 Design Requirements The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input. The design requirements for this block design are: • System Supply Voltage: ±15 V • ADC Supply Voltage: 3.3 V • ADC Sampling Rate: 400 kSPS • ADC Reference Voltage (REFP): 4.096 V • System Input Signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency (fIN) of 10 kHz are applied to each differential input of the mux. 9.2.1.2 Detailed Design Procedure This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next step is to design a digital interface to switch the mux input channels with minimum delay. The final design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage with low offset, drift, and noise contributions. 9.2.1.3 Application Curve 2.0 Integral Nonlinearity Error (LSB) ADVANCE INFORMATION The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 66. The circuit is a multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit resolution and lowest distortion system. The diagram includes the most important specifications for each individual analog block. 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –20 –15 –10 –5 0 5 10 15 20 ADC Differential Input (V) Figure 67. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High Voltage Inputs with Lowest Distortion. 32 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 9.2.2 Slew Rate Limit for Input Protection In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages. By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high output current and slew rate of the OPAx192-Q1 make the device an optimal amplifier to achieve slew rate control for both dual- and single-supply systems.Figure 68 shows the OPAx192-Q1 in a slew-rate limit design. Op Amp Gain Stage Slew Rate Limiter C1 470 nF R1 1.69 kΩ VEE VEE R2 1.6 MΩ - OPAx192-Q1 + V+ VOUT OPAx192-Q1 + V+ VCC RL 10 kΩ VCC Copyright © 2017, Texas Instruments Incorporated Figure 68. Slew Rate Limiter Uses One Op Amp For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 33 ADVANCE INFORMATION + VIN OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com 9.2.3 Precision Reference Buffer The OPAx192-Q1 features high output current drive capability and low input offset voltage, making the device an excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the 10-µF ceramic capacitor shown in Figure 69, RISO, a 37.4-Ω isolation resistor, provides separation of two feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output (VOUT). Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz and still provides a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability components: RF, RFx , CF , and RISO. RF 1 kŸ RFx 10 kŸ CF 39 nF ADVANCE INFORMATION RISO 37.4 Ÿ VOUT OPAx192-Q1 V+ CL 10 µF VREF 2.5 V VCC Copyright © 2017, Texas Instruments Incorporated Figure 69. Precision Reference Buffer 34 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 10 Power-Supply Recommendations The OPAx192-Q1 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in Typical Characteristics. CAUTION Supply voltages larger than 40 V can permanently damage the device; see Absolute Maximum Ratings. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout. 11 Layout For best operational performance of the device, use good PCB layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. . • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. • Place the external components as close to the device as possible. As illustrated in Figure 71, keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. • Cleaning the PCB following board assembly is recommended for best performance. • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 35 ADVANCE INFORMATION 11.1 Layout Guidelines OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com 11.2 Layout Example + VIN VOUT RG RF Figure 70. Schematic Representation Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF N/C N/C GND ±IN V+ VIN +IN OUTPUT V± N/C Use a low-ESR, ceramic bypass capacitor RG ADVANCE INFORMATION GND VS± GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitor Copyright © 2017, Texas Instruments Incorporated Figure 71. Operational Amplifier Board Layout for Noninverting Configuration 36 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 OPA192-Q1, OPA2192-Q1, OPA4192-Q1 www.ti.com SBOS850 – MAY 2017 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.1.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 12.1.1.2 TI Precision Designs The OPA192 is featured in several Texas Instruments (TI) Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. 12.2 Related Links Table 4 below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA192-Q1 Click here Click here Click here Click here Click here OPA2192-Q1 Click here Click here Click here Click here Click here OPA4192-Q1 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 37 ADVANCE INFORMATION Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. OPA192-Q1, OPA2192-Q1, OPA4192-Q1 SBOS850 – MAY 2017 www.ti.com 12.5 Trademarks (continued) e-trim, E2E are trademarks of Texas Instruments. TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. TINA, DesignSoft are trademarks of DesignSoft, Inc. e-trim, are trademarks of ~ Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. ADVANCE INFORMATION 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 38 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA192-Q1 OPA2192-Q1 OPA4192-Q1 PACKAGE OPTION ADDENDUM www.ti.com 23-May-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA192QDGKRQ1 PREVIEW VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 125 OPA2192QDGKRQ1 PREVIEW VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated