CPC7583 Line Card Access Switch Features • Small 28 pin surface mount SOIC package • Monolithic IC reliability • Low matched RDSON • Eliminates the need for zero cross switching • Flexible switch timing to transition from ringing mode to idle/talk mode • Clean, bounce free switching • Tertiary protection consisting of integrated current limiting, thermal shutdown and SLIC protection • 5V operation with power consumption <10mW • Intelligent battery monitor • Latched logic level inputs, no drive circuitry • Pin to pin compatible to the Lucent 7583 family Description The CPC7583 is a monolithic solid state switch in a 28 pin surface mount SOIC package. It provides the necessary functions to replace three 2-Form-C electromechanical relays on analog line cards found in Central Office, Access and PBX equipment. The device contains solid state switches for tip and ring line break, ring injection/ring return, line test access, test in access and ringing generator testing. The CPC7583 requires only a +5V supply and offers “break-before-make” or “make-before-break” switch operation using simple logic level input control. The CPC7583 has 4 versions. The CPC7583BA and the CPC7583BC contain the integrated protection SCR while the CPC7583BC and the CPC7583BD contain an extra logic state which is detailed in later sections. Ordering Information Applications • Central office (CO) • Digital Loop Carrier (DLC) • PBX Systems • Digitally Added Main Line (DAML) • Hybrid Fiber Coax (HFC) • Fiber in the Loop (FITL) • Pair Gain System • Channel Banks Part # CPC7583BA CPC7583BB CPC7583BC Description 10 Pole with protection SCR 10 Pole without protection SCR 10 Pole extra logic state with protection SCR CPC7583BD 10 Pole extra logic state without protection SCR CPC7583BATR Tape and Reel Version CPC7583BBTR Tape and Reel Version CPC7583BCTR Tape and Reel Version CPC7583BDTR Tape and Reel Version Block Diagram TTESTout (10) TTESTin(5) TRING(8) VBAT Reference (28) Ringing Test Return SW7 TIP TLINE (7) R1 SW5 Test Out SW3 Ringing Return SW9 Test In Secondary Protection Ring R2 TBAT (6) SW1 Break SCR and TRIP Circuit RLINE (22) Break SW2 SW6 Test Out SW4 Ringing Access RBAT (23) SW10 Test In SW8 Ringing Test RTESTout(19) SLIC RRING(20) CPC7583BA RTESTin (24) Ring Generator Battery DS-CPC7583-RE www.clare.com 1 CPC7583 Parameter Operating Temperature Range Storage Temperature Range Relative Humidity Range Pin Soldering Temperature (t=10 s max) +5V Power Supply Battery Supply Logic Input Voltage Logic Input to Switch Output Isolation Switch Isolation (SW1, SW2, SW3, Min -40 -40 5 - Max +110 +150 95 +260 Units ˚C ˚C % ˚C - 7 -85 7 330 330 V V V V V - 480 235 V V Absolute Maximum Ratings are stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for extended period may degrade the device and effect its reliability. SW5, SW6, SW7, SW9,SW10) Switch Isolation (SW4) Switch Isolation (SW8) Electrical Characteristics TA = -40oC to +85oC (unless otherwise specified) Minimum and maximum values are production testing requirements. Typical values are characteristic of the device and are the result of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements. Power Supply Specifications Supply VDD VBAT1 Min +4.5 -19 Typ +5.0 - Max +5.5 -72 Unit V V ESD Rating (HBM Model) 1000 1 VBAT is used only as a reference for internal protection circuitry. If VBAT rises above -10V, the device will enter an all off state and will remain in the all off state until the battery voltage drops below -15V. Table 1. Break Switch, SW1 and SW2 PARAMETERS CONDITIONS Off-state Leakage Current: +25oC Vsw (differential)= -320V to Gnd Vsw (differential)= -60V to +260V +85oC Vsw (differential)= -330V to Gnd Vsw (differential)= -60V to +270V -40oC Vsw (differential)= -310V to Gnd Vsw (differential)= -60V to +250V RDSON (SW1,SW2): +25oC TLINE= +/-10 mA, +/-40mA, TBAT= -2V +85oC TLINE= +/-10 mA, +/-40mA, TBAT= -2V -40oC TLINE= +/-10 mA, +/-40mA, TBAT= -2V RDSON Match Per ON-resistance Test Condition of SW1, SW2 DC Current Limit: +25oC Vsw (on) = +/- 10V +85oC Vsw (on) = +/- 10V -40oC Vsw (on) = +/- 10V Dynamic Current Limit: Break switches in ON state, ringing (t=<0.5µs) access switches OFF, apply +/- 1000V at 10/1000µs pulse, appropriate secondary protection in place. Logic Input to Switch Output Isolation: +25oC Vsw (TLINE, RLINE) = +/-320V Logic Inputs = Gnd +85oC Vsw (TLINE, RLINE) = +/-330V Logic Inputs = Gnd -40oC Vsw (TLINE, RLINE) = +/-310V Logic Inputs = Gnd dv/dt Sensitivity1 1 2 SYMBOL MIN TYP MAX UNITS Isw - 0.1 1 µA Isw - 0.3 1 µA Isw - 0.1 1 µA ∆V ∆V ∆V Magnitude RON SW1-RONSW2 - 14.5 20.5 10.5 0.15 28 0.8 Ω Ω Ω Ω Isw Isw Isw Isw 80 - 225 150 400 2.5 425 - mA mA mA A Isw - 0.1 1 µA Isw - 0.3 1 µA Isw - 0.1 1 µA - - 200 - V/µs Applied voltage is 100 Vp-p square wave at 100Hz. www.clare.com Rev. E CPC7583 Table 2. Ring Return Switch, SW3 PARAMETERS Off-state Leakage Current +25oC +85oC -40oC DC Current Limit +25oC +85oC -40oC Dynamic Current Limit: (t=<0.5µs) CONDITIONS Vsw (differential)= -320V to Gnd Vsw (differential)= -60V to +260V Vsw (differential)= -330V to Gnd Vsw (differential)= -60V to +270V Vsw (differential)= -310V to Gnd Vsw (differential)= -60V to +250V Vsw (on) = +/- 10V Vsw (on) = +/- 10V Vsw (on) = +/- 10V Break switches in ON state, Ringing access switches OFF, Apply +/- 1000V at 10/1000µs pulse, Appropriate secondary protection in place. RDSON +25˚C Isw (on) = +/-0mA, +/-10mA +85˚C Isw (on) = +/-0mA, +/-10mA -40˚C Isw (on) = +/-0mA, +/-10mA Logic Input to Switch Output Isolation: +25oC Vsw (TRING, TLINE) = +/-320V Logic Inputs = Gnd +85oC Vsw (TRING, TLINE) = +/-330V Logic Inputs = Gnd -40oC Vsw (TRING, TLINE) = +/-310V Logic Inputs = Gnd SYMBOL MIN TYP MAX UNITS Isw - 0.1 1 µA Isw - 0.3 1 µA Isw - 0.1 1 µA Isw Isw Isw Isw - 120 80 210 2.5 - mA mA mA A ∆V ∆V ∆V - 60 85 45 100 - Ω Ω Ω Isw - 0.1 1 µA Isw - 0.3 1 µA Isw - 0.1 1 µA SYMBOL MIN TYP MAX UNITS Isw - .05 1 µA Isw - 0.1 1 µA Isw - .05 1 µA IR - 1.5 0.1 3 0.25 V mA ∆V - 450 8.5 2 12 A µA Ω Isw - .05 1 µA Isw - 0.1 1 µA Isw - .05 1 µA Table 3. Ringing Access Switch, SW4 PARAMETERS Off-state Leakage Current +25oC CONDITIONS Vsw (differential)= -255V to +210V Vswitch (differential)= +255V to -210V +85oC Vsw (differential)= -270V to +210V Vsw (differential)= +270V to -210V -40oC Vsw (differential)= -245V to +210V Vsw (differential)= +245V to -210V ON Voltage Isw (on) = +/- 1mA Ring Generator Current Vcc = 5V, INTESTin = 0 During Ring INTESTout = 0 Surge Current Release Current ON-resistance Isw (on) = +/-70mA, +/-80mA Logic Input to Switch Output Isolation: +25oC Vsw (RRING, RLINE) = +/-320V Logic Inputs = Gnd +85oC Vsw (RRING, RLINE) = +/-330V Logic Inputs = Gnd -40oC Vsw (RRING, RLINE) = +/-310V Logic Inputs = Gnd Rev. E www.clare.com 3 CPC7583 Table 4. Loop Access Switches, SW5 and SW6 PARAMETERS CONDITIONS Off-state Leakage Current: +25oC Vsw (differential) = -320V to +Gnd Vsw (differential) = -60V to +260V +85oC Vsw (differential) = -330V to Gnd Vsw (differential) = -60V to +270V -40oC Vsw (differential) = -310V to +Gnd Vsw (differential) = -60V to +250V SYMBOL MIN TYP MAX UNITS Isw - 0.1 1 µA Isw - 0.3 1 µA Isw - 0.1 1 µA RDSON: +25oC +85oC -40oC Isw (on) = +/-5mA, +/-10mA Isw (on) = +/-5mA, +/-10mA Isw (on) = +/-5mA, +/-10mA ∆V ∆V ∆V - 35 50 26 70 - Ω Ω Ω DC Current Limit: +25oC +85oC -40oC Vsw (on) = +/-10V Vsw (on) = +/-10V Vsw (on) = +/-10V Isw Isw Isw 80 - 140 100 210 250 mA mA mA Isw - 2.5 - A Isw - 0.1 1 µA Isw - 0.3 1 µA Isw - 0.1 1 µA SYMBOL MIN TYP MAX UNITS Vsw (differential)= -320V to Gnd Vsw (differential)= -60V to +260V Isw - 0.1 1 µA +85oC Vsw (differential)= -330V to Gnd Vsw (differential)= -60V to +270V Isw - 0.3 1 µA -40oC Vsw (differential)= -310 to Gnd Vsw (differential)= -60V to +250V Isw - 0.1 1 µA RDSON +25˚C +85˚C -40˚C Isw (on) = +/-0mA, +/-10mA Isw (on) = +/-0mA, +/-10mA Isw (on) = +/-0mA, +/-10mA ∆V ∆V ∆V - 60 85 45 100 - Ω Ω Ω DC Current Limit +25oC +85oC -40oC Vsw (on) = +/- 10V Vsw (on) = +/- 10V Vsw (on) = +/- 10V Isw Isw Isw - 120 80 210 - mA mA mA Isw - 0.1 1 µA Isw - 0.3 1 µA Isw - 0.1 1 µA Dynamic Current LImit (t=<0.5µs) Break switches in ON state; ringing access switches OFF; apply +/-1000V at 10/1000µs pulse; appropriate secondary protection in place. Logic Input to Switch Output Isolation: +25oC Vsw (TTESTout, TLINE, RTESTout, RLINE) = +/-320V Logic Inputs = Gnd o +85 C Vsw (TTESTout, TLINE, RTESTout, RLINE) = +/-330V Logic Inputs = Gnd -40oC Vsw (TTESTout, TLINE, RTESTout, RLINE) = +/-310V Logic Inputs = Gnd Table 5. Ringing Test Return Switch SW7 PARAMETERS Off-state Leakage Current: +25oC CONDITIONS Logic Input to Switch Output Isolation: +25oC Vsw (TRING, TTESTin) = +/-320V Logic Inputs = Gnd o +85 C Vsw (TRING, TTESTin) = +/-330V Logic Inputs = Gnd o -40 C Vsw (TRING, TTESTin) = +/-310V Logic Inputs = Gnd 4 www.clare.com Rev. E CPC7583 Table 6. Ringing Test Switch SW8 PARAMETERS CONDITIONS SYMBOL MIN TYP MAX UNITS Isw - .05 1 µA Isw - 0.1 1 µA Isw - .05 1 µA ∆V - - 6 0.75 450 20 1.5 - Ω V µA Isw - .05 1 µA Isw - 0.1 1 µA Isw - .05 1 µA Off-state Leakage Current: +25oC Vsw (differential)= -60V to +175V Vsw (differential)= +60V to -175V +85oC Vsw (differential)= -60V to +175V Vsw (differential)= +60V to -175V -40oC Vsw (differential)= -60V to +175V Vsw (differential)= +60V to -175V ON-resistance Isw (on) = +/-70 mA, +/-80mA ON- voltage Isw (on) = +/-1mA Release Current Logic Input to Switch Output Isolation: +25oC Vsw (RRING, RTESTin) = +/-320V Logic Inputs = Gnd +85oC Vsw (RRING, RTESTin) = +/-330V Logic Inputs = Gnd -40oC Vsw (RRING, RTESTin) = +/-310V Logic Inputs = Gnd * Choice of secondary protector and series current-limit resistor should ensure these ratings are not exceeded. Table 7. Test in Switches, SW9 and SW10 PARAMETERS CONDITIONS SYMBOL MIN TYP MAX UNITS Isw - 0.1 1 µA Isw - 0.3 1 µA Isw - 0.1 1 µA Isw(on) = +/-5 mA, +/-10mA ∆V - 35 - Ω Isw(on) = +/-5 mA, +/-10mA ∆V - 50 70 Ω Isw(on) = +/-5 mA, +/-10mA ∆V - 26 - Ω Vsw (On) = +/-10V Isw - 160 - mA Vsw (On) = +/-10V Isw 80 110 - mA Vsw (On) = +/-10V Isw - 210 250 mA Isw - 0.1 1 µA Isw - 0.3 1 µA Isw - 0.1 1 µA Off-state Leakage Current: +25oC Vsw (differential)= -320V to Gnd Vsw (differential)= -60V to +260V o +85 C Vsw (differential)= -330V to Gnd Vsw (differential)= -60V to +270V o -40 C Vsw (differential)= -310V to Gnd Vsw (differential)= -60V to +250V RDSON: +25oC +85oC -40oC DC Current Limit: +25oC +85oC -40oC Logic Input to Switch Output Isolation: +25oC Vsw (TTESTin, RTESTin) = +/-320V Logic Inputs = Gnd +85oC Vsw (TTESTin, RTESTin) = +/-330V Logic Inputs = Gnd o -40 C Vsw (TTESTin, RTESTin) = +/-310V Logic Inputs = Gnd Rev. E www.clare.com 5 CPC7583 Table 8. Additional Electrical Characteristics PARAMETERS Digital Input Characteristics Input Low Voltage Input High Voltage Input Leakage Current (High) CONDITIONS VDD = 5.5V, VBAT = -75V, Vlog = 5V VDD = 5.5V, VBAT = -75V, Vlog = 0V Input Leakage Current (Low) Power Requirements Power Dissipation VDD = 5V, VBAT = -48V, Idle/Talk State or All Off State Ringing State or Test State VDD = 5V, Idle/Talk State or All Off State Ringing State or Test State VBAT = -48V, Idle/Talk State or All Off State Ringing State or Test State VDD Current VBAT Current Temperature Shutdown Requirements1 Shutdown Activation Temperature Shutdown Circuit Hysteresis 1 SYMBOL MIN TYP MAX UNITS Ilog 3.5 - 0.1 1.5 1 V V µA Ilog - 0.1 1 µA IDD, IBAT IDD - 5.0 6.0 7.5 10 mW mW IDD IDD - 1.0 1.2 1.5 1.9 mA mA IBAT IBAT - 4 4 10 10 µA µA - 110 10 125 - 150 25 oC oC - Temperature shutdown flag (TSD) will be high during normal operation and low during temperature shutdown state. Table 9. Make-Before-Break Operation (Ringing to Idle/Talk Transition) Ring Testin 5V 0V 0V 0V 0V 0V Float Float 0V 0V 0V Float 6 Testout TSD Break Switches 1&2 State Timing Ringing Make-before-break Open SW4 waiting for next zero current Closed crossing to turn off. Maximum time is half of ringing. In this transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC Zero cross current has occurred Closed Idle / Talk www.clare.com Ring Return Switch 3 Ring Access Switch 4 All Other Test Switches Closed Open Closed Closed Open Open Open Open Open Rev. E CPC7583 Table 10. Break-Before-Make Operation (Ringing to Idle/Talk Transition) Ring 5V 5V Testin 0V 0V Testout TSD 0V Float 5V Float State Ringing All Off 5V 0V 5V Float All Off 0V 0V 0V Float Idle/Talk Ring Return Switch 3 Closed Open Ring Access Switch 4 Closed Closed Open Open Break Switches 1&2 Open Open Timing Hold this state for </= 25ms. SW4 waiting for zero current to turn off. Zero current has occurred. SW4 has opened. Release Break Switches Open Closed Open Open All Other Access Switches Open Open Open Open Alternate “Break-Before-Make” Operation Note that the break-before-make operation can also be achieved using TSD as an input. In lines 2 & 3 of Table 10, instead of using the logic input pins to force the “all off” state, force TSD to ground. This will override the logic inputs and also force the all off state. Hold this state for 25 ms. During this 25 ms all off state, toggle the inputs from the 10 (ringing state) to 00 (idle/talk state). After 25 ms, release TSD to return switch control to the input pins which will set the idle talk state. When using the CPC7583 in this mode, forcing TSD to ground will override the INPUT pins and force an all off state. Setting TSD to +5V will allow switch control via the logic INPUT pins. However, setting TSD to +5V will also disable the thermal shutdown mechanism. This is not recommended. Therefore, to allow switch control via the logic INPUT pins, allow TSD to float. Thus when using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all off state) and float (allows switch control via logic input pins and thermal shutdown mechanism is active). This may require use of an open collector buffer. Table 11. Electrical Specifications, Protection Circuitry PARAMETER Parameters Related to Diodes (in Diode Bridge) Voltage Drop @ Continuous Current (50/60 Hz) Voltage Drop @ Surge Current Parameters Related to Protection SCR1 Surge Current Trigger Current (25˚C) Hold Current (25˚C) Trigger Current (85˚C) Hold Current (85˚C) Gate Trigger Voltage Reverse Leakage Current ON State Voltage1 CONDITIONS SYMBOL MIN TYP MAX UNITS Apply +/-dc current limit of break switches Apply +/-dynamic current limit of break swithces Forward Voltage Forward Voltage - 2.8 3.5 V - 5 - V - ITRIG IHOLD ITRIG IHOLD Von - 60 VBAT - 4 - 60 110 35 70 -3 -5 * - A mA mA mA mA V µA V V Trigger Current VBAT 0.5A t = 0.5 ms 2.0A t = 0.5 ms VBAT - 2 1.0 - 1 Only for the CPC7583BA and CPC7583BC. * Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. Rev. E www.clare.com 7 CPC7583 Table 12. Truth Table for the CPC7583BA and CPC7583BB INring 0V 0V 0V 5V 5V 0V 5V 5V Don’t Care 1 2 3 4 5 6 7 8 9 INtestin INtestout TSD 0V 0V 5V 0V 5V 5V 0V 5V Don’t Care 0V 5V 0V 0V 0V 5V 5V 5V Don’t Care 5V/Float1 5V/Float1 5V/Float1 5V/Float1 5V/Float1 5V/Float1 5V/Float1 5V/Float1 0V2 TESTin Switches Off Off On Off Off On Off Off Off Break Switches On Off Off Off Off Off Off Off Off RingTest Switches Off Off Off Off On Off Off Off Off Ring Switches Off Off Off On Off Off Off Off Off TESTout Switches Off3 On4 Off5 Off6 Off7 On8 Off9 Off9 Off9 If TSD = 5V, the thermal shutdown mechanism is disabled. If TSD if floating, the thermal shutdown mechanism is active. Forcing TSD to ground overrides the logic input pins and forces an all off state. Idle/Talk State. TESTout state. TESTin state. Power Ringing State. Ringing generator test state. Simultaneous TESTout and TESTin state. All OFF State A parallel in/parallel out data latch is integrated into the CPC7583. Operation of the data latch is controlled by the logic level input pin LATCH. The data input to the latch is the INPUT pin of the CPC7583 and the output of the data latch is an internal node used for state control. When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through the data latch to state control. Any changes in INPUT will be reflected in the state of the switches. When the LATCH control pin is at logic 1, the data latch is active; the CPC7583 will no longer react to changes at the INPUT control pin. The state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high. Note that the Tsd input is not tied to the data latch. Tsd is not affected by the LATCH input. Tsd input will override state control via INPUT and LATCH. 8 www.clare.com Rev. E CPC7583 Table 13. Truth Table for the CPC7583BC and CPC7583BD INring 0V 0V 0V 5V 5V 0V 5V 5V Don’t Care INtestin INtestout TSD 0V 0V 5V 0V 5V 5V 0V 5V Don’t Care 0V 5V 0V 0V 0V 5V 5V 5V Don’t Care 5V/Float1 5V/Float1 5V/Float1 5V/Float1 5V/Float1 5V/Float1 5V/Float1 5V/Float1 0V2 TESTin Switches Off Off On Off Off On Off Off Off Break Switches On Off Off Off Off Off Off Off Off RingTest Switches Off Off Off Off On Off Off On Off Ring Switches Off Off Off On Off Off Off Off Off TESTout Switches Off3 On4 Off5 Off6 Off7 On8 Off9 On10 Off9 1 If TSD = 5V, the thermal shutdown mechanism is disabled. If TSD if floating, the thermal shutdown mechanism is active. Forcing TSD to ground overrides the logic input pins and forces an all off state. 3 Idle/Talk State. 4 TESTout state. 5 TESTin state. 6 Power Ringing State. 7 Ringing generator test state. 8 Simultaneous TESTout and TESTin state. 9 All OFF State 10 Simultaneous TESTout - Ring Test state. 2 A parallel in/parallel out data latch is integrated into the CPC7583. Operation of the data latch is controlled by the logic level input pin LATCH. The data input to the latch is the INPUT pin of the CPC7583 and the output of the data latch is an internal node used for state control. When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through the data latch to state control. Any changes in INPUT will be reflected in the state of the switches. When the LATCH control pin is at logic 1, the data latch is active; the CPC7583 will no longer react to changes at the INPUT control pin. The state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high. Note that the Tsd input is not tied to the data latch. Tsd is not affected by the LATCH input. Tsd input will override state control via INPUT and LATCH. Rev. E www.clare.com 9 CPC7583 Package Pinout CPC7583 28 VBAT FGND 1 NC SCR and TRIP CKT 2 NC 4 TTESTin 5 25 NC SW10 SW9 TBAT 6 TLINE 7 SW1 SW7 SW2 SW8 SW3 SW4 SW5 SW6 NC 11 VDD 12 22 RLINE 21 NC 20 RRING 9 TTESTout 10 24 R 23 RBAT TRING 8 NC 27 NC 26 NC NC 3 Control Logic TSD 13 DGND 14 SOG 1 Symbol FGND Description Fault ground. 2 NC No Connection. 3 NC No Connection. 4 NC No Connection. 5 TTESTin Test (in) access on TIP. 6 TBAT Connect to TIP on SLIC side. 7 TLINE Connect to TIP on line side. 8 TRING Connect to return ground for ringing generator. 9 NC No connection. 19 RTESTout 10 TTESTout Test (out) access on TIP. 18 LATCH 11 NC No connection. 17 IN TESTin 12 VDD 5V supply 16 INRING 13 TSD Temperature shutdown pin. Can be used as a logic level input or an output. See Tables 9, 10, 12 and13 for more details. As an output, will read 5V when the device is in its operational mod and 0V in the thermal shutdown mode. To disable the thermal shutdown mode mechanism, tie this pin to 5V (not recommended). 14 DGND Digital ground 15 INTESTout Logic level switch input control. 16 INRING Logic level switch input control. 17 INTESTin Logic level switch input control. 18 LATCH Data input control, active-high, transparent low. 19 RTESTout Test (out) access on RING. 20 RRING Connect to ringing generator. 21 NC No connection. 22 RLINE Connect to RING on line side. 23 RBAT Connect to RING on SLIC side. 24 RTESTin Test (in) access on RING. 25 NC No connection. 26 NC No connection. 27 NC No connection 28 VBAT Battery voltage. Used as a reference for protection circuit. 15 INTESTout * Only the CPC7583BA and CPC7583BC contain the protection SCR 10 www.clare.com Rev. E CPC7583 Functional Description Introduction The CPC7583 has eight distinct states. Please consult the truth tables in table 12 and 13 for version differences. • Idle/talk state (line break switches SW1, and SW2 closed). All other switches open. • Ringing state, (ringing switches SW3, SW4 closed). All other switches open. • Loop access (loop access switches SW5, SW6 closed). All other switches open. The CPC7583 operates from a +5V supply only. This gives the device extremely low idle and active power dissipation and allows use with virtually any range of battery voltage. A battery voltage is also used by the CP7583 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7583 will enter an “all off” state. Switch Timing • Ring generator test state (SW7, SW8 closed). All other switches open. • SLIC test state Testin switches closed (SW9, SW10). • Simultaneous Loop and SLIC access state. (SW9, SW10, SW5 and SW6 closed). All other switches open. • Simultaneous test out and ring test (SW5, SW6, SW7, SW8 closed). All other switches open on the “BC” abd “BD” version. • All Off state (all switches open). The CPC7583 offers break-before-make and make-beforebreak switching with simple logic level input control. Solid state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, thus eliminating the need for external “zero cross” switching circuitry. State control is via logic level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low RDSON and excellent matching characteristics. The ringing access switch SW4 has a breakdown voltage rating of >480V which is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition. (i.e., passing the transient on to the ring generator) Integrated into the CPC7583 is a diode bridge clamping circuit, current limiting and thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and steered to ground via diodes. Power cross transients are also reduced by the current limiting and thermal shutdown circuits. To protect the CPC7583 from an overvoltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the max breakdown voltage of the switches. To minimize the stress on the solid- Rev. E state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7583 will meet all relevant ITU, LSSGR, FCC or UL protection requirements. The CPC7583 provides, when switching from the ringing state to the idle/talk state, the ability to control the timing when the ringing access switches SW3 and SW4 are released relative to the state of the line break switches SW1 and SW2 using simple logic level input. This is referred to as a “make before break” or “break before make” operation. When the line break switch contacts (SW1, SW2) are closed (or made) before the ringing access switch contact (SW3, SW4) is opened (or broken), this is referred to a ‘make-before-break’ operation. Break-before-make operation occurs when the ringing access contact (SW3, SW4) is opened (broken) before the line break switch contacts (SW1, SW2) are closed (made). With the CPC7583 the “make before break” and “break before make” operations can easily be selected by applying logic level inputs to INTESTout, INRING and INTESTin of the device. The logic sequences for either mode of operation are given in Tables 9 and 10. Logic states and explanations are given in Tables 12 and 13. Break-before make operation can also be achieved using pin 13 (TSD) as an input. In table 10 lines 2 and 3 it is possible to induce the switches to “all off” by grounding pin 13 (TSD) instead of apply logic input to the pins. This has the effect of overriding the logic inputs and forcing the device to the “all off” state. Hold this input state for 25ms. During this hold period, toggle the inputs from the ringing state to the idle/talk state. After the 25ms release pin 13 (TSD) to return the switch control to the input INTESTout, INRING, INTESTin and reset the device to the idle/talk state. Setting pin 13 (TSD) to +5V will allow switch control using the logic inputs. This setting, however, will also disable the thermal shutdown circuit and is therefore not recommended. When using logic controls via the input pins (INTESTout, INRING and INTESTin), pin 13 (TSD) should be allowed to float. As a result the two recommended states when using pin 13 www.clare.com 11 CPC7583 (TSD) as a control are 0 which forces the device to the “all off state” or float which allow logic inputs to remain active. This may require use of an open collector buffer. Ring Access Switch Zero Cross Current Turn Off After the application of a logic input to turn SW4 off, the ring access switch is designed to delay the change in state until the next zero crossing. Once on, the switch requires a zero current cross to turn off and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter what logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing access switches. The attributes of ringing access switch may make it possible to eliminate the need for a zero cross switching scheme. A minimum impedance of 300Ω in series with the ring generator is recommended. Power Supplies Both a +5V supply and battery voltage are connected to the CPC7583. CPC7583 switch state control is powered exclusively by the +5V supply. As a result, the CPC7583 exhibits extremely low power dissipation during both active and idle states. Battery Voltage Monitor The CPC7583 also uses the voltage reference to monitor battery voltage. If battery voltage is lost, the CPC7583 will immediately enter the “all off” state and remain in this state until the battery voltage is restored. The device will also enter the “all off” state if the battery voltage rises above – 10V and will remain there until the battery voltage drops below –15V. This battery monitor feature draws a small current from the battery (<1µA) and will add slightly to the device’s overall power dissipation. Protection Diode Bridge/SCR The CPC7583 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge and to ground. During a negative transient of two or four volts more negative than the battery, the SCR conducts and faults are shunted to ground via the SCR and diode bridge. Also, in order for the SCR to crowbar or foldback, the on voltage (see Table 11) of the SCR must be less negative than the battery reference voltage. If the battery voltage is 12 less negative the SCR on voltage, the SCR will not crowbar, however it will conduct fault currents to ground. For power induction or power cross fault conditions, the positive cycle of the transient is clamped to the diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the battery reference voltage by two to four volts, steering the current to ground. Current Limiting function If a lightning strike transient occurs when the device in the talk/idle state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10x1000 pulse (LSSGR lightning) is applied to the line though a properly clamped external protector, the current seen at pins 6 (TBAT) and pin 23 (RBAT) will be a pulse with a typical magnitude and duration of 2.5A and < 0.5ms. If a power cross fault occurs with device in the talk/idle state, the current is passed though the break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80mA and 400mA and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current at pin 6 (TBAT) and pin 23 (RBAT) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will default to the “all off” state. Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110ϒC placing the device in the “all off” state regardless of logic input. During this thermal shutdown mode, pin 13 (TSD) will read 0V. Normal output of TSD is +V . DD If presented with a short duration transient such as a lightning event, the thermal shutdown feature will not typically activate. But in an extended power cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to an “all off” state. At this point the current measured at pin 6 (TBAT) and pin 23 (RBAT) will drop to zero. Once the device enters thermal shutdown it will remain in the “all off” state until the temperature of the device drops below the activation level of the thermal shutdown circuit. This will return the device to the state prior to thermal shutdown. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle www.clare.com Rev. E CPC7583 of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The thermal shutdown mechanism of the CPC7583 can be disable by applying +VDD to pin 13 (TSD) External Protection Elements The CPC7583 requires only one overvoltage secondary protector on the loop side of the device. The integrated protection feature described above negates the need for protection on the line side. The purpose of the secondary protector is to limit voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7583. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare’s app note, AN-100, “Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces” for equations related to the specifications of external secondary protectors, fused resistors, and PTCs. Data Latch The CPC7583 has an integrated data latch. The latch operation is controlled by logic level input pin 18 (LATCH). The data input of the latch is pin 15 (INTESTout), pin 16 (INRING) and pin 17 (INTESTin) of the device while the output of the data latch is an internal node used for state control. When LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When LATCH control pin is at logic 1, the data latch is now active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. In addition, TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and TSD input will override state control via pin 15 (INTESTout), pin 16 (INRING) and pin 17 (INTESTin) and the LATCH. Rev. E www.clare.com 13 CPC7583 Mechanical Dimensions 28 Pin SOIC 18.034+/-.127 (.710+/-.005) 10.312+/-.051 (.406+/-.003) .330 x 45 o MAX (.013 x 45 o MAX) 7.468+/-.127 (.294+/-.005) 3o- 7o .813+/-.102 (.032+/-.004) .250 Typ (.010 Typ) 2.54+/-.127 (.100+/-.005) 1.27 Typ (.050 Typ) Dimensions mm (Inches) 14 www.clare.com Rev. E CPC7583 Notes: Rev. E www.clare.com 15 Worldwide Sales Offices CLARE LOCATIONS EUROPE ASIA PACIFIC Clare Headquarters 78 Cherry Hill Drive Beverly, MA 01915 Tel: 1-978-524-6700 Fax: 1-978-524-4900 Toll Free: 1-800-27-CLARE European Headquarters CP Clare nv Bampslaan 17 B-3500 Hasselt (Belgium) Tel: 32-11-300868 Fax: 32-11-300890 Clare Micronix Division 145 Columbia Aliso Viejo, CA 92656-1490 Tel: 1-949-831-4622 Fax: 1-949-831-4628 France Clare France Sales Lead Rep 99 route de Versailles 91160 Champlan France Tel: 33 1 69 79 93 50 Fax: 33 1 69 79 93 59 Asian Headquarters Clare Room N1016, Chia-Hsin, Bldg II, 10F, No. 96, Sec. 2 Chung Shan North Road Taipei, Taiwan R.O.C. Tel: 886-2-2523-6368 Fax: 886-2-2523-6369 Clare Switch Division 4315 N. Earth city Expressway Earth City, MO 63045 Tel: 1-314-770-1832 Fax: 1-314-770-1812 SALES OFFICES AMERICAS Americas Headquarters Clare 78 Cherry Hill Drive Beverly, MA 01915 Tel: 1-978-524-6700 Fax: 1-978-524-4900 Toll Free: 1-800-27-CLARE Eastern Region Clare P.O. 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Colombo 10/A I-20066 Melzo (Milano) Tel: 39-02-95737160 Fax: 39-02-95738829 Sweden Clare Sales Comptronic AB Box 167 S-16329 Spånga Tel: 46-862-10370 Fax: 46-862-10371 United Kingdom Clare UK Sales Marco Polo House Cook Way Bindon Road Taunton UK-Somerset TA2 6BG Tel: 44-1-823 352541 Fax: 44-1-823 352797 http://www.clare.com Clare cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in this Clare product. No circuit patent licenses nor indemnity are expressed or implied. Clare reserves the right to change the specification and circuitry, without notice at any time. The products described in this document are not intended for use in medical implantation or other direct life support applications where malfunction may result in direct physical harm, injury or death to a person. Specification: DS-CPC7583-RE © Copyright 2001, Clare, Inc. All rights reserved. Printed in USA. 8/1/01