bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com 1-A, SINGLE-CHIP, LI-ION AND LI-POL CHARGER IC Check for Samples: bq24080, bq24081 FEATURES 1 • 2 • • • • • • • Integrated Power FET and Current Sensor for Up to 1-A Charge Applications From AC Adapter Precharge Conditioning With Safety Timer Charge and Power-Good Status Output Automatic Sleep Mode for Low Power Consumption Integrated Charge-Current Monitor Fixed 7-Hour Fast Charge Safety Timer Ideal for Low-Dropout Charger Designs for Single-Cell Li-Ion or Li-Pol Packs in Space-Limited Portable Applications Small 3-mm × 3-mm SON Package APPLICATIONS • • PDAs, MP3 Players Digital Cameras • • Internet Appliances Smartphones DESCRIPTION The bq24080 and bq24081 are highly integrated and flexible Li-Ion linear charge devices targeted at space-limited charger applications. They offer an integrated power FET and current sensor, high-accuracy current and voltage regulation, charge status, and charge termination, in a single monolithic device. An external resistor sets the magnitude of the charge current. The device charges the battery in three phases: conditioning, constant current, and constant voltage. Charge is terminated based on minimum current. An internal charge timer provides a backup safety for charge termination. The device automatically restarts the charge if the battery voltage falls below an internal threshold. The device automatically enters sleep mode when the ac adapter is removed. AC Adapter VDC GND C1 0.1 mF PACK+ bq24080 1 IN C2 0.1 µF OUT 10 PACK– 2 NC CE 9 3 STAT1 PG 8 4 STAT2 VBSEL 7 5 VSS Battery Pack + System System Interface RSET ISET 6 1.13 kW 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2011, Texas Instruments Incorporated bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TJ CHARGE REGULATION VOLTAGE (V) FUNCTIONS FAST-CHARGE TIMER (HOURS) –40°C to 125°C 4.2 CE and PG 7 –40°C to 125°C 4.2 TE and TS 7 (1) (2) PART NUMBER (1) MARKINGS (2) bq24080DRCR BRO bq24080DRCT bq24081DRCR BRP bq24081DRCT The DRC package is available taped and reeled only in quantities of 3,000 devices per reel. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. DISSIPATION RATINGS (1) PACKAGE RθJA RθJC TA < 40°C POWER RATING DERATING FACTOR ABOVE TA = 40°C DRC (1) 46.87 °C/W 4.95 °C/W 1.5 W 0.021 W/°C This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is connected to the ground plane by a 2- × 3-via matrix. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) bq24080, bq24081 VI Input voltage (2) IN, CE, ISET, OUT, PG, STAT1, STAT2, TE, TS Output sink/source current Output current V STAT1, STAT2, PG 15 mA OUT 1.5 TA Operating free-air temperature range TJ Junction temperature range Tstg Storage temperature (1) (2) UNIT –0.3 to 7 A °C –40 to 125 °C –65 to 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to VSS. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage TJ Operating junction temperature range 2 MAX UNIT 4.5 6.5 V 0 125 °C Copyright © 2006–2011, Texas Instruments Incorporated bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS over 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1.2 2 2 5 UNIT INPUT CURRENT VCC current VCC > VCC(min) ICC(SLP) Sleep current Sum of currents into OUT pin, VCC < V(SLP) ICC(STBY) Standby current CE = High, 0°C ≤ TJ ≤ 85°C IIB(OUT) Input current on OUT pin Charge DONE, VCC > VCC(MIN) ICC(VCC) 150 1 mA μA 5 VOLTAGE REGULATION VO(REG) + V(DO−MAX) ≤ VCC, I(TERM) < IO(OUT) ≤ 1 A VO(REG) Output voltage Voltage regulation accuracy V(DO) Dropout voltage (V(IN) − V(OUT)) 4.2 TA = 25°C V −0.35% 0.35% −1% 1% VO(OUT) = VO(REG), IO(OUT) = 1 A VO(REG) + V(DO)) ≤ VCC 350 500 mV 1000 mA V CURRENT REGULATION IO(OUT) Output current range (1) VI(OUT) > V(LOWV), VI(IN) − VI(OUT) > V(DO), VCC ≥ 4.5 V V(SET) Output current set voltage Voltage on ISET pin, VCC ≥ 4.5 V, VI ≥ 4.5 V, VI(OUT) > V(LOWV), VI − VI(OUT) > V(DO) K(SET) Output current set factor 20 2.463 2.5 2.538 50 mA ≤ IO(OUT) ≤ 1 A 307 322 337 10 mA ≤ IO(OUT) < 50 mA 296 320 346 1 mA ≤ IO(OUT) < 10 mA 246 320 416 PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION Precharge to fast-charge transition threshold Voltage on OUT pin 2.8 3 3.2 V Deglitch time for fast-charge to precharge transition VCC(MIN) ≥ 4.5 V, tFALL = 100 ns, 10-mV overdrive, VI(OUT) decreasing below threshold 250 375 500 ms IO(PRECHG) Precharge range (2) 0 V < VI(OUT) < V(LOWV), t < t(PRECHG) 2 100 mA V(PRECHG) Precharge set voltage Voltage on ISET pin, VO(REG) = 4.2 V, 0 V < VI(OUT) > V(LOWV), t < t(PRECHG) 240 270 mV 100 mA V(LOWV) 255 TERMINATION DETECTION I(TERM) Charge termination detection range (3) VI(OUT) > V(RCH), t < t(TRMDET) 2 V(TERM) Charge termination detection set voltage Voltage on ISET pin, VO(REG) = 4.2 V, VI(OUT) > V(RCH), t < t(TRMDET) 235 250 265 mV tTRMDET Deglitch time for termination detection VCC(MIN) ≥ 4.5 V, tFALL = 100 ns charging current decreasing below 10-mV overdrive 250 375 500 ms (1) (2) (3) See Equation 2 in the Function Description section. See Equation 1 in the Function Description section. See Equation 4 in the Function Description section. Copyright © 2006–2011, Texas Instruments Incorporated 3 bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO(REG) – 0.115 VO(REG) − 0.10 VO(REG) − 0.085 250 375 500 ms 0.25 V BATTERY RECHARGE THRESHOLD V(RCH) Recharge threshold t(DEGL) Deglitch time for recharge detect VCC(MIN) ≥ 4.5 V, tFALL = 100 ns decreasing below or increasing above threshold, 10-mV overdrive V STAT1, STAT2, and PG OUTPUTS VOL Low-level output saturation voltage IO = 5 mA CE and TE INPUTS VIL Low-level input voltage 0 VIH High-level input voltage 1.4 IIL Low-level input current –1 IIH High-level input current 0.4 1 V μA TIMERS t(PRECHG) Precharge time t(CHG) Charge time I(FAULT) Timer fault recovery current 1,584 1,800 2,016 22,176 25,200 28,224 s s μA 200 SLEEP COMPARATOR V(SLP) Sleep-mode entry threshold voltage V(SLPEXIT) Sleep-mode exit threshold voltage 2.3 V ≤ VI(OUT) ≤ VO(REG) Sleep-mode entry deglitch time V(IN) decreasing below threshold, tFALL = 100 ns, 10-mV overdrive VCC ≤ VI(OUT) + 80 mV VCC ≥ VI(OUT) + 190 250 375 500 V ms THERMAL SHUTDOWN THRESHOLDS T(SHTDWN) Thermal trip threshold Thermal hysteresis 165 TJ increasing °C 15 UNDERVOLTAGE LOCKOUT UVLO Undervoltage lockout Decreasing VCC 2.4 Hysteresis 2.5 2.6 27 V mV TEMPERATURE SENSE COMPARATOR (bq24081) V(TS1) High-voltage threshold 2.475 2.5 2.525 V(TS2) Low-voltage threshold 0.485 0.5 0.515 I(TS) TS pin current source 96 102 108 μA t(DEGL) Deglitch time for temperature fault 250 375 500 ms 4 V Copyright © 2006–2011, Texas Instruments Incorporated bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com PIN ASSIGNMENT DRC PACKAGE (TOP VIEW) VSS 5 STAT2 STAT1 GND IN VSS 3 1 5 4 2 STAT2 STAT1 GND IN 3 1 4 bq24080 6 7 ISET GND 8 PG 2 bq24081 9 10 CE OUT 6 7 ISET GND 8 TE 9 10 TS OUT P0051-01 PIN FUNCTIONS PIN NAME CE NO. I/O DESCRIPTION bq24080 bq24081 9 – I Charge enable input (active-low) 2, 7 2, 7 – Ground IN 1 1 I Adapter dc voltage. Connect minimum 0.1-μF capacitor to VSS. ISET 6 6 I Charge current. External resistor to VSS sets precharge and fast-charge current, and also the termination current value. Can be used to monitor the charge current. OUT 10 10 O Charge current output. Connect minimum 0.1-μF capacitor to VSS. PG 8 – O Power-good status output (open-drain) STAT1 3 3 O STAT2 4 4 O TE – 8 I TS – 9 I/O VSS 5 5 – Ground Thermal pad – – – There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The exposed thermal pad must be connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad as the primary ground input for the device. The VSS pin must be connected to ground at all times. GND Charge status outputs (open-drain) Timer-enable input (active-low) Temperature sense; connect to NTC in battery pack. Copyright © 2006–2011, Texas Instruments Incorporated 5 bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM (3) IN OUT ISET V(PRECHG) V(SET) VO(REG) V(RCH) V(LOWV) (3) (3) (3) V(TERM) V(IN) ITS VI(OUT) + V(SLP) (3) V(TS1) V(UVLO) (2) Charge Control, Timers, and Status TS (3) V(TS2) STAT1 CE (1) STAT2 (2) TE (1) PG VSS B0193-01 6 (1) bq24080 only (2) bq24081 only (3) Signal deglitched Copyright © 2006–2011, Texas Instruments Incorporated bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 450 IO(OUT) = 1000 mA 400 Dropout Voltage - mV 350 IO(OUT) = 750 mA 300 250 IO(OUT) = 500 mA 200 150 IO(OUT) = 250 mA 100 50 0 0 50 100 o TJ - Junction Temperature - C 150 Figure 1. Figure 2. VIN Hot-Plug Power-Up Sequence Copyright © 2006–2011, Texas Instruments Incorporated 7 bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 3. Charge Enable Power-Up Sequence (CE = High-to-Low) Figure 4. Battery Hot-Plug During Charging Phase 8 Copyright © 2006–2011, Texas Instruments Incorporated bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) (6) Deglitch timer expires – charge done is declared. Figure 5. Battery Hot-Plug and Removal Power Sequence Copyright © 2006–2011, Texas Instruments Incorporated 9 bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com FUNCTIONAL DESCRIPTION The device supports a precision Li-Ion, Li-Pol charging system suitable for single cells. Figure 6 shows a typical charge profile, and Figure 7 shows an operational flow chart. Preconditioning Phase Current Regulation Phase Voltage Regulation and Charge Termination Phase Regulation Voltage Regulation Current Minimum Charge Voltage PreConditioning and Term Detect Charge Voltage Charge Complete Charge Current Safety Timer M0066-01 Figure 6. Typical Charging Profile 10 Copyright © 2006–2011, Texas Instruments Incorporated bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com POR SLEEP MODE VCC > VI(OUT) checked at all times? No Indicate SLEEP MODE Yes VI(OUT)<V(LOWV) ? Yes Regulate IO(PRECHG) and Indicate ChargeIn-Progress Reset and Start t(PRECHG) Timer No Reset All Timers, Start t(CHG) Timer Regulate Current or Voltage and Indicate ChargeIn-Progress No VI(OUT)<V(LOWV) ? Yes Yes t(CHG) Expired? t(PRECHG) Expired? No No Yes Yes Fault Condition Yes VI(OUT)<V(LOWV) ? Indicate Fault No No Yes Iterm Detection ? VI(OUT) >V(RCH) ? No Yes Enable I(FAULT) Current Turn Off Charge Indicate DONE VI(OUT) >V(RCH) ? No Yes VI(OUT) <V(RCH) ? No Disable I(FAULT) Current Yes F0018-01 Figure 7. Operational Flow Chart Copyright © 2006–2011, Texas Instruments Incorporated 11 bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com Battery Preconditioning During a charge cycle, if the battery voltage is below the V(LOWV) threshold, the device applies a precharge current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. Resistor RSET, connected between the ISET and VSS, determines the precharge rate. The V(PRECHG) and K(SET) parameters are specified in the Electrical Characteristics table. K(SET) x V(PRECHG) IO(PRECHG) = RSET (1) The device activates a safety timer, t(PRECHG), during the conditioning phase. If the V(LOWV) threshold is not reached within the timer period, the device turns off the charger and enunciates FAULT on the STATx pins. See the Timer Fault Recovery section for additional details. Battery Fast-Charge Constant Current The device offers on-chip current regulation with programmable set point. Resistor RSET, connected between the ISET and VSS, determines the charge rate. The V(SET) and K(SET) parameters are specified in the specifications table. K(SET) x V(SET) IO(OUT) = RSET (2) Charge-Current Monitor When the charge function is enabled internal circuits generate a current proportional to the charge current at the ISET pin. This current, when applied to the external charge current programming resistor RISET generates an analog voltage that can be monitored by an external host to calculate the current sourced from the OUT pin. R ISET V(ISET) + I(OUT) K(SET) (3) Battery Fast-Charge Voltage Regulation The voltage regulation feedback is through the OUT pin. This input is tied directly to the positive side of the battery pack. The device monitors the battery-pack voltage between the OUT and VSS pins. When the battery voltage rises to the VO(REG) threshold, the voltage regulation phase begins and the charging current begins to taper down. As a safety backup, the device also monitors the charge time in the charge mode. If charge is not terminated within this time period, t(CHG), the charger is turned off and FAULT is set on the STATx pins. See the Timer Fault and Recovery section for additional details. Charge Termination Detection and Recharge The device monitors the charging current during the voltage regulation phase. Once the termination threshold, I(TERM), is detected, charge is terminated. The V(TERM) and K(SET) parameters are specified in the specifications table. K x V(TERM) IO(TERM) = (SET) RSET (4) After charge termination, the device restarts the charge once the voltage on the OUT pin falls below the V(RCH) threshold. This feature keeps the battery at full capacity at all times. The device monitors the charging current during the voltage regulation phase. Once the termination threshold, I(TERM), is detected, the charge is terminated immediately. Resistor RSET, connected between the ISET and VSS, determines the current level at the termination threshold. 12 Copyright © 2006–2011, Texas Instruments Incorporated bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com Sleep Mode The device enters the low-power sleep mode if the input power (IN) is removed from the circuit. This feature prevents draining the battery during the absence of input supply. Charge Status Outputs The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the following table. These status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the open-drain transistor is turned off. Table 1. Status Pin Summary CHANGE STATE STAT1 STAT2 Precharge in progress ON ON Fast charge in progress ON OFF Charge done OFF ON OFF OFF Charge suspend (temperature) Timer fault Sleep mode PG Output (bq24080) The open-drain power-good (PG) output pulls low when a valid input voltage is present. This output is turned off (high-impedance) in sleep mode. The PG pin can be used to drive an LED or communicate to the host processor. Charge-Enabled (CE) Input (bq24080) The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the charge and a high-level signal disables the charge and places the device in a low-power mode. A high-to-low transition on this pin also resets all timers and timer fault conditions. Timer Enabled (TE) Input (bq24081) The TE digital input is used to disable or enable the fast-charge timer. A low-level signal on this pin enables the fast-charge timer, and a high-level signal disables this feature. TEMPERATURE QUALIFICATION (bq24081) The bq24081 continuously monitors battery temperature by measuring the voltage between the TS and VSS pins. An internal current source provides the bias for common 10-kΩ negative-temperature-coefficient thermistors (NTC) (see the functional block diagram). The device compares the voltage on the TS pin with the internal V(TS1) and V(TS2) thresholds to determine if charging is allowed. If a temperature outside the V(TS1) and V(TS2) thresholds is detected, the device immediately suspends the charge by turning off the power FET and holding the timer value (i.e., timers are not reset). Charge is resumed when the temperature returns within the normal range. The allowed temperature range with a 103AT-type thermistor is 0°C to 45°C. However, the user may modify these thresholds by adding external resistors (see Figure 8 and Figure 9 Copyright © 2006–2011, Texas Instruments Incorporated 13 bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com bq24081 ITS VHTF PACK+ TS NTC VLTF PACK– B0194-01 Figure 8. Default Temperature Thresholds bq24081 ITS VHTF PACK+ RT1 TS NTC RT2 VLTF PACK– B0195-01 Figure 9. Temperature Thresholds Modified by External Resistors 14 Copyright © 2006–2011, Texas Instruments Incorporated bq24080 bq24081 www.ti.com SLUS698E – MARCH 2006 – REVISED AUGUST 2011 Timer Fault and Recovery As shown in Figure 7, the device provides a recovery method to deal with timer fault conditions. The following summarizes this method: Condition Number 1 OUT pin voltage is above the recharge threshold (V(RCH)), and a timeout fault occurs. Recovery method: the device waits for the OUT pin voltage to fall below the recharge threshold. This could happen as a result of a load on the battery, self-discharge, or battery removal. Once the OUT pin voltage falls below the recharge threshold, the device clears the fault and starts a new charge cycle. A POR, TE, or CE toggle also clears the fault. Condition number 2 OUT pin voltage is below the recharge threshold (V(RCH)), and a timeout fault occurs Recovery method: Under this scenario, the device applies the I(FAULT) current. This small current is used to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge threshold. If the OUT pin voltage goes above the recharge threshold, then the device disables the I(FAULT) current and executes the recovery method described for condition number 1. Once the OUT pin voltage falls below the recharge threshold, the bq24080 clears the fault and starts a new charge cycle. A POR, TE, or CE toggle also clears the fault. Copyright © 2006–2011, Texas Instruments Incorporated 15 bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION bq24080/1 CHARGER DESIGN EXAMPLE Requirements • Supply voltage = 5 V • Fast-charge current of approximately 750 mA • Battery-Temperature sense (bq24081): default setting = –2°C to 44.5°C Calculations Program the charge current for 750 mA: RISET = [V(SET) × K(SET) / I(OUT)] From electrical characteristics table, V(SET) = 2.5 V. From electrical characteristics table, K(SET) = 322. RISET = [2.5 V × 322 / 0.75 A] = 1.073 kΩ Selecting the closest standard value, use a 1.07-kΩ resistor connected between ISET (pin 6) and ground. Battery Temperature Sense (bq24081): Use a Semitec 103AT-4 NTC thermistor connected between TS (pin 9) and ground. RTHERM-cold = [V(TS1) / I(TS) ] = 2.5V / 100 μA = 25 kΩ RTHERM-hot = [V(TS2) / I(TS) ] = 0.5V / 100 μA = 5 kΩ Look up the corresponding temperature value in the manufacturer's resistance-temperature table for the thermistor selected. For a 103AT-4 Semitec thermistor: 5 kΩ = 44.5°C 25 kΩ = 2°C STAT Pins (All Devices) and PG Pin (bq24080): Status pins Monitored by Processor: Select a pullup resistor that can source more than the input bias (leakage) current of both the processor and status pins and still provide a logic high. RPULLUP ≤ [V(cc-pullup) – V(logic hi-min) / (I(µP-monitor) + I(STAT-OpenDrain)) ] = (3.3 V – 1.9 V) / (1 μA + 1 μA) ≤ 700 kΩ; Connect a 100-kΩ pullup between each status pin and the VCC of the processor. Connect each status pin to a μP monitor pin. Status viewed by LED: Select an LED with a current rating less than 10 mA and select a resistor to place in series with the LED to limit the current to the desired current value (brightness). RLED = [(V(IN) – V(LED-on)) / I(LED)] = (5 V – 2 V) / 1.5 mA = 2 kΩ. Place an LED and resistor in series between the input and each status pin. Selecting Input and Output Capacitors In most applications, all that is needed is a high-frequency decoupling capacitor on the input power pin. A 0.1-μF ceramic capacitor, placed in close proximity to the IN pin and GND pad works well. In some applications, it may be necessary to protect against a hot plug input voltage overshoot. This is done in three ways: 1. The best way is to add an input zener, 6.2 V, between the IN pin and VSS. 2. A low-power zener is adequate for the single event transient. Increasing the input capacitance lowers the characteristic impedance which makes the input resistance move effective at damping the overshoot, but risks damaging the input contacts by the high inrush current. 3. Placing a resistor in series with the input dampens the overshoot, but causes excess power dissipation. The device only requires a small capacitor for loop stability. A 0.1-μF ceramic capacitor placed between the OUT and GND pad is typically sufficient. 16 Copyright © 2006–2011, Texas Instruments Incorporated bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com 1.5 kW SOURCE INPUT VDC bq24080 C1 0.1 mF 1 IN OUT C2 0.1 mF 1.5 kW GND 1.5 kW PACK+ 10 2 GND CE 9 3 STAT1 PG 8 4 STAT2 GND 7 5 VSS ISET 6 + PACK– 1.13 kW RSET Charge Current Translator Output Figure 10. Typical Application Circuit Thermal Considerations The bq24080 and bq24081 are packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design guidelines for this package are provided in the application report entitled, QFN/SON PCB Attachment (TI Literature Number SLUA271). The most common measure of package thermal performance is thermal impedance (RθJA) measured (or modeled) from the device junction to the air surrounding the package surface (ambient). The mathematical expression for RθJA is: RqJA = TJ - T A P (5) Where: • TJ = device junction temperature • TA = ambient temperature • P = device power dissipation Factors that can greatly influence the measurement and calculation of RθJA include: • Orientation of the device (horizontal or vertical) • Volume of the ambient air surrounding the device under test and airflow • Whether other surfaces are in close proximity to the device being tested • Use multiple 10–13 mil vias in the PowerPAD™ to copper ground plane. • Avoid cutting the ground plane with a signal trace near the power IC. • The PCB must be sized to have adequate surface area for heat dissipation. • FR4 (figerglass) thickness should be minimized. The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal Power FET. It can be calculated from the following equation: P = (V(IN) - V(OUT)) x IO(OUT) (6) Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. See Figure 6. Copyright © 2006–2011, Texas Instruments Incorporated 17 bq24080 bq24081 SLUS698E – MARCH 2006 – REVISED AUGUST 2011 www.ti.com PCB Layout Considerations It is important to pay special attention to the PCB layout. The following provides some guidelines: • To obtain optimal performance, the decoupling capacitor from VCC to V(IN) and the output filter capacitors from OUT to VSS should be placed as close as possible to the device, with short trace runs to both signal and VSS pins. The VSS pin should have short trace runs to the GND pin. • All low-current VSS connections should be kept separate from the high-current charge or discharge paths from the battery. Use a single-point ground technique incorporating both the small-signal ground path and the power ground path. • The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. • The device is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application report entitled, QFN/SON PCB Attachment (TI Literature Number SLUA271). 18 Copyright © 2006–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) BQ24080DRCR ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BRO BQ24080DRCRG4 ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BRO BQ24080DRCT ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BRO BQ24080DRCTG4 ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BRO BQ24081DRCR ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BRP BQ24081DRCRG4 ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BRP BQ24081DRCT ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BRP BQ24081DRCTG4 ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BRP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 30-Sep-2014 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing BQ24080DRCR VSON DRC 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ24080DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ24081DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ24081DRCT VSON DRC 10 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24080DRCR VSON DRC 10 3000 367.0 367.0 35.0 BQ24080DRCT VSON DRC 10 250 210.0 185.0 35.0 BQ24081DRCR VSON DRC 10 3000 338.0 355.0 50.0 BQ24081DRCT VSON DRC 10 250 338.0 355.0 50.0 Pack Materials-Page 2 www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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