NB4L52 2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip−Flop with Reset Multi−Level Inputs to LVPECL Translator w/ Internal Termination The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50 W termination resistors and will accept PECL, LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3x3 mm 16 pin QFN package. http://onsemi.com MARKING DIAGRAM* 16 1 • • Maximum Input Clock Frequency > 4 GHz Typical 330 ps Typical Propagation Delay 145 ps Typical Rise and Fall Times Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V Internal Input Termination Resistors, 50 W Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL, LVEP, EP, and SG Devices −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices* NB4L 52 ALYWG G QFN−16 MN SUFFIX CASE 485G Features • • • • • • • 1 A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. VTD D Data D Q VTD Q VTCLK CLK Clock CLK Reset VTCLK VTR R R VTR Figure 1. Logic Diagram Table 1. TRUTH TABLE *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. R D CLK Q H x x L L L Z L L H Z H Z = LOW to HIGH Transition x = Don’t Care ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 2 1 Publication Order Number: NB4L52/D NB4L52 VTR R R VTR 16 15 14 13 12 VCC 11 Q 3 10 Q 4 9 VEE VTD 1 D 2 D VTD NB4L52 5 6 7 VTCLK CLK 8 CLK VTCLK Exposed Pad (EP) Figure 2. Pinout (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 VTD − 2 D ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted Differential Input. (Note 1) 3 D ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. (Note 1) 4 VTD − Internal 50 W Termination Pin. (See Table 4) 5 VTCLK − Internal 50 W Termination Pin. (See Table 4) 6 CLK ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted Differential Input. (Note 1) 7 CLK ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. (Note 1) 8 VTCLK − Internal 50 W Termination Pin. (See Table 4) 9 VEE − Negative Supply Voltage 10 Q ECL Output Inverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V. 11 Q ECL Output Noninverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V. 12 VCC − Positive Supply Voltage 13 VTR − Internal 50 W Termination Pin. (See Table 4) 14 R LVECL, LVCMOS, LVTTL Input Noninverted Differential Reset Input. (Note 1) 15 R LVECL, LVCMOS, LVTTL Input Inverted Differential Reset Input. (Note 1) 16 VTR − Internal 50 W Termination Pin. (See Table 4) − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. Internal 50 W Termination Pin. (See Table 4) 1. In the differential configuration when the input termination pin (VTD, VTD, VTR, VTR, VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on D/D,CLK/CLK,R/R input then the device will be susceptible to self−oscillation. http://onsemi.com 2 NB4L52 Table 3. ATTRIBUTES Characteristic ESD Protection Value Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 1 kV Moisture Sensitivity (Note 2) QFN−16 Pb Pkg Pb−Free Pkg Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 164 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 6.0 V −6.0 V 6.0 −6.0 V V Static Surge 45 80 mA mA Continuous Surge 25 50 mA mA −40 to +85 °C VCC Positive Power Supply VEE = 0 V VEE Negative Power Supply VCC = 0 V VIO Positive Input/Output Negative Input/Output VEE = 0 V VCC = 0 V IIN Input Current Through RT (50 W Resistor) Iout Output Current TA Operating Temperature Range Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 16 QFN 16 QFN 42 35 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 3) 16 QFN 4.0 °C/W Tsol Wave Solder 265 °C Pb−Free VI v VCC VI w VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB4L52 Table 5. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS (VCC = 2.375 V to 5.5 V, VEE = 0 V or VCC = 0 V, VEE = −2.375 to −5.5 V, TA = −40°C to +85°C) Symbol Characteristic Min Typ Max Unit 16 25 mA IEE Power Supply Current (Inputs and Outputs Open) VOH Output HIGH Voltage (Note 4, 5) VCC = 5.0 V VCC = 3.3 V VCC = 2.5 V VCC − 1145 3855 2155 1355 VCC − 1020 3980 2280 1480 VCC − 895 4105 2405 1605 mV VOL Output LOW Voltage (Note 4, 5) VCC = 5.0V VCC = 3.3V VCC = 2.5V VCC − 1945 3055 1355 555 VCC − 1770 3230 1530 730 VCC − 1600 3400 1700 900 mV 1050 VCC − 150 mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 4 & 7) Vth Input Threshold Reference Voltage Range (Note 6) VIH Single−ended Input HIGH Voltage Vth + 150 VCC mV VIL Single−ended Input LOW Voltage VEE Vth − 150 mV DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 5, 6 & 8 ) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage VEE VCC − 150 mV VCMR Input Common Mode Range (Differential Configuration) (Note 7) 1125 VCC – 75 mV VID Differential Input Voltage (VIHD − VILD) 150 VCC mV IIH Input HIGH Current D / D, CLK / CLK, R /R (VTx/VTx Open) −150 150 mA IIL Input LOW Current D / D, CLK / CLK, R /R (VTx/VTx Open) −150 150 mA RTIN Internal Input Termination Resistor 60 W 40 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL outputs loaded with 50 W to VCC – 2.0 V for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth is applied to the complementary input when operating in single−ended mode. 7. VCMRMIN varies 1:1 with VEE, VCMRMAX varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB4L52 Table 6. AC CHARACTERISTICS VCC = 2.375 V to 5.5 V; VEE = 0 V or VCC = 0 V, VEE = −2.375 to −5.5 V (Note 8) −40°C Characteristic VOUTPP Output Voltage Amplitude (@ VINPPmin) (Note 10) (See Figure 4) fin v 2.0 GHz fin v 3.0 GHz fin v 4.0 GHz 530 490 380 770 720 580 tPLH, tPHL Propagation Delay to Output Differential 300 400 ts Setup Time 100 100 100 ps th Hold Time 50 50 50 ps tRR Reset Recovery 400 400 400 ps tPW Minimum Pulse Width 250 250 250 ps tJITTER RMS Random Clock Jitter (Note 9) VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 10) 150 tr tf Output Rise/Fall Times @ 0.5 GHz (20% − 80%) 80 R/R fin v 2.0 GHz fin v 3.0 GHz fin v 4.0 GHz Max 500 Min Typ 530 490 380 780 730 580 300 400 85°C Symbol CLK to Q, R to Q Typ 25°C Min 1 1 1 135 Max 500 Min Typ 530 490 380 760 680 530 300 400 1 1 1 2800 150 190 80 Max mV 500 150 190 80 145 155 ps ps 1 1 1 2800 Unit 2800 mV 190 ps VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC – 2.0 V. Input edge rates 40 ps (20% − 80%). 9. Additive RMS jitter with 50% duty cycle clock signal. 10. Input and output voltage swing is a single−ended measurement operating in differential mode. 800 700 600 500 400 300 200 100 0 0 1 2 3 fin, CLOCK INPUT FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (VOUTPP) vs. Clock Input Frequency at Ambient Temperature (Typical). http://onsemi.com 5 4 NB4L52 CLK/D/R VIH Vth VIL Vth CLK/D/R CLK/D/R CLK/D/R Figure 4. Differential Input Driven Single−Ended Figure 5. Differential Inputs Driven Differentially VID = |VIHD − VILD| CLK/D/R VIHD CLK/D/R VILD Figure 6. Differential Inputs Driven Differentially VCC Vthmax VCC VCMmax VIHmax CLK VILmax VIHDmax VILDmax VCMR Vth Vthmin VEE VIHmin CLK VIHDmin VILDmin VCMmin VILmin VEE Figure 7. Vth Diagram Figure 8. VCMR Diagram CLK/D/R VINPP = VIH − VIL CLK/D/R Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 9. AC Reference Measurement http://onsemi.com 6 NB4L52 NB6L239 Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 10. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping † NB4L52MNG QFN−16, 3 x 3 mm (Pb−Free) 123 Units / Rail NB4L52MNR2G QFN−16, 3 x 3 mm (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 7 NB4L52 PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C D PIN 1 LOCATION ÇÇÇ ÇÇÇ ÇÇÇ 0.15 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 SEATING PLANE A1 C D2 16X L 5 NOTE 5 e 4 16X 9 E2 K 12 1 16 16X e 13 b 0.10 C A B 0.05 C EXPOSED PAD 8 BOTTOM VIEW NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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