Renesas H8SX1642G Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 sery Datasheet

REJ09B0365-0200
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
H8SX/1648, H8SX/1648A, H8SX/1648L,
H8SX/1648G, H8SX/1648H Group
Hardware Manual
Renesas 32-Bit CISC Microcomputer
H8SX Family / H8SX/1600 Series
H8SX/1648
H8SX/1644
H8SX/1642
H8SX/1648A
H8SX/1644A
H8SX/1642A
H8SX/1648L
H8SX/1644L
H8SX/1642L
H8SX/1648G
H8SX/1644G
H8SX/1642G
H8SX/1648H
H8SX/1644H
H8SX/1642H
R5F61648
R5F61644
R5F61642
R5F61648A
R5F61644A
R5F61642A
R5F61648L
R5F61644L
R5F61642L
R5F61648G
R5F61644G
R5F61642G
R5F61648H
R5F61644H
R5F61642H
All information contained in this material, including products and product
specifications at the time of publication of this material, is subject to change by
Renesas Technology Corp. without notice. Please review the latest information
published by Renesas Technology Corp. through various means, including the
Renesas Technology Corp. website (http://www.renesas.com).
Rev.2.00
Revision Date: Jul. 31, 2008
Rev. 2.00 Jul. 31, 2008 Page ii of xxx
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 2.00 Jul. 31, 2008 Page iii of xxx
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different type numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different type numbers, implement a system-evaluation test for
each of the products.
Rev. 2.00 Jul. 31, 2008 Page iv of xxx
How to Use This Manual
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the H8SX/1648A, H8SX/1648L,
H8SX/1648G, H8SX/1648H Group. Before using any of the documents, please visit our web
site to verify that you have the most up-to-date available version of the document.
Document Type
Contents
Document Title
Document No.
Data Sheet
Overview of hardware and electrical 
characteristics
Hardware Manual
Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
H8SX/1648A,
H8SX/1648L,
H8SX/1648G,
H8SX/1648H Group
Hardware Manual
This manual
Software Manual
Detailed descriptions of the CPU
and instruction set
H8SX Family Software
Manual
REJ09B0102
Application Note
Examples of applications and
sample programs
The latest versions are available from our
web site.
Renesas Technical
Update
Preliminary report on the
specifications of a product,
document, etc.

Rev. 2.00 Jul. 31, 2008 Page v of xxx
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary:
B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal:
1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4)
(2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Rev. 2.00 Jul. 31, 2008 Page vi of xxx
3. Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of
bits, describing the meanings of the bit settings. The standard format and notation for bit charts
and tables are described below.
[Bit Chart]
Bit:
Initial value:
R/W:
15
14


13
12
11
ASID2 ASID1 ASID0
10
9
8
7
6
5
4






Q
3
2
1
ACMP2 ACMP1 ACMP0
0
IFE
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(1)
[Table of Bits]
Bit
(2)
(3)
(4)
(5)
Bit Name
−
−
Initial Value R/W
0
0
R
R
Reserved
These bits are always read as 0.
13 to 11
ASID2 to
ASID0
All 0
R/W
Address Identifier
These bits enable or disable the pin function.
10
−
0
R
Reserved
This bit is always read as 0.
9
−
1
R
Reserved
This bit is always read as 1.
−
0
15
14
Description
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this
manual.
(1) Bit
Indicates the bit number or numbers.
In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case
of a 16-bit register, the bits are arranged in order from 15 to 0.
(2) Bit name
Indicates the name of the bit or bit field.
When the number of bits has to be clearly indicated in the field, appropriate notation is
included (e.g., ASID[3:0]).
A reserved bit is indicated by "−".
Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such
cases, the entry under Bit Name is blank.
(3) Initial value
Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.
0: The initial value is 0
1: The initial value is 1
−: The initial value is undefined
(4) R/W
For each bit and bit field, this entry indicates whether the bit or field is readable or writable,
or both writing to and reading from the bit or field are impossible.
The notation is as follows:
R/W: The bit or field is readable and writable.
R/(W): The bit or field is readable and writable.
However, writing is only performed to flag clearing.
R:
The bit or field is readable.
"R" is indicated for all reserved bits. When writing to the register, write
the value under Initial Value in the bit chart to reserved bits or fields.
W:
The bit or field is writable.
(5) Description
Describes the function of the bit or field and specifies the values for writing.
Rev. 2.00 Jul. 31, 2008 Page vii of xxx
4. Description of Abbreviations
The abbreviations used in this manual are listed below.
•
Abbreviations specific to this product
Abbreviation
Description
BSC
Bus controller
CPG
DTC
INTC
PPG
SCI
TMR
Clock pulse generator
Data transfer controller
Interrupt controller
Programmable pulse generator
Serial communications interface
8-bit timer
TPU
WDT
16-bit timer pulse unit
Watchdog timer
• Abbreviations other than those listed above
Abbreviation
Description
ACIA
Asynchronous communications interface adapter
bps
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
Bits per second
Cyclic redundancy check
Direct memory access
Direct memory access controller
Global System for Mobile Communications
High impedance
Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.)
Input/output
Infrared Data Association
Least significant bit
Most significant bit
No connection
Phase-locked loop
PWM
SFR
SIM
UART
VCO
Pulse width modulation
Special function register
Subscriber Identity Module
Universal asynchronous receiver/transmitter
Voltage-controlled oscillator
All trademarks and registered trademarks are the property of their respective owners.
Rev. 2.00 Jul. 31, 2008 Page viii of xxx
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Features................................................................................................................................. 1
1.1.1
Applications .......................................................................................................... 1
1.1.2
Overview of Functions.......................................................................................... 2
List of Products................................................................................................................... 11
Block Diagram.................................................................................................................... 13
Pin Assignments ................................................................................................................. 14
1.4.1
Pin Assignments ................................................................................................. 14
1.4.2
Correspondence between Pin Configuration and Operating Modes ................... 16
1.4.3
Pin Functions ...................................................................................................... 24
Section 2 CPU......................................................................................................33
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features............................................................................................................................... 33
CPU Operating Modes........................................................................................................ 35
2.2.1
Normal Mode...................................................................................................... 35
2.2.2
Middle Mode....................................................................................................... 37
2.2.3
Advanced Mode.................................................................................................. 38
2.2.4
Maximum Mode ................................................................................................. 39
Instruction Fetch ................................................................................................................. 41
Address Space..................................................................................................................... 41
Registers ............................................................................................................................. 42
2.5.1
General Registers................................................................................................ 43
2.5.2
Program Counter (PC) ........................................................................................ 44
2.5.3
Condition-Code Register (CCR)......................................................................... 45
2.5.4
Extended Control Register (EXR) ...................................................................... 46
2.5.5
Vector Base Register (VBR)............................................................................... 47
2.5.6
Short Address Base Register (SBR).................................................................... 47
2.5.7
Multiply-Accumulate Register (MAC) ............................................................... 47
2.5.8
Initial Values of CPU Registers .......................................................................... 47
Data Formats....................................................................................................................... 48
2.6.1
General Register Data Formats ........................................................................... 48
2.6.2
Memory Data Formats ........................................................................................ 49
Instruction Set ..................................................................................................................... 50
2.7.1
Instructions and Addressing Modes.................................................................... 52
2.7.2
Table of Instructions Classified by Function ...................................................... 56
2.7.3
Basic Instruction Formats ................................................................................... 66
Rev. 2.00 Jul. 31, 2008 Page ix of xxx
2.8
2.9
Addressing Modes and Effective Address Calculation....................................................... 67
2.8.1
Register Direct—Rn ........................................................................................... 67
2.8.2
Register Indirect—@ERn................................................................................... 68
2.8.3
Register Indirect with Displacement —@(d:2, ERn), @(d:16, ERn), or
@(d:32, ERn)...................................................................................................... 68
2.8.4
Index Register Indirect with Displacement—@(d:16,RnL.B),
@(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or
@(d:32,ERn.L) ................................................................................................... 68
2.8.5
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or
Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn−................................. 69
2.8.6
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32................................... 70
2.8.7
Immediate—#xx ................................................................................................. 71
2.8.8
Program-Counter Relative—@(d:8, PC) or @(d:16, PC) .................................. 71
2.8.9
Program-Counter Relative with Index Register—@(RnL.B, PC),
@(Rn.W, PC), or @(ERn.L, PC)....................................................................... 71
2.8.10
Memory Indirect—@@aa:8 ............................................................................... 72
2.8.11
Extended Memory Indirect—@@vec:7 ............................................................. 73
2.8.12
Effective Address Calculation ............................................................................ 73
2.8.13
MOVA Instruction.............................................................................................. 75
Processing States ................................................................................................................ 76
Section 3 MCU Operating Modes ....................................................................... 77
3.1
3.2
3.3
3.4
Operating Mode Selection .................................................................................................. 77
Register Descriptions.......................................................................................................... 79
3.2.1
Mode Control Register (MDCR) ........................................................................ 79
3.2.2
System Control Register (SYSCR)..................................................................... 81
Operating Mode Descriptions ............................................................................................. 83
3.3.1
Mode 1................................................................................................................ 83
3.3.2
Mode 2................................................................................................................ 83
3.3.3
Mode 3................................................................................................................ 83
3.3.4
Mode 4................................................................................................................ 83
3.3.5
Mode 5................................................................................................................ 84
3.3.6
Mode 6................................................................................................................ 84
3.3.7
Mode 7................................................................................................................ 84
3.3.8
Pin Functions ...................................................................................................... 85
Address Map....................................................................................................................... 85
3.4.1
Address Map....................................................................................................... 85
Rev. 2.00 Jul. 31, 2008 Page x of xxx
Section 4 Reset.....................................................................................................93
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Types of Reset .................................................................................................................... 93
Input/Output Pin ................................................................................................................. 95
Register Descriptions.......................................................................................................... 96
4.3.1
Reset Status Register (RSTSR)........................................................................... 96
4.3.2
Reset Control/Status Register (RSTCSR)........................................................... 98
Pin Reset ............................................................................................................................. 99
Power-on Reset (POR) (H8SX/1648L Group and H8SX/1648H Group)........................... 99
Power Supply Monitoring Reset (H8SX1648L Group, H8SX1648H Group) .................. 100
Deep Software Standby Reset........................................................................................... 101
Watchdog Timer Reset ..................................................................................................... 101
Determination of Reset Generation Source....................................................................... 101
Section 5 Voltage Detection Circuit (LVD) ......................................................103
5.1
5.2
5.3
Features............................................................................................................................. 103
Register Descriptions........................................................................................................ 104
5.2.1
Voltage Detection Control Register (LVDCR)................................................. 104
5.2.2
Reset Status Register (RSTSR)......................................................................... 105
Voltage Detection Circuit ................................................................................................. 107
5.3.1
Voltage Monitoring Reset................................................................................. 107
5.3.2
Voltage Monitoring Interrupt............................................................................ 108
5.3.3
Release from Deep Software Standby Mode by the Voltage-Detection
Circuit ............................................................................................................... 110
5.3.4
Voltage Monitor................................................................................................ 110
Section 6 Exception Handling ...........................................................................111
6.1
6.2
6.3
6.4
6.5
6.6
Exception Handling Types and Priority............................................................................ 111
Exception Sources and Exception Handling Vector Table ............................................... 112
Reset ................................................................................................................................. 114
6.3.1
Reset Exception Handling................................................................................. 114
6.3.2
Interrupts after Reset......................................................................................... 115
6.3.3
On-Chip Peripheral Functions after Reset Release ........................................... 115
Traces................................................................................................................................ 117
Address Error.................................................................................................................... 118
6.5.1
Address Error Source........................................................................................ 118
6.5.2
Address Error Exception Handling ................................................................... 119
Interrupts........................................................................................................................... 121
6.6.1
Interrupt Sources............................................................................................... 121
6.6.2
Interrupt Exception Handling ........................................................................... 122
Rev. 2.00 Jul. 31, 2008 Page xi of xxx
6.7
6.8
6.9
Instruction Exception Handling ........................................................................................ 122
6.7.1
Trap Instruction ................................................................................................ 122
6.7.2
Sleep Instruction Exception Handling .............................................................. 123
6.7.3
Exception Handling by Illegal Instruction ........................................................ 124
Stack Status after Exception Handling ............................................................................. 125
Usage Note ....................................................................................................................... 126
Section 7 Interrupt Controller............................................................................ 127
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Features............................................................................................................................. 127
Input/Output Pins.............................................................................................................. 129
Register Descriptions........................................................................................................ 129
7.3.1
Interrupt Control Register (INTCR) ................................................................. 130
7.3.2
CPU Priority Control Register (CPUPCR) ....................................................... 131
7.3.3
Interrupt Priority Register H8SX/1648 Group, H8SX/1648A Group and
H8SX/1648L Group: Interrupt Priority Registers A to I, K to O, Q, and
R (IPRA to IPRI, IPRK to IPRO, IPRQ, and IPRR) H8SX/1648G Group, and
H8SX/1648H Group: Interrupt Priority Registers A to O, O, and R (IPRA to
IPRO, IPRQ, and IPRR) ................................................................................... 134
7.3.4
IRQ Enable Register (IER) ............................................................................... 136
7.3.5
IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 138
7.3.6
IRQ Status Register (ISR)................................................................................. 143
7.3.7
Software Standby Release IRQ Enable Register (SSIER) ................................ 147
Interrupt Sources............................................................................................................... 148
7.4.1
External Interrupts ............................................................................................ 148
7.4.2
Internal Interrupts ............................................................................................. 149
Interrupt Exception Handling Vector Table...................................................................... 150
Interrupt Control Modes and Interrupt Operation............................................................. 156
7.6.1
Interrupt Control Mode 0.................................................................................. 156
7.6.2
Interrupt Control Mode 2.................................................................................. 158
7.6.3
Interrupt Exception Handling Sequence ........................................................... 160
7.6.4
Interrupt Response Times ................................................................................. 161
7.6.5
DTC and DMAC Activation by Interrupt ......................................................... 162
CPU Priority Control Function Over DTC, DMAC, and EXDMAC ............................... 165
Usage Notes ...................................................................................................................... 168
7.8.1
Conflict between Interrupt Generation and Disabling ...................................... 168
7.8.2
Instructions that Disable Interrupts................................................................... 169
7.8.3
Times when Interrupts are Disabled ................................................................. 169
7.8.4
Interrupts during Execution of EEPMOV Instruction ...................................... 169
7.8.5
Interrupts during Execution of MOVMD and MOVSD Instructions................ 169
7.8.6
Interrupts of Peripheral Modules ...................................................................... 170
Rev. 2.00 Jul. 31, 2008 Page xii of xxx
Section 8 User Break Controller (UBC) ............................................................171
8.1
8.2
8.3
8.4
8.5
Features............................................................................................................................. 171
Block Diagram.................................................................................................................. 172
Register Descriptions........................................................................................................ 173
8.3.1
Break Address Register n (BARA, BARB, BARC, BARD) ............................ 174
8.3.2
Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... 175
8.3.3
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) ................... 176
Operation .......................................................................................................................... 178
8.4.1
Setting of Break Control Conditions................................................................. 178
8.4.2
PC Break........................................................................................................... 178
8.4.3
Condition Match Flag ....................................................................................... 179
Usage Notes ...................................................................................................................... 180
Section 9 Bus Controller (BSC).........................................................................183
9.1
9.2
9.3
9.4
9.5
Features............................................................................................................................. 183
Register Descriptions........................................................................................................ 187
9.2.1
Bus Width Control Register (ABWCR)............................................................ 188
9.2.2
Access State Control Register (ASTCR) .......................................................... 189
9.2.3
Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 190
9.2.4
Read Strobe Timing Control Register (RDNCR) ............................................. 195
9.2.5
CS Assertion Period Control Registers (CSACR) ............................................ 196
9.2.6
Idle Control Register (IDLCR) ......................................................................... 199
9.2.7
Bus Control Register 1 (BCR1) ........................................................................ 201
9.2.8
Bus Control Register 2 (BCR2) ........................................................................ 203
9.2.9
Endian Control Register (ENDIANCR)............................................................ 204
9.2.10
SRAM Mode Control Register (SRAMCR) ..................................................... 205
9.2.11
Burst ROM Interface Control Register (BROMCR)......................................... 206
9.2.12
Address/Data Multiplexed I/O Control Register (MPXCR) ............................. 208
9.2.13
DRAM Control Register (DRAMCR) .............................................................. 209
9.2.14
DRAM Access Control Register (DRACCR)................................................... 214
9.2.15
Synchronous DRAM Control Register (SDCR) ............................................... 215
9.2.16
Refresh Control Register (REFCR) .................................................................. 216
9.2.17
Refresh Timer Counter (RTCNT)..................................................................... 220
9.2.18
Refresh Time Constant Register (RTCOR) ...................................................... 220
Bus Configuration............................................................................................................. 221
Multi-Clock Function and Number of Access Cycles ...................................................... 222
External Bus...................................................................................................................... 226
9.5.1
Input/Output Pins.............................................................................................. 226
9.5.2
Area Division.................................................................................................... 230
9.5.3
Chip Select Signals ........................................................................................... 231
Rev. 2.00 Jul. 31, 2008 Page xiii of xxx
9.6
9.7
9.8
9.9
9.10
9.5.4
External Bus Interface ...................................................................................... 232
9.5.5
Area and External Bus Interface ....................................................................... 238
9.5.6
Endian and Data Alignment.............................................................................. 244
Basic Bus Interface ........................................................................................................... 247
9.6.1
Data Bus ........................................................................................................... 247
9.6.2
I/O Pins Used for Basic Bus Interface .............................................................. 247
9.6.3
Basic Timing..................................................................................................... 248
9.6.4
Wait Control ..................................................................................................... 254
9.6.5
Read Strobe (RD) Timing................................................................................. 256
9.6.6
Extension of Chip Select (CS) Assertion Period............................................... 258
9.6.7
DACK and EDACK Signal Output Timing...................................................... 260
Byte Control SRAM Interface .......................................................................................... 262
9.7.1
Byte Control SRAM Space Setting................................................................... 262
9.7.2
Data Bus ........................................................................................................... 262
9.7.3
I/O Pins Used for Byte Control SRAM Interface ............................................. 263
9.7.4
Basic Timing..................................................................................................... 264
9.7.5
Wait Control ..................................................................................................... 266
9.7.6
Read Strobe (RD) ............................................................................................. 268
9.7.7
Extension of Chip Select (CS) Assertion Period............................................... 268
9.7.8
DACK and EDACK Signal Output Timing...................................................... 268
Burst ROM Interface ........................................................................................................ 270
9.8.1
Burst ROM Space Setting................................................................................. 270
9.8.2
Data Bus ........................................................................................................... 270
9.8.3
I/O Pins Used for Burst ROM Interface............................................................ 271
9.8.4
Basic Timing..................................................................................................... 272
9.8.5
Wait Control ..................................................................................................... 274
9.8.6
Read Strobe (RD) Timing................................................................................. 274
9.8.7
Extension of Chip Select (CS) Assertion Period............................................... 274
Address/Data Multiplexed I/O Interface........................................................................... 275
9.9.1
Address/Data Multiplexed I/O Space Setting ................................................... 275
9.9.2
Address/Data Multiplex.................................................................................... 275
9.9.3
Data Bus ........................................................................................................... 275
9.9.4
I/O Pins Used for Address/Data Multiplexed I/O Interface.............................. 276
9.9.5
Basic Timing..................................................................................................... 277
9.9.6
Address Cycle Control...................................................................................... 279
9.9.7
Wait Control ..................................................................................................... 280
9.9.8
Read Strobe (RD) Timing................................................................................. 280
9.9.9
Extension of Chip Select (CS) Assertion Period............................................... 282
9.9.10
DACK and EDACK Signal Output Timing...................................................... 284
DRAM Interface ............................................................................................................... 285
Rev. 2.00 Jul. 31, 2008 Page xiv of xxx
9.11
9.12
9.13
9.14
9.15
9.10.1
Setting DRAM Space........................................................................................ 285
9.10.2
Address Multiplexing........................................................................................ 286
9.10.3
Data Bus............................................................................................................ 286
9.10.4
I/O Pins Used for DRAM Interface .................................................................. 287
9.10.5
Basic Timing..................................................................................................... 288
9.10.6
Controlling Column Address Output Cycle...................................................... 289
9.10.7
Controlling Row Address Output Cycle ........................................................... 290
9.10.8
Controlling Precharge Cycle............................................................................. 292
9.10.9
Wait Control ..................................................................................................... 293
9.10.10 Controlling Byte and Word Accesses ............................................................... 296
9.10.11 Burst Access Operation..................................................................................... 298
9.10.12 Refresh Control................................................................................................. 304
9.10.13 DRAM Interface and Single Address Transfer by DMAC and EXDMAC ...... 309
Synchronous DRAM Interface ......................................................................................... 312
9.11.1
Setting SDRAM space ...................................................................................... 312
9.11.2
Address Multiplexing........................................................................................ 313
9.11.3
Data Bus............................................................................................................ 313
9.11.4
I/O Pins Used for DRAM Interface .................................................................. 314
9.11.5
Basic Timing..................................................................................................... 315
9.11.6
CAS Latency Control........................................................................................ 317
9.11.7
Controlling Row Address Output Cycle ........................................................... 319
9.11.8
Controlling Precharge Cycle............................................................................. 321
9.11.9
Controlling Clock Suspend Insertion................................................................ 323
9.11.10 Controlling Write-Precharge Delay .................................................................. 324
9.11.11 Controlling Byte and Word Accesses ............................................................... 325
9.11.12 Fast-Page Access Operation ............................................................................. 327
9.11.13 Refresh Control................................................................................................. 333
9.11.14 Setting SDRAM Mode Register ....................................................................... 341
9.11.15 SDRAM Interface and Single Address Transfer by DMAC and EXDMAC .... 342
9.11.16 EXDMAC Cluster Transfer .............................................................................. 350
Idle Cycle.......................................................................................................................... 353
9.12.1
Operation .......................................................................................................... 353
9.12.2
Pin States in Idle Cycle ..................................................................................... 365
Bus Release....................................................................................................................... 366
9.13.1
Operation .......................................................................................................... 366
9.13.2
Pin States in External Bus Released State......................................................... 367
9.13.3
Transition Timing ............................................................................................. 369
Internal Bus....................................................................................................................... 371
9.14.1
Access to Internal Address Space ..................................................................... 371
Write Data Buffer Function .............................................................................................. 373
Rev. 2.00 Jul. 31, 2008 Page xv of xxx
9.16
9.17
9.18
9.15.1
Write Data Buffer Function for External Data Bus .......................................... 373
9.15.2
Write Data Buffer Function for Peripheral Modules ........................................ 374
Bus Arbitration ................................................................................................................. 375
9.16.1
Operation .......................................................................................................... 375
9.16.2
Bus Transfer Timing......................................................................................... 376
Bus Controller Operation in Reset.................................................................................... 379
Usage Notes ...................................................................................................................... 379
Section 10 DMA Controller (DMAC)............................................................... 383
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
Features............................................................................................................................. 383
Input/Output Pins.............................................................................................................. 386
Register Descriptions........................................................................................................ 387
10.3.1
DMA Source Address Register (DSAR) .......................................................... 388
10.3.2
DMA Destination Address Register (DDAR) .................................................. 389
10.3.3
DMA Offset Register (DOFR).......................................................................... 390
10.3.4
DMA Transfer Count Register (DTCR) ........................................................... 391
10.3.5
DMA Block Size Register (DBSR) .................................................................. 392
10.3.6
DMA Mode Control Register (DMDR)............................................................ 393
10.3.7
DMA Address Control Register (DACR)......................................................... 402
10.3.8
DMA Module Request Select Register (DMRSR) ........................................... 408
Transfer Modes................................................................................................................. 409
Operations......................................................................................................................... 410
10.5.1
Address Modes ................................................................................................. 410
10.5.2
Transfer Modes................................................................................................. 414
10.5.3
Activation Sources............................................................................................ 419
10.5.4
Bus Access Modes ............................................................................................ 421
10.5.5
Extended Repeat Area Function ....................................................................... 423
10.5.6
Address Update Function using Offset ............................................................. 426
10.5.7
Register during DMA Transfer......................................................................... 430
10.5.8
Priority of Channels .......................................................................................... 435
10.5.9
DMA Basic Bus Cycle...................................................................................... 437
10.5.10 Bus Cycles in Dual Address Mode ................................................................... 438
10.5.11 Bus Cycles in Single Address Mode................................................................. 447
DMA Transfer End ........................................................................................................... 452
Relationship among DMAC and Other Bus Masters........................................................ 455
10.7.1
CPU Priority Control Function Over DMAC ................................................... 455
10.7.2
Bus Arbitration among DMAC and Other Bus Masters ................................... 456
Interrupt Sources............................................................................................................... 457
Usage Notes ...................................................................................................................... 460
Rev. 2.00 Jul. 31, 2008 Page xvi of xxx
Section 11 EXDMA Controller (EXDMAC) ....................................................461
11.1
11.2
11.3
Features............................................................................................................................. 461
Input/Output Pins.............................................................................................................. 464
Registers Descriptions ...................................................................................................... 465
11.3.1
EXDMA Source Address Register (EDSAR)................................................... 467
11.3.2
EXDMA Destination Address Register (EDDAR)........................................... 468
11.3.3
EXDMA Offset Register (EDOFR).................................................................. 469
11.3.4
EXDMA Transfer Count Register (EDTCR).................................................... 470
11.3.5
EXDMA Block Size Register (EDBSR)........................................................... 471
11.3.6
EXDMA Mode Control Register (EDMDR) .................................................... 472
11.3.7
EXDMA Address Control Register (EDACR) ................................................. 481
11.3.8
Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7).................................... 487
11.4 Transfer Modes ................................................................................................................. 488
11.4.1
Ordinary Modes ................................................................................................ 488
11.4.2
Cluster Transfer Modes..................................................................................... 489
11.5 Mode Operation ................................................................................................................ 490
11.5.1
Address Modes ................................................................................................. 490
11.5.2
Transfer Modes ................................................................................................. 493
11.5.3
Activation Sources............................................................................................ 498
11.5.4
Bus Mode.......................................................................................................... 499
11.5.5
Extended Repeat Area Function ....................................................................... 500
11.5.6
Address Update Function Using Offset ............................................................ 503
11.5.7
Registers during EXDMA Transfer Operation ................................................. 507
11.5.8
Channel Priority Order...................................................................................... 512
11.5.9
Basic Bus Cycles .............................................................................................. 513
11.5.10 Bus Cycles in Dual Address Mode ................................................................... 514
11.5.11 Bus Cycles in Single Address Mode................................................................. 523
11.5.12 Operation Timing in Each Mode ...................................................................... 528
11.6 Operation in Cluster Transfer Mode ................................................................................. 539
11.6.1
Address Mode ................................................................................................... 539
11.6.2
Setting of Address Update Mode ...................................................................... 544
11.6.3
Caution for Combining with Extended Repeat Area Function ......................... 545
11.6.4
Bus Cycles in Cluster Transfer Dual Address Mode ........................................ 545
11.6.5
Operation Timing in Cluster Transfer Mode .................................................... 548
11.7 Ending EXDMA Transfer................................................................................................. 556
11.8 Relationship among EXDMAC and Other Bus Masters................................................... 559
11.8.1
CPU Priority Control Function Over EXDMAC .............................................. 559
11.8.2
Bus Arbitration with Another Bus Master ........................................................ 560
11.9 Interrupt Sources............................................................................................................... 561
11.10 Usage Notes ...................................................................................................................... 564
Rev. 2.00 Jul. 31, 2008 Page xvii of xxx
Section 12 Data Transfer Controller (DTC)...................................................... 567
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
Features............................................................................................................................. 567
Register Descriptions........................................................................................................ 569
12.2.1
DTC Mode Register A (MRA) ......................................................................... 570
12.2.2
DTC Mode Register B (MRB).......................................................................... 571
12.2.3
DTC Source Address Register (SAR)............................................................... 572
12.2.4
DTC Destination Address Register (DAR)....................................................... 573
12.2.5
DTC Transfer Count Register A (CRA) ........................................................... 573
12.2.6
DTC Transfer Count Register B (CRB)............................................................ 574
12.2.7
DTC enable registers A to H (DTCERA to DTCERH) .................................... 574
12.2.8
DTC Control Register (DTCCR) ...................................................................... 575
12.2.9
DTC Vector Base Register (DTCVBR)............................................................ 577
Activation Sources............................................................................................................ 577
Location of Transfer Information and DTC Vector Table................................................ 577
Operation .......................................................................................................................... 582
12.5.1
Bus Cycle Division ........................................................................................... 584
12.5.2
Transfer Information Read Skip Function ........................................................ 586
12.5.3
Transfer Information Writeback Skip Function................................................ 587
12.5.4
Normal Transfer Mode ..................................................................................... 587
12.5.5
Repeat Transfer Mode ...................................................................................... 588
12.5.6
Block Transfer Mode ........................................................................................ 590
12.5.7
Chain Transfer .................................................................................................. 591
12.5.8
Operation Timing.............................................................................................. 592
12.5.9
Number of DTC Execution Cycles ................................................................... 594
12.5.10 DTC Bus Release Timing ................................................................................. 595
12.5.11 DTC Priority Level Control to the CPU ........................................................... 595
DTC Activation by Interrupt............................................................................................. 596
Examples of Use of the DTC............................................................................................ 597
12.7.1
Normal Transfer Mode ..................................................................................... 597
12.7.2
Chain Transfer .................................................................................................. 597
12.7.3
Chain Transfer when Counter = 0..................................................................... 598
Interrupt Sources............................................................................................................... 600
Usage Notes ...................................................................................................................... 600
12.9.1
Module Stop State Setting ................................................................................ 600
12.9.2
On-Chip RAM .................................................................................................. 600
12.9.3
DMAC Transfer End Interrupt.......................................................................... 600
12.9.4
DTCE Bit Setting.............................................................................................. 600
12.9.5
Chain Transfer .................................................................................................. 601
12.9.6
Transfer Information Start Address, Source Address, and Destination
Address ............................................................................................................. 601
Rev. 2.00 Jul. 31, 2008 Page xviii of xxx
12.9.7
12.9.8
12.9.9
Transfer Information Modification ................................................................... 601
Endian Format................................................................................................... 601
Points for Caution when Overwriting DTCER. ................................................ 601
Section 13 I/O Ports ...........................................................................................603
13.1
13.2
13.3
Register Descriptions........................................................................................................ 613
13.1.1
Data Direction Register (PnDDR)
(n = 1, 2, 3, 6, A, to F, H to K, M, and N) ........................................................ 614
13.1.2
Data Register (PnDR) (n = 1, 2, 3, 6, A, to F, H to K, M, and N) .................... 615
13.1.3
Port Register (PORTn) (n = 1 to 6, A to F, H to K, M, and N)......................... 615
13.1.4
Input Buffer Control Register (PnICR)
(n = 1 to 6, A to F, H to K, M, and N) .............................................................. 616
13.1.5
Pull-Up MOS Control Register (PnPCR) (n = D to F and H to K)................... 617
13.1.6
Open-Drain Control Register (PnODR) (n = 2 and F) ...................................... 618
Output Buffer Control....................................................................................................... 618
13.2.1
Port 1................................................................................................................. 619
13.2.2
Port 2................................................................................................................. 623
13.2.3
Port 3................................................................................................................. 627
13.2.4
Port 5................................................................................................................. 632
13.2.5
Port 6................................................................................................................. 632
13.2.6
Port A................................................................................................................ 637
13.2.7
Port B ................................................................................................................ 642
13.2.8
Port C ................................................................................................................ 647
13.2.9
Port D................................................................................................................ 650
13.2.10 Port E ................................................................................................................ 651
13.2.11 Port F ................................................................................................................ 652
13.2.12 Port H................................................................................................................ 656
13.2.13 Port I ................................................................................................................. 657
13.2.14 Port J ................................................................................................................. 658
13.2.15 Port K................................................................................................................ 662
13.2.16 Port M ............................................................................................................... 666
13.2.17 Port N................................................................................................................ 667
Port Function Controller ................................................................................................... 681
13.3.1
Port Function Control Register 0 (PFCR0)....................................................... 682
13.3.2
Port Function Control Register 1 (PFCR1)....................................................... 682
13.3.3
Port Function Control Register 2 (PFCR2)....................................................... 684
13.3.4
Port Function Control Register 4 (PFCR4)....................................................... 685
13.3.5
Port Function Control Register 6 (PFCR6)....................................................... 687
13.3.6
Port Function Control Register 7 (PFCR7)....................................................... 688
13.3.7
Port Function Control Register 8 (PFCR8)....................................................... 689
Rev. 2.00 Jul. 31, 2008 Page xix of xxx
13.4
13.3.8
Port Function Control Register 9 (PFCR9)....................................................... 690
13.3.9
Port Function Control Register A (PFCRA) ..................................................... 692
13.3.10 Port Function Control Register B (PFCRB) ..................................................... 694
13.3.11 Port Function Control Register C (PFCRC) ..................................................... 697
13.3.12 Port Function Control Register D (PFCRD) ..................................................... 699
Usage Notes ...................................................................................................................... 700
13.4.1
Notes on Input Buffer Control Register (ICR) Setting ..................................... 700
13.4.2
Notes on Port Function Control Register (PFCR) Settings............................... 700
Section 14 16-Bit Timer Pulse Unit (TPU) ....................................................... 701
14.1
14.2
14.3
Features............................................................................................................................. 701
Input/Output Pins.............................................................................................................. 708
Register Descriptions........................................................................................................ 710
14.3.1
Timer Control Register (TCR).......................................................................... 715
14.3.2
Timer Mode Register (TMDR)......................................................................... 720
14.3.3
Timer I/O Control Register (TIOR).................................................................. 722
14.3.4
Timer Interrupt Enable Register (TIER)........................................................... 740
14.3.5
Timer Status Register (TSR)............................................................................. 741
14.3.6
Timer Counter (TCNT)..................................................................................... 745
14.3.7
Timer General Register (TGR) ......................................................................... 745
14.3.8
Timer Start Register (TSTR) ............................................................................ 746
14.3.9
Timer Synchronous Register (TSYR)............................................................... 747
14.4 Operation .......................................................................................................................... 748
14.4.1
Basic Functions................................................................................................. 748
14.4.2
Synchronous Operation..................................................................................... 754
14.4.3
Buffer Operation............................................................................................... 756
14.4.4
Cascaded Operation .......................................................................................... 760
14.4.5
PWM Modes..................................................................................................... 762
14.4.6
Phase Counting Mode....................................................................................... 767
14.5 Interrupt Sources............................................................................................................... 774
14.6 DTC Activation ................................................................................................................ 776
14.7 DMAC Activation ............................................................................................................ 776
14.8 A/D Converter Activation................................................................................................. 776
14.9 Operation Timing.............................................................................................................. 777
14.9.1
Input/Output Timing ......................................................................................... 777
14.9.2
Interrupt Signal Timing .................................................................................... 781
14.10 Usage Notes ...................................................................................................................... 785
14.10.1 Module Stop Function Setting .......................................................................... 785
14.10.2 Input Clock Restrictions ................................................................................... 785
14.10.3 Caution on Cycle Setting .................................................................................. 786
Rev. 2.00 Jul. 31, 2008 Page xx of xxx
14.10.4
14.10.5
14.10.6
14.10.7
14.10.8
14.10.9
14.10.10
14.10.11
14.10.12
14.10.13
14.10.14
14.10.15
Conflict between TCNT Write and Clear Operations....................................... 786
Conflict between TCNT Write and Increment Operations ............................... 787
Conflict between TGR Write and Compare Match........................................... 787
Conflict between Buffer Register Write and Compare Match .......................... 788
Conflict between TGR Read and Input Capture ............................................... 788
Conflict between TGR Write and Input Capture .............................................. 789
Conflict between Buffer Register Write and Input Capture.............................. 790
Conflict between Overflow/Underflow and Counter Clearing ......................... 791
Conflict between TCNT Write and Overflow/Underflow ................................ 791
Multiplexing of I/O Pins ................................................................................... 792
PPG1 Setting when TPU1 Pin is Used.............................................................. 792
Interrupts and Module Stop Mode .................................................................... 792
Section 15 Programmable Pulse Generator (PPG) ............................................793
15.1
15.2
15.3
15.4
15.5
Features............................................................................................................................. 793
Input/Output Pins.............................................................................................................. 796
Register Descriptions........................................................................................................ 798
15.3.1
Next Data Enable Registers H, L (NDERH, NDERL) ..................................... 799
15.3.2
Output Data Registers H, L (PODRH, PODRL)............................................... 801
15.3.3
Next Data Registers H, L (NDRH, NDRL) ...................................................... 804
15.3.4
PPG Output Control Register (PCR) ................................................................ 809
15.3.5
PPG Output Mode Register (PMR) .................................................................. 811
Operation .......................................................................................................................... 815
15.4.1
Output Timing................................................................................................... 815
15.4.2
Sample Setup Procedure for Normal Pulse Output........................................... 816
15.4.3
Example of Normal Pulse Output (Example of 5-Phase Pulse Output)............ 818
15.4.4
Non-Overlapping Pulse Output......................................................................... 819
15.4.5
Sample Setup Procedure for Non-Overlapping Pulse Output ........................... 821
15.4.6
Example of Non-Overlapping Pulse Output (Example of 4-Phase
Complementary Non-Overlapping Pulse Output)............................................. 823
15.4.7
Inverted Pulse Output ....................................................................................... 825
15.4.8
Pulse Output Triggered by Input Capture ......................................................... 826
Usage Notes ...................................................................................................................... 827
15.5.1
Module Stop State Setting ................................................................................ 827
15.5.2
Operation of Pulse Output Pins......................................................................... 827
15.5.3
TPU Setting when PPG1 is in Use.................................................................... 827
Section 16 8-Bit Timers (TMR).........................................................................829
16.1
16.2
Features............................................................................................................................. 829
Input/Output Pins.............................................................................................................. 834
Rev. 2.00 Jul. 31, 2008 Page xxi of xxx
16.3
16.4
16.5
16.6
16.7
16.8
Register Descriptions........................................................................................................ 835
16.3.1
Timer Counter (TCNT)..................................................................................... 837
16.3.2
Time Constant Register A (TCORA)................................................................ 837
16.3.3
Time Constant Register B (TCORB) ................................................................ 838
16.3.4
Timer Control Register (TCR).......................................................................... 838
16.3.5
Timer Counter Control Register (TCCR) ......................................................... 840
16.3.6
Timer Control/Status Register (TCSR)............................................................. 845
Operation .......................................................................................................................... 849
16.4.1
Pulse Output...................................................................................................... 849
16.4.2
Reset Input ........................................................................................................ 850
Operation Timing.............................................................................................................. 851
16.5.1
TCNT Count Timing ........................................................................................ 851
16.5.2
Timing of CMFA and CMFB Setting at Compare Match ................................ 852
16.5.3
Timing of Timer Output at Compare Match..................................................... 852
16.5.4
Timing of Counter Clear by Compare Match ................................................... 853
16.5.5
Timing of TCNT External Reset....................................................................... 853
16.5.6
Timing of Overflow Flag (OVF) Setting .......................................................... 854
Operation with Cascaded Connection............................................................................... 854
16.6.1
16-Bit Counter Mode ........................................................................................ 854
16.6.2
Compare Match Count Mode............................................................................ 855
Interrupt Sources............................................................................................................... 855
16.7.1
Interrupt Sources and DTC Activation ............................................................. 855
16.7.2
A/D Converter Activation................................................................................. 856
Usage Notes ...................................................................................................................... 857
16.8.1
Notes on Setting Cycle ..................................................................................... 857
16.8.2
Conflict between TCNT Write and Counter Clear ........................................... 857
16.8.3
Conflict between TCNT Write and Increment.................................................. 858
16.8.4
Conflict between TCOR Write and Compare Match........................................ 858
16.8.5
Conflict between Compare Matches A and B................................................... 859
16.8.6
Switching of Internal Clocks and TCNT Operation ......................................... 859
16.8.7
Mode Setting with Cascaded Connection ......................................................... 861
16.8.8
Module Stop State Setting ................................................................................ 861
16.8.9
Interrupts in Module Stop State ........................................................................ 861
Section 17 32K Timer (TM32K)....................................................................... 863
17.1
17.2
17.3
Features............................................................................................................................. 863
Register Descriptions........................................................................................................ 864
17.2.1
Timer Control Register (TCR32K)................................................................... 864
17.2.2
Timer Counter (TCNT32K1, TCNT32K2, TCNT32K3).................................. 865
Operation .......................................................................................................................... 867
Rev. 2.00 Jul. 31, 2008 Page xxii of xxx
17.4
17.5
17.3.1
Basic Operation................................................................................................. 867
17.3.2
EXCKSN=1 Operation ..................................................................................... 868
17.3.3
EXCKSN=0 Operation ..................................................................................... 868
Interrupt Source ................................................................................................................ 871
Usage Notes ...................................................................................................................... 872
17.5.1
Changing Values of Bits EXCKSN, CKS1, and CKS0 .................................... 872
17.5.2
Note on Register Initialization .......................................................................... 872
17.5.3
Usage Notes on 32K Timer............................................................................... 872
Section 18 Watchdog Timer (WDT)..................................................................873
18.1
18.2
18.3
18.4
18.5
18.6
Features............................................................................................................................. 873
Input/Output Pin ............................................................................................................... 874
Register Descriptions........................................................................................................ 875
18.3.1
Timer Counter (TCNT)..................................................................................... 875
18.3.2
Timer Control/Status Register (TCSR)............................................................. 875
18.3.3
Reset Control/Status Register (RSTCSR)......................................................... 877
Operation .......................................................................................................................... 878
18.4.1
Watchdog Timer Mode ..................................................................................... 878
18.4.2
Interval Timer Mode ......................................................................................... 880
Interrupt Source ................................................................................................................ 880
Usage Notes ...................................................................................................................... 881
18.6.1
Notes on Register Access.................................................................................. 881
18.6.2
Conflict between Timer Counter (TCNT) Write and Increment....................... 882
18.6.3
Changing Values of Bits CKS2 to CKS0.......................................................... 882
18.6.4
Switching between Watchdog Timer Mode and Interval Timer Mode............. 882
18.6.5
Internal Reset in Watchdog Timer Mode.......................................................... 883
18.6.6
System Reset by WDTOVF Signal................................................................... 883
18.6.7
Transition to Watchdog Timer Mode or Software Standby Mode.................... 883
Section 19 Serial Communication Interface (SCI, IrDA, CRC).......................885
19.1
19.2
19.3
Features............................................................................................................................. 885
Input/Output Pins.............................................................................................................. 890
Register Descriptions........................................................................................................ 891
19.3.1
Receive Shift Register (RSR) ........................................................................... 894
19.3.2
Receive Data Register (RDR) ........................................................................... 894
19.3.3
Transmit Data Register (TDR).......................................................................... 894
19.3.4
Transmit Shift Register (TSR) .......................................................................... 895
19.3.5
Serial Mode Register (SMR) ............................................................................ 895
19.3.6
Serial Control Register (SCR)........................................................................... 899
19.3.7
Serial Status Register (SSR) ............................................................................. 905
Rev. 2.00 Jul. 31, 2008 Page xxiii of xxx
19.3.8
Smart Card Mode Register (SCMR)................................................................. 914
19.3.9
Bit Rate Register (BRR) ................................................................................... 915
19.3.10 Serial Extended Mode Register (SEMR_2) ...................................................... 922
19.3.11 Serial Extended Mode Register 5 and 6 (SEMR_5 and SEMR_6)................... 924
19.3.12 IrDA Control Register (IrCR)........................................................................... 931
19.4 Operation in Asynchronous Mode .................................................................................... 933
19.4.1
Data Transfer Format........................................................................................ 933
19.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode................................................................................................................. 935
19.4.3
Clock................................................................................................................. 936
19.4.4
SCI Initialization (Asynchronous Mode).......................................................... 937
19.4.5
Serial Data Transmission (Asynchronous Mode) ............................................. 938
19.4.6
Serial Data Reception (Asynchronous Mode) .................................................. 940
19.5 Multiprocessor Communication Function ........................................................................ 944
19.5.1
Multiprocessor Serial Data Transmission ......................................................... 946
19.5.2
Multiprocessor Serial Data Reception .............................................................. 947
19.6 Operation in Clock Synchronous Mode............................................................................ 950
19.6.1
Clock................................................................................................................. 950
19.6.2
SCI Initialization (Clock Synchronous Mode).................................................. 951
19.6.3
Serial Data Transmission (Clock Synchronous Mode) ..................................... 952
19.6.4
Serial Data Reception (Clock Synchronous Mode) .......................................... 954
19.6.5
Simultaneous Serial Data Transmission and Reception
(Clock Synchronous Mode) .............................................................................. 955
19.7 Operation in Smart Card Interface Mode.......................................................................... 957
19.7.1
Sample Connection ........................................................................................... 957
19.7.2
Data Format (Except in Block Transfer Mode) ................................................ 958
19.7.3
Block Transfer Mode ........................................................................................ 959
19.7.4
Receive Data Sampling Timing and Reception Margin ................................... 960
19.7.5
Initialization...................................................................................................... 961
19.7.6
Data Transmission (Except in Block Transfer Mode) ...................................... 962
19.7.7
Serial Data Reception (Except in Block Transfer Mode) ................................. 965
19.7.8
Clock Output Control........................................................................................ 966
19.8 IrDA Operation................................................................................................................. 968
19.9 Interrupt Sources............................................................................................................... 971
19.9.1
Interrupts in Normal Serial Communication Interface Mode ........................... 971
19.9.2
Interrupts in Smart Card Interface Mode .......................................................... 972
19.10 Usage Notes ...................................................................................................................... 974
19.10.1 Module Stop State Setting ................................................................................ 974
19.10.2 Break Detection and Processing ....................................................................... 974
19.10.3 Mark State and Break Detection ....................................................................... 974
Rev. 2.00 Jul. 31, 2008 Page xxiv of xxx
19.10.4
Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ..................................................................... 974
19.10.5 Relation between Writing to TDR and TDRE Flag .......................................... 975
19.10.6 Restrictions on Using DTC or DMAC.............................................................. 975
19.10.7 SCI Operations during Power-Down State ....................................................... 976
19.11 CRC Operation Circuit ..................................................................................................... 979
19.11.1 Features............................................................................................................. 979
19.11.2 Register Descriptions ........................................................................................ 980
19.11.3 CRC Operation Circuit Operation..................................................................... 982
19.11.4 Note on CRC Operation Circuit........................................................................ 985
Section 20 I2C Bus Interface 2 (IIC2) ................................................................987
20.1
20.2
20.3
20.4
20.5
20.6
20.7
Features............................................................................................................................. 987
Input/Output Pins.............................................................................................................. 989
Register Descriptions........................................................................................................ 990
20.3.1
I2C Bus Control Register A (ICCRA) ............................................................... 992
20.3.2
I2C Bus Control Register B (ICCRB)................................................................ 993
20.3.3
I2C Bus Mode Register (ICMR)........................................................................ 995
20.3.4
I2C Bus Interrupt Enable Register (ICIER) ....................................................... 996
20.3.5
I2C Bus Status Register (ICSR)......................................................................... 999
20.3.6
Slave Address Register (SAR)........................................................................ 1002
20.3.7
I2C Bus Transmit Data Register (ICDRT)....................................................... 1003
20.3.8
I2C Bus Receive Data Register (ICDRR)........................................................ 1003
20.3.9
I2C Bus Shift Register (ICDRS)...................................................................... 1003
Operation ........................................................................................................................ 1004
20.4.1
I2C Bus Format................................................................................................ 1004
20.4.2
Master Transmit Operation ............................................................................. 1005
20.4.3
Master Receive Operation............................................................................... 1007
20.4.4
Slave Transmit Operation ............................................................................... 1009
20.4.5
Slave Receive Operation................................................................................. 1012
20.4.6
Noise Canceller............................................................................................... 1013
20.4.7
Example of Use............................................................................................... 1014
Interrupt Request............................................................................................................. 1018
Bit Synchronous Circuit.................................................................................................. 1018
Usage Notes .................................................................................................................... 1019
Section 21 A/D Converter................................................................................1021
21.1
21.2
21.3
Features........................................................................................................................... 1021
Input/Output Pins............................................................................................................ 1025
Register Descriptions...................................................................................................... 1027
Rev. 2.00 Jul. 31, 2008 Page xxv of xxx
21.4
21.5
21.6
21.7
21.3.1
A/D Data Registers A to H (ADDRA to ADDRH) ........................................ 1029
21.3.2
A/D Control/Status Register for Unit 0 (ADCSR_0)...................................... 1030
21.3.3
A/D Control/Status Register for Unit 1 (ADCSR_1)...................................... 1032
21.3.4
A/D Control/Status Register for Unit 2 (ADCSR_2)...................................... 1034
21.3.5
A/D Control Register (ADCR_0) Unit 0 ........................................................ 1036
21.3.6
A/D Control Register (ADCR_1) Unit 1 ........................................................ 1038
21.3.7
A/D Control Register (ADCR_2) Unit 2 ........................................................ 1040
Operation ........................................................................................................................ 1042
21.4.1
Single Mode.................................................................................................... 1042
21.4.2
Scan Mode ...................................................................................................... 1043
21.4.3
Input Sampling and A/D Conversion Time .................................................... 1046
21.4.4
External Trigger Input Timing........................................................................ 1048
Interrupt Source .............................................................................................................. 1050
A/D Conversion Accuracy Definitions ........................................................................... 1051
Usage Notes .................................................................................................................... 1053
21.7.1
Module Stop Function Setting ........................................................................ 1053
21.7.2
A/D Input Hold Function in Software Standby Mode .................................... 1053
21.7.3
Notes on A/D Activation by an External Trigger ........................................... 1053
21.7.4
Permissible Signal Source Impedance ............................................................ 1055
21.7.5
Influences on Absolute Accuracy ................................................................... 1055
21.7.6
Setting Range of Analog Power Supply and Other Pins................................. 1055
21.7.7
Notes on Board Design ................................................................................... 1056
21.7.8
Notes on Noise Countermeasures ................................................................... 1056
Section 22 D/A Converter ............................................................................... 1059
22.1
22.2
22.3
22.4
22.5
Features........................................................................................................................... 1059
Input/Output Pins............................................................................................................ 1060
Register Descriptions...................................................................................................... 1060
22.3.1
D/A Data Registers 0 and 1 (DADR0 and DADR1)....................................... 1060
22.3.2
D/A Control Register 01 (DACR01) .............................................................. 1061
Operation ........................................................................................................................ 1063
Usage Notes .................................................................................................................... 1064
22.5.1
Module Stop State Setting .............................................................................. 1064
22.5.2
D/A Output Hold Function in Software Standby Mode.................................. 1064
22.5.3
Notes on Deep Software Standby Mode ......................................................... 1064
Section 23 RAM .............................................................................................. 1065
Rev. 2.00 Jul. 31, 2008 Page xxvi of xxx
Section 24 Flash Memory ................................................................................1067
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
24.9
24.10
24.11
24.12
24.13
24.14
Features........................................................................................................................... 1067
Mode Transition Diagram............................................................................................... 1070
Memory MAT Configuration ......................................................................................... 1072
Block Structure ............................................................................................................... 1073
24.4.1
Block Diagram of H8SX/1642........................................................................ 1073
24.4.2
Block Diagram of H8SX/1644........................................................................ 1074
24.4.3
Block Diagram of H8SX/1648........................................................................ 1075
Programming/Erasing Interface ...................................................................................... 1076
Input/Output Pins............................................................................................................ 1078
Register Descriptions...................................................................................................... 1078
24.7.1
Programming/Erasing Interface Registers ...................................................... 1079
24.7.2
Programming/Erasing Interface Parameters ................................................... 1086
24.7.3
RAM Emulation Register (RAMER).............................................................. 1098
On-Board Programming Mode ....................................................................................... 1099
24.8.1
Boot Mode ...................................................................................................... 1099
24.8.2
User Program Mode........................................................................................ 1103
24.8.3
User Boot Mode.............................................................................................. 1113
24.8.4
On-Chip Program and Storable Area for Program Data ................................. 1117
Protection........................................................................................................................ 1123
24.9.1
Hardware Protection ....................................................................................... 1123
24.9.2
Software Protection......................................................................................... 1124
24.9.3
Error Protection............................................................................................... 1124
Flash Memory Emulation Using RAM........................................................................... 1126
Switching between User MAT and User Boot MAT...................................................... 1129
Programmer Mode .......................................................................................................... 1130
Standard Serial Communications Interface Specifications for Boot Mode..................... 1130
Usage Notes .................................................................................................................... 1159
Section 25 Boundary Scan ...............................................................................1161
25.1
25.2
25.3
25.4
25.5
Features........................................................................................................................... 1161
Block Diagram of Boundary Scan Function ................................................................... 1162
Input/Output Pins............................................................................................................ 1162
Register Descriptions...................................................................................................... 1163
25.4.1
Instruction Register (JTIR) ............................................................................. 1164
25.4.2
Bypass Register (JTBPR) ............................................................................... 1165
25.4.3
Boundary Scan Register (JTBSR)................................................................... 1165
25.4.4
IDCODE Register (JTID) ............................................................................... 1172
Operations....................................................................................................................... 1173
Rev. 2.00 Jul. 31, 2008 Page xxvii of xxx
25.6
25.5.1
TAP Controller ............................................................................................... 1173
25.5.2
Commands ...................................................................................................... 1174
Usage Notes .................................................................................................................... 1175
Section 26 Clock Pulse Generator................................................................... 1177
26.1
26.2
26.3
26.4
26.5
26.6
Register Description ....................................................................................................... 1179
26.1.1
System Clock Control Register (SCKCR) ...................................................... 1179
26.1.2
Subclock Control Register (SUBCKCR)........................................................ 1181
Oscillator ........................................................................................................................ 1183
26.2.1
Connecting Crystal Resonator ........................................................................ 1183
26.2.2
External Clock Input....................................................................................... 1184
PLL Circuit ..................................................................................................................... 1185
Frequency Divider .......................................................................................................... 1185
Subclock Oscillator......................................................................................................... 1185
26.5.1
Connecting 32.768 kHz Resonator ................................................................. 1185
26.5.2
Handling of Pins when the Subclock is Not to be Used.................................. 1186
Usage Notes .................................................................................................................... 1187
26.6.1
Notes on Clock Pulse Generator ..................................................................... 1187
26.6.2
Notes on Resonator......................................................................................... 1188
26.6.3
Notes on Board Design ................................................................................... 1188
Section 27 Power-Down Modes...................................................................... 1191
27.1
27.2
27.3
27.4
27.5
Features........................................................................................................................... 1191
Register Descriptions...................................................................................................... 1196
27.2.1
Standby Control Register (SBYCR) ............................................................... 1196
27.2.2
Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) ........ 1199
27.2.3
Module Stop Control Register C (MSTPCRC)............................................... 1202
27.2.4
Deep Standby Control Register (DPSBYCR)................................................. 1203
27.2.5
Deep Standby Wait Control Register (DPSWCR).......................................... 1206
27.2.6
Deep Standby Interrupt Enable Register (DPSIER) ....................................... 1208
27.2.7
Deep Standby Interrupt Flag Register (DPSIFR)............................................ 1210
27.2.8
Deep Standby Interrupt Edge Register (DPSIEGR) ....................................... 1212
27.2.9
Reset Status Register (RSTSR)....................................................................... 1213
27.2.10 Deep Standby Backup Register (DPSBKRn) ................................................. 1215
Multi-Clock Function ..................................................................................................... 1216
27.3.1
Switching of Main Clock Frequencies............................................................ 1216
27.3.2
Switching to Subclock .................................................................................... 1216
Module Stop State........................................................................................................... 1217
Sleep Mode ..................................................................................................................... 1217
27.5.1
Entry to Sleep Mode ....................................................................................... 1217
Rev. 2.00 Jul. 31, 2008 Page xxviii of xxx
27.5.2
Exit from Sleep Mode..................................................................................... 1217
27.6 All-Module-Clock-Stop Mode........................................................................................ 1218
27.7 Software Standby Mode.................................................................................................. 1219
27.7.1
Entry to Software Standby Mode.................................................................... 1219
27.7.2
Exit from Software Standby Mode ................................................................. 1219
27.7.3
Setting Oscillation Settling Time after Exit from Software Standby Mode.... 1220
27.7.4
Software Standby Mode Application Example............................................... 1222
27.8 Deep Software Standby Mode ........................................................................................ 1223
27.8.1
Entry to Deep Software Standby Mode .......................................................... 1223
27.8.2
Exit from Deep Software Standby Mode ........................................................ 1224
27.8.3
Pin State on Exit from Deep Software Standby Mode.................................... 1226
27.8.4
Bφ or SDRAMφ Operation after Exit from Deep Software Standby
Mode ............................................................................................................... 1227
27.8.5
Setting Oscillation Settling Time after Exit from Deep Software Standby
Mode ............................................................................................................... 1228
27.8.6
Deep Software Standby Mode Application Example ..................................... 1230
27.8.7
Flowchart of Deep Software Standby Mode Operation .................................. 1234
27.9 Hardware Standby Mode ................................................................................................ 1236
27.9.1
Transition to Hardware Standby Mode ........................................................... 1236
27.9.2
Clearing Hardware Standby Mode.................................................................. 1236
27.9.3
Hardware Standby Mode Timing.................................................................... 1236
27.9.4
Timing Sequence at Power-On ....................................................................... 1237
27.10 Sleep Instruction Exception Handling ............................................................................ 1238
27.11 φ Clock Output Control................................................................................................... 1241
27.12 Usage Notes .................................................................................................................... 1242
27.12.1 I/O Port Status................................................................................................. 1242
27.12.2 Current Consumption during Oscillation Settling Standby Period ................. 1242
27.12.3 Module Stop State of DMAC, EXDMAC, or DTC ........................................ 1242
27.12.4 On-Chip Peripheral Module Interrupts ........................................................... 1242
27.12.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC ..................................... 1242
27.12.6 Control of Input Buffers by DIRQnE (n = 3 to 0)........................................... 1243
27.12.7 Conflict between a transition to deep software standby mode and
interrupts ......................................................................................................... 1243
27.12.8 Bφ or SDRAMφ Output State ......................................................................... 1243
Section 28 List of Registers .............................................................................1245
28.1
28.2
28.3
Register Addresses (Address Order)............................................................................... 1246
Register Bits.................................................................................................................... 1264
Register States in Each Operating Mode ........................................................................ 1292
Rev. 2.00 Jul. 31, 2008 Page xxix of xxx
Section 29 Electrical Characteristics ............................................................... 1313
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
Absolute Maximum Ratings ........................................................................................... 1313
DC Characteristics, H8SX/1648 Group, H8SX/1648A Group, and H8SX/1648G
Group .............................................................................................................................. 1314
DC Characteristics H8SX/1648L Group and H8SX/1648H Group.............................. 1318
AC Characteristics .......................................................................................................... 1322
29.4.1
Clock Timing .................................................................................................. 1322
29.4.2
Control Signal Timing .................................................................................... 1325
29.4.3
Bus Timing ..................................................................................................... 1326
29.4.4
Timing of DMAC and EXDMAC .................................................................. 1356
29.4.5
Timing of On-Chip Peripheral Modules ......................................................... 1361
A/D Conversion Characteristics ..................................................................................... 1368
D/A Conversion Characteristics ..................................................................................... 1369
Flash Memory Characteristics ........................................................................................ 1370
Power-On Reset Circuit and Voltage-Detection Circuit Characteristics
(H8SX/1648L Group, H8SX/1648H Group) .................................................................. 1372
Appendix ........................................................................................................... 1375
A.
B.
C.
D.
Port States in Each Pin State........................................................................................... 1375
Product Lineup................................................................................................................ 1381
Package Dimensions....................................................................................................... 1382
Treatment of Unused Pins............................................................................................... 1384
Main Revisions and Additions in this Edition................................................... 1387
Index ................................................................................................................. 1431
Rev. 2.00 Jul. 31, 2008 Page xxx of xxx
Section 1 Overview
Section 1 Overview
1.1
Features
The core of each product in the H8SX/1648 Group, H8SX/1648A Group, H8SX/1648L Group,
H8SX/1648G Group, and H8SX/1648H Group of CISC (complex instruction set computer)
microcontrollers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU
provides upward-compatibility with the CPUs of other Renesas Technology-original
microcontrollers; H8/300, H8/300H, and H8S.
As peripheral functions, each LSI of the Group includes a DMA controller and EXDMA
controller*1, which enable high-speed data transfer, and a bus-state controller, which enables
direct connection to different kinds of memory. The LSI of the Group also includes serial
communication interfaces, A/D and D/A converters, and a multi-function timer that makes motor
control easy. Together, the modules realize low-cost configurations for end systems. The power
consumption of these modules is kept down dynamically by an on-chip power-management
function. The on-chip ROM is a flash memory (F-ZTATTM*) with a capacity of 1024 Kbytes
(H8SX/1648, H8SX/1648A, H8SX/1648L, H8SX/1648G, and H8SX/1648H), 512 Kbytes
(H8SX/1644, H8SX/1644A, H8SX/1644L, H8SX/1644G, and H8SX/1644H), or 256 Kbytes
(H8SX/1642, H8SX/1642A, H8SX/1642L, H8SX/1642G, and H8SX/1642H).
Note: 1. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
2. F-ZTATTM is a trademark of Renesas Technology Corp.
1.1.1
Applications
Examples of the applications of this LSI include PC peripheral equipment, optical storage devices,
office automation equipment, and industrial equipment.
Rev. 2.00 Jul. 31, 2008 Page 1 of 1438
REJ09B0365-0200
Section 1 Overview
1.1.2
Overview of Functions
Table 1.1 lists the functions of H8SX/1648 Group products in outline.
Table 1.2 shows the comparison of support functions in each group.
Table 1.1
Overview of Functions
Module/
Classification Function
Description
Memory
ROM
•
ROM capacity: 1024 Kbytes, 512 Kbytes, or 256 Kbytes
RAM
•
RAM capacity: 56 Kbytes, 40 Kbytes, or 24 Kbytes
CPU
•
32-bit high-speed H8SX CPU (CISC type)
CPU
Upwardly compatible for H8/300, H8/300H, and H8S CPUs at
object level
•
General-register architecture (sixteen 16-bit general registers)
•
Eleven addressing modes
•
4-Gbyte address space
Program: 4 Gbytes available
Data: 4 Gbytes available
Operating
mode
•
87 basic instructions, classifiable as bit arithmetic and logic
instructions, multiply and divide instructions, bit manipulation
instructions, multiply-and-accumulate instructions, and others
•
Minimum instruction execution time: 20.0 ns (for an ADD
instruction while system clock Iφ = 50 MHz and
VCC = 3.0 to 3.6 V)
•
On-chip multiplier (16 × 16 → 32 bits)
•
Supports multiply-and-accumulate instructions
(16 × 16 + 42 → 42 bits)
•
Advanced mode
Normal, middle, or maximum mode is not supported.
Rev. 2.00 Jul. 31, 2008 Page 2 of 1438
REJ09B0365-0200
Section 1 Overview
Module/
Classification Function
Description
CPU
Mode 1: User boot mode
MCU
operating
mode
(selected by driving the MD2 and MD1 pins low and driving
the MD0 pin high)
Mode 2: Boot mode
(selected by driving the MD2 and MD0 pins low and driving
the MD1 pin high)
Mode 3: Boundary scan enabled single-chip mode
(selected by driving the MD2 pin low and driving the MD1
and MD0 pins high)
Mode 4: On-chip ROM disabled external extended mode, 16-bit bus
(selected by driving the MD1 and MD0 pins low and driving
the MD2 pin high)
Mode 5: On-chip ROM disabled external extended mode, 8-bit bus
(selected by driving the MD1 pin low and driving the MD2
and MD0 pins high)
Mode 6: On-chip ROM enabled external extended mode
(selected by driving the MD0 pin low and driving the MD2
and MD1 pins high)
Mode 7: Single-chip mode (can be externally extended)
(selected by driving the MD2, MD1, and MD0 pins high)
•
Low power consumption state (transition driven by the SLEEP
instruction)
Power on reset (POR)*3
•
At power-on or low power supply voltage, an internal reset
signal is generated
Voltage detection circuit
(LVD)*3
•
At low power supply voltage, an internal reset signal and an
interrupt are generated.
Rev. 2.00 Jul. 31, 2008 Page 3 of 1438
REJ09B0365-0200
Section 1 Overview
Module/
Classification Function
Interrupt
(source)
Interrupt
controller
(INTC)
Description
•
Seventeen external interrupt pins (NMI, and IRQ15 to IRQ0)
•
Number of internal interrupt sources
H8SX/1648, H8SX/1648A Group: 113 pins
H8SX/1648L: 114 pins
H8SX/1648G: 123 pins
H8SX/1648H: 124 pins
Break
interrupt
(UBC)
DMA
•
Two interrupt control modes (specified by the interrupt control
register)
•
Eight priority orders specifiable (by setting the interrupt priority
register)
•
Independent vector addresses
•
Break point can be set for four channels
•
Address break can be set for CPU instruction fetch cycles
EXDMA
•
controller
•
(EXDMAC)*1
•
DMA
controller
(DMAC)
Four-channel DMA transfer available
Two activation methods (auto-request and external request)
Four transfer modes (normal, repeat, block, and cluster transfer)
•
Dual or single address mode selectable
•
Extended repeat area function
•
Four-channel DMA transfer available
•
Three activation methods (auto-request, on-chip module
interrupt, and external request)
•
Three transfer modes (normal, repeat, and block transfer)
•
Dual or single address mode selectable
•
Extended repeat area function
Data transfer •
controller
(DTC)
H8SX/1648, H8SX/1648A, and H8SX/1648L Groups:
Allow DMA transfer over 76 channels (number of DTC activation
sources)
•
H8SX/1648G and H8SX/1648H Groups:
•
Allow DMA transfer over 84 channels (number of DTC activation
sources)
•
Activated by interrupt sources (chain transfer enabled)
•
Three transfer modes (normal, repeat, and block transfer)
•
Short-address mode or full-address mode selectable
Rev. 2.00 Jul. 31, 2008 Page 4 of 1438
REJ09B0365-0200
Section 1 Overview
Module/
Classification Function
External bus
extension
Bus
controller
(BSC)
Description
•
16-Mbyte external address space
•
The external address space can be divided into eight areas,
each of which is independently controllable
 Chip-select signals (CS0 to CA7) can be output
 Access in two or three states can be selected for each area
 Program wait cycles can be inserted
 The period of CS assertion can be extended
 Idle cycles can be inserted
•
Bus arbitration function (arbitrates bus mastership among the
1
1
internal CPU, DMAC, EXDMAC* , DTC, refresh* , and external
bus masters)
Bus formats
Clock
Clock pulse
generator
(CPG)
•
External memory interfaces (for the connection of ROM, burst
1
1
ROM, SRAM* , byte control SRAM, DRAM* , synchronous
1
DRAM* )
•
Address/data bus format: Support for both separate and
multiplexed buses (8-bit access or 16-bit access)
•
Endian conversion function for connecting devices in littleendian format
•
One clock generation circuit available
•
Separate clock signals are provided for each of functional
modules (detailed below) and each is independently specifiable
(multi-clock function)
 System-intended data transfer modules, i.e. the CPU, runs in
synchronization with the system clock (Iφ): 8 to 50 MHz
 Internal peripheral functions run in synchronization with the
peripheral module clock (Pφ): 8 to 35 MHz
 Modules in the external space are supplied with the external
bus clock (Bφ): 8 to 50 MHz
•
Includes a PLL frequency multiplication circuit and frequency
divider, so the operating frequency is selectable
•
Five low-power-consumption modes: sleep mode, all-moduleclock-stop mode, software standby mode, deep software
standby mode, and hardware standby mode
Rev. 2.00 Jul. 31, 2008 Page 5 of 1438
REJ09B0365-0200
Section 1 Overview
Module/
Classification Function
A/D converter
A/D
converter
(ADC)
Description
•
•
10-bit resolution × three units
Selectable input channel and unit configuration
Four channels × three units (units 0, 1, and 2)
•
•
•
•
Eight channels × one unit (unit 0) + four channels × one unit
(unit 2)
Sample and hold function included
Conversion time: 2.7 µs per channel (with peripheral module
clock (Pφ) at 25-MHz operation)
Two operating modes: single mode and scan mode
Three ways to start A/D conversion:
Unit 0: Software, timer (TPU/TMR (units 0 and 1)) trigger, and
external trigger
Unit 1: Software, TMR (units 2 and 3) trigger, and external
trigger
•
Unit 2: Software, TMR (units 2 and 3) trigger, and external
trigger
Activation of DTC and DMAC by ADI interrupt:
Unit 0: DTC and DMAC can be activated by an ADI0 interrupt.
Unit 1: DMAC can be activated by an ADI1 interrupt.
Unit 2: DMAC can be activated by an ADI2 interrupt.
D/A converter
D/A
converter
(DAC)
•
•
8-bit resolution × two output channels
Output voltage: 0 V to Vref, maximum conversion time: 10 µs
(with 20-pF load)
Timer
8-bit timer
(TMR)
•
•
8 bits × eight channels (can be used as 16 bits × four channels)
Select from among seven clock sources (six internal clocks and
one external clock)
Allows the output of pulse trains with a desired duty cycle or
PWM signals
•
Rev. 2.00 Jul. 31, 2008 Page 6 of 1438
REJ09B0365-0200
Section 1 Overview
Module/
Classification Function
Timer
Watchdog
timer
Description
16-bit timer
pulse unit
(TPU)
•
•
•
•
16 bits × 12* channels (general pulse timer unit)
Select from among eight counter-input clocks for each channel
Up to 16 pulse inputs and outputs
Counter clear operation, simultaneous writing to multiple timer
counters (TCNT), simultaneous clearing by compare match and
input capture possible, simultaneous input/output for registers
possible by counter synchronous operation, and up to 15-phase
PWM output possible by combination with synchronous
operation
• Buffered operation, cascaded operation (32 bits × two
channels), and phase counting mode (two-phase encoder input)
settable for each channel
• Input capture function supported
• Output compare function (by the output of compare match
waveform) supported
Note: * The pin function of unit 1 cannot be used in external bus
extended mode.
Programmable pulse
generator
(PPG)
•
•
Watchdog
timer (WDT)
•
•
32K timer
32K timer
(TM32K)
1
2
32-bit* * pulse output
Four output groups, non-overlapping mode, and inverted output
can be set
• Selectable output trigger signals; the PPG can operate in
conjunction with the data transfer controller (DTC) and the DMA
controller (DMAC)
Notes: 1. Pulse output pins PO31 to PO16 cannot be activated by
input capture.
2. Pulse of unit 1 cannot be output in external bus
extended mode.
•
•
•
•
8 bits × one channels (selectable from eight counter input
clocks)
Switchable between watchdog timer mode and interval timer
mode
Eight counter clocks which divides the 32.768 Hz clock can be
selected
8 bits x one channel or 24 bits x 1 channel can be selected
Interrupts can be generated when the counter overflows
Eight overflow cycles selectable (250 msec, 500 msec, 1 sec, 2
sec, 30 sec, 60 sec, about 23 days, and about 48 days)
Rev. 2.00 Jul. 31, 2008 Page 7 of 1438
REJ09B0365-0200
Section 1 Overview
Module/
Classification Function
Serial interface Serial
communication
interface
(SCI)
Description
•
•
•
•
•
•
•
Smart
card/SIM
I2C bus
interface
I2C bus
interface 2
(IIC2)
•
•
•
I/O ports
•
Four channels
Bus can be directly driven (the SCL and SDA pins are NMOS
open drains).
IIC2 (unit 1) is open drain pins supporting 5 V input.
•
•
•
•
Input-only pins:
H8SX/1648 Group, H8SX/1648A Group, H8SX/1648L Group: 13
pins each.
H8SX/1648G Group, H8SX/1648H Group: 13 pins each.
Input/Output pins:
H8SX/1648 Group, H8SX/1648A Group, H8SX/1648L Group: 97
pins each.
H8SX/1648G Group, H8SX/1648H: 102 pins each.
Eight large-current drive pins (port 3)
40 pull-up resistors
16 open drains
Four open-drain I/O pins supporting 5 V input
•
•
LQFP-144 package*2
1
LFBGA176 package*
•
Package
Seven channels (select asynchronous or clock synchronous
serial communication mode)
Full-duplex communication capability
Select the desired bit rate and LSB-first or MSB-first transfer
Transfer rate clock input from TMR (SCI_5, SCI_6)
IrDA transmission and reception conformant with the IrDA
Specifications version 1.0
On-chip cyclic redundancy check (CRC) calculator for improved
reliability in data transfer
The SCI module supports a smart card (SIM) interface.
Rev. 2.00 Jul. 31, 2008 Page 8 of 1438
REJ09B0365-0200
Section 1 Overview
Module/
Classification Function
Description
Operating frequency/
Power supply voltage
•
Operating frequency: 8 to 50 MHz
Operating peripheral
temperature (°C)
•
•
−20 to +75°C (regular specifications)
−40 to +85°C (wide-range specifications)
Notes: 1. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
2. Supported only by the H8SX/1648 Group, the H8SX/1648A Group, and the
H8SX/1648L Group.
3. Supported only by the H8SX/1648L Group and the H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 9 of 1438
REJ09B0365-0200
Section 1 Overview
Table 1.2
Comparison of Support Functions in the H8SX/1648, 1648A, 1648L, 1648G, and
1648H Groups
Function
The H8SX/1648
and H8SX/1648A
Group*
The H8SX/1648L
Group
The H8SX/1648G
Group
The H8SX/1648H
Group
DMAC
O
O
O
O
DTC
O
O
O
O
PPG
O
O
O
O
UBC
O
O
O
O
SCI
O
O
O
O
IIC2
O
O
O
O
TMR
O
O
O
O
WDT
O
O
O
O
10-bit ADC
O
O
O
O
8-bit DAC
O
O
O
O
EXDMAC


O
O
SDRAM interface


O
O
32K timer


O
O
POR/LVD

O

O
Package
Note:
*
LQFP-144
O
O


LFBGA-176


O
O
The setting method of Port 6 differs in the H8SX/1648 Group and the H8SX/1648A
Group. For details, see section 13.2.5, Port 6.
Rev. 2.00 Jul. 31, 2008 Page 10 of 1438
REJ09B0365-0200
Section 1 Overview
1.2
List of Products
Table 1.3 is the list of products, and figure 1.1 shows how to read the product name code.
Table 1.3
List of Products
Group
Part No.
ROM
Capacity
RAM
Capacity
Package
Remarks
H8SX/1648
R5F61648N50FPV
1024 Kbytes
56 Kbytes
LQFP-144
R5F61644N50FPV
512 Kbytes
40 Kbytes
LQFP-144
Regular
specifications
R5F61642N50FPV
256 Kbytes
24 Kbytes
LQFP-144
R5F61648D50FPV
1024 Kbytes
56 Kbytes
LQFP-144
R5F61644D50FPV
512 Kbytes
40 Kbytes
LQFP-144
R5F61642D50FPV
256 Kbytes
24 Kbytes
LQFP-144
R5F61648AN50FPV
1024 Kbytes
56 Kbytes
LQFP-144
R5F61644AN50FPV
512 Kbytes
40 Kbytes
LQFP-144
R5F61642AN50FPV
256 Kbytes
24 Kbytes
LQFP-144
R5F61648AD50FPV
1024 Kbytes
56 Kbytes
LQFP-144
R5F61644AD50FPV
512 Kbytes
40 Kbytes
LQFP-144
R5F61642AD50FPV
256 Kbytes
24 Kbytes
LQFP-144
R5F61648GN50BGV 1024 Kbytes
56 Kbytes
LFBGA-176
R5F61644GN50BGV 512 Kbytes
40 Kbytes
LFBGA-176
R5F61642GN50BGV 256 Kbytes
24 Kbytes
LFBGA-176
R5F61648GD50BGV 1024 Kbytes
56 Kbytes
LFBGA-176
R5F61644GD50BGV 512 Kbytes
40 Kbytes
LFBGA-176
R5F61642GD50BGV 256 Kbytes
24 Kbytes
LFBGA-176
R5F61648LN50FPV
1024 Kbytes
56 Kbytes
LQFP-144
R5F61644LN50FPV
512 Kbytes
40 Kbytes
LQFP-144
R5F61642LN50FPV
256 Kbytes
24 Kbytes
LQFP-144
R5F61648LD50FPV
1024 Kbytes
56 Kbytes
LQFP-144
R5F61644LD50FPV
512 Kbytes
40 Kbytes
LQFP-144
R5F61642LD50FPV
256 Kbytes
24 Kbytes
LQFP-144
H8SX/1648A
H8SX/1648G
H8SX/1648L
Wide range
specifications
Regular
specifications
Wide range
specifications
Regular
specifications
Wide range
specifications
Regular
specifications
Wide range
specifications
Rev. 2.00 Jul. 31, 2008 Page 11 of 1438
REJ09B0365-0200
Section 1 Overview
RAM
Capacity
Package
Remarks
R5F61648HN50BGV 1024 Kbytes
56 Kbytes
LFBGA-176
R5F61644 HN50BGV 512 Kbytes
40 Kbytes
LFBGA-176
Regular
specifications
R5F61642 HN50BGV 256 Kbytes
24 Kbytes
LFBGA-176
R5F61648HD50BGV 1024 Kbytes
56 Kbytes
LFBGA-176
R5F61644 HD50BGV 512 Kbytes
40 Kbytes
LFBGA-176
R5F61642 HD50BGV 256 Kbytes
24 Kbytes
LFBGA-176
Group
Part No.
H8SX/1648H
R
Part No.
5
ROM
Capacity
F 61648N50 FP
Wide range
specifications
V
Indicates the Pb-free version.
Indicates the package.
FP: LQFP
BG: LFBGA
Indicates the product-specific number.
N: Regular specification
D: Wide range specification
Indicates the type of ROM device.
F: On-chip flash memory
Product classification
Microcontroller
Indicates a Renesas semiconductor product.
Figure 1.1 How to Read the Product Name Code
• Small Package
Package
Package Code
LQFP-144
PLQP0144KA-A (FP-144LV)* 20.0 × 20.0 mm
0.50 mm
LFBGA-176
PLBG0176GA-A (BP-176V)*
13.0 × 13.0 mm
0.80 mm
Note:
*
Pb-free version
Rev. 2.00 Jul. 31, 2008 Page 12 of 1438
REJ09B0365-0200
Body Size
Pin Pitch
Section 1 Overview
Block Diagram
Interrupt
controller
DTC
Main clock
oscillator
POR/LVD*3
WDT
Port 2
PPG × 16 channels
(Unit0)
PPG × 16 channels
(Unit1)
SCI × 7 channels
IIC2 × 4 channels
10-bit AD ×
4 channels (Unit0)
10-bit AD ×
4 channels (Unit1)
10-bit AD ×
4 channels (Unit2)
EXDMAC ×
4 channels*2
Sub clock
osillator*2
Port 1
TPU × 6 channels
(Unit0)
TPU × 6 channels
(Unit1)
DMAC ×
4 channels
Internal system bus
H8SX
CPU
Internal system bus
BSC
ROM
TM32K*2
TMR × 2 channels
(Unit0)
TMR × 2 channels
(Unit1)
TMR × 2 channels
(Unit2)
TMR × 2 channels
(Unit3)
RAM
Internal system bus
1.3
8-bitDA ×
2 channels
Port 3
Port 4
Port 5
Port 6
Port A
Port B
Port C
Port D/
Port J*1
Port E/
Port K*1
Port F
Port H
Port I
Port N
Port M*2
External bus
[Legend]
CPU:
DTC:
BSC:
DMAC:
EXDMAC*2:
TM32K*2:
WDT:
Central processing unit
Data transfer controller
Bus controller
DMA controller
EXDMA Controller
32K Timer
Watchdog timer
TMR:
TPU:
PPG:
SCI:
IIC2:
POR/LVD*3:
8-bit timer
16-bit timer pulse unit
Programmable pulse generator
Serial communications interface
IIC bus interface 2
Power-on reset / Low voltage detection circuit
Note: *1 In single-chip mode, the port D and port E functions can be used in the initial state.
Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled
when PCJKE = 0 (initial value) and ports J and K are enabled when PCJKE = 1. In external
extended mode, only ports D and E can be used.
*2 Supported only by the H8SX/1648G Group and H8SX/1648H Group.
*3 Supported only by the 8SX/1648L Group and H8SX/1648H Group.
Figure 1.2 Block Diagram
Rev. 2.00 Jul. 31, 2008 Page 13 of 1438
REJ09B0365-0200
Section 1 Overview
1.4
Pin Assignments
P61/TMCI2/RxD4/TEND2/IRQ9-B
P60/TMRI2/TxD4/DREQ2/IRQ8-B
P37/PO15/TIOCA2/TIOCB2/TCLKD-A
P36/PO14/TIOCA2
P35/PO13/TIOCA1/TIOCB1/TCLKC-A/DACK1-B
VSS
STBY
P17/TCLKD-B/SCL0/ADTRG1-A/IRQ7-A
P16/TCLKC-B/SCK3/SDA0/DACK1-A/IRQ6-A
Vcc
EXTAL
XTAL
Vss
WDTOVF/TDO
P15/TCLKB-B/RxD3/SCL1/TEND1-A/IRQ5-A
P14/TCLKA-B/TxD3/SDA1/DREQ1-A/IRQ4-A
VCL
RES
P67/IRQ15-B
P66
VSS
P13/ADTRG0-A/IRQ3-A
P12/SCK2/DACK0-A/IRQ2-A
P11/RxD2/TEND0-A/IRQ1-A
P10/TxD2/DREQ0-A/IRQ0-A
PI7/D15
PI6/D14
PI5/D13
PI4/D12
Vss
PI3/D11
PI2/D10
PI1/D9
PI0/D8
VCC
PH7/D7
1.4.1
Pin Assignments
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
109
72
110
71
111
70
112
69
113
68
114
67
115
66
116
65
117
64
118
63
119
62
120
61
121
60
122
59
123
58
124
57
125
56
LQFP-144
(Top Vew)
126
127
55
54
128
53
129
52
130
51
131
50
132
49
133
48
134
47
135
46
136
45
137
44
138
43
139
42
140
41
141
40
142
39
38
143
144
1
2
3
4
5
6
7
8
37
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
PH6/D6
PH5/D5
PH4/D4
VSS
PH3/D3
PH2/D2
PH1/D1
PH0/D0
VCC
P34/PO12/TIOCA1/TEND1-B
P33/PO11/TIOCC0/TIOCD0/TCLKB-A/DREQ1-B
NMI
P27/PO7/TIOCA5/TIOCB5/IRQ15-A
P26/PO6/TIOCA5/TMO1/TxD1/IRQ14
P32/PO10/TIOCC0/TCLKA-A/DACK0-B
P31/PO9/TIOCA0/TIOCB0/TEND0-B
P30/PO8/TIOCA0/DREQ0-B
P25/PO5/TIOCA4/TMCI1/RxD1/IRQ13-A
P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1/IRQ12-A
P23/PO3/TIOCC3/TIOCD3/IRQ11-A
P22/PO2/TIOCC3/TMO0/TxD0/IRQ10-A
P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A
VCC
P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A
VSS
PC4/ADTRG2
PC1/CS4-C/CS5-C/CS6-C/CS7-C
PC0/CS3-B/WAIT-B/ADTRG1-B
PB6/CS6-D/(RD/WR-B)/ADTRG0-B
PB5/CS5-D
PB4/CS4-B
PN3/SCL3
PN2/SDA3
EMLE *2
PJ0/PO16/TIOCA6
PD0/A0
PD1/A1
PJ1/PO17/TIOCA6/TIOCB6
*1
PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B
PB2/CS2-A/CS6-A
PB3/CS3-A/CS7-A
VSS
PB7/CS7-D
VCC
MD2
PN0/SDA2
PN1/SCL2
PC5
PF7/A23/SCK5
PF6/A22/RxD5/IrRxD
PF5/A21/TxD5/IrTxD
PF4/A20
PF3/A19
VSS
PF2/A18
PF1/A17
PF0/A16
PK7/PO31/TIOCA11/TIOCB11
PE7/A15
PK6/PO30/TIOCA11
PE6/A14
PK5/PO29/TIOCA10/TIOCB10
PE5/A13
VSS
PK4/PO28/TIOCA10
PE4/A12
VCC
PE3/A11
PK3/PO27/TIOCC9/TIOCD9
PE2/A10
PK2/PO26/TIOCC9
PE1/A9
PK1/PO25/TIOCA9/TIOCB9
PE0/A8
PK0/PO24/TIOCA9
PD7/A7
PJ7/PO23/TIOCA8/TIOCB8/TCLKH
PD6/A6
PJ6/PO22/TIOCA8
VSS
PJ5/PO21/TIOCA7/TIOCB7/TCLKG
PD5/A5
PJ4/PO20/TIOCA7
PD4/A4
PJ3/PO19/TIOCC6/TIOCD6/TCLKF
PD3/A3
PJ2/PO18/TIOCC6/TCLKE
PD2/A2
P62/TMO2/SCK4/DACK2/IRQ10-B/TRST
PLLVCC
P63/TMRI3/TxD6/DREQ3/IRQ11-B/TMS
PLLVSS
P64/TMCI3/RxD6/TEND3/IRQ12-B/TDI
P65/TMO3/SCK6/DACK3/IRQ13-B/TCK
MD0
PC2
PC3
P50/AN0/IRQ0-B
P51/AN1/IRQ1-B
P52/AN2/IRQ2-B
AVcc
P53/AN3/IRQ3-B
AVss
P54/AN4/IRQ4-B
Vref
P55/AN5/IRQ5-B
P56/AN6/DA0/IRQ6-B
P57/AN7/DA1/IRQ7-B
P44/AN8
P45/AN9
P46/AN10
P47/AN11
MD1
PA0/BREQO/BS-A
PA1/BACK/(RD/WR-A)
PA2/BREQ/WAIT-A
PA3/LLWR/LLB
PA4/LHWR/LUB
PA5/RD
PA6/AS/AH/BS-B
Vss
PA7/Bφ
Vcc
PB0/CS0/CS4-A/CS5-B
*1
Notes: 1. In single-chip mode prots D and E can be used (initial state). Pin functions are selectable by setting the PCJKE bit in PFCRD.
Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value)
and ports J and K are enabled when PCJKE = 1. In external extended mode, only ports D and E can be used.
2. This pin is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode.
The on-chip emulator function is enabled by driving this pin high. When the on-chip emulator is in use, the P62, P63,
P64, P65, and WDTOVF pins are dedicated pins for the on-chip emulator. For details on a connection example with the E10A,
see E10A Emulator User's Manual.
Figure 1.3 Pin Assignments (LQFP-144: H8SX/1648, 1648A, and 1648L Groups)
Rev. 2.00 Jul. 31, 2008 Page 14 of 1438
REJ09B0365-0200
Section 1 Overview
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
PB1
Vcc
Vcc
PA4
PA1
NC*3
P47
P57
Vref
AVcc
P51
PC3
P65
NC*3
PLLVcc
A
B
PB3
PB0
PA7
PA5
PA2
MD3*4
MD1
P44
NC*3
P53
P50
MD0
PLLVss
P62
P61
B
C
Vcc
Vss
PB2
PA6
PA0
NC*3
P46
P56
P54
NC *3
NC*3
P64
P63
P60
P36
C
D
PN0
MD2
PB7
Vss
PA3
NC*3
P45
P55
AVss
P52
PC2
P37
P35
Vss
STBY
D
E
PM2
PN1
PM1
PM0
PB4
P80
P17
NC*3
P16
Vcc
E
F
PF6
PF5
PF7
PC5
WDTOVF
Vss
EXTAL
XTAL
F
G
Vss
Vss
PF3
PF4
RES
VCL
P15
P14
G
P67
NC*3
LFBGA-176
(Top view)
OSC1*4 OSC2*4
H
PF0
PE7*1
PF1
PF2
J
Vss
PE4*1
PE5*1
PE6*1
P13
Vss
P66
Vss
J
K
PE3*1
PE2*1
NC*3
Vcc
PI7
P10
P12
P11
K
L
PE0*1
PD7*1
PE1*1
PD6*1
PI3
PI4
PI5
PI6
L
M
Vss
Vss
PD5*1
PD3*1
NC*3
PB4
NC*3
P20
P23
P31
Vcc
Vss
PI0
PI2
Vss
M
N
PD4*1
PD2*1
PN2
PM4
NC*3
PB5
PC1
Vcc
P24
P32
NMI
PH2
Vss
NC*3
PI1
N
P
PD1*1
PD0*1
PN3
NC*3
Vss
PC0
Vss
P22
P30
P27
P34
PH1
PH4
PH6
Vcc
P
R
EMLE*2
PM3
Vcc
NC*3
NC*3
PB6
PC4
P21
P25
P26
P33
PH0
PH3
PH5
PH7
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
P23
H
Notes: 1. In single-chip mode prots D and E can be used (initial state). Pin functions are selectable by setting the PCJKE bit in PFCRD.
Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value)
and ports J and K are enabled when PCJKE = 1. In external extended mode, only ports D and E can be used.
2. This pin is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode.
The on-chip emulator function is enabled by driving this pin high. When the on-chip emulator is in use, the P62, P63,
P64, P65, and WDTOVF pins are dedicated pins for the on-chip emulator. For details on a connection example with the E10A,
see E10A Emulator User's Manual.
3. NC should be left open.
Figure 1.4 Pin Assignments (LFBGA-176: H8SX/1648G and 1648H Groups)
Rev. 2.00 Jul. 31, 2008 Page 15 of 1438
REJ09B0365-0200
Section 1 Overview
1.4.2
Correspondence between Pin Configuration and Operating Modes
Table 1.4
Pin Configuration in Each Operating Mode (H8SX/1648, 1648A, 1648G, and
1648H Groups)
Pin no.
Pin name
LQFP144
LFBGA176
Mode 1, 2, 6
1
A1
PB1/CS1/CS2-B/CS5-A/
CS6-B/CS7-B
2
C3
PB2/CS2-A/CS6-A/RAS*
3
B1
4
C2
PB1/CS1/CS2-B/CS5-A/
CS6-B/CS7-B
PB1/CS1/CS2-B/CS5-A/
CS6-B/CS7-B
PB2/CS2-A/CS6-A/RAS*
PB3/CS3-A/CS7-A/CAS*
3
VSS
D3
PB7/CS7-D/SDRAMφ*
6
C1
VCC
7
D2
MD2
E4
Mode 4. 5
3
5

Mode 3, 7
3
3
PB2/CS2-A/CS6-A/RAS*
PB3/CS3-A/CS7-A/CAS*
3
PB3/CS3-A/CS7-A/CAS*
VSS
VSS
PB7/CS7-D/SDRAMφ*
VCC
PM0*
3
PB7/CS7-D/SDRAMφ*
VCC
MD2
3
3
3
MD2
3
3
PM0*
PM0*
PN0/SDA2
PN0/SDA2
8
D1
PN0/SDA2

E3
PM1*
PM1*
PM1*
9
E2
PN1/SCL2
PN1/SCL2
PN1/SCL2
3
3
3

E1
PM2*
PM2*
PM2*
10
F4
PC5
PC5
PC5
11
F3
PF7/A23/SCK5
PF7/A23/SCK5
PF7/A23/SCK5
12
F1
PF6/A22/RxD5/IrRxD
PF6/A22/RxD5/IrRxD
PF6/A22/RxD5/IrRxD
13
F2
PF5/A21/TxD5/IrTxD
PF5/A21/TxD5/IrTxD
PF5/A21/TxD5/IrTxD
14
G4
PF4/A20
PF4/A20
A20
15
G3
PF3/A19
PF3/A19
A19
16
G1
VSS
VSS
Vss

G2
VSS
VSS
VSS
17
H4
PF2/A18
PF2/A18
A18
18
H3
PF1/A17
PF1/A17
A17
19
H1
PF0/A16
PF0/A16
A16
20
H2
PE7/A15
PE7/A15
3
Rev. 2.00 Jul. 31, 2008 Page 16 of 1438
REJ09B0365-0200
3
3
PK7/PO31/
TIOCA11/
1
TIOCB11*
A15
3
Section 1 Overview
Pin no.
Pin name
LQFP144
LFBGA176
Mode 1, 2, 6
Mode 3, 7
21
J4
PE6/A14
PE6/A14
PK6/PO30/
1
TIOCA11*
A14
22
J3
PE5/A13
PE5/A13
PK5/PO29/
TIOCA10/
1
TIOCB10*
A13
23
J1
Vss
Vss
24
J2
PE4/A12
PE4/A12
25
K4
Vcc
Vcc
Vcc

K3
NC
NC
NC
26
K1
PE3/A11
PE3/A11
PK3/PO27/
TIOCC9/
1
TIOCD9*
A11
27
K2
PE2/A10
PE2/A10
PK2/PO26/
1
TIOCC9*
A10
28
L3
PE1/A9
PE1/A9
PK1/PO25/
A9
1
TIOCA9/TIOCB9*
29
L1
PE0/A8
PE0/A8
PK0/PO24/
1
TIOCA9*
A8
30
L2
PD7/A7
PD7/A7
PJ7/PO23/
TIOCA8/TIOCB8/
1
TCLKH*
A7
31
L4
PD6/A6
PD6/A6
PJ6/PO22/
1
TIOCA8*
A6
32
M1
Vss
Vss
Vss

M2
Vss
Vss
Vss
33
M3
PD5/A5
PD5/A5
PJ5/PO21/
TIOCA7/TIOCB7/
1
TCLKG*
A5
34
N1
PD4/A4
PD4/A4
PJ4/PO20/
1
TIOCA7*
A4
35
M4
PD3/A3
PD3/A3
A3
PJ3/PO19/
TIOCC6/TIOCD6/
1
TCLKF*
36
N2
PD2/A2
PD2/A2
PJ2/PO18/
A2
1
TIOCC6/TCLKE*
Mode 4. 5
Vss
PK4/PO28/
1
TIOCA10*
A12
Rev. 2.00 Jul. 31, 2008 Page 17 of 1438
REJ09B0365-0200
Section 1 Overview
Pin no.
Pin name
LQFP144
LFBGA176
Mode 1, 2, 6
Mode 3, 7
37
P1
PD1/A1
PD1/A1
PJ1/PO17/
A1
1
TIOCA6/TIOCB6*
38
P2
PD0/A0
PD0/A0
PJ0/PO16/
1
TIOCA6*
39
R1
EMLE
EMLE
EMLE
40
N3
PN2/SDA3
PN2/SDA3
PN2/SDA3
Mode 4. 5
A0

R2
PM3*
PM3*
PM3*
41
P3
PN3/SCL3
PN3/SCL3
PN3/SCL3
3
3
3

N4
PM4*
PM4*
PM4*

R3
VCC
VCC
VCC

P4
NC
NC
NC

M5
NC
NC
NC

R4
NC
NC
NC

N5
NC
NC
NC

P5
Vss
Vss
Vss

R5
NC
3
3
3
NC
3
M6
PB4/CS4-B/WE*
43
N6
PB5/CS5-D/OE/CKE*
PB5/CS5-D/OE/CKE*
PB5/CS5-D/OE/CKE*
44
R6
PB6/CS6-D/
(RD/WR-B)/ADTRG0-B
PB6/CS6-D/
(RD/WR-B)/ADTRG0-B
PB6/CS6-D/
(RD/WR-B)/ADTRG0-B
45
P6
PC0/CS3-B/WAITB/ADTRG1-B
PC0/CS3-B/WAIT-B/
ADTRG1-B
PC0/CS3-B/
WAIT-B/ADTRG1-B

M7
NC
NC
NC
46
N7
PC1/CS4-C/CS5-C/
CS6-C/CS7-C
PC1/CS4-C/CS5-C/
CS6-C/CS7-C
PC1/CS4-C/CS5-C/
CS6-C/CS7-C
47
R7
PC4/ADTRG2
PC4/ADTRG2
PC4/ADTRG2
48
P7
VSS
VSS
VSS
49
M8
P20/PO0/TIOCA3/TIOCB3/
TMRI0/SCK0/IRQ8-A
P20/PO0/TIOCA3/TIOCB3/
TMRI0/SCK0/IRQ8-A
P20/PO0/TIOCA3/TIOCB3/
TMRI0/SCK0/IRQ8-A
50
N8
VCC
VCC
VCC
51
R8
P21/PO1/TIOCA3/TMCI0/
RxD0/IRQ9-A
P21/PO1/TIOCA3/TMCI0/
RxD0/IRQ9-A
P21/PO1/TIOCA3/TMCI0/
RxD0/IRQ9-A
3
Rev. 2.00 Jul. 31, 2008 Page 18 of 1438
PB4/CS4-B/WE*
3
42
REJ09B0365-0200
PB4/CS4-B/WE*
NC
3
3
3
Section 1 Overview
Pin no.
Pin name
LQFP144
LFBGA176
Mode 1, 2, 6
52
P8
53
Mode 3, 7
Mode 4. 5
P22/PO2/TIOCC3/TMO0/
TxD0/IRQ10-A
P22/PO2/TIOCC3/TMO0/
TxD0/IRQ10-A
P22/PO2/TIOCC3/TMO0/
TxD0/IRQ10-A
M9
P23/PO3/TIOCC3/TIOCD3/
IRQ11-A
P23/PO3/TIOCC3/TIOCD3/
IRQ11-A
P23/PO3/TIOCC3/TIOCD3/
IRQ11-A
54
N9
P24/PO4/TIOCA4/TIOCB4/
TMRI1/SCK1/IRQ12-A
P24/PO4/TIOCA4/TIOCB4/
TMRI1/SCK1/IRQ12-A
P24/PO4/TIOCA4/TIOCB4/
TMRI1/SCK1/IRQ12-A
55
R9
P25/PO5/TIOCA4/TMCI1/
RxD1/IRQ13-A
P25/PO5/TIOCA4/TMCI1/
RxD1/IRQ13-A
P25/PO5/TIOCA4/TMCI1/
RxD1/IRQ13-A
56
P9
P30/PO8/TIOCA0/
3
DREQ0-B/EDREQ2*
P30/PO8/TIOCA0/
3
DREQ0-B/EDREQ2*
P30/PO8/TIOCA0/
3
DREQ0-B/EDREQ2*
57
M10
P31/PO9/TIOCA0/TIOCB0/
3
TEND0-B/ETEND2*
P31/PO9/TIOCA0/TIOCB0/
3
TEND0-B/ETEND2*
P31/PO9/TIOCA0/TIOCB0/
3
TEND0-B/ETEND2*
58
N10
P32/PO10/TIOCC0/TCLKA-A/ P32/PO10/TIOCC0/TCLKA-A/ P32/PO10/TIOCC0/TCLKA3
3
DACK0-B/EDACK2*
DACK0-B/EDACK2*
A/
3
DACK0-B/EDACK2*
59
R10
P26/PO6/TIOCA5/TMO1/
TxD1/IRQ14
P26/PO6/TIOCA5/TMO1/
TxD1/IRQ14
P26/PO6/TIOCA5/TMO1/
TxD1/IRQ14
60
P10
P27/PO7/TIOCA5/TIOCB5/
IRQ15-A
P27/PO7/TIOCA5/TIOCB5/
IRQ15-A
P27/PO7/TIOCA5/TIOCB5/
IRQ15-A
61
N11
NMI
NMI
NMI
62
R11
P33/PO11/TIOCC0/TIOCD0/
TCLKB-A/DREQ1-B/
3
EDREQ3*
P33/PO11/TIOCC0/TIOCD0/
TCLKB-A/DREQ1-B/
3
EDREQ3*
P33/PO11/TIOCC0/TIOCD0/
TCLKB-A/DREQ1-B/
3
EDREQ3*
63
P11
P34/PO12/TIOCA1/
3
TEND1-B/ETEND3*
P34/PO12/TIOCA1/
3
TEND1-B/ETEND3*
P34/PO12/TIOCA1/
3
TEND1-B/ETEND3*
64
M11
VCC
VCC
VCC
65
R12
PH0/D0
PH0/D0
D0
66
P12
PH1/D1
PH1/D1
D1
67
N12
PH2/D2
PH2/D2
D2
68
R13
PH3/D3
PH3/D3
D3
69
M12
VSS
VSS
VSS
70
P13
PH4/D4
PH4/D4
D4
71
R14
PH5/D5
PH5/D5
D5
72
P14
PH6/D6
PH6/D6
D6
Rev. 2.00 Jul. 31, 2008 Page 19 of 1438
REJ09B0365-0200
Section 1 Overview
Pin no.
Pin name
LQFP144
LFBGA176
Mode 1, 2, 6
Mode 3, 7
Mode 4. 5
73
R15
PH7/D7
PH7/D7
D7

N13
Vcc
Vcc
Vcc
74
P15
Vcc
Vcc
Vcc

N14
NC
NC
NC
75
M13
PI0/D8
PI0/D8
PI0/D8
76
N15
PI1/D9
PI1/D9
PI1/D9
77
M14
PI2/D10
PI2/D10
PI2/D10
78
L12
PI3/D11
PI3/D11
PI3/D11
79
M15
Vss
Vss
Vss
80
L13
PI4/D12
PI4/D12
PI4/D12
81
L14
PI5/D13
PI5/D13
PI5/D13
82
L15
PI6/D14
PI6/D14
PI6/D14
83
K12
PI7/D15
PI7/D15
PI7/D15
84
K13
P10/TxD2/DREQ0-A/
3
EDREQ0-A* /IRQ0-A
P10/TxD2/DREQ0-A/
3
EDREQ0-A* /IRQ0-A
P10/TxD2/DREQ0-A/
3
EDREQ0-A* /IRQ0-A
85
K15
P11/RxD2/TEND0-A/
3
ETEND0-A* /IRQ1-A
P11/RxD2/TEND0-A/
3
ETEND0-A* /IRQ1-A
P11/RxD2/TEND0-A/
3
ETEND0-A* /IRQ1-A
86
K14
P12/SCK2/DACK0-A/
3
EDACK0-A* /IRQ2-A
P12/SCK2/DACK0-A/
3
EDACK0-A* /IRQ2-A
P12/SCK2/DACK0-A/
3
EDACK0-A* /IRQ2-A
87
J12
P13/ADTRG0-A/EDRAK0-A* / P13/ADTRG0-A/EDRAK0-A* / P13/ADTRG0-A/
3
IRQ3-A
IRQ3-A
EDRAK0-A* /IRQ3-A
88
J13
Vss

J15
Vss
3
3
Vss
Vss
Vss
Vss
3
P66/EDRAK0-B*
3
3
P66/EDRAK0-B*
3
3
89
J14
P66/EDRAK0-B*
90
H12
P67/EDRAK1-B* /IRQ15-B
P67/EDRAK1-B* /IRQ15-B
P67/EDRAK1-B* /IRQ15-B

H13
NC
NC
NC
3

H15
OSC2*

H14
OSC1*
OSC1*
OSC1*
91
G12
RES
RES
RES
92
G13
VCL
VCL
VCL
3
OSC2*
3
Rev. 2.00 Jul. 31, 2008 Page 20 of 1438
REJ09B0365-0200
3
OSC2*
3
3
3
Section 1 Overview
Pin no.
Pin name
LQFP144
LFBGA176
Mode 1, 2, 6
93
G15
94
Mode 3, 7
Mode 4. 5
P14/TCLKA-B/TxD3/
SDA1/DREQ1-A/
3
EDREQ1-A* /IRQ4-A
P14/TCLKA-B/TxD3/
SDA1/DREQ1-A/
3
EDREQ1-A* /IRQ4-A
P14/TCLKA-B/TxD3/
SDA1/DREQ1-A/
3
EDREQ1-A* /IRQ4-A
G14
P15/TCLKB-B/RxD3/
SCL1/TEND1-A/
3
4
ETEND1-A* /IRQ5-A*
P15/TCLKB-B/RxD3/
SCL1/TEND1-A/
3
4
ETEND1-A* /IRQ5-A*
P15/TCLKB-B/RxD3/
SCL1/TEND1-A/
3
4
ETEND1-A* /IRQ5-A*
95
F12
WDTOVF
WDTOVF/TDO*
WDTOVF
96
F13
Vss
Vss
Vss
97
F15
XTAL
XTAL
XTAL
98
F14
EXTAL
EXTAL
EXTAL

E13
NC
NC
NC
99
E15
Vcc
Vcc
Vcc
100
E14
P16/TCLKC-B/
SCK3/SDA0/DACK1-A/
3
EDACK1-A* /IRQ6-A
P16/TCLKC-B/
SCK3/SDA0/DACK1-A/
3
EDACK1-A* /IRQ6-A
P16/TCLKC-B/
SCK3/SDA0/DACK1-A/
3
EDACK1-A* /IRQ6-A
101
E12
P17/TCLKD-B/
SCL0/ADTRG1-A/
3
EDRAK1-A* /IRQ7-A
P17/TCLKD-B/
SCL0/ADTRG1-A/
3
EDRAK1-A* /IRQ7-A
P17/TCLKD-B/
SCL0/ADTRG1-A/
3
EDRAK1-A* /IRQ7-A
102
D15
STBY
STBY
STBY
103
D14
Vss
Vss
Vss
104
D13
P35/PO13/TIOCA1/TIOCB1/
TCLKC-A/DACK1-B/
3
EDACK3*
P35/PO13/TIOCA1/TIOCB1/
TCLKC-A/DACK1-B/
3
EDACK3*
P35/PO13/TIOCA1/TIOCB1/
TCLKC-A/DACK1-B/
3
EDACK3*
105
C15
P36/PO14/TIOCA2/
3
EDRAK2*
P36/PO14/TIOCA2/
3
EDRAK2*
P36/PO14/TIOCA2/
3
EDRAK2*
106
D12
P37/PO15/TIOCA2/TIOCB2/
3
TCLKD-A/EDRAK3*
P37/PO15/TIOCA2/TIOCB2/
3
TCLKD-A/EDRAK3*
P37/PO15/TIOCA2/TIOCB2/
3
TCLKD-A/EDRAK3*
107
C14
P60/TMRI2/TxD4/DERQ2/
3
EDREQ0-B* /IRQ8-B
P60/TMRI2/TxD4/DERQ2/
3
EDREQ0-B* /IRQ8-B
P60/TMRI2/TxD4/DERQ2/
3
EDREQ0-B* /IRQ8-B
108
B15
P61/TMCI2/RxD4/TEND2/ET
3
END0-B* /IRQ9-B
P61/TMCI2/RxD4/TEND2/ET
3
END0-B* /IRQ9-B
P61/TMCI2/RxD4/TEND2/
3
ETEND0-B* /IRQ9-B
109
B14
P62/TMO2/SCK4/DACK2/
3
EDACK0-B* /
IRQ10-B
P62/TMO2/SCK4/DACK2/
3
2
EDACK0-B* /TRST*
P62/TMO2/SCK4/DACK2/
3
EDACK0-B*
110
A15
PLLVcc
PLLVcc
PLLVcc
2
Rev. 2.00 Jul. 31, 2008 Page 21 of 1438
REJ09B0365-0200
Section 1 Overview
Pin no.
Pin name
LQFP144
LFBGA176
Mode 1, 2, 6
111
C13

Mode 3, 7
Mode 4. 5
P63/TMRI3/TxD6/DREQ3/
3
EDREQ1-B*
IRQ11-B
P63/TMRI3/TxD6/DREQ3/
3
EDREQ1-B*
2
IRQ11-B/TMS*
P63/TMRI3/TxD6/DREQ3/
3
EDREQ1-B* /
IRQ11-B
A14
NC
NC
NC
112
B13
PLLVss
PLLVss
PLLVss
113
C12
P64/TMCI3/RxD6/TEND3/
3
ETEND1-B* /
IRQ12-B
P64/TMCI3/RxD6/TEND3/
3
ETEND1-B* /
2
IRQ12-B/TDI*
P64/TMCI3/RxD6/TEND3/
3
ETEND1-B* /IRQ12-B
114
A13
P65/TMO3/SCK6/DACK3/
3
EDACK1-B* /
IRQ13-B
P65/TMO3/SCK6/DACK3/
3
EDACK1-B* /
2
IRQ13-B/TCK*
P65/TMO3/SCK6/DACK3/
3
EDACK1-B* /
IRQ13-B
115
B12
MD0
MD0
MD0
3
3
D11
PC2/LUCAS/DQMLU*
117
A12
PC3/LLCAS/DQMLL*
PC3/LLCAS/DQMLL*
PC3/LLCAS/DQMLL*

C11
NC
NC
NC
118
B11
P50/AN0/IRQ0-B
P50/AN0/IRQ0-B
P50/AN0/IRQ0-B
119
A11
P51/AN1/IRQ1-B
P51/AN1/IRQ1-B
P51/AN1/IRQ1-B
120
D10
P52/AN2/IRQ2-B
P52/AN2/IRQ2-B
P52/AN2/IRQ2-B

C10
NC
NC
NC
121
A10
Avcc
Avcc
Avcc
122
B10
P53/AN3/IRQ3-B
P53/AN3/IRQ3-B
P53/AN3/IRQ3-B
123
D9
Avss
Avss
Avss
3
PC2/LUCAS/DQMLU*
3
116
3
PC2/LUCAS/DQMLU*
3
124
C9
P54/AN4/IRQ4-B
P54/AN4/IRQ4-B
P54/AN4/IRQ4-B
125
A9
Vref
Vref
Vref

B9
NC
NC
NC
126
D8
P55/AN5/IRQ5-B
P55/AN5/IRQ5-B
P55/AN5/IRQ5-B
127
C8
P56/AN6/DA0/IRQ6-B
P56/AN6/DA0/IRQ6-B
P56/AN6/DA0/IRQ6-B
128
A8
P57/AN7/DA1/IRQ7-B
P57/AN7/DA1/IRQ7-B
P57/AN7/DA1/IRQ7-B
129
B8
P44/AN8
P44/AN8
P44/AN8
130
D7
P45/AN9
P45/AN9
P45/AN9
131
C7
P46/AN10
P46/AN10
P46/AN10
132
A7
P47/AN11
P47/AN11
P47/AN11
Rev. 2.00 Jul. 31, 2008 Page 22 of 1438
REJ09B0365-0200
Section 1 Overview
Pin no.
Pin name
LQFP144
LFBGA176
Mode 1, 2, 6
Mode 3, 7
Mode 4. 5
133
B7
MD1
MD1
MD1

D6
NC
NC
NC

C6
NC
NC
NC

A6
NC
NC
NC

B6
MD3*
MD3*
MD3*
134
C5
PA0/BREQO/BS-A
PA0/BREQO/BS-A
PA0/BREQO/BS-A
135
A5
PA1/BACK/(RD/WR-A)
PA1/BACK/(RD/WR-A)
PA1/BACK/(RD/WR-A)
136
B5
PA2/BREQ/WAIT-A
PA2/BREQ/WAIT-A
PA2/BREQ/WAIT-A
137
D5
PA3/LLWR/LLB
PA3/LLWR/LLB
LLWR/LLB
138
A4
PA4/LHWR/LUB
PA4/LHWR/LUB
PA4/LHWR/LUB
139
B4
PA5/RD
PA5/RD
RD
140
C4
PA6/AS/AH/BS-B
PA6/AS/AH/BS-B
PA6/AS/AH/BS-B
3
3
3

A3
Vcc
Vcc
Vcc
141
D4
Vss
Vss
Vss
142
B3
PA7/Bφ
PA7/Bφ
PA7/Bφ
143
A2
Vcc
Vcc
Vcc
144
B2
PB0/CS0/CS4-A/CS5-B
PB0/CS0/CS4-A/CS5-B
PB0/CS0/CS4-A/CS5-B
Notes: 1.
2.
3.
4.
These pins can be used when the PCJKE bit in PFCRD is set to 1 in single-chip mode.
Pins TDO, TRST, TMS, TDI, and TCK are enabled in mode 3.
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
The IRQ15-A is not supported by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 1 Overview
1.4.3
Pin Functions
Table 1.5
Pin Functions
Classification
Pin Name
I/O
Description
Power supply
VCC
Input
Power supply pins. Connect them to the system power
supply.
VCL
Input
Connect this pin to VSS via a 0.1-µF capacitor
(The capacitor should be placed close to the pin).
VSS
Input
Ground pins. Connect them to the system power supply
(0 V).
PLLVCC
Input
Power supply pin for the PLL circuit.
PLLVSS
Input
Ground pin for the PLL circuit.
XTAL
Input
EXTAL
Input
Pins for a crystal resonator. An external clock signal can
be input through the EXTAL pin. For an example of this
connection, see section 26, Clock Pulse Generator.
Clock
3
Input
The 32.768 kHz crystal resonator is connected to this pin.
3
Input
The 32.768 kHz crystal resonator is connected to this pin.
Output
Outputs the system clock for external devices.
Output
When connecting the synchronous DRAM, connect it to
the CLK pin of synchronous DRAM. For detail, see
section 9, Bus Controller (BSC).
Input
Pins for setting the operating mode. The signal levels on
these pins must not be changed during operation.
RES
Input
Reset signal input pin. This LSI enters the reset state
when this signal goes low.
STBY
Input
This LSI enters hardware standby mode when this signal
goes low.
EMLE
Input
Input pin for the on-chip emulator enable signal. If the onchip emulator is used, the signal level should be fixed
high. If the on-chip emulator is not used, the signal level
should be fixed low.
TRST
Input
TMS
Input
On-chip emulator pins or boundary scan pins. When the
EMLE pin is driven high, these pins are dedicated for the
on-chip emulator. When the EMLE pin is driven low and
set to mode 3, these pins are dedicated for the boundary
scan mode.
OSC1*
OSC2*
Bφ
SDRAMφ*
3
Operating mode MD3 to MD0
control
System control
On-chip
emulator
Address bus
TDI
Input
TCK
Input
TDO
Output
A23 to A0
Output
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REJ09B0365-0200
Output pins for the address bits.
Section 1 Overview
Classification
Pin Name
I/O
Description
Data bus
D15 to D0
Input/
output
Input and output for the bidirectional data bus. These
pins also output addresses when accessing an address–
data multiplexed I/O interface space.
Bus control
BREQ
Input
External bus-master modules assert this signal to
request the bus.
BREQO
Output
Internal bus-master modules assert this signal to request
access to the external space via the bus in the external
bus released state.
BACK
Output
Bus acknowledge signal, which indicates that the bus has
been released.
BS-A/BS-B
Output
Indicates the start of a bus cycle.
AS
Output
Strobe signal which indicates that the output address on
the address bus is valid in access to the basic bus
interface or byte control SRAM interface space.
AH
Output
This signal is used to hold the address when accessing
the address-data multiplexed I/O interface space.
RD
Output
Strobe signal which indicates that reading from the basic
bus interface space is in progress.
RD/WR
Output
Indicates the direction (input or output) of the data bus.
LHWR
Output
Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the basic bus interface
space.
LLWR
Output
Strobe signal which indicates that the lower-order byte
(D7 to D0) is valid in access to the basic bus interface
space.
LUB
Output
Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the byte control SRAM
interface space.
LLB
Output
Strobe signal which indicates that the lower-order byte
(D7 to D0) is valid in access to the byte control SRAM
interface space.
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REJ09B0365-0200
Section 1 Overview
Classification
Pin Name
I/O
Description
Bus control
CS0
CS1
CS2-A/CS2-B
CS3-A/CS3-B
CS4-A/CS4-B/ CS4-C
CS5-A/CS5-B/
CS5-C/CS5-D
CS6-A/CS6-B/
CS6-C/CS6-D
CS7-A/CS7-B/ CS7C/CS7-D
Output
Select signals for areas 0 to 7.
WAIT-A/ WAIT-B
Input
Requests wait cycles in access to the external space.
RAS*
Output
•
Row address strobe signal when area 2 is specified
as DRAM interface space
•
Row address strobe signal when area 2 is specified
as synchronous DRAM space
3
CAS*
Output
Column address strobe signal when area 2 is specified
as synchronous DRAM interface space
WE*
Output
•
Write enable signal for DRAM space
•
Write enable signal when area 2 is specified as
synchronous DRAM interface space
•
Output enable signal for DRAM interface space
•
Clock enable signal for synchronous DRAM
interface space
3
3
OE/CKE*
3
Output
LUCAS*
Output
Upper column address strobe signal for 16-bit DRAM
interface space
LLCAS*
Output
•
Lower-column address strobe signal for 16-bit
DRAM interface space
•
Column address strobe signal for 8-bit DRAM
interface space
3
3
3
DQMLU*
Output
Upper-data mask enable signal for 16-bit synchronous
DRAM interface space
3
Output
•
Lower-data mask enable signal for 16-bit
synchronous DRAM interface space
•
Data mask enable signal for 8-bit synchronous
DRAM interface space
DQMLL*
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Section 1 Overview
Classification
Pin Name
I/O
Description
Interrupt
NMI
Input
Non-maskable interrupt request signal. When this pin is
not in use, this signal must be fixed high.
IRQ15-A* /IRQ15-B
IRQ14
IRQ13-A/IRQ13-B
IRQ12-A/IRQ12-B
IRQ11-A/IRQ11-B
IRQ10-A/IRQ10-B
IRQ9-A/IRQ9-B
IRQ8-A/IRQ8-B
IRQ7-A/IRQ7-B
IRQ6-A/IRQ6-B
IRQ5-A/IRQ5-B
IRQ4-A/IRQ4-B
IRQ3-A/IRQ3-B
IRQ2-A/IRQ2-B
IRQ1-A/IRQ1-B
IRQ0-A/IRQ0-B
Input
Maskable interrupt request signal.
DREQ0-A/DREQ0-B
DREQ1-A/DREQ1-B
DREQ2
DREQ3
Input
Requests DMAC activation.
DACK0-A/DACK0-B
DACK1-A/DACK1-B
DACK2
DACK3
Output
DMAC single address-transfer acknowledge signal.
TEND0-A/TEND0-B
TEND1-A/TEND1-B
TEND2
TEND3
Output
Indicates end of data transfer by the DMAC.
EDREQ0-A/EDREQ0-B
Input
Requests EXDMAC activation.
Output
EXDMAC single address-transfer acknowledge signal.
Output
Indicates end of data transfer by the EXDMAC.
2
DMA controller
(DMAC)
EXMDA
controller
3
(EXDMAC)*
EDREQ1-A/EDREQ1-B
EDREQ2
EDREQ3
EDACK0-A/EDACK0-B
EDACK1-A/EDACK1-B
EDACK2
EDACK3
ETEND0-A/ETEND0-B
ETEND1-A/ETEND1-B
ETEND2
ETEND3
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Section 1 Overview
Classification
Pin Name
I/O
Description
EXMDA
controller
3
(EXDMAC)*
EDRAK0-A/EDRAK0-B
Output
Notification to external device of EXDMAC external
request acceptance and start of execution
Input
Input pins for the external clock signals.
TIOCA0
TIOCB0
TIOCC0
TIOCD0
Input/
output
Signals for TGRA_0 to TGRD_0. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
TIOCA1
TIOCB1
Input/
output
Signals for TGRA_1 and TGRB_1. These pins are used
as input capture inputs, output compare outputs, or PWM
outputs.
TIOCA2
TIOCB2
Input/
output
Signals for TGRA_2 and TGRB_2. These pins are used
as input capture inputs, output compare outputs, or PWM
outputs.
TIOCA3
TIOCB3
TIOCC3
TIOCD3
Input/
output
Signals for TGRA_3 to TGRD_3. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
TIOCA4
TIOCB4
Input/
output
Signals for TGRA_4 and TGRB_4. These pins are used
as input capture inputs, output compare outputs, or PWM
outputs.
TIOCA5
TIOCB5
Input/
output
Signals for TGRA_5 and TGRB_5. These pins are used
as input capture inputs, output compare outputs, or PWM
outputs.
TCLKE
TCLKF
TCLKG
TCLKH
Input
Input pins for external clock signals.
TIOCA6
TIOCB6
TIOCC6
TIOCD6
Input/
output
Signals for TGRA_6 to TGRD_6. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
TIOCA7
TIOCB7
Input/
output
Signals for TGRA_7 and TGRB_7. These pins are used
as input capture inputs, output compare outputs, or PWM
outputs.
EDRAK1-A/EDRAK1-B
EDRAK2
EDRAK3
16-bit timer
TCLKA-A/TCLKA-B
pulse unit (TPU) TCLKB-A/TCLKB-B
TCLKC-A/TCLKC-B
TCLKD-A/TCLKD-B
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REJ09B0365-0200
Section 1 Overview
Classification
I/O
Description
16-bit timer
TIOCA8
pulse unit (TPU) TIOCB8
Input/
output
Signals for TGRA_8 and TGRB_8. These pins are used
as input capture inputs, output compare outputs, or PWM
outputs.
TIOCA9
TIOCB9
TIOCC9
TIOCD9
Input/
output
Signals for TGRA_9 to TGRD_9. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
TIOCA10
TIOCB10
Input/
output
Signals for TGRA_10 and TGRB_10. These pins are
used as input capture inputs, output compare outputs, or
PWM outputs.
TIOCA11
TIOCB11
Input/
output
Signals for TGRA_11 and TGRB_11. These pins are
used as input capture inputs, output compare outputs, or
PWM outputs.
PO31 to PO0
Output
Output pins for the pulse signals.
Output
Output pins for the compare match signals.
TMCI0 to TMCI3
Input
Input pins for the external clock signals that drive for the
counters.
TMRI0 to TMRI3
Input
Input pins for the counter-reset signals.
Watchdog timer
(WDT)
WDTOVF
Output
Output pin for the counter-overflow signal in watchdogtimer mode.
Serial
communication
interface (SCI)
TxD0
TxD1
TxD2
TxD3
TxD4
TxD5
TxD6
Output
Output pins for data transmission.
RxD0
RxD1
RxD2
RxD3
RxD4
RxD5
RxD6
Input
Input pins for data reception.
Programmable
pulse generator
(PPG)
Pin Name
8-bit timer (TMR) TMO0 to TMO3
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Section 1 Overview
Classification
Pin Name
I/O
Description
Serial
communication
interface (SCI)
SCK0
SCK1
SCK2
SCK3
SCK4
SCK5
SCK6
Input/
output
Input/output pins for clock signals.
SCI with IrDA
(SCI)
IrTxD
Output
Output pin that outputs encoded data for IrDA.
IrRxD
Input
Input pin that inputs encoded data for IrDA.
I C bus interface SCL0
2 (IIC2)
SCL1
SCL2
SCL3
Input/
output
Input/output pin for IIC clock. Bus can be directly driven
by the NMOS open drain output. SCL2 and SCL3 support
5-V input.
SDA0
SDA1
SDA2
SDA3
Input/
output
Input/output pin for IIC data. Bus can be directly driven by
the NMOS open drain output. SDA2 and SDA3 support
5-V input.
AN11 to AN0
Input
Input pins for the analog signals to be processed by the
A/D converter.
ADTRG0-A/
ADTRG0-B
ADTRG1-A/
ADTRG1-B
ADTRG2
Input
Input pins for the external trigger signal that starts A/D
conversion.
D/A converter
DA1, DA0
Output
Output pins for the analog signals from the D/A
converter.
A/D converter,
D/A converter
AVCC
Input
Analog power supply pin for the A/D and D/A converters.
When the A/D and D/A converters are not in use, connect
this pin to the system power supply.
AVSS
Input
Ground pin for the A/D and D/A converters. Connect this
pin to the system power supply (0 V).
Vref
Input
Reference power supply pin for the A/D and D/A
converters. When the A/D and D/A converters are not in
use, connect this pin to the system power supply.
P17 to P10
Input/
output
8-bit input/output pins.
P27 to P20
Input/
output
8-bit input/output pins.
2
A/D converter
Rev. 2.00 Jul. 31, 2008 Page 30 of 1438
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Section 1 Overview
Classification
Pin Name
I/O
Description
I/O ports
P37 to P30
Input/
output
8-bit input/output pins.
P47 to P44
Input
4-bit input-only pins.
P57 to P50
Input
8-bit input-only pins.
P67 to P60
Input/
output
8-bit input/output pins.
PA7
Input
Input-only pin.
PA6 to PA0
Input/
output
7-bit input/output pins.
PB7 to PB0
Input/
output
8-bit input/output pins.
PC5 to PC0
Input/
output
6-bit input/output pins.
PD7 to PD0
Input/
output
8-bit input/output pins.
PE7 to PE0
Input/
output
8-bit input/output pins.
PF7 to PF0
Input/
output
8-bit input/output pins.
PH7 to PH0
Input/
output
8-bit input/output pins.
PI7 to PI0
Input/
output
8-bit input/output pins.
PN3 to PN0
Input/
output
4-bit input/output (open drain) pins.
Input/
output
5-bit input/output pins
Input/
output
8-bit input/output pins.
Input/
output
8-bit input/output pins.
3
PM4 to PM0*
1
PJ7 to PJ0*
1
PK7 to PK0*
Note:
1. These pins can be used when the PCJKE bit in PFCRD is set to 1 in single-chip mode.
2. The IRQ15-A is not supported by the H8SX/1648G Group and the H8SX/1648H Group.
3. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 31 of 1438
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Section 1 Overview
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Section 2 CPU
Section 2 CPU
The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward
compatible with the H8/300, H8/300H, and H8S CPUs.
The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space,
and is ideal for a realtime control system.
2.1
Features
• Upward-compatible with H8/300, H8/300H, and H8S CPUs
 Can execute object programs of these CPUs
• Sixteen 16-bit general registers
 Also usable as sixteen 8-bit registers or eight 32-bit registers
• 87 basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Bit field transfer instructions
 Powerful bit-manipulation instructions
 Bit condition branch instructions
 Multiply-and-accumulate instruction
• Eleven addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)]
 Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B),
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)]
 Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @−ERn,
@ERn+, or @ERn−]
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or
@(ERn.L,PC)]
 Memory indirect [@@aa:8]
 Extended memory indirect [@@vec:7]
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Section 2 CPU
• Two base registers
 Vector base register
 Short address base register
• 4-Gbyte address space
 Program: 4 Gbytes
 Data:
4 Gbytes
• High-speed operation
 All frequently-used instructions executed in one or two states
 8/16/32-bit register-register add/subtract: 1 state
 8 × 8-bit register-register multiply:
1 state
 16 ÷ 8-bit register-register divide:
10 states
 16 × 16-bit register-register multiply:
1 state
 32 ÷ 16-bit register-register divide:
18 states
 32 × 32-bit register-register multiply:
5 states
 32 ÷ 32-bit register-register divide:
18 states
• Four CPU operating modes
 Normal mode
 Middle mode
 Advanced mode
 Maximum mode
• Power-down modes
 Transition is made by execution of SLEEP instruction
 Choice of CPU operating clocks
Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1648
Group, the H8SX/1648A Group, the H8SX/1648L Group, the H8SX/1648G Group,
and the H8SX/1648H Group. Normal, middle, and maximum modes are not supported.
2. The multiplier and divider are supported by the H8SX/1648 Group, the H8SX/1648A
Group, the H8SX/1648L Group, the H8SX/1648G Group, and the H8SX/1648H
Group.
Rev. 2.00 Jul. 31, 2008 Page 34 of 1438
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Section 2 CPU
2.2
CPU Operating Modes
The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. These
modes can be selected by the mode pins of this LSI.
Maximum 64 kbytes for program
Normal mode
and data areas combined
Maximum 16-Mbyte program
Middle mode
area and 64-kbyte data area,
maximum 16 Mbytes for program
and data areas combined
CPU operating modes
Maximum 16-Mbyte program
Advanced mode
area and 4-Gbyte data area,
maximum 4 Gbytes for program
and data areas combined
Maximum mode
Maximum 4 Gbytes for program
and data areas combined
Figure 2.1 CPU Operating Modes
2.2.1
Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
• Address Space
The maximum address space of 64 kbytes can be accessed.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. When the extended register En is used as a 16-bit register it can
contain any value, even when the corresponding general register Rn is used as an address
register. (If the general register Rn is referenced in the register indirect addressing mode with
pre-/post-increment or pre-/post-decrement and a carry or borrow occurs, however, the value in
the corresponding extended register En will be affected.)
• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
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REJ09B0365-0200
Section 2 CPU
• Exception Vector Table and Memory Indirect Branch Addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The structure of the exception vector table is shown in
figure 2.2.
H'0000
H'0001
H'0002
H'0003
Reset exception vector
Exception
vector table
Reset exception vector
Figure 2.2 Exception Vector Table (Normal Mode)
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units.
SP
PC
(16 bits)
EXR*1
Reserved*1, *3
CCR
CCR*3
SP
(SP*2
)
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored on return.
Figure 2.3 Stack Structure (Normal Mode)
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Section 2 CPU
2.2.2
Middle Mode
The program area in middle mode is extended to 16 Mbytes as compared with that in normal
mode.
• Address Space
The maximum address space of 16 Mbytes can be accessed as a total of the program and data
areas. For individual areas, up to 16 Mbytes of the program area or up to 64 kbytes of the data
area can be allocated.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. When the extended register En is used as a 16-bit register (in
other than the JMP and JSR instructions), it can contain any value even when the
corresponding general register Rn is used as an address register. (If the general register Rn is
referenced in the register indirect addressing mode with pre-/post-increment or pre-/postdecrement and a carry or borrow occurs, however, the value in the corresponding extended
register En will be affected.)
• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid and the upper eight bits are sign-extended.
• Exception Vector Table and Memory Indirect Branch Addresses
In middle mode, the top area starting at H'000000 is allocated to the exception vector table.
One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits
are stored. The structure of the exception vector table is shown in figure 2.4.
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address.
The upper eight bits are reserved and assumed to be H'00.
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.
Rev. 2.00 Jul. 31, 2008 Page 37 of 1438
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Section 2 CPU
2.2.3
Advanced Mode
The data area is extended to 4 Gbytes as compared with that in middle mode.
• Address Space
The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to
16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.
• Instruction Set
All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower
24 bits are stored. The structure of the exception vector table is shown in figure 2.4.
H'00000000
Reserved
H'00000001
H'00000002
Reset exception vector
H'00000003
H'00000004
Reserved
Exception vector table
H'00000005
H'00000006
H'00000007
Figure 2.4 Exception Vector Table (Middle and Advanced Modes)
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch
address. The upper eight bits are reserved and assumed to be H'00.
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Section 2 CPU
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.
EXR*1
Reserved*1, *3
CCR
SP
Reserved
SP
PC
(24 bits)
(a) Subroutine Branch
*2
(SP
)
PC
(24 bits)
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored on return.
Figure 2.5 Stack Structure (Middle and Advanced Modes)
2.2.4
Maximum Mode
The program area is extended to 4 Gbytes as compared with that in advanced mode.
• Address Space
The maximum address space of 4 Gbytes can be linearly accessed.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit
segments of 32-bit registers or address registers.
• Instruction Set
All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses
In maximum mode, the top area starting at H'00000000 is allocated to the exception vector
table. One branch address is stored per 32 bits. The structure of the exception vector table is
shown in figure 2.6.
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Section 2 CPU
H'00000000
H'00000001
Reset exception vector
H'00000002
H'00000003
H'00000004
Exception vector table
H'00000005
H'00000006
H'00000007
Figure 2.6 Exception Vector Table (Maximum Modes)
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch
address.
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling are shown in figure 2.7. The PC contents are saved or restored in 32-bit units. The
EXR contents are saved or restored regardless of whether or not EXR is in use.
SP
SP
PC
(32 bits)
EXR
CCR
PC
(32 bits)
(a) Subroutine Branch
(b) Exception Handling
Figure 2.7 Stack Structure (Maximum Mode)
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Section 2 CPU
2.3
Instruction Fetch
The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended
that the mode be set according to the bus width of the memory in which a program is stored. The
instruction-fetch mode setting does not affect operation other than instruction fetch such as data
accesses. Whether an instruction is fetched in 16- or 32-bit mode is selected by the FETCHMD bit
in SYSCR. For details, see section 3.2.2, System Control Register (SYSCR).
2.4
Address Space
Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the
CPU operating mode.
Normal mode
Middle mode
H'0000
H'000000
H'FFFF
H'007FFF
Program area
Data area
(64 kbytes)
Maximum mode
Advanced mode
H'00000000
H'00000000
Program area
(16 Mbytes)
Program area
(16 Mbytes)
Data area
(64 kbytes)
H'FF8000
H'FFFFFF
Program area
Data area
(4 Gbytes)
H'00FFFFFF
Data area
(4 Gbytes)
H'FFFFFFFF
H'FFFFFFFF
Figure 2.8 Memory Map
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Section 2 CPU
2.5
Registers
The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers:
general registers and control registers. The control registers are the 32-bit program counter (PC),
8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base
register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register
(MAC).
General Registers and Extended Registers
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers
31
0
PC
7 6 5 4 3 2 1 0
CCR
I UI H U N Z V C
EXR
T — — — — I2 I1 I0
7 6 5 4 3 2 1 0
31
12
0
(Reserved)
VBR
31
8
0
(Reserved)
SBR
63
41
Sign extension
MAC
32
MACH
MACL
[Legend]
SP:
PC:
CCR:
I:
UI:
H:
31
Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
0
U:
N:
Z:
V:
C:
EXR:
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Extended control register
Figure 2.9 CPU Registers
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T:
I2 to I0:
VBR:
SBR:
MAC:
Trace bit
Interrupt mask bits
Vector base register
Short address base register
Multiply-accumulate register
Section 2 CPU
2.5.1
General Registers
The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike
and can be used as both address registers and data registers. When a general register is used as a
data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the
usage of the general registers.
When the general registers are used as 32-bit registers or address registers, they are designated by
the letters ER (ER0 to ER7).
When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7)
are also referred to as extended registers.
When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing a maximum sixteen 8-bit registers.
The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index
registers. The size in the operand field determines which register is selected.
The usage of each register can be selected independently.
• Address registers
• 32-bit registers
• 32-bit index registers
General registers ER
(ER0 to ER7)
• 16-bit registers
General registers E
(E0 to E7)
• 8-bit registers
• 16-bit registers
• 16-bit index registers
General registers R
(R0 to R7)
General registers RH
(R0H to R7H)
• 8-bit registers
• 8-bit index registers
General registers RL
(R0L to R7L)
Figure 2.10 Usage of General Registers
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Section 2 CPU
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows
the stack.
Free area
SP (ER7)
Stack area
Figure 2.11 Stack
2.5.2
Program Counter (PC)
PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The
length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant
bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0.
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Section 2 CPU
2.5.3
Condition-Code Register (CCR)
CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask
(I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C)
flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc)
instructions.
Bit
Bit Name
Initial
Value
R/W
Description
7
I
1
R/W
Interrupt Mask Bit
Masks interrupts when set to 1. This bit is set to 1 at the
start of an exception handling.
6
UI
Undefined R/W
User Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, this flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag
Stores the value of the most significant bit (regarded as
sign bit) of data.
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Section 2 CPU
Bit
Bit Name
Initial
Value
2
Z
Undefined R/W
R/W
Description
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1
V
Undefined R/W
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.
0
C
Undefined R/W
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. A carry has the following types:
•
Carry from the result of addition
•
Borrow from the result of subtraction
•
Carry from the result of shift or rotation
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
2.5.4
Extended Control Register (EXR)
EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0).
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instructions.
For details, see section 6, Exception Handling.
Bit
Bit Name
Initial
Value
R/W
Description
7
T
0
R/W
Trace Bit
When this bit is set to 1, a trace exception is generated
each time an instruction is executed. When this bit is
cleared to 0, instructions are executed in sequence.
6 to 3
—
All 1
R/W
Reserved
These bits are always read as 1.
2
I2
1
R/W
Interrupt Mask Bits
1
I1
1
R/W
These bits designate the interrupt mask level (0 to 7).
0
I0
1
R/W
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Section 2 CPU
2.5.5
Vector Base Register (VBR)
VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are
read as 0s. This register is a base address of the vector area for exception handlings other than a
reset and a CPU address error (extended memory indirect is also out of the target). The initial
value is H'00000000. The VBR contents are changed with the LDC and STC instructions.
2.5.6
Short Address Base Register (SBR)
SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In
8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The
initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions.
2.5.7
Multiply-Accumulate Register (MAC)
MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists
of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the
upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC,
and STMAC instructions.
2.5.8
Initial Values of CPU Registers
Reset exception handling loads the start address from the vector table into the PC, clears the T bit
in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other
bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is
undefined. The SP should therefore be initialized using an MOV.L instruction executed
immediately after a reset.
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Section 2 CPU
2.6
Data Formats
The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword)
data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit
BCD data.
2.6.1
General Register Data Formats
Figure 2.12 shows the data formats in general registers.
1-bit data
RnH
7
0
7 6 5 4 3 2 1 0
Don't care
1-bit data
RnL
Don't care
7
0
7 6 5 4 3 2 1 0
4-bit BCD data
RnH
43
7
Upper
4-bit BCD data
RnL
Byte data
RnH
Byte data
RnL
0
Lower
Don’t care
43
7
0
Lower
0
7
Don't care
LSB
7
MSB
Word data
Upper
Don't care
Rn
0
Don't care
Word data
MSB
En
15
Longword data
0
ERn
LSB
MSB
15
0
MSB
LSB
31
MSB
16 15
En
[Legend]
ERn: General register ER
En:
General register E
Rn:
General register R
RnH: General register RH
0
Rn
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2.12 General Register Data Formats
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LSB
LSB
Section 2 CPU
2.6.2
Memory Data Formats
Figure 2.13 shows the data formats in memory.
The H8SX CPU can access word data and longword data which are stored at any addresses in
memory. When word data begins at an odd address or longword data begins at an address other
than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when
longword data begins at an odd address, the bus cycle is divided into byte, word, and byte
accesses. In this case, these accesses are assumed to be individual bus cycles.
However, instructions to be fetched, word and longword data to be accessed during execution of
the stack manipulation, branch table manipulation, block transfer instructions, and MAC
instruction should be located to even addresses.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Data Type
Data Format
Address
7
1-bit data
Address L
Byte data
Address L MSB
Word data
7
0
6
5
4
2
1
0
LSB
Address 2M MSB
Address 2M + 1
Longword data
3
LSB
Address 2N MSB
Address 2N + 1
Address 2N + 2
Address 2N + 3
LSB
Figure 2.13 Memory Data Formats
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Section 2 CPU
2.7
Instruction Set
The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown
in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are
called operation instruction in this manual.
Table 2.1
Instruction Classification
Function
Instructions
Data transfer
Block transfer
Arithmetic
operations
Size
Types
6
MOV
B/W/L
MOVFPE, MOVTPE
B
POP, PUSH*1
W/L
LDM, STM
L
MOVA
B/W*2
EEPMOV
B
MOVMD
B/W/L
MOVSD
B
ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC
B/W/L
DAA, DAS
B
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
MULU, DIVU, MULS, DIVS
W/L
6
MULU/U* , MULS/U*
6
27
L
EXTU, EXTS
W/L
TAS
B
MAC*6
3
—
6
6
LDMAC* , STMAC*
6
—
CLRMAC*
—
Logic operations
AND, OR, XOR, NOT
B/W/L
4
Shift
SHLL, SHLR, SHAL, SHAR, ROTL, ROTR, ROTXL, ROTXR B/W/L
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,
BXOR, BIXOR, BLD, BILD, BST, BIST
B
20
BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ
B
BFLD, BFST
B
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Section 2 CPU
Function
Branch
Instructions
BRA/BS, BRA/BC, BSR/BS, BSR/BC
4
System control
Size
B*
3
Bcc* , JMP, BSR, JSR, RTS
—
RTS/L
L*5
BRA/S
—
TRAPA, RTE, SLEEP, NOP
—
Types
9
10
5
RTE/L
L*
LDC, STC, ANDC, ORC, XORC
B/W/L
Total
87
[Legend]
B:
Byte size
W:
Word size
L:
Longword size
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@−SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@−SP.
2. Size of data to be added with a displacement
3. Size of data to specify a branch condition
4. Bcc is the generic designation of a conditional branch instruction.
5. Size of general register to be restored
6. Only when the multiplier is available.
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Section 2 CPU
2.7.1
Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can
use.
Table 2.2
Combinations of Instructions and Addressing Modes (1)
Addressing Mode
Classification
Data
transfer
Instruction
Size
#xx
Rn
@(d,
RnL.B/
Rn.W/
@ERn @(d,ERn) ERn.L)
MOV
B/W/L
S
SD
SD
Arithmetic
operations
SD
SD
SD
B
S/D
MOVFPE,
MOVTPE
B
S/D
POP, PUSH
W/L
S/D
S/D*
2
LDM, STM
L
S/D
S/D*
2
B/W
S
MOVA*
Block
transfer
SD
@−ERn/
@ERn+/
@ERn−/
@aa:16/
@+ERn @aa:8 @aa:32 —
4
S/D
S/D*
S
S
S
S
1
S
EEPMOV
B
SD*
3
MOVMD
B/W/L
SD*
3
MOVSD
B
SD*
3
ADD, CMP
B
D
D
D
D
D
D
D
B
S
S
D
D
D
D
D
D
B
D
S
S
S
S
S
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
D
D
D
D
D
D
B
S
D
D
D
D
D
D
B
D
S
S
S
S
S
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
B
SUB
W/L
S
B
S
B
S
SD
ADDX, SUBX B/W/L
W/L
S
SD
B/W/L
S
B/W/L
S
INC, DEC
B/W/L
SD
SD*
D
ADDS, SUBS L
D
DAA, DAS
B
MULXU,
DIVXU
B/W
S:4
SD
D
MULU, DIVU W/L
S:4
SD
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5
S
S
Section 2 CPU
Addressing Mode
@(d,
RnL.B/
Rn.W/
@ERn @(d,ERn) ERn.L)
@−ERn/
@ERn+/
@ERn−/
@aa:16/
@+ERn @aa:8 @aa:32 —
Classification
Instruction
Size
#xx
Rn
Arithmetic
operations
MULXS,
DIVXS
B/W
S:4
SD
MULS, DIVS
W/L
S:4
SD
NEG
B
D
D
D
D
D
W/L
D
D
D
D
D
D
EXTU, EXTS
W/L
D
D
D
D
D
D
TAS
B
MAC*
12
12
D
—
12
—
12
—
LDMAC*
Logic
operations
O
S
D
AND, OR, XOR B
S
D
D
D
D
D
D
B
D
S
S
S
S
S
S
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
B
W/L
NOT
Shift
SHLL, SHLR
S
B
D
D
D
D
D
W/L
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
B
W/L*
6
B/W/L*
Bit
manipulation
D
—
CLRMAC*
STMAC*
D
7
D
D
D
D
D
D
D
SHAL, SHAR
ROTL, ROTR
ROTXL,
ROTXR
B
D
D
D
D
D
W/L
D
D
D
D
D
BSET, BCLR,
BNOT, BTST,
BSET/cc,
BCLR/cc
B
D
D
D
D
BAND, BIAND, B
BOR, BIOR,
BXOR, BIXOR,
BLD, BILD,
BST, BIST,
BSTZ, BISTZ
D
D
D
D
D
D
D
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Section 2 CPU
Addressing Mode
Rn
@(d,
RnL.B/
Rn.W/
@ERn @(d,ERn) ERn.L)
Bit
manipulation
BFLD
B
D
S
S
S
BFST
B
S
D
D
D
Branch
BRA/BS, BRA/BC*
8
B
S
S
S
BSR/BS, BSR/BC*
8
B
S
S
S
Classification
Instruction
System
control
Size
#xx
9
@−ERn/
@ERn+/
@ERn−/
@aa:16/
@+ERn @aa:8 @aa:32 —
10
S
11
D
LDC
(CCR, EXR)
B/W*
LDC
(VBR, SBR)
L
STC
(CCR, EXR)
B/W*
STC
(VBR, SBR)
L
ANDC, ORC,
XORC
B
SLEEP
—
O
NOP
—
O
S
S
S
S
S*
D
D
D*
S
9
D
D
S
[Legend]
d:
d:16 or d:32
S:
Can be specified as a source operand.
D:
Can be specified as a destination operand.
SD:
Can be specified as either a source or destination operand or both.
S/D:
Can be specified as either a source or destination operand.
S:4:
4-bit immediate data can be specified as a source operand.
Notes: 1. Only @aa:16 is available.
2. @ERn+ as a source operand and @−ERn as a destination operand
3. Specified by ER5 as a source address and ER6 as a destination address for data
transfer.
4. Size of data to be added with a displacement
5. Only @ERn− is available
6. When the number of bits to be shifted is 1, 2, 4, 8, or 16
7. When the number of bits to be shifted is specified by 5-bit immediate data or a general
register
8. Size of data to specify a branch condition
9. Byte when immediate or register direct, otherwise, word
10. Only @ERn+ is available
11. Only @−ERn is available
12. Not available in this LSI.
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Section 2 CPU
Table 2.2
Combinations of Instructions and Addressing Modes (2)
Addressing Mode
@(RnL.
B/Rn.W/
Classification
Branch
System
control
ERn.L,
Instruction
Size
@ERn
BRA/BS,
BRA/BC
—
O
BSR/BS,
BSR/BC
—
O
Bcc
—
O
BRA
—
O
BRA/S
—
O*
JMP
—
BSR
—
JSR
—
@(d,PC) PC)
O
@
@aa:24 aa:32
@@vec:
@@ aa:8 7
O
O
O
O
O
O
O
O
—
O
O
O
RTS, RTS/L —
O
—
O
RTE, RTE/L —
O
TRAPA
[Legend]
d:
d:8 or d:16
Note: * Only @(d:8, PC) is available.
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Section 2 CPU
2.7.2
Table of Instructions Classified by Function
Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in
these tables is defined in table 2.3.
Table 2.3
Operation Notation
Operation Notation
Description
Rd
General register (destination)*
Rs
Rn
ERn
(EAd)
General register (source)*
General register*
General register (32-bit register)
Destination operand
(EAs)
EXR
CCR
VBR
SBR
Source operand
Extended control register
Condition-code register
Vector base register
Short address base register
N
Z
V
C
PC
SP
#IMM
disp
+
−
×
÷
∧
∨
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Stack pointer
Immediate data
Displacement
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
⊕
→
∼
:8/:16/:24/:32
Logical exclusive OR
Move
Logical not (logical complement)
8-, 16-, 24-, or 32-bit length
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.4
Data Transfer Instructions
Instruction
Size
Function
MOV
B/W/L
#IMM → (EAd), (EAs) → (EAd)
Transfers data between immediate data, general registers, and memory.
MOVFPE
B
(EAs) → Rd
MOVTPE
B
Rs → (EAs)
POP
W/L
@SP+ → Rn
Restores the data from the stack to a general register.
PUSH
W/L
Rn → @−SP
Saves general register contents on the stack.
LDM
L
@SP+ → Rn (register list)
Restores the data from the stack to multiple general registers. Two, three,
or four general registers which have serial register numbers can be
specified.
STM
L
Rn (register list) → @−SP
Saves the contents of multiple general registers on the stack. Two, three,
or four general registers which have serial register numbers can be
specified.
MOVA
B/W
EA → Rd
Zero-extends and shifts the contents of a specified general register or
memory data and adds them with a displacement. The result is stored in a
general register.
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Section 2 CPU
Table 2.5
Block Transfer Instructions
Instruction
Size
Function
EEPMOV.B
EEPMOV.W
B
Transfers a data block.
MOVMD.B
B
Transfers byte data which begins at a memory location specified by ER5
to a memory location specified by ER6. The number of byte data to be
transferred is specified by R4 or R4L.
Transfers a data block.
Transfers byte data which begins at a memory location specified by ER5
to a memory location specified by ER6. The number of byte data to be
transferred is specified by R4.
MOVMD.W
W
Transfers a data block.
Transfers word data which begins at a memory location specified by ER5
to a memory location specified by ER6. The number of word data to be
transferred is specified by R4.
MOVMD.L
L
Transfers a data block.
Transfers longword data which begins at a memory location specified by
ER5 to a memory location specified by ER6. The number of longword
data to be transferred is specified by R4.
MOVSD.B
B
Transfers a data block with zero data detection.
Transfers byte data which begins at a memory location specified by ER5
to a memory location specified by ER6. The number of byte data to be
transferred is specified by R4. When zero data is detected during transfer,
the transfer stops and execution branches to a specified address.
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Section 2 CPU
Table 2.6
Arithmetic Operation Instructions
Instruction
Size
Function
ADD
SUB
B/W/L
ADDX
SUBX
B/W/L
INC
DEC
B/W/L
ADDS
SUBS
DAA
DAS
L
MULXU
B/W
MULU
W/L
MULU/U*
L
MULXS
B/W
MULS
W/L
MULS/U*
L
DIVXU
B/W
(EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd)
Performs addition or subtraction on data between immediate data,
general registers, and memory. Immediate byte data cannot be
subtracted from byte data in a general register.
(EAd) ± #IMM ± C → (EAd), (EAd) ± (EAs) ± C → (EAd)
Performs addition or subtraction with carry on data between immediate
data, general registers, and memory. The addressing mode which
specifies a memory location can be specified as register indirect with
post-decrement or register indirect.
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a general register.
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 2-digit 4-bit BCD data.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers (32 bits
× 32 bits → upper 32 bits).
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 16
bits × 16 bits → 16 bits, or 32 bits × 32 bits → 32 bits.
Rd × Rs → Rd
Performs signed multiplication on data in two general registers (32 bits ×
32 bits → upper 32 bits).
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
B
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Section 2 CPU
Instruction
Size
Function
DIVU
W/L
DIVXS
B/W
DIVS
W/L
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits
÷ 16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient.
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient.
(EAd) − #IMM, (EAd) − (EAs)
Compares data between immediate data, general registers, and memory
and stores the result in CCR.
0 − (EAd) → (EAd)
Takes the two's complement (arithmetic complement) of data in a general
register or the contents of a memory location.
(EAd) (zero extension) → (EAd)
Performs zero-extension on the lower 8 or 16 bits of data in a general
register or memory to word or longword size.
The lower 8 bits to word or longword, or the lower 16 bits to longword can
be zero-extended.
(EAd) (sign extension) → (EAd)
Performs sign-extension on the lower 8 or 16 bits of data in a general
register or memory to word or longword size.
The lower 8 bits to word or longword, or the lower 16 bits to longword can
be sign-extended.
TAS
B
MAC*
—
CLRMAC*
—
LDMAC*
—
STMAC*
—
Note:
*
@ERd − 0, 1 → (<bit 7> of @EAd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
(EAs) × (EAd) + MAC → MAC
Performs signed multiplication on memory contents and adds the result to
MAC.
0 → MAC
Clears MAC to zero.
Rs → MAC
Loads data from a general register to MAC.
MAC → Rd
Stores data from MAC to a general register.
When supporting multiplier only
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Section 2 CPU
Table 2.7
Logic Operation Instructions
Instruction
Size
Function
AND
B/W/L
(EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd)
Performs a logical AND operation on data between immediate data,
general registers, and memory.
OR
B/W/L
(EAd) ∨ #IMM → (EAd), (EAd) ∨ (EAs) → (EAd)
Performs a logical OR operation on data between immediate data,
general registers, and memory.
XOR
B/W/L
(EAd) ⊕ #IMM → (EAd), (EAd) ⊕ (EAs) → (EAd)
Performs a logical exclusive OR operation on data between immediate
data, general registers, and memory.
NOT
B/W/L
∼ (EAd) → (EAd)
Takes the one's complement of the contents of a general register or a
memory location.
Table 2.8
Shift Operation Instructions
Instruction
Size
Function
SHLL
B/W/L
(EAd) (shift) → (EAd)
SHLR
Performs a logical shift on the contents of a general register or a memory
location.
The contents of a general register or a memory location can be shifted by
1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by
any bits. In this case, the number of bits is specified by 5-bit immediate
data or the lower 5 bits of the contents of a general register.
SHAL
B/W/L
SHAR
(EAd) (shift) → (EAd)
Performs an arithmetic shift on the contents of a general register or a
memory location.
1-bit or 2-bit shift is possible.
ROTL
B/W/L
ROTR
(EAd) (rotate) → (EAd)
Rotates the contents of a general register or a memory location.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR
B/W/L
(EAd) (rotate) → (EAd)
Rotates the contents of a general register or a memory location with the
carry bit.
1-bit or 2-bit rotation is possible.
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Section 2 CPU
Table 2.9
Bit Manipulation Instructions
Instruction
Size
Function
BSET
B
BSET/cc
B
BCLR
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in the contents of a general register or a memory
location to 1. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
if cc, 1 → (<bit-No.> of <EAd>)
If the specified condition is satisfied, this instruction sets a specified bit in
a memory location to 1. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.
0 → (<bit-No.> of <EAd>)
Clears a specified bit in the contents of a general register or a memory
location to 0. The bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
BCLR/cc
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
if cc, 0 → (<bit-No.> of <EAd>)
If the specified condition is satisfied, this instruction clears a specified bit
in a memory location to 0. The bit number can be specified by 3-bit
immediate data, or by the lower three bits of a general register. The Z flag
status can be specified as a condition.
∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in the contents of a general register or a memory
location. The bit number is specified by 3-bit immediate data or the lower
three bits of a general register.
∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in the contents of a general register or a memory
location and sets or clears the Z flag accordingly. The bit number is
specified by 3-bit immediate data or the lower three bits of a general
register.
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in the contents of a general
register or a memory location and stores the result in the carry flag. The
bit number is specified by 3-bit immediate data.
C ∧ [∼ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in the contents of a general register
or a memory location and stores the result in the carry flag. The bit
number is specified by 3-bit immediate data.
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Section 2 CPU
Instruction
Size
Function
BIOR
B
C ∨ [~ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in the contents of a
general register or a memory location and stores the result in the carry
flag. The bit number is specified by 3-bit immediate data.
BIXOR
B
C ⊕ [~ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in the
contents of a general register or a memory location and stores the result
in the carry flag. The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in the contents of a general register or a memory
location to the carry flag. The bit number is specified by 3-bit immediate
data.
BILD
B
~ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in the contents of a general
register or a memory location to the carry flag. The bit number is specified
by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in the contents of a
general register or a memory location. The bit number is specified by 3-bit
immediate data.
BSTZ
B
Z → (<bit-No.> of <EAd>)
Transfers the zero flag value to a specified bit in the contents of a
memory location. The bit number is specified by 3-bit immediate data.
BIST
B
∼ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in the
contents of a general register or a memory location. The bit number is
specified by 3-bit immediate data.
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Section 2 CPU
Instruction
Size
Function
BISTZ
B
∼ Z → (<bit-No.> of <EAd>)
Transfers the inverse of the zero flag value to a specified bit in the
contents of a memory location. The bit number is specified by 3-bit
immediate data.
BFLD
B
(EAs) (bit field) → Rd
Transfers a specified bit field in memory location contents to the lower bits
of a specified general register.
BFST
B
Rs → (EAd) (bit field)
Transfers the lower bits of a specified general register to a specified bit
field in memory location contents.
Table 2.10 Branch Instructions
Instruction
Size
Function
BRA/BS
B
Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a specified address.
B
Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a subroutine at a specified
address.
Bcc
—
Branches to a specified address if the specified condition is satisfied.
BRA/S
—
Branches unconditionally to a specified address after executing the next
instruction. The next instruction should be a 1-word instruction except for
the block transfer and branch instructions.
JMP
—
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address.
JSR
—
Branches to a subroutine at a specified address.
RTS
—
Returns from a subroutine.
RTS/L
—
Returns from a subroutine, restoring data from the stack to multiple
general registers.
BRA/BC
BSR/BS
BSR/BC
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Section 2 CPU
Table 2.11 System Control Instructions
Instruction
Size
Function
TRAPA
—
Starts trap-instruction exception handling.
RTE
—
Returns from an exception-handling routine.
RTE/L
—
Returns from an exception-handling routine, restoring data from the stack
to multiple general registers.
SLEEP
—
Causes a transition to a power-down state.
LDC
B/W
#IMM → CCR, (EAs) → CCR, #IMM → EXR, (EAs) → EXR
Loads immediate data or the contents of a general register or a memory
location to CCR or EXR.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
L
Rs → VBR, Rs → SBR
Transfers the general register contents to VBR or SBR.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers the contents of CCR or EXR to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
L
VBR → Rd, SBR → Rd
Transfers the contents of VBR or SBR to a general register.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate data.
NOP
—
PC + 2 → PC
Only increments the program counter.
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Section 2 CPU
2.7.3
Basic Instruction Formats
The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
Figure 2.14 shows examples of instruction formats.
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc
Figure 2.14 Instruction Formats
• Operation Field
Indicates the function of the instruction, and specifies the addressing mode and operation to be
carried out on the operand. The operation field always includes the first four bits of the
instruction. Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field
Specifies the branch condition of Bcc instructions.
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Section 2 CPU
2.8
Addressing Modes and Effective Address Calculation
The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a
subset of these addressing modes.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.12 Addressing Modes
No. Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)
4
Index register indirect with displacement
@(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L)
@(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)
5
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@−ERn
Register indirect with pre-increment
@+ERn
Register indirect with post-decrement
@ERn−
6
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
7
Immediate
#xx:3/#xx:4/#xx:8/#xx:16/#xx:32
8
Program-counter relative
@(d:8,PC)/@(d:16,PC)
9
Program-counter relative with index register
@(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)
10
Memory indirect
@@aa:8
11
Extended memory indirect
@@vec:7
2.8.1
Register Direct—Rn
The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the
register field in the instruction code.
R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers.
ER0 to ER7 can be specified as 32-bit registers.
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Section 2 CPU
2.8.2
Register Indirect—@ERn
The operand value is the contents of the memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field of the instruction code.
In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).
2.8.3
Register Indirect with Displacement —@(d:2, ERn), @(d:16, ERn),
or @(d:32, ERn)
The operand value is the contents of a memory location which is pointed to by the sum of the
contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the
register field of the instruction code. The displacement is included in the instruction code and the
16-bit displacement is sign-extended when added to ERn.
This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the
displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the
operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data.
2.8.4
Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)
The operand value is the contents of a memory location which is pointed to by the sum of the
following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an
address register (RnL, Rn, ERn) specified by the register field in the instruction code are zeroextended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction
code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data,
ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4,
respectively.
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Section 2 CPU
2.8.5
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,
or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn−
• Register indirect with post-increment—@ERn+
The operand value is the contents of a memory location which is pointed to by the contents of
an address register (ERn). ERn is specified by the register field of the instruction code. After
the memory location is accessed, 1, 2, or 4 is added to the address register contents and the
sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or
4 for longword access.
• Register indirect with pre-decrement—@−ERn
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is subtracted from the contents of an address register
(ERn). ERn is specified by the register field of the instruction code. After that, the operand
value is stored in the address register. The value subtracted is 1 for byte access, 2 for word
access, or 4 for longword access.
• Register indirect with pre-increment—@+ERn
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn
is specified by the register field of the instruction code. After that, the operand value is stored
in the address register. The value added is 1 for byte access, 2 for word access, or 4 for
longword access.
• Register indirect with post-decrement—@ERn−
The operand value is the contents of a memory location which is pointed to by the contents of
an address register (ERn). ERn is specified by the register field of the instruction code. After
the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and
the remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access.
Using this addressing mode, data to be written is the contents of the general register after
calculating an effective address. If the same general register is specified in an instruction and two
effective addresses are calculated, the contents of the general register after the first calculation of
an effective address is used in the second calculation of an effective address.
Example 1:
MOV.W
R0, @ER0+
When ER0 before execution is H'12345678, H'567A is written at H'12345678.
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Section 2 CPU
Example 2:
MOV.B @ER0+, @ER0+
When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at
H'00001001.
After execution, ER0 is H'00001002.
2.8.6
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The operand value is the contents of a memory location which is pointed to by an absolute address
included in the instruction code.
There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute
addresses.
To access the data area, the absolute address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specified by SBR. For a 16bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the
entire address space.
To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used.
For a 24-bit absolute address, the upper 8 bits are all assumed to be 0 (H'00).
Table 2.13 shows the accessible absolute address ranges.
Table 2.13 Absolute Address Access Ranges
Absolute
Address
Data area
Normal
Mode
Middle
Mode
Advanced
Mode
Maximum
Mode
8 bits
(@aa:8)
A consecutive 256-byte area (the upper address is set in SBR)
16 bits
(@aa:16)
H'0000 to
H'FFFF
H'000000 to
H'007FFF,
H'00000000 to H'00007FFF,
H'FFFF8000 to H'FFFFFFFF
32 bits
(@aa:32)
H'FF8000 to
H'FFFFFF
H'00000000 to H'FFFFFFFF
Program area 24 bits
(@aa:24)
H'000000 to
H'FFFFFF
H'00000000 to H'00FFFFFF
32 bits
(@aa:32)
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H'00000000 to
H'00FFFFFF
H'00000000 to
H'FFFFFFFF
Section 2 CPU
2.8.7
Immediate—#xx
The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the
instruction code.
This addressing mode has short formats in which 3- or 4-bit immediate data can be used.
When the size of immediate data is less than that of the destination operand value (byte, word, or
longword) the immediate data is zero-extended.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit
number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code,
for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction
code, for specifying a vector address.
2.8.8
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,
which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of
the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC
contents. The PC contents to which the displacement is added is the address of the first byte of the
next instruction, so the possible branching range is −126 to +128 bytes (−63 to +64 words) or
−32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting
value should be an even number. In advanced mode, only the lower 24 bits of this branch address
are valid; the upper 8 bits are all assumed to be 0 (H'00).
2.8.9
Program-Counter Relative with Index Register—@(RnL.B, PC), @(Rn.W, PC),
or @(ERn.L, PC)
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,
which is the sum of the following operation result and the 32-bit address of the PC contents: the
contents of an address register specified by the register field in the instruction code (RnL, Rn, or
ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is
the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of
this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).
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Section 2 CPU
2.8.10
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The operand value is a branch address,
which is the contents of a memory location pointed to by an 8-bit absolute address in the
instruction code.
The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes).
In normal mode, the memory location is pointed to by word-size data and the branch address is 16
bits long. In other modes, the memory location is pointed to by longword-size data. In middle or
advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).
Note that the top part of the address range is also used as the exception handling vector area. A
vector address of an exception handling other than a reset or a CPU address error can be changed
by VBR.
Figure 2.15 shows an example of specification of a branch address using this addressing mode.
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode
(b) Advanced Mode
Figure 2.15 Branch Address Specification in Memory Indirect Mode
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Section 2 CPU
2.8.11
Extended Memory Indirect—@@vec:7
This mode can be used by the JMP and JSR instructions. The operand value is a branch address,
which is the contents of a memory location pointed to by the following operation result: the sum
of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4.
The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to
H'0003FF in other modes. In assembler notation, an address to store a branch address is specified.
In normal mode, the memory location is pointed to by word-size data and the branch address is 16
bits long. In other modes, the memory location is pointed to by longword-size data. In middle or
advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).
2.8.12
Effective Address Calculation
Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The
lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign
extended) according to the CPU operating mode.
The valid bits in middle mode are as follows:
• The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for
the transfer and operation instructions.
• The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended
for the branch instructions.
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Section 2 CPU
Table 2.14 Effective Address Calculation for Transfer and Operation Instructions
No.
1
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Immediate
op
IMM
2
Register direct
3
Register indirect
op
rm
rn
31
0
31
0
31
0
31
0
31
0
31
0
31
0
31
0
0
31
0
0
31
0
0
31
0
General register contents
op
4
r
Register indirect with 16-bit displacement
31
0
General register contents
r
op
31
15
Register indirect with 32-bit displacement
+
0
disp
Sign extension
disp
31
0
General register contents
op
disp
5
Index register indirect with 16-bit displacement
r
op
disp
31
0
Zero extension
Contents of general register (RL, R, or ER) 1, 2, or 4
31
disp
r
op
15
0
Zero extension
Contents of general register (RL, R, or ER) 1, 2, or 4
0
disp
×
+
disp
31
0
General register contents
op
+
31
31
Register indirect with post-increment or post-decrement
×
0
disp
Sign extension
Index register indirect with 32-bit displacement
6
+
r
±
r
1, 2, or 4
Register indirect with pre-increment or pre-decrement
31
0
General register contents
±
r
op
1, 2, or 4
7
8-bit absolute address
31
aa
op
7
aa
SBR
16-bit absolute address
op
31
aa
15
aa
Sign extension
32-bit absolute address
op
31
aa
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aa
Section 2 CPU
Table 2.15 Effective Address Calculation for Branch Instructions
No.
1
Addressing Mode and Instruction Format
Register indirect
Effective Address Calculation
Effective Address (EA)
31
31
0
31
0
31
0
31
0
0
31
0
0
31
0
31
0
31
0
0
General register contents
r
op
2
Program-counter relative with 8-bit displacement
31
0
PC contents
31
op
7
Sign extension
disp
+
0
disp
Program-counter relative with 16-bit displacement
31
0
PC contents
31
op
disp
3
15
Program-counter relative with index register
disp
31
0
Zero extension
Contents of general register (RL, R, or ER)
op
+
0
Sign extension
r
2
×
+
0
31
PC contents
4
24-bit absolute address
Zero
31 extension 23
op
aa
aa
32-bit absolute address
op
31
aa
aa
5
Memory indirect
31
op
aa
0
7
aa
Zero extension
0
31
Memory contents
6
Extended memory indirect
31
op
vec
Zero extension
7
1
0
vec
2 or 4
31
×
0
31
0
Memory contents
2.8.13
MOVA Instruction
The MOVA instruction stores the effective address in a general register.
1. Firstly, data is obtained by the addressing mode shown in item 2 of table 2.14.
2. Next, the effective address is calculated using the obtained data as the index by the addressing
mode shown in item 5 of table 2.14. The obtained data is used instead of the general register.
The result is stored in a general register. For details, see H8SX Family Software Manual.
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Section 2 CPU
2.9
Processing States
The H8SX CPU has five main processing states: the reset state, exception-handling state, program
execution state, bus-released state, and program stop state. Figure 2.16 indicates the state
transitions.
• Reset state
In this state the CPU and internal peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, see section 6, Exception Handling.
The reset state can also be entered by a watchdog timer overflow when available.
• Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or
trap instruction. The CPU fetches a start address (vector) from the exception handling vector
table and branches to that address. For further details, see section 6, Exception Handling.
• Program execution state
In this state the CPU executes program instructions in sequence.
• Bus-released state
The bus-released state occurs when the bus has been released in response to a bus request from
a bus master other than the CPU. While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
see section 27, Power-Down Modes.
Reset state*
RES = high
Exception-handling
state
Request for exception
handling
Interrupt
request
End of exception
handling
Program execution
state
Note:
RES = low
Bus-released state
Bus
request
Bus request
Program stop state
SLEEP instruction
* A transition to the reset state occurs whenever the RES signal goes low.
A transition can also be made to the reset state when the watchdog timer overflows.
Figure 2.16 State Transitions
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End of bus request
End of
bus request
Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Operating Mode Selection
This LSI has seven operating modes (modes 1, 2, 3, 4, 5, 6, and 7). The operating mode is selected
by the setting of mode pins MD2 to MD0. Enabling and disabling of the SDRAM interface can be
selected with the MD3 setting for each operating mode. Table 3.1 lists MCU operating mode
settings. Table 3.2 shows the SDRAM interface* setting for each MCU operating mode
Table 3.1
MCU Operating Mode Settings
CPU
Operating
Mode
MCU
Operating
Mode
MD2
MD1
MD0
1
0
0
1
2
0
1
0
3
0
1
1
Boundary scan
Enabled
enabled single-chip
mode
4
1
0
0
5
1
0
1
On-chip ROM
disabled extended
mode
6
1
1
0
7
1
1
1
Table 3.2
MD3
0
1
Advanced
mode
Address
Space
LSI Initiation
Mode
On-Chip
ROM
External Data
Bus Width
Default Max.



16 bits
Disabled
16 bits
16 bits
Disabled
8 bits
16 bits
On-chip ROM
enabled extended
mode
Enabled
8 bits
16 bits
Single-chip mode
Enabled

16 bits
16 Mbytes User boot mode
Boot mode
Enabled
Enabled
16 bits
16 bits
SDRAM Interface Setting for each MCU Operating Mode
SDRAM Interface
Disabled
Enabled
In this LSI, an advanced mode as the CPU operating mode and a 16-Mbyte address space are
available. The initial external bus widths are eight or 16 bits. As the LSI initiation mode, the
external extended mode, on-chip ROM initiation mode, or single-chip initiation mode can be
selected.
Modes 1 and 2 are the user boot mode and the boot mode, respectively, in which the flash memory
can be programmed and erased. For details on the user boot mode and boot mode, see section 24,
Flash Memory.
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Section 3 MCU Operating Modes
Mode 3 is the boundary scan function enabled single-chip mode. For details on the boundary scan
function, see section 25, Boundary Scan.
Mode 7 is a single-chip initiation mode. All I/O ports can be used as general input/output ports.
The external address space cannot be accessed in the initial state, but setting the EXPE bit in the
system control register (SYSCR) to 1 enables to use the external address space. After the external
address space is enabled, ports D, E, and F can be used as an address output bus and ports H and I
as a data bus by specifying the data direction register (DDR) for each port. When the external
address space is not in use, ports J and K can be used by setting the PCJKE bit in the port function
control register D (PFCRD) to 1.
Modes 4 to 6 are external extended modes, in which the external memory and devices can be
accessed. In the external extended modes, the external address space can be designated as 8-bit or
16-bit address space for each area by the bus controller after starting program execution.
If 16-bit address space is designated for any one area, it is called the 16-bit bus widths mode. If 8bit address space is designated for all areas, it is called the 8-bit bus width mode.
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
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Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to the operating mode setting.
• Mode control register (MDCR)
• System control register (SYSCR)
3.2.1
Mode Control Register (MDCR)
MDCR indicates the current operating mode. When MDCR is read from, the states of signals
MD3 to MD0 are latched. Latching is released by a reset.
Bit
Bit Name
15
14
13
12
11
10
9
8
MDS3*3



MDS3
MDS2
MDS1
MDS0
1
0
1
Initial Value 0/Undefined*2*3
Undefined*1 Undefined*1 Undefined*1 Undefined*1
R/W
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Bit Name








Undefined*1
Undefined*1
Undefined*1
R
R
R
Initial Value
0/Undefined*2*3
1
0
1
Undefined*1
R
R
R
R
R
R/W
Notes: 1. Determined by the settings of pins MD2 to MD0
2. Determined by the setting of MD3 pin.
3. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Bit
Bit Name
Initial Value
R/W Descriptions
15

0
R
•
H8SX/1648, H8SX/1648A, H8SX/1648L Group:
Reserved
These are read-only bits and cannot be modified.
MDS7*
3
2
Undefined* *
3
R
•
H8SX/1648G, H8SX/1648H Group:
This pin indicates a value set with the mode pin
(MD3)
When MDCR is read, the signal levels input on the
MD3 pin is latched into this bit. This latch is
released by a reset.
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Section 3 MCU Operating Modes
Bit
Bit Name
Initial Value
R/W Descriptions
14

1
R
Reserved
13

0
R
These are read-only bits and cannot be modified.
12

1
11
MDS3
R
1
R
Mode Select 3 to 0
R
These bits indicate the operating mode selected by
the mode pins (MD2 to MD0) (see table 3.3).
Undefined*
10
MDS2
Undefined*
1
9
MDS1
Undefined*
1
R
8
MDS0
Undefined*
1
R
When MDCR is read, the signal levels input on pins
MD2 to MD0 are latched into these bits. These
latches are released by a reset.
7

0/Undefined* *
R
Reserved
6

1
R
These are read-only bits and cannot be modified.
5

0
R
4

1
3
2
2
3
R

Undefined*
1
R

Undefined*1
R
1

Undefined*
1
R
0

Undefined*
1
R
Notes: 1. Determined by the settings of pins MD2 to MD0
2. Determined by the setting of MD3 pin.
3. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Table 3.3
Settings of Bits MDS3 to MDS0
Mode Pins
MDCR
MCU Operating
Mode
MD2
MD1
MD0
MDS3
MDS2
MDS1
MDS0
1
0
0
1
1
1
0
1
2
0
1
0
1
1
0
0
3
0
1
1
0
1
0
0
4
1
0
0
0
0
1
0
5
1
0
1
0
0
0
1
6
1
1
0
0
1
0
1
7
1
1
1
0
1
0
0
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Section 3 MCU Operating Modes
3.2.2
System Control Register (SYSCR)
SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets
external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode.
Bit
15
14
13
12
11
10
9
8
Bit Name


MACS

FETCHMD

EXPE
RAME
Initial Value
1
1
0
1
0
Undefined*
Undefined*
1
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name






DTCMD

R/W
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
R/W
Note: * The initial value depends on the startup mode.
Bit
Bit Name
Initial
Value
R/W
Descriptions
15

1
R/W
Reserved
14

1
R/W
These bits are always read as 1. The write value
should always be 1.
13
MACS
0
R/W
MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction is non-saturation operation
1: MAC instruction is saturation operation
12

1
R/W
Reserved
This bit is always read as 1. The write value should
always be 1.
11
FETCHMD
0
R/W
Instruction Fetch Mode Select
This LSI can prefetch an instruction in units of 16 bits
or 32 bits. Select the bus width for instruction fetch
depending on the used memory for the storage of
programs.
0: 32-bit mode
1: 16-bit mode
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Section 3 MCU Operating Modes
Bit
Bit Name
10

Initial
Value
1
Undefined*
R/W
Descriptions
R
Reserved
This bit is fixed at 1 in on-chip ROM enabled mode,
and 0 in on-chip ROM disabled mode. This bit cannot
be changed.
9
EXPE
1
Undefined*
R/W
External Bus Mode Enable
Selects external bus mode. In external extended
mode, this bit is fixed 1 and cannot be changed. In
single-chip mode, the initial value of this bit is 0, and
can be read from or written to when PCKJE = 0. Do
3
not write to this bit when PCKJE = 1* .
When writing 0 to this bit after reading EXPE = 1, an
external bus cycle should not be executed.
The external bus cycle may be carried out in parallel
with the internal bus cycle depending on the setting
of the write data buffer function, refresh control
function and EXDMAC bus right release state and
others.
0: External bus disabled
1: External bus enabled
8
RAME
1
R/W
RAM Enable
Enables or disables the on-chip RAM. This bit is
initialized when the reset state is released. Do not
write 0 during access to the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
7 to 2

All 0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
1
DTCMD
1
R/W
DTC Mode Select
Selects DTC operating mode.
0: DTC is in full-address mode
1: DTC is in short address mode
0

1
R/W
Reserved
This bit is always read as 1. The write value should
always be 1.
Notes: 1. The initial value depends on the LSI initiation mode.
2. For details on the settings of the EXPE and PCJKE bits when the external address
space is in use, see section 13.3.12, Port Function Control Register D (PFCRD).
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Section 3 MCU Operating Modes
3.3
Operating Mode Descriptions
3.3.1
Mode 1
This is the user boot mode for the flash memory. The LSI operates in the same way as in mode 7
except for programming and erasing of the flash memory. For details, see section 24, Flash
Memory.
3.3.2
Mode 2
This is the boot mode for the flash memory. The LSI operates in the same way as in mode 7
except for programming and erasing of the flash memory. For details, see section 24, Flash
Memory.
3.3.3
Mode 3
This is the boundary scan function enabled single-chip activation mode. The operation is the same
as mode 7 except for the boundary scan function. For details on the boundary scan function, see
section 25, Boundary Scan.
3.3.4
Mode 4
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled.
The initial bus width mode immediately after a reset is 16 bits, with 16-bit access to all areas.
Ports D, E, and F function as an address bus, ports H and I function as a data bus, and parts of
ports A and B function as bus control signals. However, if all areas are designated as an 8-bit
access space by the bus controller, the bus mode switches to eight bits, and only port H functions
as a data bus.
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Section 3 MCU Operating Modes
3.3.5
Mode 5
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled.
The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas.
Ports D, E, and F function as an address bus, port H functions as a data bus, and parts of ports A
and B function as bus control signals. However, if any area is designated as a 16-bit access space
by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data
bus.
3.3.6
Mode 6
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is enabled.
The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas.
Ports D, E, and F function as input ports, but they can be used as an address bus by specifying the
data direction register (DDR) for each port. For details, see section 13, I/O Ports. Port H functions
as a data bus, and parts of ports A and B function as bus control signals. However, if any area is
designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits,
and ports H and I function as a data bus.
3.3.7
Mode 7
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is enabled.
All I/O ports can be used as general input/output ports. The external address space cannot be
accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1
enables the external address space. After the external address space is enabled, ports D, E, and F
can be used as an address output bus and ports H and I as a data bus by specifying the data
direction register (DDR) for each port. When the external address space is not in use, ports J and
K can be used by setting the PCJKE bit in the port function control register D (PFCRD) to 1. For
details, see section 13, I/O Ports.
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Section 3 MCU Operating Modes
3.3.8
Pin Functions
Table 3.4 shows the pin functions in each operating mode.
Table 3.4
MCU
Pin Functions in Each Operating Mode (Advanced Mode)
Port A
Port B
Port C
Port D Port E Port F
Port H Port I
Operating
Mode
PA7
PA6-3 PA2-0 PB7-1 PB0
PC1-0 PC3-2
1
PF4-0
PF7-5
1
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C*
P*/A
P*/A
P*/A
P*/A
P*/D
P*/D
2
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C*1
P*/A
P*/A
P*/A
P*/A
P*/D
P*/D
P*/C
1
P*/A
P*/A
P*/A
P*/A
P*/D
P*/D
1
A
A
A
P*/A
D
P/D*
1
A
A
A
P*/A
D
P*/D
1
P*/A
P*/A
P*/A
P*/A
D
P*/D
1
P*/A
P*/A
P*/A
P*/A
P*/D
P*/D
3
4
5
6
7
P*/C
P/C*
P/C*
P/C*
P*/C
P*/C
P/C*
P/C*
P/C*
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P/C*
P/C*
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C*
P*/C*
P*/C*
P*/C*
P*/C*
[Legend]
P: I/O port
A: Address bus output
D: Data bus input/output
C: Control signals, clock input/output
*: Immediately after a reset
Note: 1. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
3.4
Address Map
3.4.1
Address Map
Figures 3.1 to 3.3 show the address map in each operating mode.
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Section 3 MCU Operating Modes
Modes 1 and 2
User boot mode,
boot mode
(Advanced mode)
H'000000
Modes 3 and 7
Boundary scan enabled single-chip mode,
single-chip mode
(Advanced mode)
H'000000
On-chip ROM
H'100000
External address space/
reserved area*1*3
External address space/
reserved area*1*3
Reserved area*3
External address space/
reserved area*1*3
H'FFEA00
H'FDC000
H'FEC000
H'FEE000
H'FFC000
Notes:1.
2.
3.
4.
External address space/
reserved area*1*3
Reserved area*3
H'FDC000
External address space
H'FEC000
H'FEE000
Reserved area*3
On-chip RAM/
On-chip RAM/
External address space*4
External address space*4
External address space/
reserved area*1*3
H'FFC000
External address space
H'FFEA00
H'FFEA00
On-chip I/O registers
H'FFFF00 External address space/
reserved area*1*3
H'FFFF20
On-chip I/O registers
H'FFFFFF
Access prohibited area
Access prohibited area
On-chip RAM*2
H'FFC000
H'FD9000
H'FD9000
Access prohibited area
H'FEE000
External address space
H'100000
H'FD9000
H'FEC000
H'000000
On-chip ROM
External address space/
reserved area*1*3
H'FDC000
Modes 4 and 5
On-chip ROM disabled
extended mode
(Advanced mode)
On-chip I/O registers
H'FFFF00 External address space/
reserved area*1*3
H'FFFF20
On-chip I/O registers
H'FFFFFF
On-chip I/O registers
H'FFFF00
External address space
H'FFFF20
On-chip I/O registers
H'FFFFFF
This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0.
The on-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0.
Do not access the reserved areas.
This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Address Map in Each Operating Mode of H8SX/1648, 1648A, 1648L, 1648G,
and 1648H (1)
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Section 3 MCU Operating Modes
Mode 6
On-chip ROM enabled
extended mode
(Advanced mode)
H'000000
On-chip ROM
H'100000
External address space
H'FD9000
Access prohibited area
H'FDC000
External address space
H'FEC000
Reserved area*1
H'FEE000
On-chip RAM/
External address space*2
H'FFC000
External address space
H'FFEA00
On-chip I/O registers
H'FFFF00
External address space
H'FFFF20
On-chip I/O registers
H'FFFFFF
Notes: 1. Do not access the reserved area.
2. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Address Map in Each Operating Mode of H8SX/1648, 1648A, 1648L, 1648G,
and 1648H (2)
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Section 3 MCU Operating Modes
Modes 1 and 2
User boot mode,
boot mode
(Advanced mode)
Modes 3 and 7
Boundary scan enabled single-chip mode,
single-chip mode
(Advanced mode)
H'000000
H'000000
On-chip ROM
H'080000
Access prohibited area
H'100000
Modes 4 and 5
On-chip ROM disabled
extended mode
(Advanced mode)
H'000000
On-chip ROM
H'080000
Access prohibited area
H'100000
External address space/
reserved area*1*3
External address space
External address space/
reserved area*1*3
H'FD9000
H'FD9000
H'FD9000
Access prohibited area
Access prohibited area
H'FDC000 External address space/
reserved area*1*3
H'FDC000 External address space/
reserved area*1*3
H'FDC000
H'FEC000
H'FEC000
H'FEC000
Reserved area*3
H'FF2000
H'FF2000
On-chip RAM*2
External address space/
reserved area*1*3
H'FFFF20
External address space/
reserved area*1*3
On-chip I/O registers
H'FFFFFF
Notes:1.
2.
3.
4.
H'FF2000
On-chip RAM/
External address space*4
H'FFC000
External address space/
reserved area*1*3
On-chip I/O registers
On-chip I/O registers
H'FFFF00
H'FFFF20
H'FFFFFF
Reserved area*3
External address space*4
H'FFEA00
H'FFEA00
External address space
On-chip RAM/
H'FFC000
H'FFC000
H'FFFF00
Reserved area*3
Access prohibited area
External address space/
reserved area*1*3
On-chip I/O registers
External address space
H'FFEA00
On-chip I/O registers
H'FFFF00
External address space
H'FFFF20
On-chip I/O registers
H'FFFFFF
This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0.
The on-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0.
Do not access the reserved areas.
This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.2 Address Map in Each Operating Mode of H8SX/1644, 1644A, 1644L, 1644G,
and 1644H (1)
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Section 3 MCU Operating Modes
MOde 6
On-chip ROM enabled
extended mode
(Advanced mode)
H'000000
On-chip ROM
H'080000
Access prohibited area
H'100000
External address space
H'FD9000
Access prohibited area
H'FDC000
H'FEC000
H'FF2000
External address space
Reserved area*1
On-chip RAM/
External address space*2
H'FFC000
External address space
H'FFEA00
On-chip I/O registers
H'FFFF00
External address space
H'FFFF20
On-chip I/O registers
H'FFFFFF
Notes: 1. Do not access the reserved area.
2. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.2 Address Map in Each Operating Mode of H8SX/1644, 1644A, 1644L, 1644G,
and 1644H (2)
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Section 3 MCU Operating Modes
Modes 1 and 2
User boot mode,
boot mode
(Advanced mode)
H'000000
Modes 3 and 7
Boundary scan enabled single-chip mode,
single-chip mode
(Advanced mode)
H'000000
H'000000
On-chip ROM
H'060000
Access prohibited area
H'100000
On-chip ROM
H'060000
Access prohibited area
H'100000
External address space
External address space/
reserved area*1*3
External address space/
reserved area*1*3
H'FD9000
H'FD9000
H'FD9000
Access prohibited area
Access prohibited area
H'FDC000 External address space/
reserved area*1*3
H'FDC000 External address space/
reserved area*1*3
H'FDC000
H'FEC000
H'FEC000
H'FEC000
Reserved area*3
H'FF6000
H'FFEA00
H'FFFF20
Notes:1.
2.
3.
4.
H'FF6000
On-chip RAM/
External address space*4
H'FFC000
On-chip I/O registers
On-chip I/O registers
H'FFFF00
H'FFFF20
H'FFFFFF
Reserved area*3
On-chip RAM/
H'FFEA00
H'FFFFFF
External address space
External address space/
reserved area*1*3
On-chip I/O registers
External address space/
reserved area*1*3
Access prohibited area
External address space*4
H'FFC000
External address space/
reserved area*1*3
H'FFFF00
Reserved area*3
H'FF6000
On-chip RAM*2
H'FFC000
Modes 4 and 5
On-chip ROM disabled
extended mode
(Advanced mode)
External address space/
reserved area*1*3
On-chip I/O registers
External address space
H'FFEA00
On-chip I/O registers
H'FFFF00
External address space
H'FFFF20
On-chip I/O registers
H'FFFFFF
This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0.
The on-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0.
Do not access the reserved areas.
This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.3 Address Map in Each Operating Mode of H8SX/1642, 1642A, 1642L, 1642G,
and 1642H (1)
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Section 3 MCU Operating Modes
MOde 6
On-chip ROM enabled
extended mode
(Advanced mode)
H'000000
On-chip ROM
H'060000
Access prohibited area
H'100000
External address space
H'FD9000
Access prohibited area
H'FDC000
H'FEC000
H'FF6000
External address space
Reserved area*1
On-chip RAM/
External address space*2
H'FFC000
External address space
H'FFEA00
On-chip I/O registers
H'FFFF00
External address space
H'FFFF20
On-chip I/O registers
H'FFFFFF
Notes: 1. Do not access the reserved area.
2. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.3 Address Map in Each Operating Mode of H8SX/1642, 1642A, 1642L, 1642G,
and 1642H (2)
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Section 3 MCU Operating Modes
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Section 4 Reset
Section 4 Reset
4.1
Types of Reset
There are three types of reset: a pin reset, power-on reset*, voltage-monitoring reset*, deep
software standby reset, and watchdog timer reset. Table 4.1 shows the reset names and sources.
The internal state and pins are initialized by a reset. Figure 4.1 shows the reset targets to be
initialized.
When using power-on reset* and voltage monitoring reset*, RES pin must be fixed high.
Table 4.1
Reset Names And Sources
Reset Name
Source
Pin reset
Voltage input to the RES pin is driven low.
Power-on reset*
Vcc rises or lowers
Voltage-monitoring reset*
Vcc falls (voltage-detection: Vdet)
Deep software standby reset
Deep software standby mode is canceled by an
interrupt.
Watchdog timer reset
The watchdog timer overflows.
Note:
*
Supported only by the H8SX/1648L Group and the H8SX/1648H Group.
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Section 4 Reset
Pin reset
RES
Power-on rest circuit registers*
(RSTSR.PORF)
Registers for voltage-monitoring*
Vcc
Power-on reset
circuit*
Voltage
detection circuit*
Deep software
standby reset
generation circuit
Watchdog
timer
Power-on reset
Voltage-monitoring
reset
RSTSR.LVDF
LVDCR.LVDE
LVDRI
Registers related to power-down mode
RSTSR.DPSRSTF
DPSBYCR, DPSWCR
DPSIER, DPSIFR
DPSIEGR, DPSBKRn
Deep software standby
reset
RSTCR for WDT
Watchdog timer reset
Internal state other than above,
and pin states.
Note: * Supported only by the H8SX/1648LGroup and H8SX/1648H Group.
Figure 4.1 Block Diagram of Reset Circuit
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Section 4 Reset
Note that some registers are not initialized by any of the reset. The following describes the CPU
internal registers.
The PC, one of the CPU internal registers, is initialized by loading the start address from vector
addresses with the reset exception handling. At this time, the T bit in EXR is cleared to 0 and the I
bits in EXR and CCR are set to 1. The general registers, MAC, and other bits in CCR are not
initialized.
The initial value of the SP (ER7) is undefined. The SP should be initialized using the MOV.L
instruction immediately after a reset. For details, see section 2, CPU. For other registers that are
not initialized by a reset, see register descriptions in each section.
When a reset is canceled, the reset exception handling is started. For the reset exception handling,
see section 6.3, Reset.
4.2
Input/Output Pin
Table 4.2 shows the pin related to reset.
Table 4.2
Pin Configuration
Pin Name
Symbol
I/O
Function
Reset
RES
Input
Reset input
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Section 4 Reset
4.3
Register Descriptions
This LSI has the following registers for reset.
• Reset status register (RSTSR)
• Reset control/status register (RSTCSR)
4.3.1
Reset Status Register (RSTSR)
RSTSR indicates a source for generating an internal reset and voltage monitoring interrupt.
Bit
Bit name
Initial value:
R/W:
Note: 1.
2.
3.
4.
5.
Bit
7
7
6
5
4
3
2
1
0
DPSRSTF




LVDF*2

PORF*2
0*3
0*3
R/W
R/W*5
0
0
0
0
0
0* 3
R/(W)*1
R/W
R/W
R/W
R/W
R/W*4
Only 0 can be written to clear the flag.
Supported only by the H8SX/1648LGroup and H8SX/1648H Group.
Initial value is undefined in the H8SX/1648L Group and H8SX/1648H Group.
Only 0 can be written to clear the flag in the H8SX/1648L Group and H8SX/1648H Group.
Only read is possible in the H8SX/1648L Group and H8SX/1648H Group.
Bit Name
DPSRSTF
Initial
Value
0
R/W
Description
1
R/(W)*
Deep Software Standby Reset Flag
Indicates that deep software standby mode is canceled
by an interrupt source specified with DPSIER or
DPSIEGR and an internal reset is generated.
[Setting condition]
When deep software standby mode is canceled by an
interrupt source.
[Clearing conditions]
6 to 3 
All 0
R/W
•
When this bit is read as 1 and then written by 0.
•
2
When a pin reset, power-on reset* and voltagemonitoring reset*2 is generated.
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 4 Reset
•
H8SX/1648 Group, H8SX/1648A Group, H8SX/1648G Group
2 to 0 
All 0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
•
H8SX/1648L Group, H8SX/1648H Group
2
LVDF
Undefined
R/(W)*1
LVD Flag
This bit indicates that the voltage detection circuit has
detected a low voltage (Vcc at or below Vdet).
[Setting condition]
Vcc falling to or below Vdet.
[Clearing condition]
•
•
1
—
Undefined
R/W
After Vcc has exceeded Vdet and the specified
stabilization period has elapsed, writing 0 to the bit
after reading it as 1.
Generation of a pin reset or power-on reset.
Reserved
The write value should always be 0.
0
PORF
Undefined
R
Power-on Reset Flag
This bit indicates that a power-on reset has been
generated.
[Setting condition]
Generation of a power-on reset
[Clearing condition]
Generation of a pin reset
Note:
1. Only 0 can be written to clear the flag.
2. Supported only by the H8SX/1648L Group and H8SX/1648H Group.
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Section 4 Reset
4.3.2
Reset Control/Status Register (RSTCSR)
RSTCSR controls an internal reset signal generated by the watchdog timer and selects the internal
reset signal type. RSTCSR is initialized to H’1F by a pin reset or a deep software standby reset,
but not by the internal reset signal generated by a WDT overflow.
Bit
Bit name
Initial value:
R/W:
7
6
5
4
3
2
1
0
WOVF
RSTE






0
0
0
1
1
1
1
1
R/(W)*
R/W
R/W
R
R
R
R
R
Note: * Only 0 can be written to clear the flag.
Bit
Bit
Name
Initial
Value
7
WOVF 0
R/W
Description
R/(W)* Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog timer mode,
but not set in interval timer mode. Only 0 can be written to.
[Setting condition]
When TCNT overflows (H’FF → H’00) in watchdog timer mode.
[Clearing condition]
When this bit is read as 1 and then written by 0.
(The flag must be read after writing of 0, when this bit is cleared
by the CPU using an interrupt.)
6
RSTE
0
R/W
Reset Enable
Selects whether or not the LSI internal state is reset by a TCNT
overflow in watchdog timer mode.
0: Internal state is not reset when TCNT overflows. (Although
this LSI internal state is not reset, TCNT and TCSR of the
WDT are reset.)
1: Internal state is reset when TCNT overflows.
5

0
R/W
Reserved
Although this bit is readable/writable, operation is not affected
by this bit.
4 to 0 
1
R
Reserved
These are read-only bits but cannot be modified.
Note:
*
Only 0 can be written to clear the flag.
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Section 4 Reset
4.4
Pin Reset
This is a reset generated by the RES pin.
When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a
reset state. In order to firmly reset the LSI, the STBY pin should be set to high and the RES pin
should be held low at least for 20 ms at a power-on. During operation, the RES pin should be held
low at least for 20 states.
4.5
Power-on Reset (POR) (H8SX/1648L Group and H8SX/1648H
Group)
This is an internal reset generated by the power-on reset circuit.
If RES is in the high-level state when power is supplied, a power-on reset is generated. After Vcc
has exceeded Vpor and the specified period (power-on reset time) has elapsed, the chip is released
from the power-on reset state. The power-on reset time is a period for stabilization of the external
power supply and the LSI circuit.
If RES is at the high-level when the power-supply voltage (Vcc) falls to or below Vpor, a poweron reset is generated. The chip is released after Vcc has risen above Vpor and the power-on reset
time has elapsed.
After a power-on reset has been generated, the PORF bit in RSTSR is set to 1. The PORF bit is in
a read-only register and is only initialized by a pin reset. Figure 4.2 shows the operation of a
power-on reset.
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Section 4 Reset
Vpor*1
External
power supply Vcc
Reset state
RES pin
Vcc
POR signal
("L" is valid)
Vcc
Reset state
V
Reset signal
Vcc
("L" is valid)
Pin reset and
OR signal for POR
V
V
tPOR*2
Set
tPOR*2
Set
Vcc
PORF
Notes: For details of the electrical characteristics, see section 29, Electrical Characteristics.
1. VPOR shows a level of power-on reset detection level.
2. TPOR shows a time for power-on reset.
Figure 4.2 Operation of a Power on Reset
4.6
Power Supply Monitoring Reset (H8SX1648L Group, H8SX1648H
Group)
This is an internal reset generated by the power-supply detection circuit.
When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to 1 and the
LVDR1 bit has been cleared to 0, a voltage-monitoring reset is generated. When Vcc subsequently
rises above Vdet, release from the voltage-monitoring reset proceeds after a specified time has
elapsed.
For details of the voltage-monitoring reset, see section 5, Voltage Detection Circuit (LVD), and
section 29, Electrical Characteristics.
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Section 4 Reset
4.7
Deep Software Standby Reset
This is an internal reset generated when deep software standby mode is canceled by an interrupt.
When deep software standby mode is canceled, a deep software standby reset is generated, and
simultaneously, clock oscillation starts. After the time specified with DPSWCR has elapsed, the
deep software standby reset is canceled.
For details of the deep software standby reset, see section 27, Power-Down Modes.
4.8
Watchdog Timer Reset
This is an internal reset generated by the watchdog timer.
When the RSTE bit in RSTCSR is set to 1, a watchdog timer reset is generated by a TCNT
overflow. After a certain time, the watchdog timer reset is canceled.
For details of the watchdog timer reset, see section 18, Watchdog Timer (WDT).
4.9
Determination of Reset Generation Source
Reading RSTCSR, RSTSR, and LVDCR* of the voltage detection circuit determines which reset
was used to execute the reset exception handling. Figure 4.2 shows an example the flow to
identify a reset generation source.
Note: * Supported only by the H8SX/1648L Group and H8SX/1648H Group.
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Section 4 Reset
Reset exception
handling
RSTCSR.RSTE=1
and RSTCSR.WOVF=1
Yes
No
RSTSR.
DPSRSTF=1
No
Yes
LVDCR.LVDE=1
& LVDCR.LCDRI=0
& RSTSR.LVDF=1
Yes
No
RSTSR.
PORF=1
No
Yes
Watchdog timer
reset
Note:
Deep software
standby reset
Voltage monitoring
reset*
Power-on reset*
Pin reset
* Supported only by the H8SX/1648LGroup and H8SX/1648H Group.
Figure 4.3 Example of Reset Generation Source Determination Flow
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Section 5 Voltage Detection Circuit (LVD)
Section 5 Voltage Detection Circuit (LVD)
The voltage detection circuit (LVD) is only supported by the H8SX/1648L Group and the
H8SX/1648H Group.
This circuit is used to monitor Vcc. The LVD is capable of internally resetting the LSI when Vcc
falls and crosses the voltage detection level. An interrupt can also be generated.
5.1
•
Features
Voltage-detection circuit
Capable of detecting the power-supply voltage (Vcc) becoming less than or equal to Vdet.
Capable of generating an internal reset or interrupt when a low voltage is detected.
A block diagram of the voltage detection circuit is shown in figure 5.1.
Vcc
On-chip reference
voltage
(for sensing Vdet)
+
−
LVDMON
Power-supply
stabilization
time
generation
circuit
LVDF
LVDE
Reset /
interrupt
control
circuit
Voltage-monitoring
reset
Voltage-monitoring
interrupt
LVDRI
[Legend]
LVDE:
LVDRI:
LVDMON:
LVDF:
LVD enable
LVD reset / interrupt select
LVD monitor
LVD flag
Figure 5.1 Block Diagram of Voltage-Detection Circuit
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Section 5 Voltage Detection Circuit (LVD)
5.2
Register Descriptions
The registers of the voltage detection circuit are listed below.
•
•
Voltage detection control register (LVDCR)
Reset status register (RSTSR)
5.2.1
Voltage Detection Control Register (LVDCR)
The LVDCR controls the voltage-detection circuit.
LVDE, LVDRI, and LVDMON are initialized by a pin reset or power-on reset
Bit
Bit name
7
6
5
4
3
2
1
0
LVDE
LVDRI
—
LVDMON
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Initial value:
R/W:
Bit
Bit Name
Initial Value
R/W
Description
7
LVDE
0
R/W
LVD Enable
This bit enables or disables issuing of a reset or
interrupt by the voltage-detection circuit.
0: Disabled
1: Enabled
6
LVDRI
0
R/W
LVD Reset/Interrupt Select
This bit selects whether an internal reset or
interrupt is generated when the voltage detection
circuit detects a low voltage. When modifying the
LVDRI bit, ensure that low-voltage detection is in
the disabled state (the LVDE bit is cleared to 0).
0: A reset is generated when a voltage is
detected.
1: An interrupt is generated when a low voltage is
detected.
5
—
0
R/W
Reserved
This bit is always read as 0 and the write value
should always be 0.
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Section 5 Voltage Detection Circuit (LVD)
Bit
Bit Name
Initial Value
R/W
Description
4
LVDMON
0
R
LVD Monitor
This bit monitors the voltage level. This bit is valid
when the LVDE bit is 1 and read as 0 when the
LVDE bit is 0. Writing to this bit is ineffective.
0: Vcc must fall below Vdet.
1: Vcc must rise above Vdet.
3 to 0
—
0
R/W
Reserved
These bits are always read as 0 and the write
value should always be 0.
5.2.2
Reset Status Register (RSTSR)
RSTSR indicates the source of an internal reset or voltage monitoring interrupt.
Bit
Bit name
Initial value:
R/W:
Note:
*
7
6
5
4
3
2
1
0
DPSRSTF
—
—
—
—
LVDF
—
PORF
0
0
0
0
0
Undefined
Undefined
Undefined
R/(W)*
R/W
R/W
R/W
R/W
R/(W)*
R/W
R
To clear the flag, only 0 should be written to.
Bit
Bit Name
Initial Value
R/W
Description
7
DPSRSTF
0
R/W*
Deep Software Standby Reset Flag
This bit indicates release from deep software
standby mode due to the interrupt source
selected by DPSIER and DPSIEGR, and
generation of an internal reset.
[Setting condition]
Release from deep software standby mode due to
an interrupt source.
[Clearing condition]
•
•
Writing 0 to the bit after reading it as1.
Generation of a pin reset, power on reset, or
voltage monitoring reset.
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Section 5 Voltage Detection Circuit (LVD)
Bit
Bit Name
Initial Value
R/W
Description
6 to 3
—
All 0
R/W
Reserved
These bits are always read as 0 and the write
value should always be 0.
2
LVDF
Undefined
R/(W)*
LVD Flag
This bit indicates that the voltage detection circuit
has detected a low voltage (Vcc at or below
Vdet).
[Setting condition]
Vcc falling to or below Vdet.
[Clearing condition]
•
•
1
—
Undefined
R/W
After Vcc has exceeded Vdet and the
specified stabilization period has elapsed,
writing 0 to the bit after reading it as 1.
Generation of a pin reset or power-on reset.
Reserved
The write value should always be 0.
0
PORF
Undefined
R
Power-on Reset Flag
This bit indicates that a power-on reset has been
generated.
[Setting condition]
Generation of a power-on reset
[Clearing condition]
Generation of a pin reset
Note:
*
To clear the flag, only 0 should be written to.
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Section 5 Voltage Detection Circuit (LVD)
5.3
Voltage Detection Circuit
5.3.1
Voltage Monitoring Reset
Figure 5.2 shows the timing of a voltage monitoring reset by the voltage-detection circuit.
When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to 1 and the
LVDRI bit has been cleared to 0, the LVDF bit is set to 1 and the voltage-detection circuit
generates a voltage monitoring reset.
Next, after Vcc has risen above Vdet, release from the voltage-monitoring reset takes place after a
period for stabilization (tpor) has elapsed. The period for stabilization (tpor) is a time that is generated
by the voltage detection circuit in order to stabilize the Vcc and the internal circuit of the LSI.
When a voltage-monitoring reset is generated, the LVDF bit is set to 1.
For details, see section 29, Electrical Characteristics.
Vcc
Vdet
Vpor
↓Write 1
LVDE
↓Write 0
LVDRI
Stabilization time (tPOR)
Internal
reset signal
(Low)
Figure 5.2 Timing of the Voltage-Monitoring Reset
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Section 5 Voltage Detection Circuit (LVD)
5.3.2
Voltage Monitoring Interrupt
Figure 5.3 shows the timing of a voltage monitoring interrupt by the voltage-detection circuit.
When Vcc falls below the Vdet in a state where the LVDE and LVDRI bits in LVDCR are both
set to 1, the LVDF bit is set to 1 and a voltage monitoring interrupt is requested.
The voltage monitoring interrupt signal is internally connected to IRQ14-B, so the IRQ14F bit in
the ISR is set to 1 when the interrupt is generated.
As for the IRQ14 setting, set both the ITS14 bit in PFCRB and the IRQ14E bit in the IER to 1, and
the IRQ14SR and IRQ14SF bits in the ISCR to 01 (interrupt request on falling edge).
Figure 5.4 shows the procedure for setting the voltage-monitoring interrupt.
Vcc
Vdet
Vpor
↓Write 1
LVDE
↓Write 1
LVDRI
Stabilization time (tPOR)
Voltage-monitoring
signal
Set
LVDF
Voltage-monitoring
interrupt signal
(IRQ14)
Set
IRQ14F
Figure 5.3 Timing of the Voltage-Monitoring Interrupt
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Write 0 after
reading as 1
Section 5 Voltage Detection Circuit (LVD)
Start program
Voltage monitoring interrupt
(IRQ14) disabled
IER.IRQ14E = write 0
LVDCR.LVDRI = write 1
LVDCR.LVDE = write 1
Voltage detection and
IRQ register settings
PFCRB.ITS14 = write 1
ISCR setting
(IRQ14SR = 0, IRQ14SF = 1)
If the flag has been set to 1
before the voltage-monitoring
interrupt is enabled, clear it
by writing 0 after having read
it as 1.
ISR.IRQ14F = clear
LVDCR.
LVDMON = 1
Yes
No (Vcc low)
(Vcc high)
Processing
for lowered Vcc
Clear RSTSR.LVDF*
Voltage-monitoring interrupt
(IRQ14) enabled
IER.IRQ14E = write 1
Interrupt generation
when a low voltage is
detected
Processing for lowered Vcc
Note:
*
When the LVDF cannot be cleared despite Vcc being at a higher electrical potential than
Vdet (LVDMON = 1), the voltage-detection circuit is in the state of waiting for stabilization.
Clear the bit again after the stabilization time (tPOR) has elapsed.
Figure 5.4 Example of the Procedure for Setting the Voltage-Monitoring Interrupt
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Section 5 Voltage Detection Circuit (LVD)
5.3.3
Release from Deep Software Standby Mode by the Voltage-Detection Circuit
If the LVDE and LVDRI bits in LVDCR and the DLVDIE bit in DPSIER have all been set to 1
during a period in deep software standby mode, the voltage-detection circuit requests release from
deep software standby mode when Vcc falls to or below Vdet. This sets the DLVDIF bit in
DPSIFR to 1, thus producing release from the deep software standby mode. For the deep software
standby mode, see section 27, Power-Down Modes.
5.3.4
Voltage Monitor
The result of voltage detection by the voltage-detection circuit can be monitored by checking the
value of the LVDMON bit in LVDCR. When the LVDMON bit has been enabled by setting the
LVDE bit, 0 indicates that Vcc is at or below Vdet and 1 indicates that Vcc is above Vdet. This
bit should be read while the voltage-monitoring reset has been disabled by setting the LVDRI bit
to 1.
Before clearing the LVDF bit in RSTSR to 0, confirm that the LVDMON bit is set to 1 (indicating
that Vcc is above Vdet). When it is impossible to clear the LVDF bit despite the LVDMON bit
being 1, the voltage-detection circuit is in the state of waiting for stabilization. In such cases, clear
the bit again after the stabilization time (tpor) has elapsed.
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Section 6 Exception Handling
Section 6 Exception Handling
6.1
Exception Handling Types and Priority
As table 6.1 indicates, exception handling is caused by a reset, a trace, an address error, an
interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal
instruction or slot illegal instruction). Exception handling is prioritized as shown in table 6.1. If
two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode. For details on the interrupt control mode, see section 7, Interrupt Controller.
Table 6.1
Exception Types and Priority
Priority
Exception Type
Exception Handling Start Timing
High
Reset
Exception handling starts at the timing of level change from
low to high on the RES pin, or when the watchdog timer
overflows. The CPU enters the reset state when the RES
pin is low.
Illegal instruction
Exception handling starts when an undefined code is
executed.
Trace*1
Exception handling starts after execution of the current
instruction or exception handling, if the trace (T) bit in EXR
is set to 1.
Address error
After an address error has occurred, exception handling
starts on completion of instruction execution.
Interrupt
Exception handling starts after execution of the current
instruction or exception handling, if an interrupt request has
occurred.*2
Sleep instruction
Exception handling starts by execution of a sleep instruction
(SLEEP), if the SSBY bit in SBYCR is set to 0 and the
SLPIE bit in SBYCR is set to 1.
Trap instruction*3
Exception handling starts by execution of a trap instruction
(TRAPA).
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests and sleep instruction exception handling
requests are accepted at all times in program execution state.
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Section 6 Exception Handling
6.2
Exception Sources and Exception Handling Vector Table
Different vector table address offsets are assigned to different exception sources. The vector table
addresses are calculated from the contents of the vector base register (VBR) and vector table
address offset of the vector number. The start address of the exception service routine is fetched
from the exception handling vector table indicated by this vector table address.
Table 6.2 shows the correspondence between the exception sources and vector table address
offsets. Table 6.3 shows the calculation method of exception handling vector table addresses.
Table 6.2
Exception Handling Vector Table
Vector Table Address Offset*1
Exception Source
Vector Number
Normal Mode*
2
Advanced, Middle*2,
Maximum*2 Modes
Reset
0
H'0000 to H'0001
H'0000 to H'0003
Reserved for system use
1
H'0002 to H'0003
H'0004 to H'0007
2
H'0004 to H'0005
H'0008 to H'000B
3
H'0006 to H'0007
H'000C to H'000F
Illegal instruction
4
H'0008 to H'0009
H'0010 to H'0013
Trace
5
H'000A to H'000B
H'0014 to H'0017
Reserved for system use
6
H'000C to H'000D
H'0018 to H'001B
Interrupt (NMI)
7
H'000E to H'000F
H'001C to H'001F
(#0)
8
H'0010 to H'0011
H'0020 to H'0023
(#1)
9
H'0012 to H'0013
H'0024 to H'0027
(#2)
10
H'0014 to H'0015
H'0028 to H'002B
(#3)
11
H'0016 to H'0017
H'002C to H'002F
12
H'0018 to H'0019
H'0030 to H'0033
DMA address error*
13
H'001A to H'001B
H'0034 to H'0037
UBC break interrupt
14
H'001C to H'001D
H'0038 to H'003B
Reserved for system use
15

17
H'001E to H'001F

H'0022 to H'0023
H'003C to H'003F

H'0044 to H'0047
Sleep interrupt
18
H'0024 to H'0025
H'0048 to H'004B
Trap instruction
CPU address error
3
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Section 6 Exception Handling
Vector Table Address Offset*1
2
Advanced, Middle*2,
Maximum*2 Modes
Exception Source
Vector Number
Normal Mode*
Reserved for system use
19

23
H'0026 to H'0027

H'002E to H'002F
H'004C to H'004F

H'005C to H'005F
User area (not used)
24

63
H'0030 to H'0031

H'007E to H'007F
H'0060 to H'0063

H'00FC to H'00FF
External interrupt
IRQ0
64
H'0080 to H'0081
H'0100 to H'0103
IRQ1
65
H'0082 to H'0083
H'0104 to H'0107
IRQ2
66
H'0084 to H'0085
H'0108 to H'010B
IRQ3
67
H'0086 to H'0087
H'010C to H'010F
IRQ4
68
H'0088 to H'0089
H'0110 to H'0113
IRQ5
69
H'008A to H'008B
H'0114 to H'0117
IRQ6
70
H'008C to H'008D
H'0118 to H'011B
IRQ7
71
H'008E to H'008F
H'011C to H'011F
IRQ8
72
H'0090 to H'0091
H'0120 to H'0123
IRQ9
73
H'0092 to H'0093
H'0124 to H'0127
IRQ10
74
H'0094 to H'0095
H'0128 to H'012B
IRQ11
75
H'0096 to H'0097
H'012C to H'012F
IRQ12
76
H'0098 to H'0099
H'0130 to H'0133
IRQ13
77
H'009A to H'009B
H'0134 to H'0137
IRQ14
78
H'009C to H'009D
H'0138 to H'013B
IRQ15
79
H'009E to H'009F
H'013C to H'013F
80

255
H'00A0 to H'00A1

H'01FE to H'01FF
H'0140 to H'0143

H'03FC to H'03FF
4
Internal interrupt*
Notes: 1.
2.
3.
4.
Lower 16 bits of the address.
Not available in this LSI.
5
A DMA address error is generated by the DTC, DMAC, and EXDMAC* .
For details of internal interrupt vectors, see section 7.5, Interrupt Exception Handling
Vector Table.
5. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 6 Exception Handling
Table 6.3
Calculation Method of Exception Handling Vector Table Address
Exception Source
Calculation Method of Vector Table Address
Reset, CPU address error
Vector table address = (vector table address offset)
Other than above
Vector table address = VBR + (vector table address offset)
[Legend]
VBR: Vector base register
Vector table address offset: See table 6.2.
6.3
Reset
A reset has priority over any other exception. When the RES pin goes low, all processing halts and
this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20
ms with the STBY pin driven high when the power is turned on. When operation is in progress,
hold the RES pin low for at least 20 cycles.
The chip can also be reset by release of deep software standby mode or overflow of the watchdog
timer. For details, see section 18, Watchdog Timer (WDT) and section 27, Power-Down Modes.
A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules.
The interrupt control mode is 0 immediately after a reset.
6.3.1
Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are
set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 6.1 and 6.2 show examples of the reset sequence.
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Section 6 Exception Handling
6.3.2
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
6.3.3
On-Chip Peripheral Functions after Reset Release
After the reset state is released, MSTPCRA and MSTPCRB are initialized to H'0FFF and H'FFFF,
respectively, and all modules except for EXDMAC*, the DTC, and DMAC enter the module stop
state.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when the module stop state is canceled.
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Vector
fetch
Internal
operation
First
instruction
prefetch
Iφ
RES
Internal
address bus
(1)
(3)
Internal read
signal
Internal write
signal
Internal data
bus
High
(2)
(4)
(1): Reset exception handling vector address (when reset, (1) = H'000000)
(2): Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First instruction in the exception handling routine
Figure 6.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)
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Section 6 Exception Handling
Internal First instruction
operation
prefetch
Vector fetch
*
*
*
Bφ
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
D15 to D0
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5) = (2)(4))
(6) First instruction in the exception handling routine
Note: * Seven program wait cycles are inserted.
Figure 6.2 Reset Sequence
(16-Bit External Access in On-chip ROM Disabled Advanced Mode)
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Section 6 Exception Handling
6.4
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit
must be cleared. For details on interrupt control modes, see section 7, Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table
6.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is
canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit
saved on the stack retains its value of 1, and when control is returned from the trace exception
handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not
carried out after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 6.4
Status of CCR and EXR after Trace Exception Handling
CCR
Interrupt Control Mode
I
UI
EXR
T
0
Trace exception handling cannot be used.
2
1

0
I2 to I0

[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains the previous value.
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Section 6 Exception Handling
6.5
Address Error
6.5.1
Address Error Source
Instruction fetch, stack operation, or data read/write shown in table 6.5 may cause an address
error.
Table 6.5
Bus Cycle and Address Error
Bus Cycle
Type
Bus Master
Description
Address Error
Instruction fetch
CPU
Fetches instructions from even addresses
No (normal)
Fetches instructions from odd addresses
Occurs
Fetches instructions from areas other than on-chip
1
peripheral module space*
No (normal)
Fetches instructions from on-chip peripheral module
1
space*
Occurs
Fetches instructions from external memory space in
single-chip mode
Occurs
Fetches instructions from access prohibited area.*
Stack operation
Data read/write
CPU
CPU
2
Accesses stack when the stack pointer value is even
address
No (normal)
Accesses stack when the stack pointer value is odd
Occurs
Accesses word data from even addresses
No (normal)
Accesses word data from odd addresses
No (normal)
Accesses external memory space in single-chip mode
Occurs
2
Data read/write
DTC or DMAC
Accesses to access prohibited area*
Occurs
Accesses word data from even addresses
No (normal)
Accesses word data from odd addresses
No (normal)
Accesses external memory space in single-chip mode
Occurs
2
Data read/write
3
EXDMAC*
Accesses to access prohibited area*
Occurs
Accesses word data from even addresses
No (normal)
Accesses word data from odd addresses
No (normal)
Accesses external memory space in single-chip mode
Occurs
2
Accesses to access prohibited area*
Occurs
Accesses to external memory space
No (normal)
Accesses to space other than external memory space
Occurs
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Occurs
Section 6 Exception Handling
Bus Cycle
Type
Bus Master
Description
Single address
transfer
DMAC/
3
EXDMAC*
Address access space is the external memory space for No (normal)
single address transfer
Address Error
Address access space is not the external memory space Occurs
for single address transfer
Notes: 1. For on-chip peripheral module space, see section 9, Bus Controller (BSC).
2. For the access prohibited area, refer to figure 3.1 in section 3.4, Address Map.
3. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
6.5.2
Address Error Exception Handling
When an address error occurs, address error exception handling starts after the bus cycle causing
the address error ends and current instruction execution completes. The address error exception
handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the address error is generated, the
start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
Even though an address error occurs during a transition to an address error exception handling, the
address error is not accepted. This prevents an address error from occurring due to stacking for
exception handling, thereby preventing infinitive stacking.
If the SP contents are not a multiple of 2 when an address error exception handling occurs, the
stacked values (PC, CCR, and EXR) are undefined.
When an address error occurs, the following is performed to halt the DTC, DMAC, and
EXDMAC*.
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Section 6 Exception Handling
•
•
•
•
The ERR bit of DTCCR in the DTC is set to 1.
The ERRF bit of DMDR_0 in the DMAC is set to 1.
The ERRF bit of EDMDR_0 in the EXDMAC* is set to 1.
The DTE bits of DMDRs for all channels in the DMAC are cleared to 0 to forcibly terminate
transfer.
• The DTE bits of EDMDRs for all channels in the EXDMAC* are cleared to 0 to forcibly
terminate transfer.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Table 6.6 shows the state of CCR and EXR after execution of the address error exception
handling.
Table 6.6
Status of CCR and EXR after Address Error Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
T
I2 to I0
0
1



2
1

0
7
[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains the previous value.
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Section 6 Exception Handling
6.6
Interrupts
6.6.1
Interrupt Sources
Interrupt sources are NMI, UBC break interrupt, IRQ0 to IRQ15, and on-chip peripheral modules,
as shown in table 6.7.
Table 6.7
Interrupt Sources
Type
Source
Number of Sources
NMI
NMI pin (external input)
1
UBC break
interrupt
User break controller (UBC)
1
IRQ0 to IRQ15
IRQ0 to IRQ15 pin (external input)
16
VoltageVoltage-detection circuit (LVD) *2
2
detection circuit*
On-chip
peripheral
module
32K timer (TM32K)*1
1
DMA controller (DMAC)
1
1
8
1
EXDMA controller* (EXDMAC)*
8
Watchdog timer (WDT)
1
A/D converter
3
16-bit timer pulse unit (TPU)
52
8-bit timer (TMR)
16
Serial communications interface (SCI)
28
2
I C bus interface 2 (IIC2)
Refresh controller*
1
4
1
Notes: 1. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
2. Supported only by the H8SX/1648L Group and the H8SX/1648H Group.
Different vector numbers and vector table offsets are assigned to different interrupt sources. For
vector number and vector table offset, refer to table 7.2, Interrupt Sources, Vector Address
Offsets, and Interrupt Priority in section 7, Interrupt Controller.
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Section 6 Exception Handling
6.6.2
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiple-interrupt control. The source to start interrupt exception handling and the vector address
differ depending on the product. For details, refer to section 7, Interrupt Controller.
The interrupt exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the interrupt source is generated,
the start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
6.7
Instruction Exception Handling
There are three instructions that cause exception handling: trap instruction, sleep instruction, and
illegal instruction.
6.7.1
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state. The trap
instruction exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the vector number specified in
the TRAPA instruction is generated, the start address of the exception service routine is loaded
from the vector table to PC, and program execution starts from that address.
A start address is read from the vector table corresponding to a vector number from 0 to 3, as
specified in the instruction code.
Table 6.8 shows the state of CCR and EXR after execution of trap instruction exception handling.
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Section 6 Exception Handling
Table 6.8
Status of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
T
I2 to I0
0
1



2
1

0

[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains the previous value.
6.7.2
Sleep Instruction Exception Handling
The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY
bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The sleep instruction exception
handling can always be executed in the program execution state. In the exception handling, the
CPU operates as follows.
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the vector number specified in
the SLEEP instruction is generated, the start address of the exception service routine is loaded
from the vector table to PC, and program execution starts from that address.
Bus masters other than the CPU may gain the bus mastership after a sleep instruction has been
executed. In such cases the sleep instruction will be started when the transactions of a bus master
other than the CPU has been completed and the CPU has gained the bus mastership.
Table 6.9 shows the state of CCR and EXR after execution of sleep instruction exception
handling. For details, see section 27.10, Sleep Instruction Exception Handling.
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Section 6 Exception Handling
Table 6.9
Status of CCR and EXR after Sleep Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
T
I2 to I0
0
1



2
1

0
7
[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains the previous value.
6.7.3
Exception Handling by Illegal Instruction
The illegal instructions are general illegal instructions and slot illegal instructions. The exception
handling by the general illegal instruction starts when an undefined code is executed. The
exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code
length is two words or more, or it changes the PC contents) at a delay slot (immediately after a
delayed branch instruction) is executed. The exception handling by the general illegal instruction
and slot illegal instruction is always executable in the program execution state.
The exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the occurred exception is
generated, the start address of the exception service routine is loaded from the vector table to
PC, and program execution starts from that address.
Table 6.10 shows the state of CCR and EXR after execution of illegal instruction exception
handling.
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Section 6 Exception Handling
Table 6.10 Status of CCR and EXR after Illegal Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
T
I2 to I0
0
1



2
1

0

[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains the previous value.
6.8
Stack Status after Exception Handling
Figure 6.3 shows the stack after completion of exception handling.
Advanced mode
SP
EXR
Reserved*
SP
CCR
PC (24 bits)
Interrupt control mode 0
CCR
PC (24 bits)
Interrupt control mode 2
Note: * Ignored on return.
Figure 6.3 Stack Status after Exception Handling
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Section 6 Exception Handling
6.9
Usage Note
When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by a word transfer instruction or a longword transfer instruction,
and the value of the stack pointer (SP: ER7) should always be kept even. Use the following
instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Performing stack manipulation while SP is set to an odd value leads to an address error. Figure 6.4
shows an example of operation when the SP value is odd.
Address
CCR
SP
R1L
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFE
SP
H'FFFEFF
TRAPA instruction executed
SP set to H'FFFEFF
MOV.B R1L, @-ER7 executed
Data saved above SP
Contents of CCR lost
(Address error occurred)
[Legend]
CCR :
PC :
R1L :
SP :
Condition code register
Program counter
General register R1L
Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 6.4 Operation when SP Value is Odd
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Section 7 Interrupt Controller
Section 7 Interrupt Controller
7.1
Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the
interrupt control register (INTCR).
• Priority can be assigned by the interrupt priority register (IPR)
IPR provides for setting interrupt priory. Eight levels can be set for each module for all
interrupts except for the interrupt requests listed below. The following eight interrupt requests
are given priority of 8, therefore they are accepted at all times.
 NMI
 Illegal instructions
 Trace
 Trap instructions
 CPU address error
 DMA address error*1
 Sleep instruction
 UBC break interrupt
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Seventeen external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level
sensing, can be selected for IRQ15 to IRQ0.
• DTC and DMAC control
DTC and DMAC can be activated by means of interrupts.
• CPU priority control function
The priority levels can be assigned to the CPU, DTC, DMAC, and EXDMAC*2. The priority
level of the CPU can be automatically assigned on an exception generation. Priority can be
given to the CPU interrupt exception handling over that of the DTC, DMAC, and EXDMAC*2
transfer.
Notes: 1. DMA address error is occurred in the DTC, DMAC, and EXDMAC*2.
2. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 7 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 7.1.
CPU
INTM1, INTM0
INTCR
IPR
NMIEG
I
I2 to I0
NMI input
LVD2*2
IRQ15
NMI input unit
CPU
vector
IRQ input unit
ISR
Priority
determination
IRQ14
DMAC
ISCR
Internal interrupt
sources
WOVI to ADI1
EXR
CPU
interrupt request
IRQ input
TM32K*1
CCR
IER
DMAC
activation
permission
SSIER
DMAC priority
control
DMDR
Source selector
CPU priority
DTC activation
request
DTCER DTCCR
CPUPCR
DTC priority
control
DTC priority
Interrupt controller
DTC vector
Activation
request
clear signal
[Legend]
INTCR: Interrupt control register
CPUPCR: CPU priority control register
IRQ sense control register
ISCR:
IRQ enable register
IER:
IRQ status register
ISR:
SSIER:
IPR:
DTCER:
DTCCR:
Software standby release IRQ enable register
Interrupt priority register
DTC enable register
DTC control register
Notes: 1. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
2. Supported only by the H8SX/1648L Group and H8SX/1648H Group.
Figure 7.1 Block Diagram of Interrupt Controller
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DTC
Section 7 Interrupt Controller
7.2
Input/Output Pins
Table 7.1 shows the pin configuration of the interrupt controller.
Table 7.1
Pin Configuration
Name
I/O
Function
NMI
Input
Nonmaskable External Interrupt
Rising or falling edge can be selected.
IRQ15 to IRQ0
Input
Maskable External Interrupts
Rising, falling, or both edges, or level sensing, can be
independently selected.
7.3
Register Descriptions
The interrupt controller has the following registers.
• Interrupt control register (INTCR)
• CPU priority control register (CPUPCR)
• Interrupt priority register
H8SX/1648 Group, H8SX/1648A Group, H8SX/1648L Group:
Interrupt priority registers A to I, K to O, Q, and R
(IPRA to IPRI, IPRK to IPRO, IPRQ, and IPRR)
H8SX/1648G Group, H8SX/1648H Group:
Interrupt priority registers A to O, Q, and R
(IPRA to IPRO, IPRQ, and IPRR)
• IRQ enable register (IER)
• IRQ sense control registers H and L (ISCRH, ISCRL)
• IRQ status register (ISR)
• Software standby release IRQ enable register (SSIER)
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Section 7 Interrupt Controller
7.3.1
Interrupt Control Register (INTCR)
INTCR selects the interrupt control mode, and the edge which detects NMI.
Bit
7
6
5
4
3
2
1
0
Bit Name


INTM1
INTM0
NMIEG



Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R
R
R
Bit
Bit Name
Initial
Value
R/W
Description
7

0
R
Reserved
6

0
R
These are read-only bits and cannot be modified.
5
INTM1
0
R/W
Interrupt Control Select Mode 1 and 0
4
INTM0
0
R/W
These bits select either of two interrupt control modes for
the interrupt controller.
00: Interrupt control mode 0
Interrupts are controlled by I bit in CCR.
01: Setting prohibited.
10: Interrupt control mode 2
Interrupts are controlled by bits I2 to I0 in EXR, and
IPR.
11: Setting prohibited.
3
NMIEG
0
R/W
NMI Edge Select
Selects the input edge for the NMI pin.
0: Interrupt request generated at falling edge of NMI input
1: Interrupt request generated at rising edge of NMI input
2 to 0

All 0
R
Reserved
These are read-only bits and cannot be modified.
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Section 7 Interrupt Controller
7.3.2
CPU Priority Control Register (CPUPCR)
CPUPCR sets whether or not the CPU has priority over the DTC, DMAC, and EXDMAC*. The
interrupt exception handling by the CPU can be given priority over that of the DTC, DMAC, and
EXDMAC* transfer. The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR.
The priority level of the DMAC and EXDMAC* is set by the DMAC and EXDMAC* control
registers for each channel.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
CPUPCE
DTCP2
DTCP1
DTCP0
IPSETE
CPUP2
CPUP1
CPUP0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/(W)*
R/(W)*
R/(W)*
Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.
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Section 7 Interrupt Controller
Bit
Bit Name
Initial
Value
R/W
Description
7
CPUPCE
0
R/W
6
5
4
DTCP2
DTCP1
DTCP0
0
0
0
R/W
R/W
R/W
3
IPSETE
0
R/W
CPU Priority Control Enable
Controls the CPU priority control function. Setting this bit
to 1 enables the CPU priority control over the DTC,
1
DMAC, and EXDMAC* .
0: CPU always has the lowest priority
1: CPU priority control enabled
DTC Priority Level 2 to 0
These bits set the DTC priority level.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
Interrupt Priority Set Enable
Controls the function which automatically assigns the
interrupt priority level of the CPU. Setting this bit to 1
automatically sets bits CPUP2 to CPUP0 by the CPU
interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR).
0: Bits CPUP2 to CPUP0 are not updated automatically
1: The interrupt mask bit value is reflected in bits CPUP2
to CPUP0
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Section 7 Interrupt Controller
Bit
Bit Name
Initial
Value
R/W
2
CPUP2
0
R/(W)*
2
CPU Priority Level 2 to 0
1
CPUP1
0
R/(W)*
2
R/(W)*
2
These bits set the CPU priority level. When the
CPUPCE is set to 1, the CPU priority control function
1
over the DTC, DMAC, and EXDMAC* becomes valid
and the priority of CPU processing is assigned in
accordance with the settings of bits CPUP2 to CPUP0.
0
CPUP0
0
Description
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
Notes: 1. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
2. When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits
cannot be modified.
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Section 7 Interrupt Controller
7.3.3
Interrupt Priority Register
H8SX/1648 Group, H8SX/1648A Group and H8SX/1648L Group:
Interrupt Priority Registers A to I, K to O, Q, and R
(IPRA to IPRI, IPRK to IPRO, IPRQ, and IPRR)
H8SX/1648G Group, and H8SX/1648H Group:
Interrupt Priority Registers A to O, O, and R
(IPRA to IPRO, IPRQ, and IPRR)
IPR sets priory (levels 7 to 0) for interrupts other than NMI.
Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4,
and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between
the interrupt sources and the IPR settings, see table 7.2.
Bit
15
14
13
12
11
10
9
8
Bit Name

IPR14
IPR13
IPR12

IPR10
IPR9
IPR8
Initial Value
0
1
1
1
0
1
1
1
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name

IPR6
IPR5
IPR4

IPR2
IPR1
IPR0
Initial Value
0
1
1
1
0
1
1
1
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15

0
R
14
13
12
IPR14
IPR13
IPR12
1
1
1
R/W
R/W
R/W
Reserved
This is a read-only bit and cannot be modified.
Sets the priority level of the corresponding interrupt
source.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
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Section 7 Interrupt Controller
Bit
Bit Name
Initial
Value
R/W
Description
11

0
R
10
9
8
IPR10
IPR9
IPR8
1
1
1
R/W
R/W
R/W
7

0
R
6
5
4
IPR6
IPR5
IPR4
1
1
1
R/W
R/W
R/W
Reserved
This is a read-only bit and cannot be modified.
Sets the priority level of the corresponding interrupt
source.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
Reserved
This is a read-only bit and cannot be modified.
Sets the priority level of the corresponding interrupt
source.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
3

0
R
2
IPR2
1
R/W
1
IPR1
1
R/W
Sets the priority level of the corresponding interrupt
source.
0
IPR0
1
R/W
000: Priority level 0 (lowest)
Reserved
This is a read-only bit and cannot be modified.
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
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Section 7 Interrupt Controller
7.3.4
IRQ Enable Register (IER)
IER enables interrupt requests IRQ15 to IRQ0.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
IRQ15E
IRQ14E
IRQ13E
IRQ12E
IRQ11E
IRQ10E
IRQ9E
IRQ8E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
IRQ15E
0
R/W
IRQ15 Enable
The IRQ15 interrupt request is enabled when this bit is 1.
1
The 32KOVI interrupt in the TM32K* is also enabled.
14
IRQ14E
0
R/W
IRQ14 Enable
The IRQ14 interrupt request is enabled when this bit is 1
2
The voltage-monitoring interrupt in the LVD* is enabled.
13
IRQ13E
0
R/W
IRQ13 Enable
The IRQ13 interrupt request is enabled when this bit is 1.
12
IRQ12E
0
R/W
IRQ12 Enable
The IRQ12 interrupt request is enabled when this bit is 1.
11
IRQ11E
0
R/W
IRQ11 Enable
10
IRQ10E
0
R/W
IRQ10 Enable
The IRQ11 interrupt request is enabled when this bit is 1.
The IRQ10 interrupt request is enabled when this bit is 1.
9
IRQ9E
0
R/W
IRQ9 Enable
The IRQ9 interrupt request is enabled when this bit is 1.
8
IRQ8E
0
R/W
IRQ8 Enable
The IRQ8 interrupt request is enabled when this bit is 1.
7
IRQ7E
0
R/W
IRQ7 Enable
The IRQ7 interrupt request is enabled when this bit is 1.
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Section 7 Interrupt Controller
Bit
Bit Name
Initial
Value
R/W
Description
6
IRQ6E
0
R/W
IRQ6 Enable
The IRQ6 interrupt request is enabled when this bit is 1.
5
IRQ5E
0
R/W
IRQ5 Enable
The IRQ5 interrupt request is enabled when this bit is 1.
4
IRQ4E
0
R/W
IRQ4 Enable
The IRQ4 interrupt request is enabled when this bit is 1.
3
IRQ3E
0
R/W
IRQ3 Enable
The IRQ3 interrupt request is enabled when this bit is 1.
2
IRQ2E
0
R/W
IRQ2 Enable
The IRQ2 interrupt request is enabled when this bit is 1.
1
IRQ1E
0
R/W
IRQ1 Enable
The IRQ1 interrupt request is enabled when this bit is 1.
0
IRQ0E
0
R/W
IRQ0 Enable
The IRQ0 interrupt request is enabled when this bit is 1.
Notes: 1. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
2. Supported only by the H8SX/1648L Group and the H8SX/1648H Group.
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Section 7 Interrupt Controller
7.3.5
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCRH and ISCRL select the source that generates an interrupt request from IRQ15 to IRQ0
input.
Upon changing the setting of ISCR, IRQnF (n = 0 to 15) in ISR is often set to 1 accidentally
through an internal operation. In this case, an interrupt exception handling is executed if an IRQn
interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the
setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in
ISR should be cleared to 0.
• ISCRH
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
IRQ15SR
IRQ15SF
IRQ14SR
IRQ14SF
IRQ13SR
IRQ13SF
IRQ12SR
IRQ12SF
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
IRQ11SR
IRQ11SF
IRQ10SR
IRQ10SF
IRQ9SR
IRQ9SF
IRQ8SR
IRQ8SF
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
IRQ7SR
IRQ7SF
IRQ6SR
IRQ6SF
IRQ5SR
IRQ5SF
IRQ4SR
IRQ4SF
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• ISCRL
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
IRQ3SR
IRQ3SF
IRQ2SR
IRQ2SF
IRQ1SR
IRQ1SF
IRQ0SR
IRQ0SF
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 7 Interrupt Controller
• ISCRH
Bit
Bit Name
Initial
Value
R/W
Description
15
IRQ15SR
0
R/W
14
IRQ15SF
0
R/W
IRQ15 Sense Control Rise
IRQ15 Sense Control Fall
•
When used as IRQ15
00: Interrupt request generated by low level of IRQ15
01: Interrupt request generated at falling edge of IRQ15
10: Interrupt request generated at rising edge of IRQ15
11: Interrupt request generated at both falling and rising
edges of IRQ15
•
TM32K*1: When used as 32KOVI
IRQ15 is used as the 32KOVI interrupt in the TM32K.
IRQ15 is generated at falling edge of IRQ15.
00: Initial value
01: Interrupt request generated at falling edge of IRQ15
10: Setting prohibited
11: Setting prohibited
13
IRQ14SR
0
R/W
12
IRQ14SF
0
R/W
IRQ14 Sense Control Rise
IRQ14 Sense Control Fall
•
When used as IRQ14
00: Interrupt request generated by low level of IRQ14
01: Interrupt request generated at falling edge of IRQ14
10: Interrupt request generated at rising edge of IRQ14
11: Interrupt request generated at both falling and rising
edges of IRQ14
•
LVD*2: When used as a voltage-monitoring
interrupt
IRQ14 is used as the LVD voltage-monitoring interrupt.
IRQ14 is generated at falling edge of IRQ14.
00: Initial value
01: Interrupt request generated at falling edge of IRQ14
10: Setting prohibited
11: Setting prohibited
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Section 7 Interrupt Controller
Bit
Bit Name
Initial
Value
R/W
Description
11
IRQ13SR
0
R/W
10
IRQ13SF
0
R/W
IRQ13 Sense Control Rise
IRQ13 Sense Control Fall
00: Interrupt request generated by low level of IRQ13
01: Interrupt request generated at falling edge of IRQ13
10: Interrupt request generated at rising edge of IRQ13
11: Interrupt request generated at both falling and rising
edges of IRQ13
9
IRQ12SR
0
R/W
8
IRQ12SF
0
R/W
IRQ12 Sense Control Rise
IRQ12 Sense Control Fall
00: Interrupt request generated by low level of IRQ12
01: Interrupt request generated at falling edge of IRQ12
10: Interrupt request generated at rising edge of IRQ12
11: Interrupt request generated at both falling and rising
edges of IRQ12
7
IRQ11SR
0
R/W
6
IRQ11SF
0
R/W
IRQ11 Sense Control Rise
IRQ11 Sense Control Fall
00: Interrupt request generated by low level of IRQ11
01: Interrupt request generated at falling edge of IRQ11
10: Interrupt request generated at rising edge of IRQ11
11: Interrupt request generated at both falling and rising
edges of IRQ11
5
IRQ10SR
0
R/W
4
IRQ10SF
0
R/W
IRQ10 Sense Control Rise
IRQ10 Sense Control Fall
00: Interrupt request generated by low level of IRQ10
01: Interrupt request generated at falling edge of IRQ10
10: Interrupt request generated at rising edge of IRQ10
11: Interrupt request generated at both falling and rising
edges of IRQ10
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Section 7 Interrupt Controller
Bit
Bit Name
Initial
Value
R/W
Description
3
IRQ9SR
0
R/W
2
IRQ9SF
0
R/W
IRQ9 Sense Control Rise
IRQ9 Sense Control Fall
00: Interrupt request generated by low level of IRQ9
01: Interrupt request generated at falling edge of IRQ9
10: Interrupt request generated at rising edge of IRQ9
11: Interrupt request generated at both falling and rising
edges of IRQ9
1
IRQ8SR
0
R/W
0
IRQ8SF
0
R/W
IRQ8 Sense Control Rise
IRQ8 Sense Control Fall
00: Interrupt request generated by low level of IRQ8
01: Interrupt request generated at falling edge of IRQ8
10: Interrupt request generated at rising edge of IRQ8
11: Interrupt request generated at both falling and rising
edges of IRQ8
Notes: 1. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
2. Supported only by the H8SX/1648L Group and H8SX/1648H Group.
• ISCRL
Bit
Bit Name
Initial
Value
R/W
Description
15
IRQ7SR
0
R/W
14
IRQ7SF
0
R/W
IRQ7 Sense Control Rise
IRQ7 Sense Control Fall
00: Interrupt request generated by low level of IRQ7
01: Interrupt request generated at falling edge of IRQ7
10: Interrupt request generated at rising edge of IRQ7
11: Interrupt request generated at both falling and rising
edges of IRQ7
13
IRQ6SR
0
R/W
12
IRQ6SF
0
R/W
IRQ6 Sense Control Rise
IRQ6 Sense Control Fall
00: Interrupt request generated by low level of IRQ6
01: Interrupt request generated at falling edge of IRQ6
10: Interrupt request generated at rising edge of IRQ6
11: Interrupt request generated at both falling and rising
edges of IRQ6
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Section 7 Interrupt Controller
Bit
Bit Name
Initial
Value
R/W
Description
11
IRQ5SR
0
R/W
10
IRQ5SF
0
R/W
IRQ5 Sense Control Rise
IRQ5 Sense Control Fall
00: Interrupt request generated by low level of IRQ5
01: Interrupt request generated at falling edge of IRQ5
10: Interrupt request generated at rising edge of IRQ5
11: Interrupt request generated at both falling and rising
edges of IRQ5
9
IRQ4SR
0
R/W
8
IRQ4SF
0
R/W
IRQ4 Sense Control Rise
IRQ4 Sense Control Fall
00: Interrupt request generated by low level of IRQ4
01: Interrupt request generated at falling edge of IRQ4
10: Interrupt request generated at rising edge of IRQ4
11: Interrupt request generated at both falling and rising
edges of IRQ4
7
IRQ3SR
0
R/W
6
IRQ3SF
0
R/W
IRQ3 Sense Control Rise
IRQ3 Sense Control Fall
00: Interrupt request generated by low level of IRQ3
01: Interrupt request generated at falling edge of IRQ3
10: Interrupt request generated at rising edge of IRQ3
11: Interrupt request generated at both falling and rising
edges of IRQ3
5
IRQ2SR
0
R/W
4
IRQ2SF
0
R/W
IRQ2 Sense Control Rise
IRQ2 Sense Control Fall
00: Interrupt request generated by low level of IRQ2
01: Interrupt request generated at falling edge of IRQ2
10: Interrupt request generated at rising edge of IRQ2
11: Interrupt request generated at both falling and rising
edges of IRQ2
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Section 7 Interrupt Controller
Bit
Bit Name
Initial
Value
R/W
Description
3
IRQ1SR
0
R/W
2
IRQ1SF
0
R/W
IRQ1 Sense Control Rise
IRQ1 Sense Control Fall
00: Interrupt request generated by low level of IRQ1
01: Interrupt request generated at falling edge of IRQ1
10: Interrupt request generated at rising edge of IRQ1
11: Interrupt request generated at both falling and rising
edges of IRQ1
1
IRQ0SR
0
R/W
0
IRQ0SF
0
R/W
IRQ0 Sense Control Rise
IRQ0 Sense Control Fall
00: Interrupt request generated by low level of IRQ0
01: Interrupt request generated at falling edge of IRQ0
10: Interrupt request generated at rising edge of IRQ0
11: Interrupt request generated at both falling and rising
edges of IRQ0
7.3.6
IRQ Status Register (ISR)
ISR is an IRQ15 to IRQ0 interrupt request register.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note:
*
15
14
13
12
11
10
9
8
IRQ15F
IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
7
6
5
4
3
2
1
0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should
be used to clear the flag.
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Section 7 Interrupt Controller
Bit
15
Bit Name
IRQ15F
Initial
Value
0
R/W
Description
R/(W)*
1
When used as IRQ15:
[Setting condition]
•
When the interrupt selected by ISCR occurs
[Clearing conditions]
•
Writing 0 after reading IRQ15F = 1
•
When interrupt exception handling is executed while
low-level sensing is selected and IRQ15 input is
high
•
When IRQ15 interrupt exception handling is
executed while falling-, rising-, or both-edge sensing
is selected
•
When the DTC is activated by an IRQ15 interrupt,
and the DISEL bit in MRB of the DTC is cleared to 0
TM32K*2: When used as 32KOVI
[Setting condition]
•
When the interrupt selected by ISCR occurs
[Clearing condition]
Rev. 2.00 Jul. 31, 2008 Page 144 of 1438
REJ09B0365-0200
•
Writing 0 after reading IRQ15F = 1
•
When IRQ15 interrupt exception handling is
executed while falling-edge sensing is selected
Section 7 Interrupt Controller
Bit
14
Bit Name
IRQ14F
Initial
Value
0
R/W
R/(W)*
Description
1
When used as IRQ14:
[Setting condition]
•
When the interrupt selected by ISCR occurs
[Clearing conditions]
•
Writing 0 after reading IRQ14F = 1
•
When interrupt exception handling is executed while
low-level sensing is selected and IRQ14 input is
high
•
When IRQ14 interrupt exception handling is
executed while falling-, rising-, or both-edge sensing
is selected
•
When the DTC is activated by an IRQ14 interrupt,
and the DISEL bit in MRB of the DTC is cleared to 0
LVD*3: When used as a voltage-monitoring interrupt
[Setting condition]
•
When the interrupt selected by ISCR occurs
[Clearing condition]
•
Writing 0 after reading IRQ14F = 1
•
When IRQ14 interrupt exception handling is
executed while falling-edge sensing is selected
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Section 7 Interrupt Controller
Bit
13
12
Bit Name
IRQ13F
IRQ12F
Initial
Value
0
0
R/W
Description
1
R/(W)*
•
1
[Clearing conditions]
1
•
Writing 0 after reading IRQnF = 1 (n=13 to 0)
1
•
When interrupt exception handling is executed while
low-level sensing is selected and IRQn input is high
•
When IRQn interrupt exception handling is executed
while falling-, rising-, or both-edge sensing is
selected
•
When the DTC is activated by an IRQn interrupt,
and the DISEL bit in MRB of the DTC is cleared to 0
R/(W)*
11
IRQ11F
0
R/(W)*
10
IRQ10F
0
R/(W)*
9
IRQ9F
0
R/(W)*
1
8
IRQ8F
0
R/(W)*
7
IRQ7F
0
R/(W)*
1
1
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
Note:
[Setting condition]
1
1
1
1
When the interrupt selected by ISCR occurs
1
1
1
1. Only 0 can be written, to clear the flag.
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
3. Supported only by the H8SX/1648L Group and H8SX/1648H Group.
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Section 7 Interrupt Controller
7.3.7
Software Standby Release IRQ Enable Register (SSIER)
SSIER selects the IRQ interrupt used to leave software standby mode.
The IRQ interrupt used to leave software standby mode should not be set as the DTC activation
source.
Bit
Bit Name
15
14
13
12
11
10
9
8
SSI15
SSI14
SSI13
SSI12
SSI11
SSI10
SSI9
SSI8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
R/W
7
6
5
4
3
2
1
0
SSI7
SSI6
SSI5
SSI4
SSI3
SSI2
SSI1
SSI0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
SSI15
0
R/W
Software Standby Release IRQ Setting
14
SSI14
0
R/W
13
SSI13
0
R/W
These bits select the IRQn interrupt used to leave
software standby mode (n = 15 to 0).
12
SSI12
0
R/W
11
SSI11
0
R/W
10
SSI10
0
R/W
9
SSI9
0
R/W
8
SSI8
0
R/W
7
SSI7
0
R/W
6
SSI6
0
R/W
5
SSI5
0
R/W
4
SSI4
0
R/W
3
SSI3
0
R/W
2
SSI2
0
R/W
1
SSI1
0
R/W
0
SSI0
0
R/W
0: An IRQn request is not sampled in software standby
mode
1: When an IRQn request occurs in software standby
mode, this LSI leaves software standby mode after
the oscillation settling time has elapsed
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Section 7 Interrupt Controller
7.4
Interrupt Sources
7.4.1
External Interrupts
There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to
leave software standby mode.
(1)
NMI Interrupts
Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by
the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits.
The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on
the NMI pin.
When an NMI interrupt is generated, the interrupt controller determines that an error has occurred,
and performs the following procedure.
•
•
•
•
Sets the ERR bit of DTCCR in the DTC to 1.
Sets the ERRF bit of DMDR_0 in the DMAC to 1
Sets the ERRF bit of DMDR_0 in the EXDMAC* to 1
Clears the DTE bits of DMDRs for all channels in the DMAC to 0 to forcibly terminate
transfer
• Clears the DTE bits of DMDRs for all channels in the EXDMAC* to 0 to forcibly terminate
transfer
Note: * Supported only by the H8SX/1648G and H8SX/1648H groups.
(2) IRQn Interrupts
An IRQn interrupt is requested by a signal input on pins IRQ15 to IRQ0. IRQn (n = 15 to 0) have
the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, on pins IRQn.
• Enabling or disabling of interrupt requests IRQn can be selected by IER.
• The interrupt priority can be set by IPR.
• The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by
software. The bit manipulation instructions and memory operation instructions should be used
to clear the flag.
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Section 7 Interrupt Controller
Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, P5ICR, and P6ICR register
settings, and does not change regardless of the output setting. However, when a pin is used as an
external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing
the corresponding DDR bit to 0.
A block diagram of interrupts IRQn is shown in figure 7.2.
Corresponding bit
in ICR
IRQnSF, IRQnSR
Input buffer
Edge/level
detection circuit
IRQnE
IRQnF
IRQn interrupt request
S
Q
R
IRQn input
Clear signal
[Legend]
n = 15 to 0
Figure 7.2 Block Diagram of Interrupts IRQn
When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn
should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn
to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed
when the corresponding input signal IRQn is set to high before the interrupt handling begins.
7.4.2
Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that enable or disable these interrupts. They can be controlled independently.
When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.
• The interrupt priority can be set by means of IPR.
• The DTC and DMAC can be activated by a TPU, SCI, or other interrupt request.
• The priority levels of DTC and DMAC activation can be controlled by the DTC and DMAC
priority control functions.
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Section 7 Interrupt Controller
7.5
Interrupt Exception Handling Vector Table
Table 7.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority.
In the default priority order, a lower vector number corresponds to a higher priority. When
interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The
priority for interrupt sources allocated to the same level in IPR follows the default priority, that is,
they are fixed.
Table 7.2
Interrupt Sources, Vector Address Offsets, and Interrupt Priority
Vector Address
Offset*1
Advanced Mode
Middle Mode
Maximum Mode IPR
Classification
Interrupt
Source
Vector
Number
External pin
NMI
7
H'001C

UBC
UBC break
interrupt
14
H'0038

External pin
LVD*
3
DTC
Activation
DMAC
Activation
High




IRQ0
64
H'0100
IPRA14 to IPRA12
O

IRQ1
65
H'0104
IPRA10 to IPRA8
O

IRQ2
66
H'0108
IPRA6 to IPRA4
O

IRQ3
67
H'010C
IPRA2 to IPRA0
O

IRQ4
68
H'0110
IPRB14 to IPRB12
O

IRQ5
69
H'0114
IPRB10 to IPRB8
O

IRQ6
70
H'0118
IPRB6 to IPRB4
O

IRQ7
71
H'011C
IPRB2 to IPRB0
O

IRQ8
72
H'0120
IPRC14 to IPRC12
O

IRQ9
73
H'0124
IPRC10 to IPRC8
O

IRQ10
74
H'0128
IPRC6 to IPRC4
O

IRQ11
75
H'012C
IPRC2 to IPRC0
O

IRQ12
76
H'0130
IPRD14 to IPRD12
O

IRQ13
77
H'0134
IPRD10 to IPRD8
O

IRQ14
78
H'0138
IPRD6 to IPRD4
O

O

O







Voltagemonitoring
interrupt
External pin
TM32K*
Priority
2
IRQ15
79
H'013C
IPRD2 to IPRD0
32KOVI

Reserved for
system use
80
H'0140

WDT
WOVI
81
H'0144
IPRE10 to IPRE8
Rev. 2.00 Jul. 31, 2008 Page 150 of 1438
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Low
Section 7 Interrupt Controller
Vector Address
Offset*1
Interrupt
Source
Vector
Number
Advanced Mode
Middle Mode
Maximum Mode IPR

Reserved for
system use
82
H'0148

Refresh
controller*2
CMI
83
H'014C

Reserved for
system use
84
H'0150

Reserved for
system use
85
H'0154
A/D_0
ADI0
86
H'0158

Reserved for
system use
87
TPU_0
TGI0A
Classification
TPU_1
TPU_2
TPU_3
TPU_4
Priority
DTC
Activation
DMAC
Activation
High


IPRE2 to IPRE0







IPRF10 to IPRF8
O
O
H'015C



88
H'0160
IPRF6 to IPRF4
O
O
TGI0B
89
H'0164
O

TGI0C
90
H'0168
O

TGI0D
91
H'016C
O



TCI0V
92
H'0170
TGI1A
93
H'0174
TGI1B
94
TCI1V
TCI1U
IPRF2 to IPRF0
O
O
H'0178
O

95
H'017C


96
H'0180


TGI2A
97
H'0184
O
O
TGI2B
98
H'0188
O

TCI2V
99
H'018C




TCI2U
100
H'0190
TGI3A
101
H'0194
TGI3B
102
TGI3C
TGI3D
IPRG14 to IPRG12
O
O
H'0198
O

103
H'019C
O

104
H'01A0
O



TCI3V
105
H'01A4
TGI4A
106
H'01A8
TGI4B
107
H'01AC
TCI4V
108
H'01B0
TCI4U
109
H'01B4
IPRG10 to IPRG8
IPRG6 to IPRG4
Low
O
O
O





Rev. 2.00 Jul. 31, 2008 Page 151 of 1438
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Section 7 Interrupt Controller
Vector Address
Offset*1
Interrupt
Classification Source
TPU_5
Vector
Number
Advanced Mode
Middle Mode
Maximum Mode IPR
Priority
High
110
H'01B8
O
O
TGI5B
111
H'01BC
O

TCI5V
112
H'01C0






TCI5U
113
H'01C4
Reserved for
system use
114
H'01C8
115
H'01CC
TMR_0
CMI0A
116
H'01D0
CMI0B
117
H'01D4
TMR_1
TMR_2
TMR_3
DMAC
EXDMAC*2
DMAC
DMAC
Activation
TGI5A

OV0I
118
H'01D8
CMI1A
119
H'01DC
CMI1B
120
H'01E0
OV1I
121
H'01E4
CMI2A
122
H'01E8
IPRG2 to IPRG0
DTC
Activation

IPRH14 to IPRH12
IPRH10 to IPRH8
IPRH6 to IPRH4


O

O



O

O



O

CMI2B
123
H'01EC
O

OV2I
124
H'01F0


CMI3A
125
H'01F4
O

IPRH2 to IPRH0
CMI3B
126
H'01F8
O

OV3I
127
H'01FC


DMTEND0
128
H'0200
IPRI14 to IPRI12
O

DMTEND1
129
H'0204
IPRI10 to IPRI8
O

DMTEND2
130
H'0208
IPRI6 to IPRI4
O

DMTEND3
131
H'020C
IPRI2 to IPRI0
O

EXDMTEND0
132
H'0210
IPRJ14 to IPRJ12
O

EXDMTEND1
133
H'0214
IPRJ10 to IPRJ8
O

EXDMTEND2
134
H'0218
IPRJ6 to IPRJ4
O

EXDMTEND3
135
H'021C
IPRJ2 to IPRJ0
O

DMEEND0
136
H'0220
IPRK14 to IPRK12
O

DMEEND1
137
H'0224
O

DMEEND2
138
H'0228
O

DMEEND3
139
H'022C
O

Rev. 2.00 Jul. 31, 2008 Page 152 of 1438
REJ09B0365-0200
Low
Section 7 Interrupt Controller
Vector Address
Offset*1
Advanced Mode
Classification
Interrupt
Source
EXDMAC*2
SCI_0
SCI_1
SCI_2
SCI_3
SCI_4
Vector
Number
Middle Mode
Maximum Mode IPR
Priority
DTC
DMAC
Activation Activation
EXDMTEEND0 140
H'0230
High
O

EXDMTEEND1 141
H'0234
O

EXDMTEEND2 142
H'0238
O

EXDMTEEND3 143
H'023C
O

ERI0
144
H'0240


RXI0
145
H'0244
O
O
TXI0
146
H'0248
O
O
TEI0
147
H'024C


ERI1
148
H'0250


RXI1
149
H'0254
O
O
TXI1
150
H'0258
O
O
TEI1
151
H'025C


ERI2
152
H'0260


RXI2
153
H'0264
O
O
TXI2
154
H'0268
O
O
TEI2
155
H'026C


ERI3
156
H'0270


RXI3
157
H'0274
O
O
TXI3
158
H'0278
O
O
IPRK10 to IPRK8
IPRK6 to IPRK4
IPRK2 to IPRK0
IPRL14 to IPRL12
IPRL10 to IPRL8




H'0284
O
O
162
H'0288
O
O
163
H'028C


TEI3
159
H'027C
ERI4
160
H'0280
RXI4
161
TXI4
TEI4
IPRL6 to IPRL4
Low
Rev. 2.00 Jul. 31, 2008 Page 153 of 1438
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Section 7 Interrupt Controller
Vector Address
Offset*1
Interrupt
Classification Source
Vector
Number
Advanced Mode
Middle Mode
Maximum Mode IPR
TPU_6
TGI6A
164
H'0290
O
O
TGI6B
165
H'0294
O

TGI6C
166
H'0298
O

TGI6D
167
H'029C
O

TCI6V
168
H'02A0
IPRM14 to IPRM12


TGI7A
169
H'02A4
IPRM10 to IPRM8
TGI7B
170
H'02A8
TCI7V
171
H'02AC
TPU_7
TPU_8
TPU_9
TPU_10
TCI7U
172
H'02B0
TGI8A
173
H'02B4
TGI8B
174
H'02B8
TCI8V
175
H'02BC
TCI8U
176
H'02C0
High
IPRM6 to IPRM4
IPRM2 to IPRM0
IPRN14 to IPRN12
DTC
Activation
DMAC
Activation
O
O
O





O
O
O





TGI9A
177
H'02C4
O
O
TGI9B
178
H'02C8
O

TGI9C
179
H'02CC
O

TGI9D
180
H'02D0
O

TCI9V
181
H'02D4
IPRN6 to IPRN4


TGI10A
182
H'02D8
IPRN2 to IPRN0
O
O
TGI10B
183
H'02DC
O

Reserved for
system use
184
H'02E0



Reserved for
system use
185
H'02E4


TCI10V
186
H'02E8
O



O
O
TCI10U
187
H'02EC
TGI11A
188
H'02F0
TGI11B
189
H'02F4
TCI11V
190
H'02F8
TCI11U
191
H'02FC
—
Reserved for
system use
192
|
215
IIC2_0
IICI0
—
Reserved for
system use
TPU_11
IPRL2 to IPRL0
Priority
IPRO14
to IPRO12
IPRO10
to IPRO8
O

IPRO6
to IPRO4




H'0300
|
H'035C
—
—
|
—
—
|
—
216
H'0360
IPRQ6 to IPRQ4
—
—
217
H'0364
—
—
Rev. 2.00 Jul. 31, 2008 Page 154 of 1438
REJ09B0365-0200
IPRN10 to IPRN8
Low
Section 7 Interrupt Controller
Vector Address
Offset*1
Interrupt
Classification Source
Vector
Number
Advanced Mode
Middle Mode
Maximum Mode IPR
Priority
IIC2_1
IICI1
218
H'0368
High
—
Reserved for
system use
219
H'036C
SCI_5
RXI5
220
H'0370
—
O
TXI5
221
H'0374
—
O
ERI5
222
H'0378
—
—
TEI5
223
H'037C
RXI6
224
H'0380
TXI6
225
ERI6
226
TEI6
TMR_4
IPRQ2 to IPRQ0
DTC
Activation
DMAC
Activation
—
—
—
—
—
—
—
O
H'0384
—
O
H'0388
—
—
227
H'038C
—
—
CMIA4 or
CMIB4
228
H'0390
—
—
TMR_5
CMIA5 or
CMIB5
229
H'0394
—
—
TMR_6
CMIA6 or
CMIB6
230
H'0398
—
—
TMR_7
CMIA7 or
CMIB7
231
H'039C
—
—
A/D_2
ADI2
232
H'03A0
—
O
—
Reserved for
system use
233
H'03A4
—
—
IIC2_2
IICI2
234
H'03A8
—
—
IIC2_3
IICI3
235
H'03AC
—
Reserved for
system use
236
H'03B0
A/D_1
ADI1
237
—
Reserved for
system use
238
|
255
SCI_6
IPRR14 to IPRR12
IPRR10 to IPRR8
IPRR6 to IPRR4
—
—
—
—
—
H'03B4
IPRR2 to IPRR0
—
O
H'03B8
|
H'03FC
—
—
|
—
—
|
—
Low
Notes: 1. Lower 16 bits of the start address.
2. Supported only by the H8SX/1648G and the H8SX/1648H groups.
3. Supported only by the H8SX/1648L and the H8SX/1648H groups.
Rev. 2.00 Jul. 31, 2008 Page 155 of 1438
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Section 7 Interrupt Controller
7.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt
control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt
control mode is selected by INTCR. Table 7.3 shows the differences between interrupt control
mode 0 and interrupt control mode 2.
Table 7.3
Interrupt Control Modes
Interrupt
Control
Mode
Priority
Setting
Register
Interrupt
Mask Bit
0
Default
I
The priority levels of the interrupt sources are fixed
default settings.
The interrupts except for NMI is masked by the I bit.
2
IPR
I2 to I0
Eight priority levels can be set for interrupt sources
except for NMI with IPR.
8-level interrupt mask control is performed by bits I2 to
I0.
7.6.1
Description
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of
the CPU. Figure 7.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the
interrupt request is sent to the interrupt controller.
2. If the I bit in CCR is set to 1, NMI is accepted, and other interrupt requests are held pending. If
the I bit is cleared to 0, an interrupt request is accepted.
3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the
highest priority, sends the request to the CPU, and holds other interrupt requests pending.
4. When the CPU accepts the interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR contents are saved to the stack area during the interrupt exception handling.
The PC contents saved on the stack is the address of the first instruction to be executed after
returning from the interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
Rev. 2.00 Jul. 31, 2008 Page 156 of 1438
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Section 7 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution state
No
Interrupt generated?
Yes
Yes
NMI
No
No
I=0
Pending
Yes
No
IRQ0
Yes
No
IRQ1
Yes
TEI4
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 7.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
Rev. 2.00 Jul. 31, 2008 Page 157 of 1438
REJ09B0365-0200
Section 7 Interrupt Controller
7.6.2
Interrupt Control Mode 2
In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the
interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels
in mask control. Figure 7.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the
highest priority according to the IPR setting, and holds other interrupt requests pending. If
multiple interrupt requests have the same priority, an interrupt request is selected according to
the default setting shown in table 7.2.
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
in EXR. When the interrupt request does not have priority over the mask level set, it is held
pending, and only an interrupt request with a priority over the interrupt mask level is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception
handling. The PC saved on the stack is the address of the first instruction to be executed after
returning from the interrupt handling routine.
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the
accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 2.00 Jul. 31, 2008 Page 158 of 1438
REJ09B0365-0200
Section 7 Interrupt Controller
Program execution state
No
Interrupt generated?
Yes
Yes
NMI
No
Level 7 interrupt?
No
No
Yes
Mask level 6
or below?
Yes
Level 6 interrupt?
No
Yes
Level 1 interrupt?
Mask level 5
or below?
No
No
Yes
Yes
Mask level 0?
No
Yes
Save PC, CCR, and EXR
Pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 7.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2
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REJ09B0365-0200
Rev. 2.00 Jul. 31, 2008 Page 160 of 1438
Figure 7.5 Interrupt Exception Handling
(2) (4)
(3)
(5)
(7)
(1)
(1)
(2)
(4)
(3)
Instruction prefetch address (Not executed. This is
the contents of the saved PC, the return address.)
Instruction code (Not executed.)
Instruction prefetch address (Not executed.)
SP − 2
SP − 4
Internal
data bus
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
Iφ
Instruction
prefetch
(6) (8)
(9)
(10)
(11)
(12)
Internal
operation
(6)
(7)
(8)
(10)
(9)
Vector fetch
Internal
operation
(12)
(11)
Saved PC and saved CCR
Vector address
Start address of interrupt handling routine (vector address contents)
Start address of Interrupt handling routine ((11) = (10))
First instruction of interrupt handling routine
(5)
Stack
Instruction
prefetch
in interrupt
handling
routine
7.6.3
Interrupt level determination
Wait for end of instruction
Interrupt
acceptance
Section 7 Interrupt Controller
Interrupt Exception Handling Sequence
Figure 7.5 shows the interrupt exception handling sequence. The example is for the case where
interrupt control mode 0 is set in maximum mode, and the program area and stack area are in onchip memory.
Section 7 Interrupt Controller
7.6.4
Interrupt Response Times
Table 7.4 shows interrupt response times – the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The symbols for execution
states used in table 7.4 are explained in table 7.5.
This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in onchip ROM and the stack area in on-chip RAM enables high-speed processing.
Table 7.4
Interrupt Response Times
5
Normal Mode*
Interrupt
Control
Mode 0
Execution State
Interrupt
Control
Mode 2
Advanced Mode
Interrupt
Control
Mode 0
Interrupt
Control
Mode 2
1
Interrupt priority determination*
3
Number of states until executing
2
instruction ends*
1 to 19 + 2·SI
PC, CCR, EXR stacking
6
SK to 2·SK*
2·SK
6
SK to 2·SK*
Vector fetch
Interrupt
Control
Mode 0
Interrupt
Control
Mode 2
2·SK
2·SK
11 to 31
11 to 31
Sh
Instruction fetch*
3
2·SI
4
Internal processing*
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
5.
6.
2·SK
5
Maximum Mode*
2
10 to 31
11 to 31
10 to 31
11 to 31
Two states for an internal interrupt.
In the case of the MULXS or DIVXS instruction
Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine.
Internal operation after interrupt acceptance or after vector fetch
Not available in this LSI.
When setting the SP value to 4n, the interrupt response time is SK; when setting to 4n +
2, the interrupt response time is 2·SK.
Rev. 2.00 Jul. 31, 2008 Page 161 of 1438
REJ09B0365-0200
Section 7 Interrupt Controller
Table 7.5
Number of Execution States in Interrupt Handling Routine
Object of Access
External Device
8-Bit Bus
16-Bit Bus
Symbol
On-Chip
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Vector fetch Sh
1
8
12 + 4m
4
6 + 2m
Instruction fetch SI
1
4
6 + 2m
2
3+m
Stack manipulation SK
1
8
12 + 4m
4
6 + 2m
[Legend]
m:
Number of wait cycles in an external device access.
7.6.5
DTC and DMAC Activation by Interrupt
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available:
•
•
•
•
Interrupt request to the CPU
Activation request to the DTC
Activation request to the DMAC
Combination of the above
For details on interrupt requests that can be used to activate the DTC and DMAC, see table 7.2,
section 10, DMA Controller (DMAC), and section 12, Data Transfer Controller (DTC).
Figure 7.6 shows a block diagram of the DTC, DMAC, and interrupt controller.
Rev. 2.00 Jul. 31, 2008 Page 162 of 1438
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Section 7 Interrupt Controller
Select signal
DMRSR_0 to DMRSR_3
Control signal
Interrupt request
On-chip
peripheral
module
Interrupt request
clear signal
DMAC activation request signal
DMAC
Clear signal
DMAC
select
circuit
DTCER
Clear signal
Select signal
Interrupt request
DTC activation request
vector number
Clear signal
DTC control
DTC/CPU
Interrupt request
IRQ
interrupt
select
Clear signal
CPU interrupt request
vector number
circuit
Interrupt request clear signal
DTC
circuit
Priority
determination
CPU
I, I2 to I0
Interrupt controller
Figure 7.6 Block Diagram of DTC, DMAC, and Interrupt Controller
(1)
Selection of Interrupt Sources
The activation source for each DMAC channel is selected by DMRSR. The selected activation
source is input to the DMAC through the select circuit. When transfer by an on-chip module
interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is
set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC
and cannot be used as a DTC activation source or CPU interrupt source.
Interrupt sources that are not controlled by the DMAC are set for DTC activation sources or CPU
interrupt sources by the DTCE bit in DTCERA to DTCERH of the DTC.
Specifying the DISEL bit in MRB of the DTC generates an interrupt request to the CPU by
clearing the DTCE bit to 0 after the individual DTC data transfer.
Note that when the DTC performs a predetermined number of data transfers and the transfer
counter indicates 0, an interrupt request is made to the CPU by clearing the DTCE bit to 0 after the
DTC data transfer.
When the same interrupt source is set as both the DTC and DMAC activation source and CPU
interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in
CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP
setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal
to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or
DMAC may not be activated, and the data transfer may not be performed.
Rev. 2.00 Jul. 31, 2008 Page 163 of 1438
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Section 7 Interrupt Controller
(2)
Priority Determination
The DTC activation source is selected according to the default priority, and the selection is not
affected by its mask level or priority level. For respective priority levels, see table 12.1, Interrupt
Sources, DTC Vector Addresses, and Corresponding DTCEs.
(3)
Operation Order
If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the
CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is
selected as the DTC or DMAC activation source or CPU interrupt source, respective operations
are performed independently.
Table 7.6 lists the selection of interrupt sources and interrupt source clear control by setting the
DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the
DISEL bit in MRB of the DTC.
Table 7.6
Interrupt Source Selection and Clear Control
DMAC Setting
DTC Setting
Interrupt Source Selection/Clear Control
DTA
DTCE
DISEL
DMAC
DTC
CPU
0
0
*
O
X
√
1
0
O
√
X
1
O
O
√
*
√
X
X
1
*
[Legend]
√: The corresponding interrupt is used. The interrupt source is cleared.
(The interrupt source flag must be cleared in the CPU interrupt handling routine.)
O: The corresponding interrupt is used. The interrupt source is not cleared.
X: The corresponding interrupt is not available.
*: Don't care.
(4)
Usage Note
The interrupt sources of the SCI, and A/D converter are cleared according to the setting shown in
table 7.6, when the DTC or DMAC reads/writes the prescribed register.
To initiate multiple channels for the DTC with the same interrupt, the same priority (DTCP =
DMAP) should be assigned.
Rev. 2.00 Jul. 31, 2008 Page 164 of 1438
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Section 7 Interrupt Controller
7.7
CPU Priority Control Function Over DTC, DMAC, and EXDMAC*
The interrupt controller has a function to control the priority among the DTC, DMAC,
EXDMAC* and the CPU by assigning different priority levels to the DTC, DMAC, EXDMAC*
and CPU. Since the priority level can automatically be assigned to the CPU on an interrupt
occurrence, it is possible to execute the CPU interrupt exception handling prior to the DTC,
DMAC, or EXDMAC* transfer.
The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level
of the DTC is assigned by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC is
assigned by bits DMAP2 to DMAP0 in DMDR for each channel. The priority level of the
EXDMAC* is assigned by bits EDMAP2 to EDMAP0 in the EXDMA mode control register
(EDMDR_0 to EDMDR_3) for each channel.
The priority control function over the DTC, DMAC, and EXDMAC* is enabled by setting the
CPUPCE bit in CPUPCR to 1. When the CPUPCE bit is 1, the DTC, DMAC, and EXDMAC*
activation sources are controlled according to the respective priority levels.
The DTC activation source is controlled according to the priority level of the CPU indicated by
bits CPUP2 to CPUP0 and the priority level of the DTC indicated by bits DTCP2 to DTCP0. If the
CPU has priority, the DTC activation source is held. The DTC is activated when the condition by
which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0
is greater than that of bits DTCP2 to DTCP0). The priority level of the DTC is assigned by the
DTCP2 to DTCP0 bits regardless of the activation source.
For the DMAC, the priority level can be specified for each channel. The DMAC activation source
is controlled according to the priority level of each DMAC channel indicated by bits DMAP2 to
DMAP0 and the priority level of the CPU. If the CPU has priority, the DMAC activation source is
held. The DMAC is activated when the condition by which the activation source is held is
cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to
DMAP0). If different priority levels are specified for channels, the channels of the higher priority
levels continue transfer and the activation sources for the channels of lower priority levels than
that of the CPU are held.
Rev. 2.00 Jul. 31, 2008 Page 165 of 1438
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Section 7 Interrupt Controller
For the EXDMAC*, the priority level can be specified for each channel. The EXDMAC*
activation source is controlled according to the priority level of each EXDMAC* channel
indicated by bits EDMAP2 to EDMAP0 and the priority level of the CPU. If the CPU has priority,
the EXDMAC* activation source is held. The EXDMAC* is activated when the condition by
which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0
is greater than that of bits DMAP2 to EDMAP0). If different priority levels are specified for
channels, the channels of the higher priority levels continue transfer and the activation sources for
the channels of lower priority levels than that of the CPU are held.
There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR.
Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt
mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function
to automatically assign the priority level. Therefore, the priority level is assigned directly by
software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the
CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0
bits in EXR).
The priority level which is automatically assigned when the IPSETE bit is 1 differs according to
the interrupt control mode.
In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1
and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU
are reflected in bits CPUP2 to CPUP0.
Table 7.7 shows the CPU priority control.
Table 7.7
CPU Priority Control
Control Status
Interrupt
Control Interrupt
Mode
Priority
Interrupt
Mask Bit
IPSETE in
CPUPCR CPUP2 to CPUP0
Updating of CPUP2
to CPUP0
0
I = any
0
B'111 to B'000
Enabled
I=0
1
B'000
Disabled
Default
I=1
2
IPR setting
I2 to I0
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B'100
0
B'111 to B'000
Enabled
1
I2 to I0
Disabled
Section 7 Interrupt Controller
Table 7.8 shows a setting example of the priority control function over the DTC, DMAC, and
EXDMAC* and the transfer request control state. A priority level can be independently set to each
DMAC and EXDMAC* channels, but the table only shows one of the each channel for example.
Transfers through the DMAC and EXDMAC* channels can be separately controlled by assigning
different priority levels for channels.
Table 7.8
Example of Priority Control Function Setting and Control State
Interrupt
Control
Mode
CPUPCE CPUP2
to
in
CPUPCR CPUP0
DTCP2
to
DTCP0
DMAP2
to
DMAP0
EDMAP2* Transfer Request Control State
to
EDMAP0* DTC
DMAC
EXDMAC*
0
0
Any
Any
Any
Any
Enabled
Enabled
Enabled
1
B'000
B'000
B'000
B'000
Enabled
Enabled
Enabled
B'100
B'000
B'000
B'000
Masked
Masked
Masked
B'100
B'000
B'011
B'100
Masked
Masked
Enabled
B'100
B'111
B'101
B'000
Enabled
Enabled
Masked
B'000
B'111
B'101
B'000
Enabled
Enabled
Enabled
0
Any
Any
Any
Any
Enabled
Enabled
Enabled
1
B'000
B'000
B'000
B'000
Enabled
Enabled
Enabled
B'000
B'011
B'101
B'110
Enabled
Enabled
Enabled
B'011
B'011
B'101
B'110
Enabled
Enabled
Enabled
B'100
B'011
B'101
B'110
Masked
Enabled
Enabled
B'101
B'011
B'101
B'110
Masked
Enabled
Enabled
B'110
B'011
B'101
B'110
Masked
Masked
Enabled
B'111
B'011
B'101
B'110
Masked
Masked
Masked
B'101
B'011
B'101
B'011
Masked
Enabled
Masked
B'101
B'110
B'101
B'011
Enabled
Enabled
Masked
2
Note:
*
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 7 Interrupt Controller
7.8
Usage Notes
7.8.1
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request with priority
over that interrupt, interrupt exception handling will be executed for the interrupt with priority,
and another interrupt will be ignored. The same also applies when an interrupt source flag is
cleared to 0. Figure 7.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared
to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
TIER_0 write cycle by CPU
TCIV exception handling
Pφ
Internal
address bus
TIER_0 address
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Figure 7.7 Conflict between Interrupt Generation and Disabling
Similarly, when an interrupt is requested immediately before the DTC enable bit is changed to
activate the DTC, DTC activation and the interrupt exception handling by the CPU are both
executed. When changing the DTC enable bit, make sure that an interrupt is not requested.
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Section 7 Interrupt Controller
7.8.2
Instructions that Disable Interrupts
Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and
XORC. After any of these instructions is executed, all interrupts including NMI are disabled and
the next instruction is always executed. When the I bit is set by one of these instructions, the new
value becomes valid two states after execution of the instruction ends.
7.8.3
Times when Interrupts are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of
writing to the registers of the interrupt controller.
7.8.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at the end of the individual transfer cycle. The PC value saved on the
stack in this case is the address of the next instruction. Therefore, if an interrupt is generated
during execution of an EEPMOV.W instruction, the following coding should be used.
L1:
7.8.5
EEPMOV.W
MOV.W
R4,R4
BNE
L1
Interrupts during Execution of MOVMD and MOVSD Instructions
With the MOVMD or MOVSD instruction, if an interrupt request is issued during the transfer,
interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved
on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the
remaining data is resumed after returning from the interrupt handling routine.
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Section 7 Interrupt Controller
7.8.6
Interrupts of Peripheral Modules
To clear an interrupt source flag by the CPU using an interrupt function of a peripheral module,
the flag must be read from after clearing within the interrupt processing routine. This makes the
request signal synchronized with the peripheral module clock. For details, refer to section 26.6.1,
Notes on Clock Pulse Generator.
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Section 8 User Break Controller (UBC)
Section 8 User Break Controller (UBC)
The user break controller (UBC) generates a UBC break interrupt request each time the state of
the program counter matches a specified break condition. The UBC break interrupt is a nonmaskable interrupt and is always accepted, regardless of the interrupt control mode and the state of
the interrupt mask bit of the CPU.
For each channel, the break control register (BRCR) and break address register (BAR) are used to
specify the break condition as a combination of address bits and type of bus cycle.
Four break conditions are independently specifiable on four channels, A to D.
8.1
Features
• Number of break channels: four (channels A, B, C, and D)
• Break comparison conditions (each channel)
 Address
 Bus master (CPU cycle)
 Bus cycle (instruction execution (PC break))
• UBC break interrupt exception handling is executed immediately before execution of the
instruction fetched from the specified address (PC break).
• Module stop state can be set
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Section 8 User Break Controller (UBC)
8.2
Block Diagram
Instruction execution pointer
Mode control
Instruction
execution pointer
Break control
Internal bus (input side)
Internal bus (output side)
PC break control
Break
address
BARAH
BARAL
BARBH
BARBL
BARCH
BARCL
Condition
Address
match
comparator determination
BARDH
BARDL
C ch
BRCRC
Flag set control
Condition
Address
match
comparator determination
Break
control
B ch
BRCRA
Sequential control
A ch
A ch PC
Condition match
B ch PC
Condition match
Condition
Address
match
comparator determination
C ch PC
Condition match
D ch
D ch PC
Condition match
BRCRB
Condition
Address
match
comparator determination
BRCRD
CPU status
[Legend]
BARAH, BARAL:
BARBH, BARBL:
BARCH, BARCL:
BARDH, BARDL:
BRCRA:
BRCRB:
BRCRC:
BRCRD:
Break address register A
Break address register B
Break address register C
Break address register D
Break control register A
Break control register B
Break control register C
Break control register D
Figure 8.1 Block Diagram of UBC
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UBC break
interrupt request
Section 8 User Break Controller (UBC)
8.3
Register Descriptions
Table 8.1 lists the register configuration of the UBC.
Table 8.1
Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access
Size
Break address register A
BARAH
R/W
H'0000
H'FFA00
16
BARAL
R/W
H'0000
H'FFA02
16
Break address mask register A
Break address register B
Break address mask register B
Break address register C
Break address mask register C
BAMRAH
R/W
H'0000
H'FFA04
16
BAMRAL
R/W
H'0000
H'FFA06
16
BARBH
R/W
H'0000
H'FFA08
16
BARBL
R/W
H'0000
H'FFA0A
16
BAMRBH
R/W
H'0000
H'FFA0C
16
BAMRBL
R/W
H'0000
H'FFA0E
16
BARCH
R/W
H'0000
H'FFA10
16
BARCL
R/W
H'0000
H'FFA12
16
BAMRCH
R/W
H'0000
H'FFA14
16
BAMRCL
R/W
H'0000
H'FFA16
16
BARDH
R/W
H'0000
H'FFA18
16
BARDL
R/W
H'0000
H'FFA1A
16
BAMRDH
R/W
H'0000
H'FFA1C
16
BAMRDL
R/W
H'0000
H'FFA1E
16
Break control register A
BRCRA
R/W
H'0000
H'FFA28
8/16
Break control register B
BRCRB
R/W
H'0000
H'FFA2C
8/16
Break control register C
BRCRC
R/W
H'0000
H'FFA30
8/16
Break control register D
BRCRD
R/W
H'0000
H'FFA34
8/16
Break address register D
Break address mask register D
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Section 8 User Break Controller (UBC)
8.3.1
Break Address Register n (BARA, BARB, BARC, BARD)
Each break address register n (BARn) consists of break address register nH (BARnH) and break
address register nL (BARnL). Together, BARnH and BARnL specify the address used as a break
condition on channel n of the UBC.
BARnH
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BARn31 BARn30 BARn29 BARn28 BARn27 BARn26 BARn25 BARn24 BARn23 BARn22 BARn21 BARn20 BARn19 BARn18 BARn17 BARn16
Initial Value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
BARnL
Bit:
BARn15 BARn14 BARn13 BARn12 BARn11 BARn10
Initial Value:
R/W:
9
8
7
6
5
4
3
2
1
0
BARn9
BARn8
BARn7
BARn6
BARn5
BARn4
BARn3
BARn2
BARn1
BARn0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• BARnH
Bit
Bit Name
31 to 16
BARn31 to
BARn16
Initial
Value
R/W
Description
All 0
R/W
Break Address n31 to 16
These bits hold the upper bit values (bits 31 to 16) for
the address break-condition on channel n.
[Legend]
n = Channels A to D
• BARnL
Bit
Bit Name
15 to 0
BARn15 to
BARn0
Initial
Value
R/W
Description
All 0
R/W
Break Address n15 to 0
[Legend]
n = Channels A to D
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These bits hold the lower bit values (bits 15 to 0) for
the address break-condition on channel n.
Section 8 User Break Controller (UBC)
8.3.2
Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD)
Be sure to write H'FF00 0000 to break address mask register n (BAMRn). Operation is not
guaranteed if another value is written here.
BAMRnH
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BAMRn31 BAMRn30 BAMRn29 BAMRn28 BAMRn27 BAMRn26 BAMRn25 BAMRn24 BAMRn23 BAMRn22 BAMRn21 BAMRn20 BAMRn19 BAMRn18 BAMRn17 BAMRn16
Initial Value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BAMRnL
Bit:
BAMRn15 BAMRn14 BAMRn13 BAMRn12 BAMRn11 BAMRn10 BAMRn9 BAMRn8 BAMRn7 BAMRn6 BAMRn5 BAMRn4 BAMRn3 BAMRn2 BAMRn1 BAMRn0
Initial Value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• BAMRnH
Initial
Value
Bit
Bit Name
31 to 16
BAMRn31 to All 0
BAMRn16
R/W
Description
R/W
Break Address Mask n31 to 16
Be sure to write H'FF00 here before setting a break
condition in the break control register.
[Legend]
n = Channels A to D
• BAMRnL
Initial
Value
Bit
Bit Name
15 to 0
BAMRn15 to All 0
BAMRn0
R/W
Description
R/W
Break Address Mask n15 to 0
Be sure to write H'0000 here before setting a break
condition in the break control register.
[Legend]
n = Channels A to D
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Section 8 User Break Controller (UBC)
8.3.3
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD)
BRCRA, BRCRB, BRCRC, and BRCRD are used to specify and control conditions for channels
A, B, C, and D of the UBC.
Bit:
Initial Value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
−
−
CMFCPn
−
CPn2
CPn1
CPn0
−
−
−
IDn1
IDn0
RWn1
RWn0
−
−
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[Legend]
n = Channels A to D
Bit
Bit Name
Initial
Value
R/W
Description
15

0
R/W
Reserved
14

0
R/W
These bits are always read as 0. The write value
should always be 0.
13
CMFCPn
0
R/W
Condition Match CPU Flag
UBC break source flag that indicates satisfaction of a
specified CPU bus cycle condition.
0: The CPU cycle condition for channel n break
requests has not been satisfied.
1: The CPU cycle condition for channel n break
requests has been satisfied.
12

0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
11
CPn2
0
R/W
CPU Cycle Select
10
CPn1
0
R/W
9
CPn0
0
R/W
These bits select CPU cycles as the bus cycle break
condition for the given channel.
000: Break requests will not be generated.
001: The bus cycle break condition is CPU cycles.
01x: Setting prohibited
1xx: Setting prohibited
8

0
R/W
Reserved
7

0
R/W
6

0
R/W
These bits are always read as 0. The write value
should always be 0.
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Section 8 User Break Controller (UBC)
Bit
Bit Name
Initial
Value
R/W
Description
5
IDn1
0
R/W
Break Condition Select
4
IDn0
0
R/W
These bits select the PC break as the source of UBC
break interrupt requests for the given channel.
00: Break requests will not be generated.
01: UBC break condition is the PC break.
1x: Setting prohibited
3
RWn1
0
R/W
Read Select
2
RWn0
0
R/W
These bits select read cycles as the bus cycle break
condition for the given channel.
00: Break requests will not be generated.
01: The bus cycle break condition is read cycles.
1x: Setting prohibited
1

0
R/W
Reserved
0

0
R/W
These bits are always read as 0. The write value
should always be 0.
[Legend]
n = Channels A to D
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Section 8 User Break Controller (UBC)
8.4
Operation
The UBC does not detect condition matches in standby states (sleep mode, all module clock stop
mode, software standby mode, deep software standby, and hardware standby mode).
8.4.1
Setting of Break Control Conditions
1. The address condition for the break is set in break address register n (BARn). A mask for the
address is set in break address mask register n (BAMRn).
2. The bus and break conditions are set in break control register n (BRCRn). Bus conditions
consist of CPU cycle, PC break, and reading. Condition comparison is not performed when the
CPU cycle setting is CPn = B'000, the PC break setting is IDn = B'00, or the read setting is
RWn = B'00.
3. The condition match CPU flag (CMFCPn) is set in the event of a break condition match on the
corresponding channel. These flags are set when the break condition matches but are not
cleared when it no longer does. To confirm setting of the same flag again, read the flag once
from the break interrupt handling routine, and then write 0 to it (the flag is cleared by writing 0
to it after reading it as 1).
[Legend]
n = Channels A to D
8.4.2
PC Break
1. When specifying a PC break, specify the address as the first address of the required instruction.
If the address for a PC break condition is not the first address of an instruction, a break will
never be generated.
2. The break occurs after fetching and execution of the target instruction have been confirmed. In
cases of contention between a break before instruction execution and a user maskable interrupt,
priority is given to the break before instruction execution.
3. A break will not be generated even if a break before instruction execution is set in a delay slot.
4. The PC break condition is generated by specifying CPU cycles as the bus condition in break
control register n (BRCRn.CPn0 = 1), PC break as the break condition (IDn0 = 1), and read
cycles as the bus-cycle condition (RWn0 = 1).
[Legend]
n = Channels A to D
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Section 8 User Break Controller (UBC)
8.4.3
Condition Match Flag
Condition match flags are set when the break conditions match. The condition match flags of the
UBC are listed in table 8.2.
Table 8.2
List of Condition Match Flags
Register
Flag Bit
Source
BRCRA
CMFCPA (bit 13)
Indicates that the condition matches in the CPU cycle
for channel A
BRCRB
CMFCPB (bit 13)
Indicates that the condition matches in the CPU cycle
for channel B
BRCRC
CMFCPC (bit 13)
Indicates that the condition matches in the CPU cycle
for channel C
BRCRD
CMFCPD (bit 13)
Indicates that the condition matches in the CPU cycle
for channel D
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Section 8 User Break Controller (UBC)
8.5
Usage Notes
1. PC break usage note
 Contention between a SLEEP instruction (to place the chip in the sleep state or on software
standby) and PC break
If a break before a PC break instruction is set for the instruction after a SLEEP instruction
and the SLEEP instruction is executed with the SSBY bit cleared to 0, break interrupt
exception handling is executed without sleep mode being entered. In this case, the
instruction after the SLEEP instruction is executed after the RTE instruction.
When the SSBY bit is set to 1, break interrupt exception handling is executed after the
oscillation settling time has elapsed subsequent to the transition to software standby mode.
When an interrupt is the canceling source, interrupt exception handling is executed after the
RTE instruction, and the instruction following the SLEEP instruction is then executed.
CLK
SLEEP
Software standby
Break interrupt
exception handling
(PC break source)
Interrupt
exception handling
(Cancelling source)
Cancelling source
Figure 8.2 Contention between SLEEP Instruction (Software Standby) and PC Break
2. Prohibition on Setting of PC Break
 Setting of a UBC break interrupt for program within the UBC break interrupt handling
routine is prohibited.
3. The procedure for clearing a UBC flag bit (condition match flag) is shown below. A flag bit is
cleared by writing 0 to it after reading it as 1. As the register that contains the flag bits is
accessible in byte units, bit manipulation instructions can be used.
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Section 8 User Break Controller (UBC)
CKS
Register read
The value read as 1
is retained
Register write
Flag bit
Flag bit is set to 1
Flag bit is cleared to 0
Figure 8.3 Flag Bit Clearing Sequence (Condition Match Flag)
4. After setting break conditions for the UBC, an unexpected UBC break interrupt may occur
after the execution of an illegal instruction. This depends on the value of the program counter
and the internal bus cycle.
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Section 8 User Break Controller (UBC)
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Section 9 Bus Controller (BSC)
Section 9 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters; CPU, DMAC, EXDMAC*, and DTC.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
9.1
Features
• Manages external address space in area units
Manages the external address space divided into eight areas
Chip select signals (CS0 to CS7) can be output for each area
Bus specifications can be set independently for each area
8-bit access or 16-bit access can be selected for each area
DRAM*, synchronous DRAM*, burst ROM, byte control SRAM, or address/data multiplexed
I/O interface can be set
An endian conversion function is provided to connect a device of little endian
• Basic bus interface
This interface can be connected to the SRAM and ROM
2-state access or 3-state access can be selected for each area
Program wait cycles can be inserted for each area
Wait cycles can be inserted by the WAIT pin.
Extension cycles can be inserted while CSn is asserted for each area (n = 0 to 7)
The negation timing of the read strobe signal (RD) can be modified
• Byte control SRAM interface
Byte control SRAM interface can be set for areas 0 to 7
The SRAM that has a byte control pin can be directly connected
• Burst ROM interface
Burst ROM interface can be set for areas 0 and 1
Burst ROM interface parameters can be set independently for areas 0 and 1
• Address/data multiplexed I/O interface
Address/data multiplexed I/O interface can be set for areas 3 to 7
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Section 9 Bus Controller (BSC)
• DRAM interface*
DRAM interface is available as area 2
Row/column address-multiplexed output (8, 9, 10, or 11 bits)
Two CAS signals control byte accesses for 16-bit data bus device
CAS assertion period can be extended by a program wait and a pin wait
Burst access can be performed in fast page mode
Tp cycle for ensuring a RAS precharge time can be inserted
CAS-before-RAS refresh (CBR refresh) and self refresh are selectable
• Synchronous DRAM interface*
Synchronous DRAM interface is available as area 2
Row/column address-multiplexed output (8, 9, 10, or 11 bits)
DQM signals control byte access for 16-bit data bus device
Auto refresh and self refresh are selectable
CAS latency can be selected from 2 to 4
High-speed data transfer is available using EXDMAC cluster transfer
• Idle cycle insertion
Idle cycles can be inserted between external read accesses to different areas
Idle cycles can be inserted before the external write access after an external read access
Idle cycles can be inserted before the external read access after an external write access
Idle cycles can be inserted before the external access after a DMAC/EXDMAC* single address
transfer (write access)
• Write buffer function
External write cycles and internal accesses can be executed in parallel
Write accesses to the on-chip peripheral module and on-chip memory accesses can be executed
in parallel
DMAC single address transfers and internal accesses can be executed in parallel
• External bus release function
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, EXDMAC*,
DTC, refresh*, and external bus master
• EXDMAC external bus transfers and internal accesses can be executed in parallel*.
• Multi-clock function
The internal peripheral functions can be operated in synchronization with the peripheral
module clock (Pφ). Accesses to the external address space can be operated in synchronization
with the external bus clock (Bφ).
Rev. 2.00 Jul. 31, 2008 Page 184 of 1438
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Section 9 Bus Controller (BSC)
• The bus start (BS) and read/write (RD/WR) signals can be output.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
A block diagram of the bus controller is shown in figure 9.1.
Rev. 2.00 Jul. 31, 2008 Page 185 of 1438
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Section 9 Bus Controller (BSC)
CPU address bus
DMAC address bus
DTC address bus
EXDMAC address bus*
Address
selector
Internal bus
control signals
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
CPU bus request signal
DTC bus request signal
DMAC bus request signal
Area decoder
Internal bus
control unit
External bus
control unit
Internal
bus
arbiter
CS7 to CS0
External bus
control signals
WAIT
External bus
arbiter
EXDMAC bus acknowledge signal*
EXDMAC bus request signal*
BREQ
BACK
BREQO
Refresh timer*
Control registers
Internal data bus
ABWCR
SRAMCR
ASTCR
BROMCR
WTCRA
MPXCR
WTCRB
DRAMCR*
RDNCR
DRACCR*
CSACR
SDCR*
IDLCR
REFCR*
BCR1
BCR2
[Legend]
Bus width control register
ABWCR:
Access state control register
ASTCR:
Wait control register A
WTCRA:
Wait control register B
WTCRB:
Read strobe timing control register
RDNCR:
CS assertion period control register
CSACR:
Idle control register
IDLCR:
Bus control register 1
BCR1:
Bus control register 2
BCR2:
ENDIANCR:Endian control register
Note:
*
RTCNT*
RTCOR*
ENDIANCR
SRAMCR:
BROMCR:
MPXCR:
DRAMCR*:
DRACCR*:
SDCR*:
REFCR*:
RTCNT*:
RTCOR*:
SRAM mode control register
Burst ROM interface control register
Address/data multiplexed I/O control register
DRAM control register
DRAM access control register
Synchronous DRAM control register
Refresh control register
Refresh timer counter
Refresh time constant register
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.1 Block Diagram of Bus Controller
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Section 9 Bus Controller (BSC)
9.2
Register Descriptions
The bus controller has the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bus width control register (ABWCR)
Access state control register (ASTCR)
Wait control register A (WTCRA)
Wait control register B (WTCRB)
Read strobe timing control register (RDNCR)
CS assertion period control register (CSACR)
Idle control register (IDLCR)
Bus control register 1 (BCR1)
Bus control register 2 (BCR2)
Endian control register (ENDIANCR)
SRAM mode control register (SRAMCR)
Burst ROM interface control register (BROMCR)
Address/data multiplexed I/O control register (MPXCR)
DRAM control register (DRAMCR)*
DRAM access control register (DRACCR)*
Synchronous DRAM control register (SDCR)*
Refresh control register (REFCR)*
Refresh timer counter (RTCNT)*
Refresh time constant register (RTCOR)*
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.2.1
Bus Width Control Register (ABWCR)
ABWCR specifies the data bus width for each area in the external address space.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
ABWH7
ABWH6
ABWH5
ABWH4
ABWH3
ABWH2
ABWH1
ABWH0
1
1
1
1
1
1
1
1/0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
ABWL7
ABWL6
ABWL5
ABWL4
ABWL3
ABWL2
ABWL1
ABWL0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF.
Bit
Bit Name
Initial
Value*1
R/W
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ABWH7
ABWH6
ABWH5
ABWH4
ABWH3
ABWH2
ABWH1
ABWL0
ABWL7
ABWL6
ABWL5
ABWL4
ABWL3
ABWL2
ABWL1
ABWL0
1
1
1
1
1
1
1
1/0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 Bus Width Control
These bits select whether the corresponding area is to be
designated as 8-bit access space or 16-bit access space.
ABWHn ABWLn (n = 7 to 0)
×
0:
Setting prohibited
0
1:
Area n is designated as 16-bit
access space
1
1:
Area n is designated as 8-bit access
2
space*
[Legend]
×: Don't care
Notes: 1. Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF.
2. An address space specified as byte control SRAM interface must not be specified as 8bit access space.
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Section 9 Bus Controller (BSC)
9.2.2
Access State Control Register (ASTCR)
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space and enables/disables wait cycle insertion.
Bit
15
14
13
12
11
10
9
8
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name








Bit Name
Initial Value
R/W
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial
Value
R/W
Description
15
AST7
1
R/W
Area 7 to 0 Access State Control
14
AST6
1
R/W
13
AST5
1
R/W
12
AST4
1
R/W
These bits select whether the corresponding area is to be
designated as 2-state access space or 3-state access
space. Wait cycle insertion is enabled or disabled at the
same time.
11
AST3
1
R/W
0: Area n is designated as 2-state access space
10
AST2
1
R/W
9
AST1
1
R/W
8
AST0
1
R/W
Wait cycle insertion in area n access is disabled
1: Area n is designated as 3-state access space
Wait cycle insertion in area n access is enabled
(n = 7 to 0)
7 to 0

All 0
R
Reserved
These are read-only bits and cannot be modified.
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Section 9 Bus Controller (BSC)
9.2.3
Wait Control Registers A and B (WTCRA, WTCRB)
WTCRA and WTCRB select the number of program wait cycles for each area in the external
address space.
• WTCRA
Bit
15
14
13
12
11
10
9
8
Bit Name

W72
W71
W70

W62
W61
W60
Initial Value
0
1
1
1
0
1
1
1
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name

W52
W51
W50

W42
W41
W40
Initial Value
0
1
1
1
0
1
1
1
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit
15
14
13
12
11
10
9
8
Bit Name

W32
W31
W30

W22
W21
W20
Initial Value
0
1
1
1
0
1
1
1
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name

W12
W11
W10

W02
W01
W00
• WTCRB
Initial Value
0
1
1
1
0
1
1
1
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
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Section 9 Bus Controller (BSC)
• WTCRA
Bit
Bit Name
Initial
Value
R/W
Description
15

0
R
Reserved
14
W72
1
R/W
Area 7 Wait Control 2 to 0
13
W71
1
R/W
12
W70
1
R/W
These bits select the number of program wait cycles
when accessing area 7 while bit AST7 in ASTCR is 1.
This is a read-only bit and cannot be modified.
000: Program wait cycle not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted
11

0
R
10
W62
1
R/W
Area 6 Wait Control 2 to 0
9
W61
1
R/W
8
W60
1
R/W
These bits select the number of program wait cycles
when accessing area 6 while bit AST6 in ASTCR is 1.
Reserved
This is a read-only bit and cannot be modified.
000: Program wait cycle not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted
7

0
R
Reserved
This is a read-only bit and cannot be modified.
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
6
W52
1
R/W
Area 5 Wait Control 2 to 0
5
W51
1
R/W
4
W50
1
R/W
These bits select the number of program wait cycles
when accessing area 5 while bit AST5 in ASTCR is 1.
000: Program cycle wait not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted
3

0
R
Reserved
This is a read-only bit and cannot be modified.
2
W42
1
R/W
Area 4 Wait Control 2 to 0
1
W41
1
R/W
0
W40
1
R/W
These bits select the number of program wait cycles
when accessing area 4 while bit AST4 in ASTCR is 1.
000: Program wait cycle not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted
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Section 9 Bus Controller (BSC)
• WTCRB
Bit
Bit Name
Initial
Value
R/W
Description
15

0
R
Reserved
14
W32
1
R/W
Area 3 Wait Control 2 to 0
13
W31
1
R/W
12
W30
1
R/W
These bits select the number of program wait cycles
when accessing area 3 while bit AST3 in ASTCR is 1.
This is a read-only bit and cannot be modified.
000: Program wait cycle not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted
11

0
R
10
9
8
W22
W21
W20
1
1
1
R/W
R/W
R/W
Reserved
This is a read-only bit and cannot be modified.
Area 2 Wait Control 2 to 0
These bits select the number of program wait cycles
when accessing area 2 while bit AST2 in ASTCR is 1.
When SDRAM* is connected, the CAS latency is
specified. At this time, W22 is ignored. The CAS latency
can be specified even if the wait cycle insertion is
disabled by ASTCR.
Selection of number of program wait cycles:
000: Program wait cycle not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted
Setting of CAS latency (W22 is ignored.)*:
00: Setting prohibited
01: SDRAM with a CAS latency of 2 is connected.
10: SDRAM with a CAS latency of 3 is connected.
11: SDRAM with a CAS latency of 4 is connected.
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
7

0
R
Reserved
This is a read-only bit and cannot be modified.
6
W12
1
R/W
Area 1 Wait Control 2 to 0
5
W11
1
R/W
4
W10
1
R/W
These bits select the number of program wait cycles
when accessing area 1 while bit AST1 in ASTCR is 1.
000: Program wait cycle not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted

3
0
R
Reserved
This is a read-only bit and cannot be modified.
2
W02
1
R/W
Area 0 Wait Control 2 to 0
1
W01
1
R/W
0
W00
1
R/W
These bits select the number of program wait cycles
when accessing area 0 while bit AST0 in ASTCR is 1.
000: Program wait cycle not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted
Note:
*
Supported only by the H8SX1648G Group and the H8SX1648H Group.
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Section 9 Bus Controller (BSC)
9.2.4
Read Strobe Timing Control Register (RDNCR)
RDNCR selects the negation timing of the read strobe signal (RD) when reading the external
address spaces specified as a basic bus interface or the address/data multiplexed I/O interface.
Bit
15
14
13
12
11
10
9
8
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name








Bit Name
Initial Value
R/W
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial
Value
R/W
Description
15
RDN7
0
R/W
Read Strobe Timing Control
14
RDN6
0
R/W
13
RDN5
0
R/W
RDN7 to RDN0 set the negation timing of the read
strobe in a corresponding area read access.
12
RDN4
0
R/W
11
RDN3
0
R/W
10
RDN2
0
R/W
9
RDN1
0
R/W
8
RDN0
0
R/W
As shown in figure 9.2, the read strobe for an area for
which the RDNn bit is set to 1 is negated one halfcycle earlier than that for an area for which the RDNn
bit is cleared to 0. The read data setup and hold time
are also given one half-cycle earlier.
0: In an area n read access, the RD signal is negated
at the end of the read cycle
1: In an area n read access, the RD signal is negated
one half-cycle before the end of the read cycle
(n = 7 to 0)
7 to 0

All 0
R
Reserved
These are read-only bits and cannot be modified.
Notes: 1. In an external address space which is specified as byte control SRAM interface, the
RDNCR setting is ignored and the same operation when RDNn = 1 is performed.
2. In an external address space which is specified as the burst ROM interface, the
RDNCR setting is ignored and the same operation when RDNn = 0 is performed during
read accesses by the CPU and EXDMAC* cluster transfer.
* Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
Bus cycle
T3
T2
T1
Bφ
RD
RDNn = 0
Data
RD
RDNn = 1
Data
(n = 7 to 0)
Figure 9.2 Read Strobe Negation Timing (Example of 3-State Access Space)
9.2.5
CS Assertion Period Control Registers (CSACR)
CSACR selects whether or not the assertion periods of the chip select signals (CSn) and address
signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O
interface are to be extended. Extending the assertion period of the CSn and address signals allows
the setup time and hold time of read strobe (RD) and write strobe (LHWR/LLWR) to be assured
and to make the write data setup time and hold time for the write strobe become flexible.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
15
CSXH7
0
R/W
CS and Address Signal Assertion Period Control 1
14
CSXH6
0
R/W
13
CSXH5
0
R/W
12
CSXH4
0
R/W
11
CSXH3
0
R/W
These bits specify whether or not the Th cycle is to be
inserted (see figure 9.3). When an area for which bit
CSXHn is set to 1 is accessed, one Th cycle, in which
the CSn and address signals are asserted, is inserted
before the normal access cycle.
10
CSXH2
0
R/W
9
CSXH1
0
R/W
8
CSXH0
0
R/W
7
CSXT7
0
R/W
CS and Address Signal Assertion Period Control 2
6
CSXT6
0
R/W
5
CSXT5
0
R/W
4
CSXT4
0
R/W
3
CSXT3
0
R/W
These bits specify whether or not the Tt cycle is to be
inserted (see figure 9.3). When an area for which bit
CSXTn is set to 1 is accessed, one Tt cycle, in which
the CSn and address signals are retained, is inserted
after the normal access cycle.
2
CSXT2
0
R/W
1
CSXT1
0
R/W
0
CSXT0
0
R/W
0: In access to area n, the CSn and address assertion
period (Th) is not extended
1: In access to area n, the CSn and address assertion
period (Th) is extended
(n = 7 to 0)
0: In access to area n, the CSn and address assertion
period (Tt) is not extended
1: In access to area n, the CSn and address assertion
period (Tt) is extended
(n = 7 to 0)
Notes: In burst ROM interface, the CSXTn settings are ignored during read accesses by the CPU
and EXDMAC* cluster transfer.
* Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
Bus cycle
Th
T1
T2
T3
Tt
Bφ
Address
CSn
AS
BS
RD/WR
RD
Read
Read data
Data bus
LHWR, LLWR
Write
Data bus
Write data
Figure 9.3 CS and Address Assertion Period Extension
(Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0)
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Section 9 Bus Controller (BSC)
9.2.6
Idle Control Register (IDLCR)
IDLCR specifies the idle cycle insertion conditions and the number of idle cycles.
Bit
Bit Name
15
14
13
12
11
10
9
8
IDLS3
IDLS2
IDLS1
IDLS0
IDLCB1
IDLCB0
IDLCA1
IDLCA0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
IDLSEL7
IDLSEL6
IDLSEL5
IDLSEL4
IDLSEL3
IDLSEL2
IDLSEL1
IDLSEL0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
IDLS3
1
R/W
Idle Cycle Insertion 3
Inserts an idle cycle between the bus cycles when the
DMAC or EXDMAC* single address transfer (write
cycle) is followed by external access.
0: No idle cycle is inserted
1: An idle cycle is inserted
14
IDLS2
1
R/W
Idle Cycle Insertion 2
Inserts an idle cycle between the bus cycles when the
external write cycle is followed by external read cycle.
0: No idle cycle is inserted
1: An idle cycle is inserted
13
IDLS1
1
R/W
Idle Cycle Insertion 1
Inserts an idle cycle between the bus cycles when the
external read cycles of different areas continue.
0: No idle cycle is inserted
1: An idle cycle is inserted
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
12
IDLS0
1
R/W
Idle Cycle Insertion 0
Inserts an idle cycle between the bus cycles when the
external read cycle is followed by external write cycle.
0: No idle cycle is inserted
1: An idle cycle is inserted
11
IDLCB1
1
R/W
Idle Cycle State Number Select B
10
IDLCB0
1
R/W
Specifies the number of idle cycles to be inserted for
the idle condition specified by IDLS1 and IDLS0.
00: No idle cycle is inserted
01: 2 idle cycles are inserted
00: 3 idle cycles are inserted
01: 4 idle cycles are inserted
9
IDLCA1
1
R/W
Idle Cycle State Number Select A
8
IDLCA0
1
R/W
Specifies the number of idle cycles to be inserted for
the idle condition specified by IDLS3 to IDLS0.
00: 1 idle cycle is inserted
01: 2 idle cycles are inserted
10: 3 idle cycles are inserted
11: 4 idle cycles are inserted
7
IDLSEL7
0
R/W
Idle Cycle Number Select
6
IDLSEL6
0
R/W
5
IDLSEL5
0
R/W
4
IDLSEL4
0
R/W
Specifies the number of idle cycles to be inserted for
each area for the idle insertion condition specified by
IDLS1 and IDLS0.
3
IDLSEL3
0
R/W
2
IDLSEL2
0
R/W
1
IDLSEL1
0
R/W
1: Number of idle cycles to be inserted for area n is
specified by IDLCB1 and IDLCB0.
0
IDLSEL0
0
R/W
(n = 7 to 0)
Note:
*
0: Number of idle cycles to be inserted for area n is
specified by IDLCA1 and IDLCA0.
Supported only by the groups H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.2.7
Bus Control Register 1 (BCR1)
BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the
write data buffer function, and enabling/disabling of the WAIT pin input.
Bit
Bit Name
15
14
13
12
11
10
9
8
BRLE
BREQOE




WDBE
WAITE
0
0
0
0
0
0
0
0
R/W
R/W
R
R
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
DKC
EDKC*






Initial Value
R/W
Bit
Bit Name
0
0
0
0
0
0
0
0
R/W
R/W
R
R
R
R
R
R
Initial Value
R/W
Note: *
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Bit
Bit Name
Initial
Value
R/W
Description
15
BRLE
0
R/W
External Bus Release Enable
Enables/disables external bus release.
0: External bus release disabled
BREQ, BACK, and BREQO pins can be used as I/O
ports
1: External bus release enabled*
For details, see section 13, I/O Ports.
14
BREQOE
0
R/W
BREQO Pin Enable
Controls outputting the bus request signal (BREQO) to
the external bus master in the external bus released
state when an internal bus master performs an
external address space access.
0: BREQO output disabled
BREQO pin can be used as I/O port
1: BREQO output enabled
13, 12

All 0
R
Reserved
These are read-only bits and cannot be modified.
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
11, 10

All 0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
9
WDBE
0
R/W
Write Data Buffer Enable
The write data buffer function can be used for an
external write cycle and a DMAC single address
transfer cycle.
The changed setting may not affect an external access
immediately after the change.
0: Write data buffer function not used
1: Write data buffer function used
8
WAITE
0
R/W
WAIT Pin Enable
Selects enabling/disabling of wait input by the WAIT
pin. When area 2 is specified as the synchronous
DRAM space, the setting of this bit does not affect the
synchronous DRAM space access operation.
0: Wait input by WAIT pin disabled
WAIT pin can be used as I/O port
1: Wait input by WAIT pin enabled
For details, see section 13, I/O Ports.
7
DKC
0
R/W
DACK Control
Selects the timing of DMAC transfer acknowledge
signal assertion.
0: DACK signal is asserted at the Bφ falling edge
1: DACK signal is asserted at the Bφ rising edge
6
EDKC*
0
R/W
EDACK Control
Controls the assertion timing of an acknowledge signal
for an EXDMAC transfer.
0: EDACK signal asserted at the falling edge of Bφ
1: EDACK signal asserted at the rising edge of Bφ
5 to 0

All 0
R
Reserved
These are read-only bits and cannot be modified.
Notes: When external bus release is enabled or input by the WAIT pin is enabled, make sure to set
the ICR bit to 1. For details, see section 13, I/O Ports.
* Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.2.8
Bus Control Register 2 (BCR2)
BCR2 is used for bus arbitration control of the CPU, DMAC, EXDMAC*, and DTC, and
enabling/disabling of the write data buffer function to the peripheral modules.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Bit
7
6
5
4
3
2
1
0
Bit Name


EBCCS*
IBCCS



PWDBE
Initial Value
0
0
0
0
0
0
1
0
R/W
R
R
R/W
R/W
R
R
R/W
R/W
Note: *
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0
R
Reserved
These are read-only bits and cannot be modified.
5
EBCCS*
0
R/W
External Bus Cycle Control Select
Selects the method for external bus arbitration.
0: Releases the bus depending on the priority
1: Executes the bus cycle alternatively when a conflict
occurs between a bus request by the EXDMAC,
external bus master or refresh bus and a request for
an external space access by the CPU, DMAC, or
DTC.
4
IBCCS
0
R/W
Internal Bus Cycle Control Select
Selects the internal bus arbiter function.
0: Releases the bus mastership according to the priority
1: Executes the bus cycles alternatively when a CPU
bus mastership request conflicts with a DMAC or
DTC bus mastership request
3, 2

All 0
R
Reserved
These are read-only bits and cannot be modified.
1

1
R/W
Reserved
This bit is always read as 1. The write value should
always be 1.
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
0
PWDBE
0
R/W
Peripheral Module Write Data Buffer Enable
Specifies whether or not to use the write data buffer
function for the peripheral module write cycles.
0: Write data buffer function not used
1: Write data buffer function used
Note:
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
*
9.2.9
Endian Control Register (ENDIANCR)
ENDIANCR selects the endian format for each area of the external address space. Though the data
format of this LSI is big endian, data can be transferred in the little endian format during external
address space access.
Note that the data format for the areas used as a program area or a stack area should be big endian.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
LE7
LE6
LE5
LE4
LE3
LE2


0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Bit
Bit Name
Initial
Value
R/W
Description
7
LE7
0
R/W
Little Endian Select
6
LE6
0
R/W
Selects the endian for the corresponding area.
5
LE5
0
R/W
0: Data format of area n is specified as big endian
4
LE4
0
R/W
1: Data format of area n is specified as little endian
3
LE3
0
R/W
(n = 7 to 2)
2
LE2
0
R/W
1, 0

All 0
R
Reserved
These are read-only bits and cannot be modified.
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Section 9 Bus Controller (BSC)
9.2.10
SRAM Mode Control Register (SRAMCR)
SRAMCR specifies the bus interface of each area in the external address space as a basic bus
interface or a byte control SRAM interface.
In areas specified as 8-bit access space by ABWCR, the SRAMCR setting is ignored and the byte
control SRAM interface cannot be specified.
Bit
15
14
13
12
11
10
9
8
BCSEL7
BCSEL6
BCSEL5
BCSEL4
BCSEL3
BCSEL2
BCSEL1
BCSEL0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name








Bit Name
Initial Value
R/W
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial
Value
R/W
Description
15
BCSEL7
0
R/W
Byte Control SRAM Interface Select
14
BCSEL6
0
R/W
Selects the bus interface for the corresponding area.
13
BCSEL5
0
R/W
12
BCSEL4
0
R/W
11
BCSEL3
0
R/W
When setting a bit to 1, the bus interface select bits in
BROMCR, DRAMCR* and MPXCR must be cleared to
0.
10
BCSEL2
0
R/W
9
BCSEL1
0
R/W
8
BCSEL0
0
R/W
7 to 0

All 0
R
0: Area n is basic bus interface
1: Area n is byte control SRAM interface
(n = 7 to 0)
Reserved
These are read-only bits and cannot be modified.
Note:
*
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.2.11
Burst ROM Interface Control Register (BROMCR)
BROMCR specifies the burst ROM interface.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
BSRM0
BSTS02
BSTS01
BSTS00


BSWD01
BSWD00
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R/W
R/W
7
6
5
4
3
2
1
0
BSRM1
BSTS12
BSTS11
BSTS10


BSWD11
BSWD10
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
BSRM0
0
R/W
Area 0 Burst ROM Interface Select
Specifies the area 0 bus interface. To set this bit to 1,
clear bit BCSEL0 in SRAMCR to 0.
0: Basic bus interface or byte-control SRAM interface
1: Burst ROM interface
14
BSTS02
0
R/W
Area 0 Burst Cycle Select
13
BSTS01
0
R/W
Specifies the number of burst cycles of area 0
12
BSTS00
0
R/W
000: 1 cycle
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: 6 cycles
110: 7 cycles
111: 8 cycles
11, 10

All 0
R
Reserved
These are read-only bits and cannot be modified.
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
9
BSWD01
0
R/W
Area 0 Burst Word Number Select
8
BSWD00
0
R/W
Selects the number of words in burst access to the area
0 burst ROM interface
00: Up to 4 words (8 bytes)
01: Up to 8 words (16 bytes)
10: Up to 16 words (32 bytes)
11: Up to 32 words (64 bytes)
7
BSRM1
0
R/W
Area 1 Burst ROM Interface Select
Specifies the area 1 bus interface as a basic interface
or a burst ROM interface. To set this bit to 1, clear bit
BCSEL1 in SRAMCR to 0.
0: Basic bus interface or byte-control SRAM interface
1: Burst ROM interface
6
BSTS12
0
R/W
Area 1 Burst Cycle Select
5
BSTS11
0
R/W
Specifies the number of cycles of area 1 burst cycle
4
BSTS10
0
R/W
000: 1 cycle
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: 6 cycles
110: 7 cycles
111: 8 cycles
3, 2

All 0
R
Reserved
These are read-only bits and cannot be modified.
1
BSWD11
0
R/W
Area 1 Burst Word Number Select
0
BSWD10
0
R/W
Selects the number of words in burst access to the area
1 burst ROM interface
00: Up to 4 words (8 bytes)
01: Up to 8 words (16 bytes)
10: Up to 16 words (32 bytes)
11: Up to 32 words (64 bytes)
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Section 9 Bus Controller (BSC)
9.2.12
Address/Data Multiplexed I/O Control Register (MPXCR)
MPXCR specifies the address/data multiplexed I/O interface.
Bit
15
14
13
12
11
10
9
8
MPXE7
MPXE6
MPXE5
MPXE4
MPXE3



0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R
R
Bit
7
6
5
4
3
2
1
0
Bit Name







ADDEX
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R/W
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
MPXE7
0
R/W
Address/Data Multiplexed I/O Interface Select
14
MPXE6
0
R/W
Specifies the bus interface for the corresponding area.
13
MPXE5
0
R/W
12
MPXE4
0
R/W
To set this bit to 1, clear the BCSELn bit in SRAMCR to
0.
11
MPXE3
0
R/W
0: Area n is specified as a basic interface or a byte
control SRAM interface.
1: Area n is specified as an address/data multiplexed
I/O interface
(n = 7 to 3)
10 to 1 
All 0
R
Reserved
These are read-only bits and cannot be modified.
0
ADDEX
0
R/W
Address Output Cycle Extension
Specifies whether a wait cycle is inserted for the
address output cycle of address/data multiplexed I/O
interface.
0: No wait cycle is inserted for the address output cycle
1: One wait cycle is inserted for the address output
cycle
Rev. 2.00 Jul. 31, 2008 Page 208 of 1438
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Section 9 Bus Controller (BSC)
9.2.13
DRAM Control Register (DRAMCR)
DRAMCR specifies the DRAM/SDRAM interface. Rewrite this register while the
DRAM/SDRAM is not accessed.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
DRAME
DTYPE


OEE
RAST

CAST
0
0
0
0
0
0
0
0
R/W
R/W
R
R
R/W
R/W
R
R/W
7
6
5
4
3
2
1
0
BE
RCDM
DDS
EDDS


MXC1
MXC0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
DRAME
0
R/W
Area 2 DRAM Interface Select
Selects whether or not area 2 is specified as the
DRAM/SDRAM interface. When this bit is set to 1,
select the type of DRAM to be used in area 2 with the
DTYPE bit. When this bit is set to 1, the BCSEL2 bit in
SRAMCR should be set to 0.
0: Basic bus interface or byte-control SRAM interface
1: DRAM/SDRAM interface
14
DTYPE
0
R/W
DRAM Select
Selects the type of DRAM to be used in area 2.
0: DRAM is used in area 2
1: SDRAM is used in area 2
13, 12

All 0
R
Reserved
The initial value should not be changed.
Rev. 2.00 Jul. 31, 2008 Page 209 of 1438
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
11
OEE
0
R/W
OE Output Enable
The OE signal is output when DRAM with the EDO
page mode is connected, whereas the CKE signal is
output when SDRAM is connected.
0: OE/CKE signal output disabled (the OE/CKE pin can
be used as an I/O port)
1: OE/CKE signal enabled
10
RAST
0
R/W
RAS Assertion Timing Select
Selects whether the RAS signal is asserted at the rising
edge or falling edge of the Bφ signal in the Tr cycle
during a DRAM access. The relationship between this
bit and RAS assertion timing is shown in figure 9.4.
When SDRAM is used, the setting of this bit does not
affect operation.
0: RAS signal is asserted at the falling edge of the Bf
signal in the Tr cycle
1: RAS signal is asserted at the rising edge of the Bf
signal in the Tr cycle
9

0
R
Reserved
8
CAST
0
R/W
Column Address Output Cycle Count Select
The initial value should not be changed.
Selects whether the number of column address output
cycles is two or three during a DRAM access.
When SDRAM is used, the setting of this bit does not
affect operation.
0: Column address is output for two cycles
1: Column address is output for three cycles
7
BE
0
R/W
Burst Access Enable
Enables or disables a burst access to the
DRAM/SDRAM. The DRAM/SDRAM is accessed in
high-speed page mode. When DRAM with the EDO
page mode is used, connect the OE signal of this LSI to
the OE signal of DRAM.
0: DRAM/SDRAM is accessed with full access
1: DRAM/SDRAM is accessed in high-speed page
mode
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
6
RCDM
0
R/W
RAS Down Mode
Selects the RAS signal state while a DRAM access is
halted when a basic bus interface area or an on-chip
I/O register is accessed: keep the RAS signal low (RAS
down mode) and high (RAS up mode).
This bit is effective when BE = 1. Clearing this bit to 0
with RCDM = 1 in RAS down mode cancels the RAS
down mode and the RAS signal goes high.
If the RAS down mode is selected for the SDRAM
interface, the READ/WRIT command is issued without
issuance of the ACTV command when the same row
address is accessed consecutively.
0: RAS up mode when the DRAM/SDRAM is accessed
1: RAS down mode when the DRAM/SDRAM is
accessed
5
DDS
0
R/W
DMAC Single Address Transfer Option
Selects whether a DMAC single address transfer
through the DRAM/SDRAM interface is enabled only in
full access mode or is also enabled in fast-page access
mode.
When clearing the BE bit to 0 to disable a burst access
to the DRAM/SDRAM interface, a DMAC single address
transfer is performed in full access mode regardless of
this bit.
This bit does not affect an external access by other bus
masters or a DMAC dual address transfer. Setting this
bit to 1 changes the DACK output timing.
0: DMAC single address transfer through the
DRAM/SDRAM is enabled only in full access mode
1: DMAC single address transfer through the
DRAM/SDRAM is also enabled in fast-page access
mode
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
4
EDDS
0
R/W
EXDMAC Single Address Transfer Option
Selects whether an EXDMAC single address transfer
through the DRAM/SDRAM interface is enabled only in
full access mode or is also enabled in fast-page access
mode.
When clearing the BE bit to 0 to disable a burst access
to the DRAM/SDRAM interface, an EXDMAC single
address transfer is performed in full access mode
regardless of this bit.
This bit does not affect an external access by other bus
masters or an EXDMAC dual address transfer. Setting
this bit to 1 changes the EDACK output timing.
0: EXDMAC single address transfer through the
DRAM/SDRAM is enabled only in full access mode
1: EXDMAC single address transfer through the
DRAM/SDRAM is also enabled in fast-page access
mode
3

0
R
Reserved
2

0
R/W
The initial value should not be changed.
Rev. 2.00 Jul. 31, 2008 Page 212 of 1438
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
1
0
MCX1
MCX0
0
0
R/W
R/W
Multiplexed Address Bit Select
Select the number of bits by which a row address
multiplexed with a column address is shifted to
the lower side. At the same time, these bits
select row address bits compared during a burst
access to the DRAM/SDRAM interface.
00: Shifted by 8 bits
A23 to A8 are compared for 8-bit access space
A23 to A9 are compared for 16-bit access space
01: Shifted by 9 bits
A23 to A9 are compared for 8-bit access space
A23 to A10 are compared for 16-bit access space
10: Shifted by 10 bits
A23 to A10 are compared for 8-bit access space
A23 to A11 are compared for 16-bit access space
11: Shifted by 11 bits
A23 to A11 are compared for 8-bit access space
A23 to A12 are compared for 16-bit access space
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Bus cycle
Tp
Tr
Tc1
Tc2
Bφ
Address
Row address
Column address
RAS
(When RAST = 0)
RAS
(When RAST = 1)
LUCAS, LLCAS
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Figure 9.4 RAS Assertion Timing (Column Address Output for 2 states
in Full Access Mode)
Rev. 2.00 Jul. 31, 2008 Page 213 of 1438
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Section 9 Bus Controller (BSC)
9.2.14
DRAM Access Control Register (DRACCR)
DRACCR specifies the settings for the DRAM/SDRAM interface. Rewrite this register while the
DRAM/SDRAM is not accessed.
Bit
15
14
13
12
11
10
9
8
Bit Name


TPC1
TPC0


RCD1
RCD0
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R
R
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name








Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial
Value
R/W
15, 14

All 0
R
Description
Reserved
The initial value should not be changed.
13
TPC1
0
R/W
Precharge Cycle Control
12
TPC0
0
R/W
Select the number of RAS precharge cycles on a
normal access and a refresh cycle.
00: One cycle
01: Two cycles
10: Three cycles
11: Four cycles
11, 10

All 0
R
Reserved
The initial value should not be changed.
9
RCD1
0
R/W
RAS-CAS Wait Control
8
RCD0
0
R/W
Select the number of wait cycles inserted between RAS
and CAS cycles.
00: No wait cycle inserted
01: One wait cycle inserted
10: Two wait cycles inserted
11: Three wait cycles inserted
7 to 0

All 0
R
Reserved
The initial value should not be changed.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.2.15
Synchronous DRAM Control Register (SDCR)
SDCR specifies the settings for the SDRAM interface (when the DTYPE bit in DRAMCR is set
to 1). Rewrite this register while the SDRAM is not accessed. When the SDRAM interface is not
used, the initial value must not be changed.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
MRSE







0
0
0
0
0
0
0
0
R/W
R
R
R
R/W
R/W
R
R/W
7
6
5
4
3
2
1
0
CKSPE






TRWL
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
MRSE
0
R/W
Mode Register Set Enable
Enables the setting in the SDRAM mode register. See
section 9.11.14, Setting SDRAM Mode Register.
0: Disables to set the SDRAM mode register
1: Enables to set the SDRAM mode register
14 to 12 
All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
11, 10

0
R/W
9

0
R
Reserved
8

0
R/W
The initial value should not be changed.
7
CKSPE
0
R/W
Clock Suspend Enable
Reserved
The initial value should not be changed.
Enables the clock suspend mode in which read data
output cycles are extended. Setting this bit to 1 extends
cycles in which read data is output from SDRAM.
0: Disables the clock suspend mode
1: Enables the clock suspend mode
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
6 to 1

All 0
R
Description
Reserved
The initial value should not be changed.
0
TRWL
0
R/W
Write-Precharge Delay Control
Specifies the time until the precharge command is
issued after the write command is issued to the
SDRAM. Setting this bit to 1 inserts one wait cycle after
the write command is issued.
0: No wait cycle inserted
1: One wait cycle inserted
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
9.2.16
Refresh Control Register (REFCR)
REFCR specifies the refresh type for the DRAM/SDRAM interface.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
CMF
CMIE
RCW1
RCW0

RTCK2
RTCK1
RTCK0
0
0
0
0
0
0
0
0
R/(W)*
R/W
R/W
R/W
R
R/W
R/W
R/W
7
6
5
4
3
2
1
0
RFSHE
RLW2
RLW1
RLW0
SLFRF
TPCS2
TPCS1
TPCS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
15
CMF
0
R/(W)* Compare Match Flag
Description
Indicates that the refresh timer counter (RTCNT) and
refresh timer constant register (RTCOR) match.
[Clearing conditions]
•
When 0 is written to this bit after this bit is read as 1
with RFSHE = 0
•
When CBR refresh is performed with RFSHE = 1
[Setting condition]
•
14
CMIE
0
R/W
When RTCNT matches RTCOR
Compare Match Interrupt Enable
Enables or disables an interrupt request (CMI) when the
CMF flag is set to 1.
This bit is effective when refresh control is not
performed (RFSHE = 0). When refresh control is
performed (RFSHE = 1), this bit is always cleared to 0.
This bit cannot be modified.
0: Interrupt requests by the CMF flag disabled
1: Interrupt requests by the CMF flag enabled
13 to 12 RCW1
0
R/W
CAS-RAS Wait Control
RCW0
0
R/W
Select the number of wait cycles inserted between the
CAS asserted cycle and CAS asserted cycle during
DRAM refresh.
When the SDRAM space is selected, these bits do not
affect operations although they can be read from or
written to.
00: No wait cycle inserted
01: One wait cycle inserted
10: Two wait cycles inserted
11: Three wait cycles inserted
11

0
R
Reserved
The initial value should not be changed.
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10
RTCK2
0
R/W
Refresh Counter Clock Select
9
RTCK1
0
R/W
8
RTCK0
0
R/W
Select the clock used to count up the refresh counter
from the seven internal clocks generated by dividing the
on-chip peripheral module clock (Pφ). When the clock is
selected, the refresh counter starts to count up.
000: Counting halted
001: Counts on Pφ/2
010: Counts on Pφ/8
011: Counts on Pφ/32
100: Counts on Pφ/128
101: Counts on Pφ/512
110: Counts on Pφ/2048
111: Counts on Pφ/4096
7
RFSHE
0
R/W
Refresh Control
Enables or disables refresh control. When refresh
control is disabled, the refresh timer can be used as the
interval timer.
In single-chip activation mode, the setting of this bit
should be made after setting the EXPE bit in SYSCR to
1. For SYSCR, see section 3, MCU Operating Modes.
0: Refresh control enabled
1: Refresh control disabled
6
RLW2
0
R/W
Refresh Cycle Wait Control
5
RLW1
0
R/W
4
RLW0
0
R/W
Select the number of wait cycles during a CAS before
RAS refresh cycle for the DRAM interface and an autorefresh cycle for the SDRAM interface.
000: No wait cycle inserted
001: One wait cycle inserted
010: Two wait cycles inserted
010: Three wait cycles inserted
010: Four wait cycles inserted
010: Five wait cycles inserted
010: Six wait cycles inserted
010: Seven wait cycles inserted
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Section 9 Bus Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
3
SLFRF
0
R/W
Self-Refresh Enable
Selects the self-refresh mode for the DRAM/SDRAM
interface when a transition to the software standby
mode is made with this bit set to 1. To perform a refresh
cycle by setting the RFSHE bit is set to 1, this bit is
effective.
To perform a self-refresh cycle when the SDRAM
interface is selected, enable the CKE output by setting
the OEE bit in DRAMCR.
0: Disables self-refresh
1: Enables self-refresh
2
TPCS2
0
R/W
Precharge Cycle Control during Self-Refresh
1
TPCS1
0
R/W
0
TPCS0
0
R/W
Selects the number of precharge cycles immediately
after a self-refresh cycle. The number of actual number
of precharge cycles is the sum of the numbers indicated
by these bits and bits TPC1 and TPC0.
000: No wait cycle inserted
001: One wait cycle inserted
010: Two wait cycles inserted
011: Three wait cycles inserted
100: Four wait cycles inserted
101: Five wait cycles inserted
110: Six wait cycles inserted
111: Seven wait cycles inserted
Notes: * Only 0 can be written to this bit, to clear the flag.
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.2.17
Refresh Timer Counter (RTCNT)
RTCNT counts up on the internal clock selected by bits RTCK2 to RTCK0 in REFCR.
When the RTCNT value matches the RTCOR value (compare match), the CMF flag in REFCR is
set to 1 and RTCNT is initialized to H'00. At this time, when the RFSHE bit in REFCR is set to 1,
a refresh cycle is generated. When the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is
set to 1, a compare match interrupt (CMI) is generated.
Bit
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Initial Value
R/W
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
9.2.18
Refresh Time Constant Register (RTCOR)
RTCOR specifies intervals at which a compare match for RTCOR and RTCNT is generated.
The RTCOR value is always compared with the RTCNT value. When they match, the CMF flag
in REFCR is set to 1 and RTCNT is initialized to H'00.
Bit
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.3
Bus Configuration
Figure 9.5 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of
the following three types.
1. Internal system bus 1: A bus that connects the CPU, DTC, DMAC, on-chip RAM, on-chip
ROM, internal peripheral bus, and external access bus.
2. Internal system bus 2*: A bus that connects the EXDMAC and external access bus
3. Internal peripheral bus: A bus that accesses registers in the bus controller, interrupt controller,
DMAC, and EXDMAC*, and registers of peripheral modules such as SCI and timer.
4. External access bus: A bus that accesses external devices via the external bus interface.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Iφ
synchronization
CPU
DTC
On-chip
RAM
On-chip
ROM
Internal system bus 1
Write data
buffer
Bus controller,
interrupt controller,
power-down controller
Internal peripheral bus
Pφ
synchronization
Internal system bus 2*
DMAC
EXDMAC*
Write data
buffer
External access bus
Bφ
synchronization
Peripheral
functions
External bus
interface
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.5 Internal Bus Configuration
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Section 9 Bus Controller (BSC)
9.4
Multi-Clock Function and Number of Access Cycles
The internal functions of this LSI operate synchronously with the system clock (Iφ), the peripheral
module clock (Pφ), or the external bus clock (Bφ). Table 9.1 shows the synchronization clock and
their corresponding functions.
Table 9.1
Synchronization Clocks and Their Corresponding Functions
Synchronization Clock
Function Name
Iφ
MCU operating mode
Interrupt controller
Bus controller
CPU
DTC
DMAC
EXDMAC*
Internal memory
Clock pulse generator
Power down control
Pφ
I/O ports
TPU
PPG
TMR
WDT
SCI
A/D
D/A
IIC2
Bφ
External bus interface
Note:
*
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
The frequency of each synchronization clock (Iφ, Pφ, and Bφ) is specified by the system clock
control register (SCKCR) independently. For further details, see section 26, Clock Pulse
Generator.
There will be cases when Pφ and Bφ are equal to Iφ and when Pφ and Bφ are different from Iφ
according to the SCKCR specifications. In any case, access cycles for internal peripheral functions
and external space is performed synchronously with Pφ and Bφ, respectively.
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Section 9 Bus Controller (BSC)
For example, in an external address space access where the frequency rate of Iφ and Bφ is n : 1,
the operation is performed in synchronization with Bφ. In this case, external 2-state access space is
2n cycles and external 3-state access space is 3n cycles (no wait cycles is inserted) if the number
of access cycles is counted based on Iφ.
If the frequencies of Iφ, Pφ and Bφ are different, the start of bus cycle may not synchronize with
Pφ or Bφ according to the bus cycle initiation timing. In this case, clock synchronization cycle
(Tsy) is inserted at the beginning of each bus cycle.
For example, if an external address space access occurs when the frequency rate of Iφ and Bφ is
n : 1, 0 to n-1 cycles of Tsy may be inserted. If an internal peripheral module access occurs when
the frequency rate of Iφ and Pφ is m : 1, 0 to m-1 cycles of Tsy may be inserted.
Figure 9.6 shows the external 2-state access timing when the frequency rate of Iφ and Bφ is 4 : 1.
Figure 9.7 shows the external 3-state access timing when the frequency rate of Iφ and Bφ is 2 : 1.
Rev. 2.00 Jul. 31, 2008 Page 223 of 1438
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Section 9 Bus Controller (BSC)
Divided clock
synchronization
cycle
Tsy
T1
T2
Iφ
Bφ
Address
CSn
AS
RD
Read
D15 to D8
D7 to D0
LHWR
LLWR
Write
D15 to D8
D7 to D0
BS
RD/WR
Figure 9.6 System Clock: External Bus Clock = 4:1, External 2-State Access
Rev. 2.00 Jul. 31, 2008 Page 224 of 1438
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Section 9 Bus Controller (BSC)
Divided clock
synchronization
cycle
Tsy
T1
T2
T3
Iφ
Bφ
Address
CSn
AS
RD
Read
D15 to D8
D7 to D0
LHWR
LLWR
Write
D15 to D8
D7 to D0
BS
RD/WR
Figure 9.7 System Clock: External Bus Clock = 2:1, External 3-State Access
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Section 9 Bus Controller (BSC)
9.5
External Bus
9.5.1
Input/Output Pins
Table 9.2 shows the pin configuration of the bus controller and table 9.3 shows the pin functions
on each interface.
Table 9.2
Pin Configuration
Name
Symbol
I/O
Function
Bus cycle start
BS
Output
Signal indicating that the bus cycle has started
Address strobe/
address hold
AS/AH
Output
•
Strobe signal indicating that the basic bus, byte control
SRAM, or burst ROM space is accessed and address
output on address bus is enabled
•
Signal to hold the address during access to the
address/data multiplexed I/O interface
Read strobe
RD
Output
Strobe signal indicating that the basic bus, byte control
SRAM, burst ROM, or address/data multiplexed I/O space
is being read
Read/write
RD/WR
Output
•
•
Signal indicating the input or output direction
Write enable signal of the SRAM during access to the
byte control SRAM space
Low-high write/
lower-upper byte
select
LHWR/LUB
Output
•
Strobe signal indicating that the basic bus, burst ROM,
or address/data multiplexed I/O space is written to,
and the upper byte (D15 to D8) of data bus is enabled
•
Strobe signal indicating that the byte control SRAM
space is accessed, and the upper byte (D15 to D8) of
data bus is enabled
Low-low write/
lower-lower byte
select
LLWR/LLB
Output
•
Strobe signal indicating that the basic bus, burst ROM,
or address/data multiplexed I/O space is written to,
and the lower byte (D7 to D0) of data bus is enabled
•
Strobe signal indicating that the byte control SRAM
space is accessed, and the lower byte (D7 to D0) of
data bus is enabled
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Section 9 Bus Controller (BSC)
Name
Symbol
I/O
Function
Chip select 0
CS0
Output
Strobe signal indicating that area 0 is selected
Chip select 1
CS1
Output
Strobe signal indicating that area 1 is selected
Chip select 2
CS2
Output
Strobe signal indicating that area 2 is selected
Chip select 3
CS3
Output
Strobe signal indicating that area 3 is selected
Chip select 4
CS4
Output
Strobe signal indicating that area 4 is selected
Chip select 5
CS5
Output
Strobe signal indicating that area 5 is selected
Chip select 6
CS6
Output
Strobe signal indicating that area 6 is selected
Chip select 7
CS7
Output
Strobe signal indicating that area 7 is selected
Row address strobe*
RAS
Output
•
Row address strobe signal when area 2 is
specified as DRAM space
•
Row address strobe signal when area 2 is
specified as SDRAM space
Column address strobe*
CAS
Output
Column address strobe signal when area 2 is
specified as SDRAM space
Write enable*
WE
Output
•
Write enable signal for DRAM
•
Write enable signal when area 2 is specified as
SDRAM space
•
Lower-upper-column address strobe signal for 32bit DRAM
•
Upper-column address strobe signal for 16-bit
DRAM
•
Lower-upper-data mask enable signal for 32-bit
SDRAM
Lower-upper-column address
strobe/lower-upper-data mask
enable*
Lower-lower-column address
strobe/lower-lower-data mask
enable*
LUCAS/
DQMLU
LLCAS/
DQMLL
Output
Output
•
Upper-data mask enable signal for 16-bit SDRAM
•
Lower-lower-column address strobe signal for 32bit DRAM
•
Lower-column address strobe signal for 16-bit
DRAM
•
Column address strobe signal for 8-bit DRAM
•
Lower-lower-data mask enable signal for 32-bit
SDRAM
•
Lower-data mask enable signal for 16-bit SDRAM
•
Data mask enable signal for 8-bit SDRAM
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Section 9 Bus Controller (BSC)
Name
Symbol
I/O
Function
Output enable/clock enable*
OE/CKE
Output
•
Output enable signal for DRAM
•
Clock enable signal for SDRAM
SDRAMφ*
SDRAMφ
Output
SDRAM dedicated clock
Wait
WAIT
Input
Wait request signal when accessing external address
space
Bus request
BREQ
Input
Request signal for release of bus to external bus
master
Bus request acknowledge
BACK
Output
Acknowledge signal indicating that bus has been
released to external bus master
Bus request output
BREQO
Output
External bus request signal used when internal bus
master accesses external address space in the
external-bus released state
Data transfer acknowledge 3
(DMAC_3)
DACK3
Output
Data acknowledge signal for DMAC_3 single address
transfer
Data transfer acknowledge 2
(DMAC_2
DACK2
Output
Data acknowledge signal for DMAC_2 single address
transfer
Data transfer acknowledge 1
(DMAC_1)
DACK1
Output
Data acknowledge signal for DMAC_1 single address
transfer
Data transfer acknowledge 0
(DMAC_0)
DACK0
Output
Data acknowledge signal for DMAC_0 single address
transfer
Data transfer acknowledge 3
(EXDMAC_3)*
EDACK3
Output
Data acknowledge signal for EXDMAC_3 single
address transfer
Data transfer acknowledge 2
(EXDMAC_2)*
EDACK2
Output
Data acknowledge signal for EXDMAC_2 single
address transfer
Data transfer acknowledge 1
(EXDMAC_1)*
EDACK1
Output
Data acknowledge signal for EXDMAC_1 single
address transfer
Data transfer acknowledge 0
(EXDMAC_0)*
EDACK0
Output
Data acknowledge signal for EXDMAC_0 single
address transfer
External bus clock
Bφ
Output
External bus clock
Note:
*
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
Table 9.3
Pin Functions in Each Interface
16
Pin Name
Output
Bφ
Basic
Bus
Initial State
Single
8
8
Chip 16
Output
Byte-Control
SRAM
Burst
ROM
Address/Data
Multiplexed I/O DRAM* SDRAM*
16
16
8
16
8
16
8
16
8

O
O
O
O
O
O
O
O
O
O
O
O










O
CS0
Output
Output

O
O
O
O
O




 
CS1



O
O
O
O
O




 
CS2



O
O
O




O
O
O
CS3



O
O
O


O
O


 
CS4



O
O
O


O
O


 
CS5



O
O
O


O
O


 
CS6



O
O
O


O
O


 
CS7



O
O
O


O
O


 
BS



O
O
O
O
O
O
O
O
O
O
O
RD/WR



O
O
O
O
O
O
O
O
O
O
O
Output
Output

O
O
O
O
O




 
(Output) (Output)
SDRAMφ∗
AS
Remarks
Controlled by MD3
O
AH








O
O


 
RD
Output
Output

O
O
O
O
O
O
O
O
O
 
LHWR/LUB
Output
Output

O

O
O

O



 
LLWR/LLB
Output
Output

O
O
O
O
O
O
O


 
RAS*










O
O
O
O
CAS*












O
O
WE*










O
O
O
O
LUCAS/DQMLU*










O

O

LLCAS/DQMLL*










O
O
O
O
OE*










O
O
 
Controlled by DRAME and OEE
CKE*












O
O
Controlled by DRAME and OEE
WAIT



O
O
O
O
O
O
O
O
O
 
Controlled by WAITE
[Legend]
O: Used as bus control signal.
: Not used as bus control signal (I/O port as initial state).
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 229 of 1438
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Section 9 Bus Controller (BSC)
9.5.2
Area Division
The bus controller divides the 16-Mbyte address space into eight areas, and performs bus control
for the external address space in area units. Chip select signals (CS0 to CS7) can be output for
each area.
Figure 9.8 shows an area division of the 16-Mbyte address space. For details on address map, see
section 3, MCU Operating Modes.
H'000000
Area 0
(2 Mbytes)
H'1FFFFF
H'200000
Area 1
(2 Mbytes)
H'3FFFFF
H'400000
Area 2
(8 Mbytes)
H'BFFFFF
H'C00000
Area 3
(2 Mbytes)
H'DFFFFF
H'E00000
Area 4
(1 Mbyte)
H'EFFFFF
H'F00000
Area 5
(1 Mbyte − 8 kbytes)
H'FFDFFF
H'FFE000
Area 6
H'FFFEFF (8 kbytes − 256 bytes)
H'FFFF00
Area 7
H'FFFFFF
(256 bytes)
16-Mbyte space
Figure 9.8 Address Space Area Division
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Section 9 Bus Controller (BSC)
9.5.3
Chip Select Signals
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external address space area is accessed. Figure 9.9 shows an example of CSn (n
= 0 to 7) signal output timing.
Enabling or disabling of CSn signal output is set by the port function control register (PFCR). For
details, see section 13.3, Port Function Controller.
In on-chip ROM disabled extended mode, pin CS0 is placed in the output state after a reset. Pins
CS1 to CS7 are placed in the input state after a reset and so the corresponding PFCR bits should
be set to 1 when outputting signals CS1 to CS7.
In on-chip ROM enabled extended mode, pins CS0 to CS7 are all placed in the input state after a
reset and so the corresponding PFCR bits should be set to 1 when outputting signals CS0 to CS7.
The PFCR can specify multiple CS outputs for a pin. If multiple CSn outputs are specified for a
single pin by the PFCR, CS to be output are generated by mixing all the CS signals. In this case,
the settings for the external bus interface areas in which the CSn signals are output to a single pin
should be the same.
Figure 9.10 shows the signal output timing when the CS signals to be output to areas 5 and 7 are
output to the same pin.
Bus cycle
T1
T2
T3
Bφ
Address bus
External address of area n
CSn
Figure 9.9 CSn Signal Output Timing (n = 0 to 7)
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Section 9 Bus Controller (BSC)
Area 5 access
Area 6 access
Area 5 access
Area 6 access
Bφ
CS5
CS6
Output waveform
Address bus
Figure 9.10 Timing When CS Signal is Output to the Same Pin
9.5.4
External Bus Interface
The type of the external bus interfaces, bus width, endian format, number of access cycles, and
strobe assert/negate timings can be set for each area in the external address space. The bus width
and the number of access cycles for both on-chip memory and internal I/O registers are fixed, and
are not affected by the external bus settings.
(1)
Type of External Bus Interface
Six types of external bus interfaces are provided and can be selected in area units. Table 9.4 shows
each interface name, description, area name to be set for each interface. Table 9.5 shows the areas
that can be specified for each interface. The initial state of each area is a basic bus interface.
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Section 9 Bus Controller (BSC)
Table 9.4
Interface Names and Area Names
Interface
Description
Area Name
Basic interface
Directly connected to ROM and
RAM
Basic bus space
Byte control SRAM interface
Directly connected to byte
SRAM with byte control pin
Byte control SRAM space
Burst ROM interface
Directly connected to the ROM
that allows page access
Burst ROM space
Address/data multiplexed I/O
interface
Directly connected to the
peripheral LSI that requires
address and data multiplexing
Address/data multiplexed I/O
space
DRAM interface*
Directly connected to DRAM
DRAM space
Synchronous DRAM interface*
Directly connected to
synchronous DRAM
Synchronous DRAM space
Note:
*
Table 9.5
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Areas Specifiable for Each Interface
Areas
Interface
Related
Registers
0
1
2
3
4
5
6
7
Basic interface
SRAMCR
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Byte control SRAM interface
Burst ROM interface
BROMCR
O
O






Address/data multiplexed I/O
interface
MPXCR



O
O
O
O
O
DRAM interface*
DRAMCR


O







O





Synchronous DRAM interface*
Note:
*
Supported only by the H8SX/1648LGroup and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
(2)
Bus Width
A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is
selected functions as an 8-bit access space and an area for which a 16-bit bus is selected functions
as a 16-bit access space. In addition, the bus width of address/data multiplexed I/O space is 8 bits
or 16 bits, and the bus width for the byte control SRAM space is 16 bits.
The initial state of the bus width is specified by the operating mode.
If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as
16-bit access space, 16-bit bus mode is set.
(3)
Endian Format
Though the endian format of this LSI is big endian, data can be converted into little endian format
when reading or writing to the external address space.
Areas 7 to 2 can be specified as either big endian or little endian format by the LE7 to LE2 bits in
ENDIANCR.
The initial state of each area is the big endian format.
Note that the data format for the areas used as a program area or a stack area should be big endian.
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Section 9 Bus Controller (BSC)
(4)
Number of Access Cycles
(a)
Basic Bus Interface
The number of access cycles in the basic bus interface can be specified as two or three cycles by
the ASTCR. An area specified as 2-state access is specified as 2-state access space; an area
specified as 3-state access is specified as 3-state access space.
For the 2-state access space, a wait cycle insertion is disabled. For the 3-state access space, a
program wait (0 to 7 cycles) specified by WTCRA and WTCRB or an external wait by WAIT can
be inserted.
Assertion period of the chip select signal can be extended by CSACR.
Number of access cycles in the basic bus interface
= number of basic cycles (2, 3) + number of program wait cycles (0 to 7)
+ number of CS extension cycles (0, 1, 2)
[+ number of external wait cycles by the WAIT pin]
(b)
Byte Control SRAM Interface
The number of access cycles in the byte control SRAM interface is the same as that in the basic
bus interface.
Number of access cycles in byte control SRAM interface
= number of basic cycles (2, 3) + number of program wait cycles (0 to 7)
+ number of CS extension cycles (0, 1, 2)
[+ number of external wait cycles by the WAIT pin]
(c)
Burst ROM Interface
The number of access cycles at full access in the burst ROM interface is the same as that in the
basic bus interface. The number of access cycles in the burst access can be specified as one to
eight cycles by the BSTS bit in BROMCR.
Number of access cycles in the burst ROM interface
= number of basic cycles (2, 3) + number of program wait cycles (0 to 7)
+ number of CS extension cycles (0, 1)
[+number of external wait cycles by the WAIT pin]
+ number of burst access cycles (1 to 8) × number of burst accesses (0 to 63)
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Section 9 Bus Controller (BSC)
(d)
Address/data multiplexed I/O interface
The number of access cycles in data cycle of the address/data multiplexed I/O interface is the
same as that in the basic bus interface. The number of access cycles in address cycle can be
specified as two or three cycles by the ADDEX bit in MPXCR.
Number of access cycles in the address/data multiplexed I/O interface
= number of address output cycles (2, 3) + number of data output cycles (2, 3)
+ number of program wait cycles (0 to 7)
+ number of CS extension cycles (0, 1, 2)
[+number of external wait cycles by the WAIT pin]
(e)
DRAM Interface
In the DRAM interface, the numbers of precharge cycles, row address output cycles, and column
address output cycles can be specified.
The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in
DRACCR. The number of row address output cycles can be specified as one to four cycles by bits
RCD1 and RCD0 in DRACCR. The number of column address output cycles can be specified as
two or three cycles by the CAST bit in DRAMCR. For the column address output cycle, program
wait (0 to 7 cycles) specified by WTCRB or external wait by WAIT can be inserted.
Number of access cycles in the DRAM interface
= number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4)
+ number of column address output cycles (2 or 3)
+ number of program wait cycles (0 to 7)
[+number of external wait cycles by the WAIT pin]
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
(f)
SDRAM Interface
In the SDRAM interface, the numbers of precharge cycles, row address output cycles, and column
address output cycles, as well as clock suspend and write-precharge delay, can be specified by
DRACCR and WTCRB.
The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in
DRACCR. The number of row address output cycles can be specified as one to four cycles by bits
RCD1 and RCD0 in DRACCR. The number of column address output cycles during read access
can be specified as two to four cycles by bits W21 and W20 in WTCRB.
The cycles for clock suspend and write-precharge delay can be inserted by bits CKSPE and
TRWL in SDCR.
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Section 9 Bus Controller (BSC)
Number of access cycles in the SDRAM interface
= number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4)
+ number of column address output cycles (read: 2 to 4, write: 2)
+ number of clock suspend cycles (only read: 0 or 1)
+ number of write precharge delay cycles (only write: 0 or 1)
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Table 9.6 lists the number of access cycles for each interface.
Table 9.6
Basic bus interface
Number of Access Cycles
=
=
Byte-control SRAM interface
=
=
Burst ROM interface
=
=
Address/data multiplexed I/O
interface
Full access
DRAM
interface*
Fast page
Refresh
Self-refresh
SDRAM
interface*
Setting mode
register
Full access
(read)
Full access
(write)
Page access
(read)
Page access
(write)
Cluster transfer
(read)
=Tma
[2,3]
=Tma
[2,3]
=Tp
[1 to 4]
=
=TRp
[1 to 4]
=TRp
[1 to 4]
=
=
=
Th
[0,1]
Th
[0,1]
Th
[0,1]
Th
[0,1]
Th
[0,1]
Th
[0,1]
+Th
[0,1]
+Th
[0,1]
+Tr
[1]
+T1
[1]
+T1
[1]
+T1
[1]
+T1
[1]
+T1
[1]
+T1
[1]
+T1
[1]
+T1
[1]
+Trw
[0 to 3]
+TRrw
[0 to 3]
+TRrw
[0 to 3]
Tp
[1 to 4]
Tp
[1 to 4]
Tp
[1 to 4]
+TRr
[1]
+TRr
[1]
+Tr
[1]
+Tr
[1]
+Tr
[1]
=
=
=
Tp
[1 to 4]
+Tr
[1]
Tp
[1 to 4]
+Tr
[1]
TRp
[1 to 4]
TRp
[1 to 4]
+TRr
[1]
+TRr
[1]
=
Cluster transfer
(write)
=
=
Refresh
=
Self-refresh
=
+T2
[1]
+T2
+Tpw
[1]
[0 to 7]
+T2
[1]
+T2
+Tpw
[1]
[0 to 7]
+T2
[1]
+T2
+Tpw
[1]
[0 to 7]
+T2
[1]
+T2
+Tpw
[1]
[0 to 7]
+TC1
+Tpw
[1]
[0 to 7]
TC1
+Tpw
[1]
[0 to 7]
+TRc1
+TRcw
[1]
[0 to 7]
Software
+
standby mode
[1+s]
+Ttw
[n]
+T3
[1]
+Ttw
[n]
+T3
[1]
+Ttw
[n]
+Ttw
[n]
+Ttw
[n]
+Ttw
[n]
+TRc2
[1]
+Trw
[0 to 3]
+Trw
[0 to 3]
+Trw
[0 to 3]
+Tc1
[1]
+Tc1
[1]
+Tc1
[1]
Tc1
[1]
Tc1
[1]
+Trw
+Tc1
[0 to 3]
[1]
Tc1
[1]
+Trw
+Tc1
[0 to 3]
[1]
Tc1
[1]
+TRc1
+TRcw
[1]
[0 to 7]
Software
+
standby mode
[1+s]
+Tt
[0,1]
+Tt
[0,1]
+Tt
[0,1]
+Tt
[0,1]
[3 to 12+n]
[2 to 4]
[3 to 12+n]
+Tb
[(1 to 8) x m]
+Tb
[(1 to 8) x m]
+T3
[1]
+T3
[1]
+Tc2
[1]
+Tc2
[1]
+Tt
[0,1]
+Tt
[0,1]
+Tc3
[0,1]
+Tc3
[0,1]
+TRc3
[1]
+TRc4
[1]
[(2 to 3)+(1 to 8) x m]
[(2 to 11+n)+(1 to 8) x m]
[4 to 7]
[5 to 15+n]
[4 to 18+n]
[2 to 10+n]
[4 to 17]
+Tcl
[1 to 3]
+Tcl
[1 to 3]
+Tsp
[0,1]
+Tsp
[0,1]
+Tcb
+Tcl
[0 to 31] [1 to 3]
+Tcb
+Tcl
[0 to 31] [1 to 3]
+TRc2
[1]
+TRc2
[1]
[2 to 4]
+TRp
[0 to 7]
+Tc2
[1]
+Tc2
[1]
+Tc2
[1]
+Tc2
[1]
+Tc2
[1]
+Tc2
[1]
+Tc2
[1]
+Tc2
[1]
+Tc2
[1]
[5 to 18+s]
+Trwl
[0,1]
[4 to 11]
[5 to 14]
+Trwl
[0,1]
[4 to 11]
[3 to 6]
+Trwl
[0,1]
[2 to 3]
[5 to 44]
[3 to 36]
+Tcb
[0 to 31]
+Tcb
[0 to 31]
[4 to 41]
[2 to 33]
[4 to 14]
+TRc3
[1]
+TRp
[0 to 7]
[5 to 15+s]
[Legend]
Number enclosed by bracket: Number of access cycles
n: Pin wait (0 to ∞)
m: Number of burst accesses (0 to 63)
s: Time for a transition to or from software standby mode
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
(5)
Strobe Assert/Negate Timings
The assert and negate timings of the strobe signals can be modified as well as number of access
cycles.
•
•
•
•
Read strobe (RD) in the basic bus interface
Chip select assertion period extension cycles in the basic bus interface
Data transfer acknowledge (DACK3 to DACK0) output for DMAC single address transfers
Data transfer acknowledge (EDACK3 to EDACK0) output for EXDMAC* single address
transfers
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
9.5.5
(1)
Area and External Bus Interface
Area 0
Area 0 includes on-chip ROM. All of area 0 is used as external address space in on-chip ROM
disabled extended mode, and the space excluding on-chip ROM is external address space in onchip ROM enabled extended mode.
When area 0 external address space is accessed, the CS0 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or burst ROM interface can be
selected for area 0 by bit BSRM0 in BROMCR and bit BCSEL0 in SRAMCR. Table 9.7 shows
the external interface of area 0.
Table 9.7
Area 0 External Interface
Register Setting
Interface
BSRM0 of BROMCR
BCSEL0 of SRAMCR
Basic bus interface
0
0
Byte control SRAM interface
0
1
Burst ROM interface
1
0
Setting prohibited
1
1
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Section 9 Bus Controller (BSC)
(2)
Area 1
In externally extended mode, all of area 1 is external address space. In on-chip ROM enabled
extended mode, the space excluding on-chip ROM is external address space.
When area 1 external address space is accessed, the CS1 signal can be output.
Either of the basic bus interface, byte control SRAM, or burst ROM interface can be selected for
area 1 by bit BSRM1 in BROMCR and bit BCSEL1 in SRAMCR. Table 9.8 shows the external
interface of area 1.
Table 9.8
Area 1 External Interface
Register Setting
Interface
BSRM1 of BROMCR
BCSEL1 of SRAMCR
Basic bus interface
0
0
Byte control SRAM interface
0
1
Burst ROM interface
1
0
Setting prohibited
1
1
(3)
Area 2
In externally extended mode, all of area 2 is external address space.
When area 2 external address space is accessed, the CS2 signal can be output.
The basic bus interface, byte-control SRAM interface, DRAM interface*, or SDRAM interface*
can be selected for area 2 by the DRAME and DTYPE bits in DRAMCR* and bit BCSEL2 in
SRAMCR. Table 9.9 shows the external interface of area 2.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
Table 9.9
Area 2 External Interface
DRAME in
DRAMCR*
0
0
1
1
1
Interface
Basic bus interface
Byte-control SRAM interface
DRAM interface*
SDRAM interface*
Setting prohibited
Note:
(4)
*
Register Setting
DTYPE in
DRAMCR*
*
*
0
1
*
BCSEL2 in
SRAMCR
0
1
0
0
1
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Area 3
In externally extended mode, all of area 3 is external address space.
When area 3 external address space is accessed, the CS3 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 3 by bit MPXE3 in MPXCR and bit BCSEL3 in SRAMCR.
Table 9.10 shows the external interface of area 3.
Table 9.10 Area 3 External Interface
Register Setting
Interface
MPXE3 of MPXCR
BCSEL3 of SRAMCR
Basic bus interface
0
0
Byte control SRAM interface
0
1
Address/data multiplexed I/O
interface
1
0
Setting prohibited
1
1
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Section 9 Bus Controller (BSC)
(5)
Area 4
In externally extended mode, all of area 4 is external address space.
When area 4 external address space is accessed, the CS4 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 4 by bit MPXE4 in MPXCR and bit BCSEL4 in SRAMCR.
Table 9.11 shows the external interface of area 4.
Table 9.11 Area 4 External Interface
Register Setting
Interface
MPXE4 of MPXCR
BCSEL4 of SRAMCR
Basic bus interface
0
0
Byte control SRAM interface
0
1
Address/data multiplexed I/O
interface
1
0
Setting prohibited
1
1
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Section 9 Bus Controller (BSC)
(6)
Area 5
Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area
5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that
the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME bit in
SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an
external address space. For details, see section 3, MCU Operating Modes.
When area 5 external address space is accessed, the CS5 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in
SRAMCR. Table 9.12 shows the external interface of area 5.
Table 9.12 Area 5 External Interface
Register Setting
Interface
MPXE5 of MPXCR
BCSEL5 of SRAMCR
Basic bus interface
0
0
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
0
1
1
0
1
1
(7)
Area 6
Area 6 includes internal I/O registers. In external extended mode, area 6 other than on-chip I/O
register area is external address space.
When area 6 external address space is accessed, the CS6 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 6 by the MPXE6 bit in MPXCR and the BCSEL6 bit in
SRAMCR. Table 9.13 shows the external interface of area 6.
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Section 9 Bus Controller (BSC)
Table 9.13 Area 6 External Interface
Register Setting
Interface
MPXE6 of MPXCR
BCSEL6 of SRAMCR
Basic bus interface
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
0
0
1
0
1
0
1
1
(8)
Area 7
Area 7 includes internal I/O registers. In external extended mode, area 7 other than internal I/O
register area is external address space.
When area 7 external address space is accessed, the CS7 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 7 by the MPXE7 bit in MPXCR and the BCSEL7 bit in
SRAMCR. Table 9.14 shows the external interface of area 7.
Table 9.14 Area 7 External Interface
Register Setting
Interface
MPXE7 of MPXCR
BCSEL7 of SRAMCR
Basic bus interface
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
0
0
1
0
1
0
1
1
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Section 9 Bus Controller (BSC)
9.5.6
Endian and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)
or lower data bus (D7 to D0) is used according to the bus specifications for the area being
accessed (8-bit access space or 16-bit access space), the data size, and endian format when
accessing external address space.
(1)
8-Bit Access Space
With the 8-bit access space, the lower byte data bus (D7 to D0) is always used for access. The
amount of data that can be accessed at one time is one byte: a word access is performed as two
byte accesses, and a longword access, as four byte accesses.
Figures 9.11 and 9.12 illustrate data alignment control for the 8-bit access space. Figure 9.11
shows the data alignment when the data endian format is specified as big endian. Figure 9.12
shows the data alignment when the data endian format is specified as little endian.
Strobe signal
LHWR/LUB
LLWR/LLB
RD
Data
Size
Access
Address
Byte
n
1
Word
n
2
Longword
n
Access
Count
4
Bus
Cycle
Data Size
D15
Data bus
D8 D7
D0
1st
Byte
7
0
1st
Byte
15
8
2nd
Byte
7
0
1st
Byte
31
24
2nd
Byte
23
16
3rd
Byte
15
8
4th
Byte
7
0
Figure 9.11 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian)
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Section 9 Bus Controller (BSC)
Strobe signal
LHWR/LUB
LLWR/LLB
RD
Data
Size
Access
Address
Bus
Cycle
1st
Byte
7
0
1st
Byte
7
0
2nd
Byte
15
8
1st
Byte
7
0
2nd
Byte
15
8
3rd
Byte
23
16
4th
Byte
31
24
Byte
n
1
Word
n
2
Longword
n
Data bus
D8 D7
Access
Count
4
Data Size
D15
D0
Figure 9.12 Access Sizes and Data Alignment Control for 8-Bit Access Space
(Little Endian)
(2)
16-Bit Access Space
With the 16-bit access space, the upper byte data bus (D15 to D8) and lower byte data bus (D7 to
D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one
word.
Figures 9.13 and 9.14 illustrate data alignment control for the 16-bit access space. Figure 9.13
shows the data alignment when the data endian format is specified as big endian. Figure 9.14
shows the data alignment when the data endian format is specified as little endian.
In big endian, byte access for an even address is performed by using the upper byte data bus and
byte access for an odd address is performed by using the lower byte data bus.
In little endian, byte access for an even address is performed by using the lower byte data bus, and
byte access for an odd address is performed by using the third byte data bus.
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Section 9 Bus Controller (BSC)
Strobe signal
LHWR/LUB
LLWR/LLB
RD
Access
Size
Byte
Word
Longword
Access
Address
Even
(2n)
Odd
(2n+1)
Even
(2n)
Odd
(2n+1)
Even
(2n)
Odd
(2n+1)
Access
Count
Bus
Cycle
Data Size
1
1st
Byte
1
1st
Byte
1
1st
Word
2
2
3
D15
Data bus
D8 D7
D0
0
7
15
7
0
8 7
0
15
8
1st
Byte
2nd
Byte
7
0
1st
Word
31
24 23
16
2nd
Word
15
8 7
0
1st
Byte
31
24
2nd
Word
23
16 15
8
3rd
Byte
7
0
Figure 9.13 Access Sizes and Data Alignment Control for 16-Bit Access Space (Big Endian)
Strobe signal
LHWR/LUB
LLWR/LLB
RD
Access
Size
Byte
Word
Longword
Access
Address
Even
(2n)
Odd
(2n+1)
Even
(2n)
Access
Count
Bus
Cycle
Data Size
1
1st
Byte
1
1st
1
1st
Odd
(2n+1)
2
Even
(2n)
2
Odd
(2n+1)
3
D15
Data bus
D8 D7
7
0
Byte
7
0
Word
15
8 7
0
1st
Byte
7
2nd
Byte
1st
2nd
0
15
8
Word
15
8 7
0
Word
31
24 23
16
1st
Byte
7
2nd
Word
23
3rd
Byte
0
16 15
8
31
24
Figure 9.14 Access Sizes and Data Alignment Control for 16-Bit Access Space
(Little Endian)
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D0
Section 9 Bus Controller (BSC)
9.6
Basic Bus Interface
The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications
can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, CSACR, and
ENDIANCR.
9.6.1
Data Bus
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)
or lower byte data bus (D7 to D0) is used according to the bus specifications for the area being
accessed (8-bit access space or 16-bit access space), the data size, and endian format when
accessing external address space,. For details, see section 9.5.6, Endian and Data Alignment.
9.6.2
I/O Pins Used for Basic Bus Interface
Table 9.15 shows the pins used for basic bus interface.
Table 9.15 I/O Pins for Basic Bus Interface
Name
Symbol
I/O
Bus cycle start
BS
Output
Signal indicating that the bus cycle has started
Address strobe
AS*
Output
Strobe signal indicating that an address output on the
address bus is valid during access
Read strobe
RD
Output
Strobe signal indicating the read access
Read/write
RD/WR
Output
Signal indicating the data bus input or output
direction
Low-high write
LHWR
Output
Strobe signal indicating that the upper byte (D15 to
D8) is valid during write access
Low-low write
LLWR
Output
Strobe signal indicating that the lower byte (D7 to
D0) is valid during write access
Chip select 0 to 7
CS0 to CS7 Output
Strobe signal indicating that the area is selected
Wait
WAIT
Wait request signal used when an external address
space is accessed
Note:
*
Input
Function
When the address/data multiplexed I/O is selected, this pin only functions as the AH
output and does not function as the AS output.
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Section 9 Bus Controller (BSC)
9.6.3
Basic Timing
This section describes the basic timing when the data is specified as big endian.
(1)
16-Bit 2-State Access Space
Figures 9.15 to 9.17 show the bus timing of 16-bit 2-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles
can be inserted.
Bus cycle
T1
T2
Bφ
Address
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
LHWR
LLWR
High level
D15 to D8
Valid
D7 to D0
High-Z
Write
BS
RD/WR
DACK or EDACK*
Notes: 1.
2.
3.
*
n = 0 to 7
When RDNn = 0
When DKC and EDKC* = 0
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address)
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Section 9 Bus Controller (BSC)
Bus cycle
T1
T2
Bφ
Address
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
LHWR
Write
High level
LLWR
D15 to D8
D7 to D0
High-Z
Valid
BS
RD/WR
DACK or EDACK*
Notes: 1. n = 0 to 7
2. When RDNn = 0
3. When DKC and EDKC* = 0
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.16 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address)
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Section 9 Bus Controller (BSC)
Bus cycle
T2
T1
Bφ
Address
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
LHWR
LLWR
Write
D15 to D8
Valid
D7 to D0
Valid
BS
RD/WR
DACK or EDACK*
Notes: 1.
2.
3.
*
n = 0 to 7
When RDNn = 0
When DKC and EDKC* = 0
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.17 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address)
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Section 9 Bus Controller (BSC)
(2)
16-Bit 3-State Access Space
Figures 9.18 to 9.20 show the bus timing of 16-bit 3-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be
inserted.
Bus cycle
T1
T2
T3
Bφ
Address
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
LHWR
LLWR
High level
Write
D15 to D8
Valid
D7 to D0
High-Z
BS
RD/WR
DACK or EDACK*
Notes: 1.
2.
3.
*
n = 0 to 7
When RDNn = 0
When DKC and EDKC* = 0
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.18 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)
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Section 9 Bus Controller (BSC)
Bus cycle
T1
T2
T3
Bφ
Address
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
LHWR
High level
LLWR
Write
D15 to D8
D7 to D0
High-Z
Valid
BS
RD/WR
DACK or EDACK*
Notes: 1.
2.
3.
*
n = 0 to 7
When RDNn = 0
When DKC and EDKC* = 0
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.19 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address)
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Section 9 Bus Controller (BSC)
Bus cycle
T1
T2
T3
Bφ
Address
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
LHWR
LLWR
Write
D15 to D8
Valid
D7 to D0
Valid
BS
RD/WR
DACK or EDACK*
Notes: 1.
2.
3.
*
n = 0 to 7
When RDNn = 0
When DKC and EDKC* = 0
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.20 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address)
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Section 9 Bus Controller (BSC)
9.6.4
Wait Control
This LSI can extend the bus cycle by inserting wait cycles (Tw) when the external address space is
accessed. There are two ways of inserting wait cycles: program wait (Tpw) insertion and pin wait
(Ttw) insertion using the WAIT pin.
(1)
Program Wait Insertion
From 0 to 7 wait cycles can be inserted automatically between the T2 state and T3 state for 3-state
access space, according to the settings in WTCRA and WTCRB.
(2)
Pin Wait Insertion
For 3-state access space, when the WAITE bit in BCR1 is set to 1 and the corresponding ICR bit
is set to 1, wait input by means of the WAIT pin is enabled. When the external address space is
accessed in this state, a program wait (Tpw) is first inserted according to the WTCRA and
WTCRB settings. If the WAIT pin is low at the falling edge of Bφ in the last T2 or Tpw cycle,
another Ttw cycle is inserted until the WAIT pin is brought high. The pin wait insertion is
effective when the Tw cycles are inserted to seven cycles or more, or when the number of Tw
cycles to be inserted is changed according to the external devices. The WAITE bit is common to
all areas. For details on ICR, see section 13, I/O Ports.
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Section 9 Bus Controller (BSC)
Figure 9.21 shows an example of wait cycle insertion timing. After a reset, the 3-state access is
specified, the program wait is inserted for seven cycles, and the WAIT input is disabled.
T1
T2
Wait by
program
Wait by WAIT pin
wait
Tpw
Ttw
Ttw
T3
Bφ
WAIT
Address
CSn
AS
RD
Read
Read
data
Data bus
LHWR, LLWR
Write
Data bus
Write data
BS
RD/WR
Notes: 1. Upward arrows indicate the timing of WAIT pin sampling.
2. n = 0 to 7
3. When RDNn = 0
Figure 9.21 Example of Wait Cycle Insertion Timing
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Section 9 Bus Controller (BSC)
9.6.5
Read Strobe (RD) Timing
The read strobe timing can be modified in area units by setting bits RDN7 to RDN0 in RDNCR to
1.
Note that the RD timing with respect to the DACK and EDACK*rising edge will change if the
read strobe timing is modified by setting RDNn to 1 when the DMAC or the EXDMAC* is used
in the single address mode.
Figure 9.22 shows an example of timing when the read strobe timing is changed in the basic bus 3state access space.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
Bus cycle
T1
T3
T2
Bφ
Address bus
CSn
AS
RD
RDNn = 0
Data bus
RD
RDNn = 1
Data bus
BS
RD/WR
DACK or EDACK*
Notes: 1. n = 0 to 7
2. When DKC and EDKC* = 0
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.22 Example of Read Strobe Timing
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Section 9 Bus Controller (BSC)
9.6.6
Extension of Chip Select (CS) Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, LHWR, and LLWR.
Settings can be made in CSACR to insert cycles in which only the CS, AS, and address signals are
asserted before and after a basic bus space access cycle. Extension of the CS assertion period can
be set in area units. With the CS assertion extension period in write access, the data setup and hold
times are less stringent since the write data is output to the data bus.
Figure 9.23 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Both extension cycle Th inserted before the basic bus cycle and extension cycle Tt inserted after
the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th cycle with the upper eight bits (CSXH7 to CSXH0) in
CSACR, and for the Tt cycle with the lower eight bits (CSXT7 to CSXT0).
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Section 9 Bus Controller (BSC)
Bus cycle
Th
T1
T2
T3
Tt
Bφ
Address
CSn
AS
RD
Read
Data bus
Read data
LHWR, LLWR
Write
Data bus
Write data
BS
RD/WR
DACK or EDACK*
Notes: 1. n = 0 to 7
2. When DKC and EDKC* = 0
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.23 Example of Timing when Chip Select Assertion Period is Extended
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Section 9 Bus Controller (BSC)
9.6.7
DACK and EDACK* Signal Output Timing
When the DMAC or EXDMAC* transfers data in single address mode, the output timing of the
DACK and EDACK* signals can be changed by the DKC and EDKC* bits in BCR1.
Figure 9.24 shows the output timing of the DACK and EDACK *signals. The DACK and
EDACK* signals are asserted a half cycle earlier by setting the DKC or EDKC* bits to 1.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
Bus cycle
T1
T2
Bφ
Address bus
CSn
AS
RD
Read
Data bus
Read data
LHWR, LLWR
Write
Data bus
Write data
BS
RD/WR
DKC, EDKC* = 0
DACK or
EDACK*
DKC, EDKC* = 1
Notes: 1. n = 7 to 0
2. RDNn = 0
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.24 DACK and EDACK* Signal Output Timing
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.7
Byte Control SRAM Interface
The byte control SRAM interface is a memory interface for outputting a byte select strobe during
a read or a write bus cycle. This interface has 16-bit data input/output pins and can be connected to
the SRAM that has the upper byte select and the lower byte select strobes such as UB and LB.
The operation of the byte control SRAM interface is the same as the basic bus interface except
that: the byte select strobes (LUB and LLB) are output from the write strobe output pins (LHWR
and LLWR), respectively; the read strobe (RD) negation timing is a half cycle earlier than that in
the case where RDNn = 0 in the basic bus interface regardless of the RDNCR settings; and the
RD/WR signal is used as write enable.
9.7.1
Byte Control SRAM Space Setting
Byte control SRAM interface can be specified for areas 0 to 7. Each area can be specified as byte
control SRAM interface by setting bits BCSELn (n = 0 to 7) in SRAMCR. For the area specified
as burst ROM interface or address/data multiplexed I/O interface, the SRAMCR setting is invalid
and byte control SRAM interface cannot be used.
9.7.2
Data Bus
The bus width of the byte control SRAM space can be specified as 16-bit byte control SRAM
space according to bits ABWHn and ABWLn (n = 0 to 7) in ABWCR. The area specified as 8-bit
access space cannot be specified as the byte control SRAM space.
For the 16-bit byte control SRAM space, data bus (D15 to D0) is valid.
Access size and data alignment are the same as the basic bus interface. For details, see section
9.5.6, Endian and Data Alignment.
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Section 9 Bus Controller (BSC)
9.7.3
I/O Pins Used for Byte Control SRAM Interface
Table 9.16 shows the pins used for the byte control SRAM interface.
In the byte control SRAM interface, write strobe signals (LHWR and LLWR) are output from the
byte select strobes. The RD/WR signal is used as a write enable signal.
Table 9.16 I/O Pins for Byte Control SRAM Interface
Pin
When Byte Control
SRAM is Specified
AS/AH
Name
I/O
Function
AS
Address
strobe
Output
Strobe signal indicating that the address
output on the address bus is valid when a
basic bus interface space or byte control
SRAM space is accessed
CSn
CSn
Chip select
Output
Strobe signal indicating that area n is
selected
RD
RD
Read strobe
Output
Output enable for the SRAM when the byte
control SRAM space is accessed
RD/WR
RD/WR
Read/write
Output
Write enable signal for the SRAM when the
byte control SRAM space is accessed
LHWR/LUB
LUB
Lower-upper
byte select
Output
Upper byte select when the 16-bit byte
control SRAM space is accessed
LLWR/LLB
LLB
Lower-lower
byte select
Output
Lower byte select when the 16-bit byte
control SRAM space is accessed
WAIT
WAIT
Wait
Input
Wait request signal used when an external
address space is accessed
A23 to A0
A23 to A0
Address pin
Output
Address output pin
D15 to D0
D15 to D0
Data pin
Input/
output
Data input/output pin
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Section 9 Bus Controller (BSC)
9.7.4
(1)
Basic Timing
2-State Access Space
Figure 9.25 shows the bus timing when the byte control SRAM space is specified as a 2-state
access space.
Data buses used for 16-bit access space is the same as those in basic bus interface. No wait cycles
can be inserted.
T1
Bus cycle
T2
Bφ
Address
CSn
AS
LUB
LLB
RD/WR
Read
RD
D15 to D8
Valid
D7 to D0
Valid
RD/WR
Write
High level
RD
D15 to D8
Valid
D7 to D0
Valid
BS
DACK or EDACK*
Note: n = 0 to 7
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.25 16-Bit 2-State Access Space Bus Timing
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Section 9 Bus Controller (BSC)
(2)
3-State Access Space
Figure 9.26 shows the bus timing when the byte control SRAM space is specified as a 3-state
access space.
Data buses used for 16-bit access space is the same as those in the basic bus interface. Wait cycles
can be inserted.
T1
Bus cycle
T2
T3
Bφ
Address
CSn
AS
LUB
LLB
RD/WR
RD
Read
D15 to D8
Valid
D7 to D0
Valid
RD/WR
Write
RD
High level
D15 to D8
Valid
D7 to D0
Valid
BS
DACK or EDACK*
Note: n = 0 to 7
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.26 16-Bit 3-State Access Space Bus Timing
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Section 9 Bus Controller (BSC)
9.7.5
Wait Control
The bus cycle can be extended for the byte control SRAM interface by inserting wait cycles (Tw)
in the same way as the basic bus interface.
(1)
Program Wait Insertion
From 0 to 7 wait cycles can be inserted automatically between T2 cycle and T3 cycle for the 3state access space in area units, according to the settings in WTCRA and WTCRB.
(2)
Pin Wait Insertion
For 3-state access space, when the WAITE bit in BCR1 is set to 1, the corresponding DDR bit is
cleared to 0, and the ICR bit is set to 1, wait input by means of the WAIT pin is enabled. For
details on DDR and ICR, refer to section 13, I/O Ports.
Figure 9.27 shows an example of wait cycle insertion timing.
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Section 9 Bus Controller (BSC)
Wait by
program wait
T1
T2
Tpw
Wait by WAIT pin
Ttw
Ttw
T3
Bφ
WAIT
Address
CSn
AS
LUB, LLB
RD/WR
Read
RD
Data bus
Read data
RD/WR
Write
RD
High level
Data bus
Write data
BS
DACK or EDACK*
Notes: 1. Upward arrows indicate the timing of WAIT pin sampling.
2. n = 0 to 7
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.27 Example of Wait Cycle Insertion Timing
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Section 9 Bus Controller (BSC)
9.7.6
Read Strobe (RD)
When the byte control SRAM space is specified, the RDNCR setting for the corresponding space
is invalid.
The read strobe negation timing is the same timing as when RDNn = 1 in the basic bus interface.
Note that the RD timing with respect to the DACK and EDACK*rising edge becomes different.
9.7.7
Extension of Chip Select (CS) Assertion Period
In the byte control SRAM interface, the extension cycles can be inserted before and after the bus
cycle in the same way as the basic bus interface. For details, refer to section 9.6.6, Extension of
Chip Select (CS) Assertion Period.
9.7.8
DACK and EDACK* Signal Output Timing
For DMAC or EXDMAC* single address transfers, the DACK and EDACK*signal assert timing
can be modified by using the DKC and EDKC* bits in BCR1.
Figure 9.28 shows the DACK and EDACK* signal output timing. Setting the DKC bit or the
EDKC* bit to 1 asserts the DACK or EDACK* signal a half cycle earlier.
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Section 9 Bus Controller (BSC)
Bus cycle
T2
T1
Bφ
Address
CSn
AS
LUB
LLB
RD/WR
RD
Read
D15 to D8
Valid
D7 to D0
Valid
RD/WR
RD
High level
Write
D15 to D8
Valid
D7 to D0
Valid
BS
DACK or
EDACK*
DKC, EDKC* = 0
DKC, EDKC* = 1
Note:
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.28 Output Timing for DACK and EDACK*Signals
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.8
Burst ROM Interface
In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst
ROM interfacing performed. The burst ROM interface enables ROM with page access capability
to be accessed at high speed.
Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in
BROMCR. Consecutive burst accesses of up to 32 words can be performed, according to the
setting of bits BSWDn1 and BSWDn0 (n = 0, 1) in BROMCR. From one to eight cycles can be
selected for burst access.
Settings can be made independently for area 0 and area 1.
In the burst ROM interface, the burst access covers only read accesses by the CPU and EXDMAC
cluster transfer. Other accesses are performed with the similar method to the basic bus interface.
9.8.1
Burst ROM Space Setting
Burst ROM interface can be specified for areas 0 and 1. Areas 0 and 1 can be specified as burst
ROM space by setting bits BSRMn (n = 0, 1) in BROMCR.
9.8.2
Data Bus
The bus width of the burst ROM space can be specified as 8-bit or 16-bit burst ROM interface
space according to the ABWHn and ABWLn bits (n = 0, 1) in ABWCR.
For the 8-bit bus width, data bus (D7 to D0) is valid. For the 16-bit bus width, data bus (D15 to
D0) is valid.
Access size and data alignment are the same as the basic bus interface. For details, see section
9.5.6, Endian and Data Alignment.
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Section 9 Bus Controller (BSC)
9.8.3
I/O Pins Used for Burst ROM Interface
Table 9.17 shows the pins used for the burst ROM interface.
Table 9.17 I/O Pins Used for Burst ROM Interface
Name
Symbol
I/O
Function
Bus cycle start
BS
Output
Signal indicating that the bus cycle has
started.
Address strobe
AS
Output
Strobe signal indicating that an address output on
the address bus is valid during access
Read strobe
RD
Output
Strobe signal indicating the read access
Read/write
RD/WR
Output
Signal indicating the data bus input or output
direction
Low-high write
LHWR
Output
Strobe signal indicating that the upper byte (D15 to
D8) is valid during write access
Low-low write
LLWR
Output
Strobe signal indicating that the lower byte (D7 to
D0) is valid during write access
Output
Strobe signal indicating that the area is selected
Input
Wait request signal used when an external address
space is accessed
Chip select 0 and 1 CS0, CS1
Wait
WAIT
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Section 9 Bus Controller (BSC)
9.8.4
Basic Timing
The number of access cycles in the initial cycle (full access) on the burst ROM interface is
determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits
CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space is read by
the CPU or EXDMAC* cluster transfer, the settings in RDNCR and bits CSXTn in CSACR (n = 0
to 7) are ignored.
From one to eight cycles can be selected for the burst cycle, according to the settings of bits
BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait cycles cannot be inserted. In
addition, 4-word, 8-word, 16-word, or 32-word consecutive burst access can be performed
according to the settings of BSTS01, BSTS00, BSTS11, and BSTS10 bits in BROMCR.
The basic access timing for burst ROM space is shown in figures 9.29 and 9.30.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Burst access
Full access
T1
T2
T3
T1
T2
T1
T2
Bφ
Upper
address bus
Lower
address bus
CSn
AS
RD
Data bus
BS
RD/WR
Note: n = 1, 0
Figure 9.29 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)
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Section 9 Bus Controller (BSC)
Burst access
Full access
T1
T2
T1
T1
Bφ
Upper address bus
Lower address bus
CSn
AS
RD
Data bus
BS
RD/WR
Note: n = 1, 0
Figure 9.30 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle)
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Section 9 Bus Controller (BSC)
9.8.5
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion by the WAIT
pin can be used in the initial cycle (full access) on the burst ROM interface. See section 9.6.4,
Wait Control. Wait cycles cannot be inserted in a burst cycle.
9.8.6
Read Strobe (RD) Timing
When the burst ROM space is read by the CPU or EXDMAC* cluster transfer, the RDNCR
setting for the corresponding space is invalid.
The read strobe negation timing is the same timing as when RDNn = 0 in the basic bus interface.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
9.8.7
Extension of Chip Select (CS) Assertion Period
In the burst ROM interface, the extension cycles can be inserted in the same way as the basic bus
interface.
For the burst ROM space, the burst access can be enabled only in read access by the CPU or
EXDMAC* cluster transfer. In this case, the setting of the corresponding CSXTn bit in CSACR is
ignored and an extension cycle can be inserted only before the full access cycle. Note that no
extension cycle can be inserted before or after the burst access cycles.
In accesses other than read accesses by the CPU and EXDMAC* cluster transfer, the burst ROM
space is equivalent to the basic bus interface space. Accordingly, extension cycles can be inserted
before and after the burst access cycles.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.9
Address/Data Multiplexed I/O Interface
If areas 3 to 7 of external address space are specified as address/data multiplexed I/O space in this
LSI, the address/data multiplexed I/O interface can be performed. In the address/data multiplexed
I/O interface, peripheral LSIs that require the multiplexed address/data can be connected directly
to this LSI.
9.9.1
Address/Data Multiplexed I/O Space Setting
Address/data multiplexed I/O interface can be specified for areas 3 to 7. Each area can be
specified as the address/data multiplexed I/O space by setting bits MPXEn (n = 3 to 7) in
MPXCR.
9.9.2
Address/Data Multiplex
In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 9.18
shows the relationship between the bus width and address output.
Table 9.18 Address/Data Multiplex
Data Pins
Bus Width
8 bits
16 bits
9.9.3
Cycle
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
Address
-
-
-
-
-
-
-
-
A7
A6
A5
A4
A3
A2
A1
A0
Data
-
-
-
-
-
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
Address
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Data
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data Bus
The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access
space or 16-bit access space by the ABWHn and ABWLn bits (n = 3 to 7) in ABWCR.
For the 8-bit access space, D7 to D0 are valid for both address and data. For 16-bit access space,
D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is
accessed, the corresponding address will be output to the address bus.
For details on access size and data alignment, see section 9.5.6, Endian and Data Alignment.
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Section 9 Bus Controller (BSC)
9.9.4
I/O Pins Used for Address/Data Multiplexed I/O Interface
Table 9.19 shows the pins used for the address/data multiplexed I/O Interface.
Table 9.19 I/O Pins for Address/Data Multiplexed I/O Interface
Pin
When Byte
Control
SRAM is
Specified
Name
I/O
Function
CSn
CSn
Chip select
Output
Chip select (n = 3 to 7) when area n is specified as the
address/data multiplexed I/O space
AS/AH
AH*
Address hold
Output
Signal to hold an address when the address/data
multiplexed I/O space is specified
RD
RD
Read strobe
Output
Signal indicating that the address/data multiplexed I/O
space is being read
LHWR/LUB
LHWR
Low-high write Output
Strobe signal indicating that the upper byte (D15 to
D8) is valid when the address/data multiplexed I/O
space is written
LLWR/LLB
LLWR
Low-low write
Output
Strobe signal indicating that the lower byte (D7 to D0)
is valid when the address/data multiplexed I/O space is
written
D15 to D0
D15 to D0
Address/data
Input/
output
Address and data multiplexed pins for the
address/data multiplexed I/O space.
Only D7 to D0 are valid when the 8-bit space is
specified. D15 to D0 are valid when the 16-bit space is
specified.
A23 to A0
A23 to A0
Address
Output
Address output pin
WAIT
WAIT
Wait
Input
Wait request signal used when the external address
space is accessed
BS
BS
Bus cycle start Output
Signal to indicate the bus cycle start
RD/WR
RD/WR
Read/write
Signal indicating the data bus input or output direction
Note:
*
Output
The AH output is multiplexed with the AS output. At the timing that an area is specified
as address/data multiplexed I/O, this pin starts to function as the AH output meaning
that this pin cannot be used as the AS output. At this time, when other areas set to the
basic bus interface is accessed, this pin does not function as the AS output. Until an
area is specified as address/data multiplexed I/O, be aware that this pin functions as
the AS output.
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Section 9 Bus Controller (BSC)
9.9.5
Basic Timing
The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data
cycle. The data cycle is based on the basic bus interface timing specified by the ABWCR,
ASTCR, WTCRA, WTCRB, RDNCR, and CSACR.
Figures 9.31 and 9.32 show the basic access timings.
Data cycle
Address cycle
Tma1
Tma2
T1
T2
Bφ
Address bus
CSn
AH
RD
Read
D7 to D0
Address
Read data
LLWR
Write
D7 to D0
Address
Write data
BS
RD/WR
DACK or EDACK*
Notes: n = 3 to 7
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.31 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1)
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Section 9 Bus Controller (BSC)
Bus cycle
Data cycle
Address cycle
Tma1
Tma2
T1
T2
Bφ
Address bus
CSn
AH
RD
Read
D15 to D0
Address
Read data
LHWR
LLWR
Write
D15 to D0
Address
Write data
BS
RD/WR
DACK or EDACK*
Note: n = 3 to 7
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.32 16-Bit Access Space Access Timing (ABWHn = 0, ABWLn = 1)
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Section 9 Bus Controller (BSC)
9.9.6
Address Cycle Control
An extension cycle (Tmaw) can be inserted between Tma1 and Tma2 cycles to extend the AH
signal output period by setting the ADDEX bit in MPXCR. By inserting the Tmaw cycle, the
address setup for AH and the AH minimum pulse width can be assured.
Figure 9.33 shows the access timing when the address cycle is three cycles.
Data cycle
Address cycle
Tma1
Tmaw
Tma2
T1
T2
Bφ
Address bus
CSn
AH
RD
Read
D15 to D0
Address
Read data
LHWR
Write
LLWR
D15 to D0
Address
Write data
BS
RD/WR
DACK or EDACK*
Note: n = 3 to 7
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.33 Access Timing of 3 Address Cycles (ADDEX = 1)
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Section 9 Bus Controller (BSC)
9.9.7
Wait Control
In the data cycle of the address/data multiplexed I/O interface, program wait insertion and pin wait
insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details,
refer to section 9.6.4, Wait Control.
Wait control settings do not affect the address cycles.
9.9.8
Read Strobe (RD) Timing
In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified
in the same way as in basic bus interface. For details, refer to section 9.6.5, Read Strobe (RD)
Timing.
Figure 9.34 shows an example when the read strobe timing is modified.
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Section 9 Bus Controller (BSC)
Data cycle
Address cycle
Tma1
Tma2
T1
T2
Bφ
Address bus
CSn
AH
RD
RDNn = 0
D15 to D0
Address
Read data
RD
RDNn = 1
D15 to D0
Read
data
Address
BS
RD/WR
DACK or EDACK*
Note: n = 3 to 7
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.34 Read Strobe Timing
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Section 9 Bus Controller (BSC)
9.9.9
Extension of Chip Select (CS) Assertion Period
In the address/data multiplexed interface, the extension cycles can be inserted before and after the
bus cycle. For details, see section 9.6.6, Extension of Chip Select (CS) Assertion Period.
Figure 9.35 shows an example of the chip select (CS) assertion period extension timing.
Bus cycle
Data cycle
Address cycle
Tma1
Tma2
Th
T1
T2
Tt
Bφ
Address bus
CSn
AH
RD
Read
D15 to D0
Address
Read data
LHWR
Write
LLWR
D15 to D0
Address
Write data
BS
RD/WR
DACK or EDACK*
Note: n = 3 to 7
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.35 Chip Select (CS) Assertion Period Extension Timing in Data Cycle
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Section 9 Bus Controller (BSC)
When consecutively reading from the same area connected to a peripheral LSI whose data hold
time is long, data outputs from the peripheral LSI and this LSI may conflict. Inserting the chip
select assertion period extension cycle after the access cycle can avoid the data conflict.
Figure 9.36 shows an example of the operation. In the figure, both bus cycles A and B are read
access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown
in (a), and an example of avoiding the data conflict by the CS assertion period extension cycle in
(b).
Bus cycle A
Bus cycle B
Bφ
Address bus
CS
AH
RD
Data bus
Data hold time is long.
Data conflict
(a) Without CS assertion period extension cycle (CSXTn = 0)
Bus cycle A
Bus cycle B
Bφ
Address bus
CS
AH
RD
Data bus
(b) With CS assertion period extension cycle (CSXTn = 1)
Figure 9.36 Consecutive Read Accesses to Same Area
(Address/Data Multiplexed I/O Space)
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Section 9 Bus Controller (BSC)
9.9.10
DACK and EDACK* Signal Output Timing
For DMAC or EXDMAC* single address transfers, the DACK and EDACK* signal assert timing
can be modified by using bits DKC and EDKC* in BCR1.
Figure 9.37 shows the DACK and EDACK* signal output timing. Setting the DKC bit or the
EDKC* bit to 1 asserts the DACK or EDACK* signal a half cycle earlier.
Address cycle
Tma1
Tma2
Data cycle
T1
T2
Bφ
Address bus
CSn
AH
RD
RDNn = 0
D15 to D0
Address
Read data
RD
RDNn = 1
D15 to D0
Address
Read
data
BS
RD/WR
DKC, EDKC* = 0
DACK or
EDACK*
DKC, EDKC* = 1
Note: n = 3 to 7
* Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Figure 9.37 Output Timing for DACK and EDACK* Signals
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.10
DRAM Interface
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
In this LSI, area 2 in the external space can be used as the DRAM interface space. Up to 8 Mbytes
of DRAM is directly connected via the DRAM interface.
9.10.1
Setting DRAM Space
Area 2 can be specified as the DRAM space by the DRAME and DTYPE bits in DRAMCR.
Table 9.20 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces.
The bus settings of the DRAM space such as bus width and wait cycle number depend on area 2
settings.
Table 9.20 Relationship Among DRAME and DTYPE and Area 2 Interfaces
DRAME
DTYPE
Area 2 Interface
0
×
Basic bus space (initial state)/byte-control SRAM space
1
0
DRAM space
1
1
SDRAM space
[Legend]
×: Don't care
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Section 9 Bus Controller (BSC)
9.10.2
Address Multiplexing
A Row address and a column address are multiplexed in the DRAM space. Select the number of
row address bits to be shifted with bits MXC1 and MXC0 in DRAMCR. Table 9.21 lists the
relationship among bits MXC1 and MXC0 and shifted bit number.
Table 9.21 Relationship Among MXC1 and MXC0 and Shifted Bit Count
DRAMCR
Shit Bit
MXC1 MXC0 Count
External Address Pin
Data Bus
Width
Address
A27 to A18
A17 A16 A15 A14 A13 A12 A11 A10
Row address
A23 to A18
A17
0
0
8 bits
8/16 bits
0
1
9 bits
8/16 bits
1
0
10 bits
8/16 bits
1
1
11 bits
8/16 bits
A2
A1
A0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A9
A8
Column address A23 to A18
A17 A16 A15 A14 A13 A12 A11 A10
Row address
A17
A23 to A18
Column address A23 to A18
Row address
A23 to A18
-
-
-
-
A17 A16 A15 A14 A13 A12 A11 A10
A17
-
-
-
A7
A6
A5
A6
A5
A4
A5
A4
A3
A4
A3
A3
A2
A2
A1
A0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
Row address
A23 to A18
A8
A7
A6
A0
A9
A8
A7
A9
-
A9
A8
A1
A17 A16 A15 A14 A13 A12 A11 A10
A17
A9
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
Column address A23 to A18
Column address A23 to A18
9.10.3
-
-
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
A17 A16 A15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Data Bus
The data bus width of the DRAM space can be selected from 8 and 16 bits by bits ABWH2 and
ABWL2 in ABWCR. DRAM with 16-bit words can be connected directly to 16-bit bus width
space.
D7 to D0 are valid in 8-bit DRAM space, and D15 to D0 are valid in 16-bit DRAM space.
The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size
and alignment, see section 9.5.6, Endian and Data Alignment.
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Section 9 Bus Controller (BSC)
9.10.4
I/O Pins Used for DRAM Interface
Table 9.22 shows the pins used for the DRAM interface.
Table 9.22 I/O Pins for DRAM Interface
Pin
DRAM
Selected
Name
I/O
Function
WE
WE
Write enable
Output
Write enable signal for accessing the
DRAM interface
RAS
RAS
Row address
strobe
Output
Row address strobe when the DRAM
space is specified as area 2
LUCAS/
DQMLU
LUCAS
Lower-upper
Output
column address
strobe
LLCAS/
DQMLL
LLCAS
Lower-lower
Output
column address
strobe
•
Lower-upper column address strobe
when the 32-bit DRAM space is
accessed
•
Upper column address strobe when the
16-bit DRAM space is accessed
•
Lower-lower column address strobe
when the 32-bit DRAM space is
accessed
•
Lower column address strobe when the
16-bit DRAM space is accessed
OE
OE
Output enable
Output
Output enable signal when the DRAM
space is accessed
WAIT
WAIT
Wait
Input
Wait request signal used when an external
address space is accessed
A17 to A0
A17 to A0
Address pin
Output
Multiplexed address/data output pin
D15 to D0
D15 to D0
Data pin
Input/
output
Data input/output pin
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Section 9 Bus Controller (BSC)
9.10.5
Basic Timing
Figure 9.38 shows a basic access timing of the DRAM space.
A basic bus cycle consists of four clock cycles: one precharge cycle (Tp), one row address output
cycle (Tr), and two column address output cycles (Tc1 and Tc2).
The RD signal is output to DRAM as an OE signal on a DRAM access. When DRAM with the
EDO page mode function is in use, connect the OE signal to the OE pin of the DRAM.
Tp
Tr
Tc1
Tc2
Bφ
Address bus
Row address
Column address
RAS
LUCAS
LLCAS
WE
Read
High
OE (RD)
Data bus
WE
Write
OE (RD)
High
Data bus
BS
RD/WR
Figure 9.38 DRAM Basic Access Timing (RAS = 0 and CAST = 0)
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Section 9 Bus Controller (BSC)
9.10.6
Controlling Column Address Output Cycle
The number of column address output cycles can be changed from two to three clock cycles by
setting the CAST bit in DRAMCR. Set the bit according to the DRAM to be used and the
frequency of this LSI so that the CAS pulse width can be optimal.
Figure 9.39 shows a timing example when the number of column address output cycles is set to
three clock cycles.
Tp
Tr
Tc1
Tc2
Tc3
Bφ
Address bus
Row address
Column address
RAS
LUCAS
LLCAS
WE
Read
High
OE (RD)
Data bus
WE
Write
OE (RD)
High
Data bus
BS
RD/WR
Figure 9.39 Access Timing Example of Column Address Output Cycles for 3 Clock Cycles
(RAST = 0)
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Section 9 Bus Controller (BSC)
9.10.7
Controlling Row Address Output Cycle
The RAS signal is driven low at the start of the Tr cycle by setting the RAST bit to 1. The row
address hold time to the falling edge of the RAS signal and the DRAM read access time are
changed. Set the bit according to the DRAM to be used and the frequency of this LSI so that
required performance can be obtained.
Figure 9.40 shows a timing example when the RAS signal is driven low at the start of the Tr cycle.
Tp
Tr
Tc1
Tc2
Bφ
Address bus
Row address
Column address
RAS
LUCAS
LLCAS
WE
Read
High
OE (RD)
Data bus
WE
Write
OE (RD)
High
Data bus
BS
RD/WR
Figure 9.40 Access Timing Example of RAS Signal Driven Low at Start of Tr Cycle
(CAST = 0)
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Section 9 Bus Controller (BSC)
To ensure the row address hold time or read access time, one to three of Trw cycles in which the
row address output is retained can be inserted between the Tr and Tc1 cycles. The RAS signal is
driven low in the Tr cycle and the column address is output in the Tc1 cycle. Set the bit according
to the DRAM to be used and the frequency of this LSI so that the row address hold time to the
rising edge of the RAS signal is ensured.
Figure 9.41 shows an access timing example when one Trw cycle is specified.
Tp
Tr
Trw
Tc1
Tc2
Bφ
Address bus
Row address
Column address
RAS
LUCAS
LLCAS
WE
Read
High
OE (RD)
Data bus
WE
Write
OE (RD)
High
Data bus
BS
RD/WR
Figure 9.41 Access Timing Example when One Trw Cycle is Specified (RAST=0, CAST=0)
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Section 9 Bus Controller (BSC)
9.10.8
Controlling Precharge Cycle
The number of precharge cycles (Tp) can be selected from one to four clock cycles by bits TPC1
and TPC0 in DRACCR. Set the bit according to the DRAM to be used and the frequency of this
LSI so that the number of precharge cycle can be optimal.
Figure 9.42 shows an access timing example when two Tp cycles are specified.
The setting of bits TPC1 and TPC0 affect the Tp cycle of a refresh cycle.
Tp1
Tp2
Tr
Tc1
Tc2
Bφ
Address bus
Row address
Column address
RAS
LUCAS
LLCAS
WE
Read
High
OE (RD)
Data bus
WE
Write
OE (RD)
High
Data bus
BS
RD/WR
Figure 9.42 Access Timing Example of Two Precharge Cycles (RAST = 0 and CAST = 0)
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Section 9 Bus Controller (BSC)
9.10.9
Wait Control
There are two methods of inserting wait cycles during a DRAM access cycle: program wait
insertion and pin wait insertion using the WAIT pin.
Wait cycles are inserted to extend the CAS assertion period during a DRAM read cycle and to
ensure the write data setup time to the falling edge of the CAS signal during a DRAM write cycle.
(1)
Program Wait Insertion
When bit AST2 in ASTCR is set to 1, zero to seven of wait cycles can automatically be inserted
between the Tc1 and Tc2 cycles. The number of wait cycles is selected by bits W22 to W20 in
WTCRB.
(2)
Pin Wait Insertion
When the WAITE bit in BCR1 is set to 1, and the AST2 bit in ASTCR is set to 1, setting the ICR
bit for the corresponding pin to 1 enables wait input by the WAIT pin. When the DRAM space is
accessed in this state, a program wait (Tpw) is first inserted. If the WAIT pin is low at the rising
edge of Bφ in the last Tc1 or Tpw cycle, another Ttw cycle is inserted until the WAIT pin is driven
high. For details on ICR, see section 13, I/O Ports.
Figure 9.43 shows an example of wait cycle insertion timing for 2-cycle column address output.
Figure 9.44 shows an example of wait cycle insertion timing for 3-cycle column address output.
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Wait by
program Wait by
wait WAIT pin
Tpw
Ttw
Tc2
Bφ
WAIT
Address bus
Row address
Column address
RAS
LUCAS, LLCAS
WE
Read
High
OE (RD)
Data bus
LUCAS, LLCAS
WE
Write
OE (RD)
High
Data bus
BS
RD/WR
Note:
Upward arrows indicate the timing of WAIT pin sampling.
Figure 9.43 Example of Wait Cycle Insertion Timing for 2-Cycle Column Address Output
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Wait by
program Wait by
wait WAIT pin
Tpw
Ttw
Tc2
Tc3
Bφ
WAIT
Address bus
Row address
Column address
RAS
LUCAS, LLCAS
WE
High
Read
OE (RD)
Data bus
LUCAS, LLCAS
WE
Write
OE (RD)
High
Data bus
BS
RD/WR
Note:
Upward arrows indicate the timing of WAIT pin sampling.
Figure 9.44 Example of Wait Cycle Insertion Timing for 3-Cycle Column Address Output
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Section 9 Bus Controller (BSC)
9.10.10 Controlling Byte and Word Accesses
When 16-bit bus DRAM is used, two CAS signals can be used to control byte and word accesses.
Figures 9.45 and 9.46 show control timing examples with use of two CAS signals (in big endian
format). Figure 9.47 shows an example of connection for control with two CAS signals.
Tp
Tr
Tc1
Tc2
Bφ
Address bus
Row address
Column address
RAS
LUCAS
LLCAS
WE
OE (RD)
High
D15 to D8
D7 to D0
BS
RD/WR
Figure 9.45 Timing Example of Byte Control with Use of Two CAS Signals
(Write Access with Lowest Bit of Address = B'0, RAST = 0, CAST = 0)
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
Bφ
Address bus
Row address
Column address
RAS
LUCAS
LLCAS
WE
High
OE (RD)
D15 to D8
D7 to D0
BS
RD/WR
Figure 9.46 Timing Example of Word Control with Use of Two CAS Signals
(Read Access with Lowest Bit of Address = B'0, RAST = 0, CAST = 0)
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Section 9 Bus Controller (BSC)
This LSI
(Address shifted by 11 bits)
RAS
LUCAS
LLCAS
WE
RD (OE)
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
D15 to D0
Two CAS signals used 64-Mbit DRAM
(4 Mwords × 16 bits)
11-bit column address
RAS
UCAS
LCAS
WE
OE
A10
A9 Row address input:
A10 to A0
A8 Column address input: A10 to A0
A7
A6
A5
A4
A3
A2
A1
A0
D15 to D0
Figure 9.47 Example of Connection for Control with Two CAS Signals
9.10.11 Burst Access Operation
Besides an accessing method in which this LSI outputs a row address every time it accesses the
DRAM (called full access or normal access), some DRAMs have a fast-page mode function in
which fast speed access can be achieved by modifying only a column address with the same row
address output (burst access) when consecutive accesses are made to the same row address.
The fast-page mode (burst access) can be specified when the BE bit in DRAMCR is set to one,
(1)
Burst Access (Fast-Page Mode) Operation Timing
Figures 9.48 and 9.49 show operation timing of the fast-page mode.
When access cycles to the DRAM space are continued and the row addresses of the consecutive
two cycles are the same, output cycles of the CAS and column address signals follow. The row
address bits to be compared are decided by bits MXC1 and MXC0 in DRAMCR.
Wait cycles can be inserted during a burst access. The method and timing of the wait insertion are
the same as that of full access mode. For details, see section 9.10.9, Wait Control.
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
Tc1
Tc2
Bφ
Address bus
Row address
Column address
Column address
RAS
LUCAS
LLCAS
WE
Read
OE (RD)
Data bus
WE
Write
OE (RD)
Data bus
BS
RD/WR
Figure 9.48 Operation Timing of Fast-Page Mode (RAST = 0, CAST = 0)
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
Tc3
Tc1
Tc2
Tc3
Bφ
Address bus
Row address
Column address
Column address
RAS
LUCAS
LLCAS
WE
Read
High
OE (RD)
Data bus
WE
Write
OE (RD)
High
Data bus
BS
RD/WR
Figure 9.49 Operation Timing of Fast-Page Mode (RAST = 0, CAST = 1)
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Section 9 Bus Controller (BSC)
(2)
RAS Down Mode and RAS Up Mode
Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other
spaces may be accessed. The RAS signal can be held low during other space accesses. The fastpage mode access can be resumed (burst access) when the same row address in the DRAM space
is accessed.
(a)
RAS Down Mode
Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode.
The RCDM bit is enabled only when the BE bit is set to 1.
The fast-page mode access (burst access) is resumed when the row addresses of the current cycle
and previous cycle are the same. While other spaces are accessed when the DRAM space access is
halted, the RAS signal must be low. Figure 9.50 shows a timing example of RAS down mode.
The RAS signal goes high under the following conditions.
•
•
•
•
•
When a refresh cycle is performed during RAS down mode
When a self-refresh is performed
When a transition to software standby mode is made
When the external bus requested by the BREQ signal is released
When either the RCDM or BE bit is cleared to 0
If a transition to the all-module clock-stop mode is made during RAS down mode, clocks are
stopped with the RAS signal driven low. To make a transition with the RAS signal driven high,
clear the RCDM bit to 0 before execution of the SLEEP instruction.
Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see
section 26, Clock Pulse Generator.
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Section 9 Bus Controller (BSC)
DRAM space read
Tp
Tr
Tc1
Basic bus space read DRAM space read
Tc2
Tc1
Tc2
Tc1
Tc2
Bφ
Address bus
Row address
Column address
External address
Column address
RAS
LUCAS
LLCAS
WE
High
OE
RD
Data bus
BS
RD/WR
Figure 9.50 Timing Example of RAS Down Mode (RAST = 0, CAST = 0)
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Section 9 Bus Controller (BSC)
(b)
RAS Up Mode
Set the BE bit in DRAMCR to 1 and clear the RCDM bit in DRAMCR to 0 to set the RAS up
mode.
Whenever a DRAM space access is halted and other spaces are accessed, the RAS signal is driven
high. Only when the DRAM space continues to be accessed, the fast-page mode access (burst
access) is performed.
Figure 9.51 shows a timing example of RAS up mode.
DRAM space read
Tp
Tr
Tc1
DRAM space read Basic bus space read
Tc2
Tc1
Tc2
T1
T2
Bφ
Address bus
Row address
Column address
Column address
External address
RAS
LUCAS
LLCAS
WE
High
RD
OE
Data bus
BS
RD/WR
Figure 9.51 Timing Example of RAS Up Mode (RAST = 0, CAST = 0)
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Section 9 Bus Controller (BSC)
9.10.12 Refresh Control
This LSI includes a DRAM refresh control function. The refresh method is the CAS before RAS
(CBR) refresh. Self-refresh cycles can be performed in software standby mode.
The refresh control function is enabled when area 2 is specified as the DRAM space by the
DRAME and DTYPE bits in DRAMCR.
(1)
CAS before RAS (CBR) Refresh Mode
Set the RFSHE bit in REFCR to 1 to select the CBR refresh mode.
A CBR refresh cycle is performed when the value set in RTCOR matches the RTCNT value
(compare match). RTCNT is an up-counter operated on the input clock specified by bits RTCK2
to RTCK0 in REFCR. RTCNT is initialized upon the compare match and restarts to count up with
H'00. Accordingly, a CBR refresh cycle is repeated at intervals specified by bits RTCK2 to
RTCK0 in RTCOR. Set the bits so that the required refresh intervals of the DRAM must be
satisfied.
Since setting bits RTCK2 to RTCK0 starts RTCNT to count up, set RTCNT and RTCOR before
setting bits RTCK2 to RTCK0. When changing RTCNT and RTCOR, the counting operation
should be halted. When changing bits RTCK2 to RTCK0, change them only after disabling
external access and bus release by the EXDMAC, and if the write data buffer function is in use,
disabling the write data buffer function and reading the external space.
The external space cannot be accessed in CBR refresh mode.
Figure 9.52 shows RTCNT operation, figure 9.53 shows compare match timing, and figure 9.54
shows CBR refresh timing. Table 9.23 lists the pin states during a CBR refresh cycle.
RTCNT
RTCOR
H'00
Refresh request
Figure 9.52 RTCNT Operation
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Section 9 Bus Controller (BSC)
Pφ
RTCNT
N
RTCOR
H'00
N
Refresh request
and CMF bit set signal
Figure 9.53 Compare Match Timing
TRp
TRr
TRc1
TRc2
Bφ
RAS
LUCAS
LLCAS
BS
RD/WR
High
High
Figure 9.54 CBR Refresh Timing
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Section 9 Bus Controller (BSC)
Table 9.23 Pin States during DRAM Refresh Cycle
Pin
State
A17 to A0
Hold the value of the previous bus cycle
D15 to D0
Hi-Z
RAS
Used for refresh control
LUCAS, LLCAS
Used for refresh control
WE
High
AS
High
RD
High
BS
High
RD/WR
High
The RAS signal can be delayed for one to three clock cycles by setting bits RCW1 and RCW0 in
REFCR. The pulse width of the RAS signal is changed by bits RLW2 to RLW0 in REFCR. The
settings of bits RCW1, RCW0, and RLW2 to RLW0 are effective only for a refresh cycle. The
precharge time set by bit TPC1 and TPC0 is effective for a refresh cycle.
Figure 5.55 shows a timing for setting bits RCW1 and RCW0
TRp
TRrw
TRr
TRc1
TRc2
Bφ
RAS
LUCAS
LLCAS
BS
High
RD/WR
High
Figure 9.55 CBR Refresh Timing
(RCW1 = 0, RCW0 = 1, RLW2 = 0, RLW1 = 0, RLW0 = 0)
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Section 9 Bus Controller (BSC)
(2)
Self-Refresh Mode
Some DRAMs have a self-refresh mode (battery backup mode). The self-refresh mode is a kind of
standby mode and refresh timing and refresh address are controlled internally.
The self-refresh mode is selected by setting the RFSHE and SLFRF bits in REFCR to 1. The CAS
and RAS signals are output as shown in figure 9.56 by executing the SLEEP instruction. Then,
DRAM enters self-refresh mode.
When a CBR refresh is requested on a transition to the standby mode, the CBR refresh is first
performed and then the self-refresh mode is entered.
When the self-refresh mode is used, do not clear the OPE bit in SBYCR to 0.
For details, see section 27.2.1, Standby Control Register (SBYCR).
TRp
Software
standby
TRr
TRc3
TRc4
Bφ
RAS
LUCAS
LLCAS
WE
High
BS
High
RD/WR
High
Figure 9.56 Self-Refresh Timing
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Section 9 Bus Controller (BSC)
Some DRAMs having the self-refresh mode needs longer precharge time of the RAS signal
immediately after the self-refresh mode than that in normal operation. From one to seven of
precharge cycles immediately after a self-refresh cycle can be inserted. Precharging is also
performed according to bits TPC1 and TPC0 in DRACCR. Set the precharge time so that the
precharge time immediately after a self-refresh cycle is optimal.
Figure 9.57 shows a timing example when one precharge cycle is added.
Software standby
DRAM space write
TRc3
TRc4
TRp1
Tp
Tr
Tc1
Tc2
Bφ
Address bus
RAS
LUCAS
LLCAS
RD
High
OE
WE
Data bus
BS
High
RD/WR
High
Figure 9.57 Timing Example when 1 Precharge Cycle Added
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Section 9 Bus Controller (BSC)
(3)
Refresh and All-Module Clock Stop Mode
This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of
all on-chip peripheral modules by setting the ACSE bit in MSTPCR to 1 (MSTPCRA, MSTPCRB
= H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), then
execute the SLEEP instruction to enter the sleep mode.
In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the
clock for the bus controller is stopped, a CBR refresh cycle cannot be performed. When external
DRAM is used and the contents of the DRAM in sleep mode should be held, clear the ACSE bit in
MSTPCE to 0.
For details, see section 27.2.2, Module Stop Control Registers A and B (MSTPCRA and
MSTPCRB).
9.10.13 DRAM Interface and Single Address Transfer by DMAC and EXDMAC
When fast-page mode (BE = 1) is set for the DRAM space, either fast-page access or full access
can be selected, by the setting of bits DDS and EDDS in DRAMCR, for the single address transfer
by the DMAC or EXDMAC where the DRAM space is specified as the transfer source or
destination. At the same time, the output timings of the DACK, EDACK and BS signals are
changed. When BE = 0, full access to the DRAM space is performed by single address transfer
regardless of the setting of bits DDS and EDDS. However, the output timing of the DACK,
EDACK and BS signals can be changed by the setting of bits DDS and EDDS.
The assertion timing of the DACK and EDACK signal can be changed by bits DKC and EDKC in
BCR1.
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Section 9 Bus Controller (BSC)
(1)
When DDS = 1 or EDDS = 1
A fast-page access is performed regardless of the bus master, only according to the address. The
DACK and EDACK signals are asserted at the start of the Tc1 cycle.
Figure 9.58 shows the output timing example of the DACK and EDACK signals when DDS = 1 or
EDDS = 1.
Tp
Tr
Tc1
Tc2
Bφ
Address bus
Row address
Column address
RAS
LUCAS
LLCAS
WE
Read
High
OE (RD)
Data bus
WE
Write
OE (RD)
High
Data bus
DACK or
EDACK
DKC, EDKC = 0
DKC, EDKC = 1
BS
RD/WR
Figure 9.58 Output Timing Example of DACK and EDACK when DDS = 1 or EDDS = 1
(RAST = 0, CAST = 0)
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Section 9 Bus Controller (BSC)
(2)
When DDS = 0 or EDDS = 0
Single address transfer by the DMAC or EXDMAC takes place as a full access (normal access).
The DACK and EDACK signals are asserted within the Tr cycle and the BS signal is also asserted
during the Tr cycle.
When the DRAM space is accessed with other than the single address transfer by the DMAC or
EXDMAC, a fast-page access is available.
Figure 9.59 shows an output timing example of the DACK and EDACK signals when DDS = 0 or
EDDS = 0.
Tp
Tr
Tc1
Tc2
Tc3
Bφ
Address bus
Row address
Column address
RAS
LUCAS
LLCAS
WE
Read
High
OE (RD)
Data bus
WE
Write
OE (RD)
High
Data bus
DACK or
EDACK
DKC, EDKC = 0
DKC, EDKC = 1
BS
RD/WR
Figure 9.59 Output Timing Example of DACK and EDACK when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1)
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Section 9 Bus Controller (BSC)
9.11
Synchronous DRAM Interface
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
In this LSI, area 2 in the external space can be used as the SDRAM interface space. Up to 8
Mbytes (64 Mbits) of DRAM is directly connected via the SDRAM interface. The CAS latency
with 2 to 4 is supported.
9.11.1
Setting SDRAM space
Area 2 can be specified as the SDRAM space by the DRAME and DTYPE bits in DRAMCR.
Table 9.24 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces.
In the SDRAM space, pins PB2, PB3, and PB4 are used as the RAS, CAS, and WE signals. The
PB1 pin is used as the CS2 signal by the PFCR setting, and the PB5 pin is used as the CKE signal
by setting the OEE bit in DRAMCR to 1. The bus settings of the SDRAM space depend on area 2
settings. The pin wait and program wait for the SDRAM space are not available. For PFCR, see
section 13, I/O Ports.
An SDRAM command is designated by the combination of the RAS, CAS, and WE signals and
the precharge-sel command (Precharge-sel) output on the upper column address.
This LSI supports the following commands: the NOP, auto-refresh (REF), self-refresh (SELF), allbank-precharge (PALL), bank active (ACTV), read (READ), write (WRIT), and mode register
setting (MRS). Commands controlling a bank are not supported.
Table 9.24 Relationship among DRAME and DTYPE and Area 2 Interfaces
DRAME
DTYPE
Area 2 Interface
0
X
Basic bus space (initial state)/byte-control SRAM space
1
0
DRAM space
1
1
SDRAM space
[Legend]
X: Don't care
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Section 9 Bus Controller (BSC)
9.11.2
Address Multiplexing
A Row address and a column address are multiplexed in the SDRAM space. Select the number of
row address bits to be shifted with bits MXC1 and MXC0 in DRAMCR. The precharge set
command (Precharge-sel) is output on the upper column address. Table 9.25 lists the relationship
among bits MXC1 and MXC0 and shifted bit number.
Table 9.25 Relationship Among MXC1 and MXC0 and Shifted Bit Count
DRAMCR Shift Bit Data Bus
Address
MXC1 MXC0 Count Width
0
0
0
1
8 bits
9 bits
8 bits
Row address
External Address Pin
A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10
A2
A1
A0
A23 to A18
-
-
A23 A22 A21 A20 A19 P/A18* A17 A16 A15 A14 A13 A12 A11 A10
A9
A8
1
A5
A4
A3
-
-
A23 A22 A21 A20 A19
A2
A1
A0
A23 to A18
-
-
A23 A22 A21 A20 P/A19* A18 A17 A16 A15 A14 A13 A12 A11 A10
A9
A8
Column address A23 to A18
-
-
A23 A22 A21 A20
8 bits
Row address
10 bits 8 bits
11 bits 8 bits
16 bits
Note:
A6
Row address
16 bits
1
A7
Column address A23 to A18
A10
A9
A9
-
-
A23 A22 A21 A20
A1
A0
Row address
-
-
A23 A22 A21 P/A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A9
A23 A22 A21
A0
A5
A4
A3
Column address A23 to A18 A17
A6
A5
A4
A0
A7
A6
A5
A1
A8
A7
A6
A23 A22 A21 A20 P/A19* A18 A17 A16 A15 A14 A13 A12 A11 A10
A9
A8
A7
-
P
A9
A8
-
A23 to A18 A17
P
P
A23 to A18 A17
A4
A3
A3
A2
A2
-
-
A23 to A18
-
-
-
-
A23 A22 A21 P/A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
Column address A23 to A18
-
-
-
-
A23 A22 A21
Row address
A23 to A18
-
-
-
-
A23 A22 P/A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
Column address A23 to A18
-
A23 A22
Column address A23 to A18 A17
0
A8
16 bits
16 bits
1
A9
Row address
P
A10
P
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
-
-
-
A23 to A18 A17
-
-
-
-
A23 A22 P/A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Column address A23 to A18 A17
-
-
-
-
A23 A10
Row address
A23 to A18 A17
-
-
-
-
A23 P/A22* A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Column address A23 to A18 A17
-
-
-
-
A11
Row address
P
P
A10
P
A10
A9
A9
A9
A8
A8
A8
A7
A7
A7
A6
A6
A6
A5
A5
A5
A4
A4
A4
A3
A3
A3
A2
A2
A2
A1
A1
A1
A0
A0
A0
* When issuing the PALL command, precharge-sel = 1 is output and when issuing the ACTIV command, a corresponding address is output.
9.11.3
Data Bus
Either 8 or 16 bits can be selected as the data bus width of the SDRAM space by bits ABWH2 and
ABWL2 in ABWCR. SDRAM with 16-bit words can be connected directly to 16-bit bus width
space.
D7 to D0 are valid in 8-bit SDRAM space and D15 to D0 are valid in 16-bit SDRAM space.
The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size
and alignment, see section 9.5.6, Endian and Data Alignment.
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Section 9 Bus Controller (BSC)
9.11.4
I/O Pins Used for DRAM Interface
Table 9.26 shows the pins used for the SDRAM interface.
Since a CS pin functions as an input after a reset, set the bit in PFCR to 1 to output the CS signal.
For details, see section 13, I/O Ports.
To enable the SDRAM interface, select the appropriate MCU operating mode. For details, see
section 3, MCU Operating Modes.
Table 9.26 I/O Pins for SDRAM Interface
Pin
DRAM
Selected
RAS
Name
I/O
Function
RAS
Row address
strobe
Output
Row address strobe when the SDRAM
space is specified as area 2
CAS
CAS
Column address
strobe
Output
Column address strobe when the
SDRAM space is specified as area 2
WE
WE
Write enable
Output
Write enable signal for accessing the
SDRAM interface
OE/CKE
CKE
Clock enable
Output
Clock enable signal when the SDRAM
space is specified as area 2.
LLCAS/
DQMLU
DQMLU
Lower-upper data
mask enable
Output
Upper data mask enable when the 16bit SDRAM space is accessed
LLCAS/
DQMLL
DQMLL
Lower-lower data
mask enable
Output
•
Lower data mask enable when the
16-bit SDRAM space is accessed
•
Data mask enable when the 8-bit
SDRAM is accessed
A17 to A0
A17 to A0
Address pin
Output
Multiplexed row/column-address output
pin
D15 to D0
D15 to D0
Data pin
Input/
output
Data input/output pin
PB7
SDRAMφ
Clock
Output
SDRAM clock
CS2
CS
Chip select
Output
Strobe signal indicating that SDRAM is
selected
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Section 9 Bus Controller (BSC)
9.11.5
Basic Timing
Figures 9.60 and 9.61 show a basic access timing of the SDRAM space.
A basic read cycle consists of five clock cycles: one precharge cycle (Tp), one row address output
cycle (Tr), and three column address output cycles (Tc1, Tcl, and Tc2).
A basic write cycle consists of four clock cycles: one precharge cycle (Tp), one row address
output cycle (Tr), and two column address output cycles (Tc1 and Tc2).
When the SDRAM space is selected, the WAITE bit in BCR, the RAST and CAST bits in
DRAMCR, bits RCW1 and RCW0 in REFCR are ignored.
Tp
Tr
Tc1
Tcl
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
READ
NOP
Figure 9.60 SDRAM Basic Read Access Timing (CAS Latency = 2)
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
CKE
High
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
NOP
WRIT
Figure 9.61 SDRAM Basic Write Access Timing
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Section 9 Bus Controller (BSC)
9.11.6
CAS Latency Control
The CAS latency is controlled by bits W21 and W20 in WTCRB. Table 9.27 lists the setting and
CAS latency. CAS latency control cycles (Tcl) are inserted in a read cycle according to the W21
and W20 settings. WTCRB can be specified regardless of bit AST2 in ASTCR.
Figure 9.62 shows a timing example when SDRAM with a CAS latency of 3 is in use.
Bits W21 and W20 is initialized to B'11.
Table 9.27 CAS Latency Setting
W21
0
1
W20
Description
Number of CAS
Latency Cycles
0
Setting prohibited

1
SDRAM with CAS latency of 2 is in use
1
0
SDRAM with CAS latency of 3 is in use
2
1
SDRAM with CAS latency of 4 is in use
3
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl1
Tcl2
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
CKE
High
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
READ
NOP
Figure 9.62 Timing Example of CAS Latency (CAS Latency = 3)
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Section 9 Bus Controller (BSC)
9.11.7
Controlling Row Address Output Cycle
When the time between the ACTV command and the subsequent READ or WRIT command does
not meet a given specification, the Trw cycle in which the NOP command is output can be
inserted for one to three cycles between the Tr cycle in which the ACTV command is output and
the Tc1 cycle in which the column address is output. Set the bit according to the SDRAM to be
used and the frequency of this LSI so that the number of wait cycles can be optimal.
Figures 9.63 and 9.64 show a timing example when the one Trw cycle is inserted.
Tp
Tr
Trw
Tc1
Tcl
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
NOP
READ
NOP
Figure 9.63 Read Timing Example of Row Address Output Retained for 1 Clock Cycle
(RCD1 = 0, RCD0 = 1, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
Tp
Tr
Trw
Tc1
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
CKE
High
DQMUU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
NOP
NOP
WRIT
Figure 9.64 Write Timing Example of Row Address Output Retained for 1 Clock Cycle
(RCD1 = 0, RCD0 = 1)
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Section 9 Bus Controller (BSC)
9.11.8
Controlling Precharge Cycle
When the time between the PALL or PRE command and the subsequent ACTV or REF command
does not meet a given specification, the Tp cycles can be extended by one to four cycles by bits
TPC1 and TPC0 in DRACCR. Set the bit according to the SDRAM to be used and the frequency
of this LSI so that the number of Tp cycles can be optimal.
Figures 9.65 and 9.66 show a timing example when the two Tp cycles are inserted.
Bits TPC1 and TPC0 are effective for the Tp cycle in a refresh cycle.
Tp1
Tp2
Tr
Tc1
Tcl
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
NOP
ACTV
READ
NOP
Figure 9.65 Read Timing Example of Two Precharge Cycles
(TPC1 = 0, TPC0 = 1, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
Tp1
Tp2
Tr
Tc1
Tc2
SDRAMφ
Address bus
Row address
Precharge-sel
Column address
Row address
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
NOP
ACTV
NOP
WRIT
Figure 9.66 Write Timing Example of Two Precharge Cycles (TPC1 = 0, TPC0 = 1)
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Section 9 Bus Controller (BSC)
9.11.9
Controlling Clock Suspend Insertion
When the SDRAM space is read, the read data settling cycle can be inserted for one cycle using
the clock suspend mode. To enter the clock suspend mode, set the CKSPE bit in SDCR and the
OEE bit in DRAMCR to 1and enable the CKE pin.
Figure 9.67 shows a read timing example when CKSPE = 1.
Tp
Tr
Tc1
Tcl
Tsp
Tc2
Tc1
Tcl
Tsp
Tc2
SDRAMφ
Address bus
Column address 1
Row address
Column address 2
Row
address
Precharge-sel
CS
RAS
CAS
WE
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
READ
NOP
READ
NOP
Figure 9.67 Read Timing Example when CKSPE = 1 (CAS Latency = 2)
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Section 9 Bus Controller (BSC)
9.11.10 Controlling Write-Precharge Delay
In an SDRAM write cycle, a certain time is required until the write operation is completed inside
of the SDRAM. When the time between the WRIT command and the subsequent PALL command
does not meet a given specification, the Trwl cycle can be inserted for one cycle by the TRWL bit
in SDCR. Whether or not to insert the Trwl cycle depends on the SDRAM to be used and the
frequency of this LSI.
Figure 9.68 shows a timing example when one Trwl cycle is inserted.
Tp
Tr
Tc1
Tc2
Trwl
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
NOP
WRIT
NOP
Figure 9.68 Write Timing Example when Write-Precharge Delay Cycle Insertion
(TRWL = 1)
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Section 9 Bus Controller (BSC)
9.11.11 Controlling Byte and Word Accesses
When 16-bit bus SDRAM is used, byte and word accesses are performed through the control of
DQMLU and DQMLL.
Figures 9.69 and 9.70 show control timing examples of the DQM signals in the big endian format.
Figure 9.71 shows a connection example when the DQM signals are used for the byte and word
control.
Tp
Tr
Tc1
Tcl
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
CKE
High
DQMLU
DQMLL
High
D15 to D8
D7 to D0
Hi-Z
BS
RD/WR
PALL
ACTV
READ
NOP
Figure 9.69 Control Timing Example of Byte Control by DQM in 16-Bit Access Space
(Read Access with Lowest Bit of Address = B'0)
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
CKE
High
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
READ
NOP
Figure 9.70 Control Timing Example of Word Control by DQM in 16-Bit Access Space
(Read Access with Lowest Bit of Address = B'0, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
64-Mbit synchronous DRAM
(1 Mwords × 16 bits × 4 banks)
10-bit column address
This LSI
(Address shifted by 8 bis)
RAS
CAS
WE
DQMLU
DQMLL
SDφ
RAS
CAS
WE
DQMU
DQML
CLK
OE/CKE
CKE
CS
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
D15 to D0
CS
Row address:
Column address:
Bank select address:
A11 to A0
A9 to A0
A11/A10
A11 (BA1)
A10 (BA0)
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ15 to DQ0
Figure 9.71 Connection Example of DQM Byte/Word Control
9.11.12 Fast-Page Access Operation
Besides an accessing method in which this LSI outputs a row address every time it accesses the
SDRAM (called full access or normal access), some SDRAMs have a fast-page mode function in
which fast speed access can be achieved by modifying only a column address with the same row
address output when consecutive accesses are made to the same row address.
The fast-page mode can be used by setting the BE bit in DRAMCR to 1.
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Section 9 Bus Controller (BSC)
(1)
Fast-Page Mode Operation Timing
When access cycles to the SDRAM space are continued and the row addresses of the consecutive
two cycles are the same, a column address output cycle follows. The row address bits to be
compared are decided by bits MXC1 and MXC0 in DRAMCR.
A fast-page mode access is performed when the access data size exceeds the bus width of the
SDRAM and when consecutive accesses to the SDRAM are generated.
Figures 9.72 and 9.73 show longword access timing of the 16-bit bus SDRAM and word access
timing of the 8-bit bus SDRAM, respectively.
Tp
Tr
Tc1
Tc2
Tc1
Tc2
SDRAMφ
Address bus
Row address
Column address 1
Column address 2
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
NOP
WRIT
NOP
WRIT
Figure 9.72 Longword Write Timing in 16-Bit Access Space (BE = 1, RCDM = 0)
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl
Tc2
Tc1
Tcl
Tc2
SDRAMφ
Address bus
Column address 1
Row address
Column address 2
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLL
D7 to D0
BS
RD/WR
PALL
ACTV
READ
NOP
READ
NOP
Figure 9.73 Word Read Timing in 8-Bit Access Space
(BE = 1, RCDM = 0, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
(2)
RAS Down Mode
Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode. The
RCDM bit is enabled only when the BE bit is set to 1.
Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other
spaces may be accessed. The RAS signal can be held low during other space accesses. Similarly to
the DRAM RAS down mode, the READ or WRIT command can be issued without the ACTV
command. However, two DQM cycles are always inserted for a SDRAM read cycle.
Figures 9.74 and 9.75 show a timing example of RAS down mode.
The next cycle after one of the following conditions is satisfied is a full access cycle.
•
•
•
•
•
•
When a refresh cycle is performed during RAS down mode
When a self-refresh is performed
When a transition to software standby mode is made
When the external bus requested by the BREQ signal is released
When either the RCDM or BE bit is cleared to 0
When setting the SDRAM mode register
Some SDRAMs have a limitation on the time to hold each bank active. When such SDRAM is in
use, if the user program cannot control the time (such as software standby or sleep mode), select
the auto-refresh or self-refresh so that the given specification can be satisfied. If a refresh cycle is
not used, the user program must control the time.
Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see
section 26, Clock Pulse Generator.
(3)
RAS Up Mode
Clear the RCDM bit in DRAMCR to 0 to set the RAS up mode.
Whenever a SDRAM space access is halted and other spaces are accessed, the next cycle is the
PALL command cycle. Only when the SDRAM space continues to be accessed, the fast-page
mode access is performed.
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Section 9 Bus Controller (BSC)
SDRAM space read
Tp
Tr
Tc1
Tcl
Tc2
External
space read
SDRAM space read
T1
Tc1
T2
Tcl
Tc2
SDRAMφ
Address bus
Row address
Column address 1
Row
address
Precharge-sel
External address
Column address 2
External address
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
READ
NOP
READ
NOP
Figure 9.74 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
SDRAM space read
Tp
Tr
Tc1
Tcl
Tc2
External
space read
SDRAM
space read
T1
Tc1
T2
Tc2
SDRAMφ
Address bus
Row address
Column address 1
Row
address
Precharge-sel
External address
Column address 2
External address
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL
ACTV
READ
NOP
WRIT
Figure 9.75 Timing Example of RAS Down Mode (BE = 1, RCDM = 1, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
9.11.13 Refresh Control
This LSI includes a DRAM refresh control function. The refresh method is the auto-refresh. Selfrefresh cycles can be performed in software standby mode.
The refresh control function is enabled when area 2 is specified as the SDRAM space by the
DRAME and DTYPE bits in DRAMCR.
(1)
Auto-Refresh Mode
Set the RFSHE bit in REFCR to 1 to select auto-refreshing.
An auto-refresh cycle is performed when the value set in RTCOR matches the RTCNT value
(compare match). RTCNT is an up-counter operated on the input clock specified bits RTCK2 to
RTCK0 in REFCR. RTCNT is initialized upon the compare match and restarts to count up with
H'00. Accordingly, an auto-refresh cycle is repeated at intervals specified by bits RTCK2 to
RTCK0 in RTCOR. Set the bits so that the required refresh intervals of the DRAM must be
satisfied.
Since setting bits RTCK2 to RTCK0 starts RTCNT to count up, set RTCNT and RTCOR before
setting bits RTCK2 to RTCK0. When changing RTCNT and RTCOR, the count operation should
be halted. When changing bits RTCK2 to RTCK0, change them only after disabling the external
access and external bus release by the EXDMAC, if the write data buffer function is in use,
disabling the write data buffer function and reading the external space.
The external space cannot be accessed during auto-refresh.
Figure 9.76 shows auto-refresh cycle timing. For details, see section 9.10.12, Refresh Control.
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Section 9 Bus Controller (BSC)
TRp
TRr
TRc1
TRc2
SDRAMφ
Address bus
Precharge-sel
CS
RAS
CAS
WE
CKE
High
BS
High
RD/WR
High
PALL
REF
NOP
Figure 9.76 Auto-Refresh Operation
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Section 9 Bus Controller (BSC)
The time between the PALL or PRE command and the subsequent REF command can be changed
by wait cycle insertion. The number of wait cycles is selected from one to three cycles by bits
TPC1 and TPC0 in DRACCR. Set the bit according to the SDRAM to be used and the frequency
of this LSI so that the number of wait cycles can be optimal.
Figure 9.77 shows a timing example when the one wait cycles are inserted.
TRp1
TRp2
TRr
TRc1
TRc2
SDRAMφ
Address bus
Precharge-sel
CS
RAS
CAS
WE
CKE
High
BS
High
High
RD/WR
PALL
NOP
REF
NOP
Figure 9.77 Auto-Refresh Timing (TPC1 = 0, TPC0 = 1)
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Section 9 Bus Controller (BSC)
When the time between the REF command and the subsequent ACTV command does not meet a
given specification, a wait cycle can be inserted for one to seven cycles during a refresh cycle by
bits RLW2 to RLW0 in REFCR. Set the bit according to the SDRAM to be used and the
frequency of this LSI so that the number of wait cycles can be optimal.
Figure 9.78 shows a timing example when the one wait cycle is inserted.
TRp
TRr
TRc1
TRcw
TRc2
SDRAMφ
Address bus
Precharge-sel
CS
RAS
CAS
WE
CKE
High
BS
High
RD/WR
High
PALL
REF
NOP
Figure 9.78 Auto-Refresh Timing (TPC1 = 0, TPC0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 1)
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Section 9 Bus Controller (BSC)
(2)
Self-Refresh Mode
Some SDRAMs have a self-refresh mode (battery backup mode). The self-refresh is a kind of
standby mode and refresh timing and refresh address are controlled internally.
(a) Self-Refresh in Software Standby Mode
The self-refresh is selected by setting the RFSHE and SLFRF bits in REFCR to 1. The SELFcommand is issued as shown in figure 9.79 by executing the SLEEP instruction to enter the
software standby mode.
When an auto-refresh is requested on a transition to the software standby mode, the auto-refresh is
first performed and then the self-refresh is entered.
When making a transition to the self-refresh, set the OEE bit in SBYCR to 1 and connect the CKE
pin.
When the self-refresh is used, do not clear the OPE bit in SBYCR to 0.
TRp
Software standby
TRr
TRc2
TRc3
SDRAMφ
Address bus
Precharge-sel
CS
RAS
CAS
WE
CKE
High
BS
High
RD/WR
PALL
SELF
NOP
Figure 9.79 Self-Refresh Timing in software standby mode
(TPC1 = 0, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 0)
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Section 9 Bus Controller (BSC)
Some DRAMs with the self-refresh have a given time between cancellation of the self-refresh
mode and the subsequent command issued cycle. From one to seven of precharge cycles
immediately after cancellation of the self-refresh mode can be inserted. Normal precharge is also
performed according to bits TPC1 and TPC0 in DRACCR. Set the precharge time including the
normal precharge so that the precharge time immediately after a self-refresh cycle is optimal.
Figure 9.80 shows a timing example when one precharge cycle is added.
Software
standby
SDRAM space write
TRc2
TRc3
TRp1
Tp
Tr
Tc1
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
CKE
DQMLU, DQMLL
Data bus
BS
RD/WR
NOP
PALL
ACTV
NOP WRITE
Figure 9.80 Timing Example when 1 Precharge Cycle Added in the
Software Standby Mode (TPCS2 to TPCS0 = H'1, TPC1 = 0, TPC0 = 0)
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Section 9 Bus Controller (BSC)
(b) Self-Refresh in Deep Software Standby Mode
The chip passes through the software standby mode in transitions to deep software standby mode.
The states of pins in software standby mode are retained in the deep software standby mode.
Therefore, the transition to self-refreshing is possible in deep software standby mode as well as in
software standby mode.
In deep software standby mode, initiate the transition to the self-refresh after having set the
IOKEEP bit in DPSBYCR to 1 as well as making the setting in "(a) Self-Refresh in Software
Standby Mode ".
On exit from deep software standby mode, use the following procedure to cancel self-refresh. (See
figure 9.81).
1. In PBDDR/PBDR, set PB1 (CS2) as a high-level output and PB5(CKE) as a low-level
output.
Since the setting of the IOKEEP bit ensures retention of pin state at this time, the existing
state of high-level output on CS2 and low-level output on is retained.
2. Set the PSTOP0 bit in SCKCR to1 and SDRAMφ as a high level output. Since the setting
of the IOKEEP bit continues to ensure retention of pin state, the existing state of highlevel output on SDRAMφ is retained.
3. Clear the IOKEEP bit in DPSBYCR.
This releases pin states from retention due to the setting of the IOKEEP bit, but the states
of pins CS2, CKE, and SDRAMφ as set in steps 1and 2 do not change.
4. In the synchronous DRAM-related control registers that were initialized by the internal
reset that accompanied the transition to deep software standby mode, remake the settings
to enable the synchronous DRAM interface. At this time, do not make settings in REFCR,
RTCNT, and RTCOR.
Once the synchronous DRAM interface has been enabled, the state of the CKE pin
changes from low-level output to high-level output.
5. Restart output of the SDRAMφ clock signal by clearing the PSTOP0 bit in SCKCR. This
restarts supply of SDRAMφ to the synchronous DRAM.
6. Set REFCR, RTCNT, and RTCOR and enable refreshing.
As the state of the CKE pin has been changed in the step 4, adjust the time between the
state of change of the CKE pin and the next cycle of auto-refreshing in this procedure
within the stipulated refreshing interval of the synchronous DRAM.
7. Resume access to the synchronous DRAM.
Pre-charging time after the termination of self-refresh will be secured by the timing of the
setting in step 6.
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Section 9 Bus Controller (BSC)
For details on the software standby mode and deep software standby mode, see section 27,
Power-Down Modes.
TRp TRr
Deep software
standby mode
EXTAL
Internal reset
PSTOP0 IOKEEP
set
clear
PSTOP0
clear
SDRAMφ
Address bus
Precharge-sel
Port setting
PB1/CS2 = H output setting
PB5/CKE = L output setting
Register setting in SDRAM
(DRAMCR, etc.)
REFCR, RTCNT,
RTCOR
CS2
RAS
CAS
WE
CKE
Pin status saved with deep software
standby mode (IOKEEP=1)
Pin status depends on
I/O port register
Pin status in DRAM
interface
Figure 9.81 Self-Refresh Timing in Deep Software Standby Mode
(TPC1 = 0, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 0)
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Section 9 Bus Controller (BSC)
(3)
Refresh and All-Module Clock Stop Mode
This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of
all on-chip peripheral modules by setting the ACSE bit in MSTPCRA to 1 (MSTPCRA,
MSTPCRB = H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to
F]FFFFFF), then execute the SLEEP instruction to enter the sleep mode.
In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the
clock for the bus controller is stopped, an auto-refresh cycle cannot be performed. When external
SDRAM is used and the contents of the SDRAM in sleep mode should be held, clear the ACSE bit
in MSTPCE to 0.
For details, see section 27.2.2, Module Stop Control Registers A and B (MSTPCRA and
MSTPCRB).
9.11.14 Setting SDRAM Mode Register
To use SDRAM, the mode register must be specified after a power-on reset.
Setting the MRSE bit in SDCR to 1 enables the SDRAM mode register setting. After this, write to
the SDRAM space in bytes.
When the value to be set in the SDRAM mode register is x, write to the following memory
location (address). The value of x is written to the SDRAM mode register.
• H'4000000/H'400000 + x for 8-bit bus SDRAM
• H'4000000/H'400000 + 2x for 16-bit bus SDRAM
The SDRAM mode register latches the address signals when the MRS command is issued.
This LSI does not support the burst read/burst write mode of SDRAM. When setting the SDRAM
mode register, use the burst read/single write mode and set the burst length to 1. Setting in the
SDRAM mode register must be consistent with that in the bus controller.
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Section 9 Bus Controller (BSC)
Figure 9.82 shows the timing of setting SDRAM mode register.
Tp
Tr
Tc1
Tc2
SDRAMφ
Address bus
Mode register setting
Mode register setting
Precharge-sel
CS
RAS
CAS
WE
CKE
High
BS
High
RD/WR
High
PALL
NOP
MRS
NOP
Figure 9.82 Timing of Setting SDRAM Mode Register
9.11.15 SDRAM Interface and Single Address Transfer by DMAC and EXDMAC
When fast-page mode (BE = 1) is set for the SDRAM space, either fast-page access or full access
can be selected, by the setting of bits DDS and EDDS in DRAMCR, for the single address transfer
by the DMAC or EXDMAC where the SDRAM space is specified as the transfer source or
destination. At the same time, the output timing of the DACK and EDACK and BS signals can be
changed. When BE = 0, a full access to the SDRAM space is performed with a single address
transfer regardless of the setting of bits DDS and EDDS. However, the output timing of the
DACK, EDACK and BS signals can be changed by the setting of bits DDS and EDDS.
The assertion timing of the DACK and EDACK signals can be changed by the bits DKC and
EDKC in BCR1.
The output timing of the DACK and EDACK signals can be independently set by the bits TRWL
and CKSPE in SDCR and bit DKC and EDKC in BCR1 regardless of the setting of bits DDS and
EDDS.
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Section 9 Bus Controller (BSC)
(1)
When DDS = 1 or EDDS = 1
A fast-page access is performed regardless of the bus master, only according to the address. The
DACK and EDACK signals are asserted within the Tc1 cycle in both read and write accesses.
Figures 9.83 and 9.84 show the output timing example of the DACK and EDACK signals when
DDS = 1 or EDDS = 1.
Tp
Tr
Tc1
Tc2
Tc1
Tc2
SDRAMφ
Address bus
Row address
Column address 1
Column address 2
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
DACK or EDACK
PALL
ACTV
NOP
WRIT
NOP
WRIT
Figure 9.83 Output Timing Example of DACK and EDACK when DDS = 1 or EDDS = 1
(Write)
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl
Tc2
Tc1
Tcl
Tc2
SDRAMφ
Address bus
Row address
Column address 1
Column address 2
Row
address
Precharge-sel
CS
RAS
CAS
WE
CKE
High
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
DACK or EDACK
PALL
ACTV
READ
NOP
READ
NOP
Figure 9.84 Output Timing Example of DACK and EDACK when DDS = 1 or EDDS = 1
(Read, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
(2)
When DDS = 0 or EDDS = 0
Single address transfer by the DMAC or EXDMAC takes place as a full access (normal access) to
the SDRAM space. The DACK and EDACK signals are asserted within the Tr cycle and the BS
signal is also asserted in the Tr cycle.
When the SDRAM space is accessed with other than the single address transfer by the DMAC or
EXDMAC, a fast-page access is available.
Figures 9.85 and 9.86 show an output timing example of the DACK and EDACK signals when
DDS = 0 or EDDS = 0.
Tp
Tr
Tc1
Tc2
SDRAMφ
Address bus
Row address
Column address
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
DACK or EDACK
PALL
ACTV
NOP
WRIT
Figure 9.85 Output Timing Example of DACK and EDACK when DDS = 0 or EDDS = 0
(Write)
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl
Tc2
SDRAMφ
Address bus
Row address
Cloumn address
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
DACK or EDACK
PALL
ACTV
READ
NOP
Figure 9.86 Output Timing Example of DACK and EDACK when DDS = 0 or EDDS = 0
(Read, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
(3)
When TRWL = 1
When the SDRAM interface is written to, one Trwl cycle is inserted after the Tc2 cycle. The
DACK and EDACK signals stay asserted until the end of the Trwl cycle. The hold time of data
output from an external device can be extended by one cycle.
Figure 9.87 shows an output timing example of the DACK and EDACK signals when TRWL = 1
with DDS = 1, EDDS = 1, DKC = 0 and EDKC = 0.
Tp
Tr
Tc1
Tc2
Trwl
Tc1
Tc2
Trwl
SDRAMφ
Address bus
Row address
Precharge-sel
Row
address
Column address 1
Column address 2
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
DACK or EDACK
PALL ACTV NOP
WRIT
NOP
WRIT
NOP
Figure 9.87 Output Timing Example of DACK and EDACK when TRWL = 1 (Write)
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Section 9 Bus Controller (BSC)
(4)
When CKSPE = 1
When the SDRAM space is read, the read data settling cycle can be inserted for one cycle using
the clock suspend mode. To enter the clock suspend mode, set the OEE bit in DRAMCR to 1, and
connect the CKE pin.
Figure 9.88 shows an output timing example of the DACK and EDACK signals when CKSPE = 1
with DDS = 1, EDDS = 1, DKC = 0 and EDKC = 0.
Tp
Tr
Tc1
Tcl
Tsp
Tc2
Tc1
Tcl
Tsp
Tc2
SDRAMφ
Address bus
Row address
Precharge-sel
Row
address
Column address 1
Column address 2
CS
RAS
CAS
WE
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
DACK or EDACK
PALL ACTV READ
NOP
READ
NOP
Figure 9.88 Output Timing Example of DACK and EDACK when CKSPE = 1
(Read, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
(5)
When DKC = 1
With DKC = 1 or EDKC = 1, the DACK and EDACK signals are asserted a half cycle earlier
compared to the case when DKC = 0 or EDKC = 0.
In fast-page access, the DACK signal continues to be low. In this case, bus cycles can be
distinguished by the BS output timing.
Figure 9.89 shows an output timing example of the DACK and EDACK signals when DKC = 1 or
EDKC = 1, and DDS = 1 or EDDS = 1. Figure 9.90 shows an output timing example of the DACK
and EDACK signals when DKC = 1 or EDKC = 1, and DDS = 0 or EDDS = 0.
Tp
Tr
Tc1
Tc2
Tc1
Tc2
SDRAMφ
Address bus
Row address
Column address 1
Column address 2
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
DACK or EDACK
PALL
ACTV
NOP
WRIT
NOP
WRIT
Figure 9.89 Output Timing Example of DACK and EDACK when DKC = 1 or EDKC = 1
and DDS = 1 or EDDS = 1 (Write)
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
SDRAMφ
Address bus
Row address
Cloumn address
Row
address
Precharge-sel
CS
RAS
CAS
WE
High
CKE
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
DACK or EDACK
PALL
ACTV
NOP
WRIT
Figure 9.90 Output Timing Example of DACK and EDACK when DKC = 1 or EDKC = 1
and DDS = 0 or EDDS = 0 (Write)
9.11.16 EXDMAC Cluster Transfer
Using an EXDMAC cluster transfer mode, data can be read from or written to consecutively. For
details, see section 11, EXDMA Controller (EXDMAC).
Figures 9.91 and 9.92 show a read/write timing using a cluster transfer.
For 1-cycle read or write, set the BE bit in DRAMCR to 1, clear the TRWL bit in SDCR to 0, and
set the CAS latency to 2. During a read cycle, the clock suspend mode cannot be used.
Do not change the bus controller register settings during a cluster transfer.
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Section 9 Bus Controller (BSC)
A refresh cycle is not executed during a consecutive cluster transfer even if a refresh request is
generated. Therefore, user program must control the time so that each bank should not be activated
over a given specification. The external bus is not released during a cluster transfer.
Tp
Tr
Tcb
Tcb
Tcb
Tcb
Tcb
Tc1
Tcl
Tc2
SDRAMφ
Address bus
Precharge-sel
Row
Cloumn 1 Cloumn 2 Cloumn 3 Cloumn 4 Cloumn 5
Cloumn 6
Row
CS
RAS
CAS
WE
High
CKE
DQMUU
DQMUL
DQMLU
DQMLL
D31 to D24
D23 to D16
D15 to D8
D7 to D0
BS
RD/WR
PALL ACTV
READ
NOP
Figure 9.91 Word-Size 6-Word Cluster Transfer
(Read, BE = 1, EDDS = 1, CAS Latency = 2)
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Section 9 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
Tcb
Tcb
Tcb
Tcb
Tcb
SDRAMφ
Row
Address bus
Precharge-sel
Cloumn 1
Cloumn 2 Cloumn 3 Cloumn 4 Cloumn 5 Cloumn 6
Row
CS
RAS
CAS
WE
High
CKE
DQMUU
DQMUL
DQMLU
DQMLL
D31 to D24
D23 to D16
D15 to D8
D7 to D0
BS
RD/WR
PALL ACTV
NOP
WRIT
Figure 9.92 Word-Size 6-Word Cluster Transfer
(Write, BE = 1, EDDS = 1)
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Section 9 Bus Controller (BSC)
9.12
Idle Cycle
In this LSI, idle cycles can be inserted between the consecutive external accesses. By inserting the
idle cycle, data conflicts between ROM read cycle whose output floating time is long and an
access cycle from/to high-speed memory or I/O interface can be prevented.
9.12.1
Operation
When this LSI consecutively accesses external address space, it can insert an idle cycle between
bus cycles in the following four cases. These conditions are determined by the sequence of read
and write and previously accessed area.
1.
2.
3.
4.
When read cycles of different areas in the external address space occur consecutively
When an external write cycle occurs immediately after an external read cycle
When an external read cycle occurs immediately after an external write cycle
When an external access occurs immediately after a DMAC or EXDMAC* single address
transfer (write cycle)
Up to four idle cycles can be inserted under the conditions shown above. The number of idle
cycles to be inserted should be specified to prevent data conflicts between the output data from a
previously accessed device and data from a subsequently accessed device.
Under conditions 1 and 2, which are the conditions to insert idle cycles after read, the number of
idle cycles can be selected from setting A specified by bits IDLCA1 and IDLCA0 in IDLCR or
setting B specified by bits IDLCB1 and IDLCB0 in IDLCR: Setting A can be selected from one to
four cycles, and setting B can be selected from one or two to four cycles. Setting A or B can be
specified for each area by setting bits IDLSEL7 to IDLSEL0 in IDLCR. Note that bits IDLSEL7
to IDLSEL0 correspond to the previously accessed area of the consecutive accesses.
The number of idle cycles to be inserted under conditions 3 and 4, which are conditions to insert
idle cycles after write, can be determined by setting A as described above.
After the reset release, IDLCR is initialized to four idle cycle insertion under all conditions 1 to 4
shown above.
Table 9.28 shows the correspondence between conditions 1 to 4 and number of idle cycles to be
inserted for each area. Table 9.29 shows the correspondence between the number of idle cycles to
be inserted specified by settings A and B, and number of cycles to be inserted.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
Table 9.28 Number of Idle Cycle Insertion Selection in Each Area
Bit Settings
IDLSn
Insertion Condition
n
Consecutive reads in different areas 1
Write after read
0
Read after write
2
Setting
IDLSELn
n = 0 to 7
Area of Previous Access
0
1
2
3
5
6
7
0

1
0
A
A
A
A
A
A
A
A
1
B
B
B
B
B
B
B
B
Invalid
0

1
0
A
A
A
A
A
A
A
A
1
B
B
B
B
B
B
B
B
0
Invalid

Invalid
1
External access after single address 3
transfer
4
0
A

Invalid
1
A
[Legend]
A: Number of idle cycle insertion A is selected.
B: Number of idle cycle insertion B is selected.
Invalid: No idle cycle is inserted for the corresponding condition.
Table 9.29 Number of Idle Cycles Inserted
Bit Settings
A
IDLCA1
IDLCA0
B
IDLCB1
IDLCB0
Number of Cycles


0
0
0
0
0


1
0
1
0
1
2
1
0
1
0
3
1
1
1
1
4
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Section 9 Bus Controller (BSC)
(1)
Consecutive Reads in Different Areas
If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0, or bits
IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read
cycle (n = 0 to 7).
Figure 9.93 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a conflict occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data conflict is prevented.
Bus cycle B
Bus cycle A
T1
T2
T3
T1
T2
Bus cycle B
Bus cycle A
T1
T2
T3
Ti
T1
T2
Bφ
Address bus
CS (area A)
CS (area B)
RD
Data bus
Data conflict
Data hold
time is long.
(a) No idle cycle inserted
(IDLS1 = 0)
(b) Idle cycle inserted
(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.93 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)
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Section 9 Bus Controller (BSC)
(2)
Write after Read
If an external write occurs after an external read while bit IDLS0 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0 when
IDLSELn = 0, or bits IDLCB1 and IDLCB0 when IDLSELn is set to 1 are inserted at the start of
the write cycle (n = 0 to 7).
Figure 9.94 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bus cycle B
Bus cycle A
T1
T2
T3
T1
Bus cycle B
Bus cycle A
T1
T2
T2
T3
Ti
T1
T2
Bφ
Address bus
CS (area A)
CS (area B)
RD
LLWR
Data bus
Data hold
time is long.
(a) No idle cycle inserted
(IDLS0 = 0)
Data conflict
(b) Idle cycle inserted
(IDLS0 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.94 Example of Idle Cycle Operation (Write after Read)
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Section 9 Bus Controller (BSC)
(3)
Read after Write
If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7).
Figure 9.95 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted,
and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM
device. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bus cycle B
Bus cycle A
T1
T2
T3
T1
T2
Bus cycle B
Bus cycle A
T1
T2
T3
Ti
T1
T2
Bφ
Address bus
CS (area A)
CS (area B)
RD
LLWR
Data bus
Data conflict
Output floating
time is long.
(a) No idle cycle inserted
(IDLS2 = 0)
(b) Idle cycle inserted
(IDLS2 = 1, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.95 Example of Idle Cycle Operation (Read after Write)
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Section 9 Bus Controller (BSC)
(4)
External Access after Single Address Transfer Write
If an external access occurs after a single address transfer write while bit IDLS3 in IDLCR is set
to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the external
access (n = 0 to 7).
Figure 9.96 shows an example of the operation in this case. In this example, bus cycle A is a
single address transfer (write cycle) and bus cycle B is a CPU write cycle. In (a), an idle cycle is
not inserted, and a conflict occurs in bus cycle B between the external device write data and this
LSI write data. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bus cycle B
Bus cycle A
T1
T2
T3
T1
T2
Bus cycle B
Bus cycle A
T1
T2
T3
Ti
T1
T2
Bφ
Address bus
CS (area A)
CS (area B)
LLWR
DACK
Data bus
Data conflict
Output floating
time is long.
(a) No idle cycle inserted
(IDLS3 = 0)
(b) Idle cycle inserted
(IDLS3 = 1, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.96 Example of Idle Cycle Operation (Write after Single Address Transfer Write)
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Section 9 Bus Controller (BSC)
(5)
External NOP Cycles and Idle Cycles
A cycle in which an external space is not accessed due to internal operations is called an external
NOP cycle. Even when an external NOP cycle occurs between consecutive external bus cycles, an
idle cycle can be inserted. In this case, the number of external NOP cycles is included in the
number of idle cycles to be inserted.
Figure 9.97 shows an example of external NOP and idle cycle insertion.
No external access Idle cycle
(NOP)
(remaining)
Preceding bus cycle
T1
T2
Tpw
T3
Ti
Ti
Following bus cycle
T1
T2
Tpw
T3
Bφ
Address bus
CS (area A)
CS (area B)
RD
Data bus
Specified number of idle cycles or more
including no external access cycles (NOP)
(Condition: Number of idle cycles to be inserted when different reads continue: 4 cycles)
Figure 9.97 Idle Cycle Insertion Example
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Section 9 Bus Controller (BSC)
(6)
Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system's load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 9.98. In this case, with the setting for no idle cycle insertion (a), there
may be a period of overlap between the RD signal in bus cycle A and the CS signal in bus cycle B.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals. In the initial state after reset release, idle cycle indicated in (b) is set.
Bus cycle B
Bus cycle A
T1
T2
T3
T1
T2
Bus cycle B
Bus cycle A
T1
T2
T3
Ti
T1
T2
Bφ
Address bus
CS (area A)
CS (area B)
RD
Overlap time may occur between the
CS (area B) and RD
(a) No idle cycle inserted
(IDLS1 = 0)
(b) Idle cycle inserted
(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.98 Relationship between Chip Select (CS) and Read (RD)
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Section 9 Bus Controller (BSC)
(7)
Idle Cycle for Accessing to DRAM/SDRAM Space
In the following read cycles, when the DRAM/SDRAM space is accessed in a full access, the Tp
and Tr cycles are also counted as idle cycles.
Figures 9.99 and 9.100 show timing examples of full accesses to the DRAM/SDRAM space when
four idle cycles are inserted.
When accessing the DRAM/SDRAM space, the Ti cycles are inserted so that the sum of the
numbers of Tp (precharge), Tr (row address output), and Ti cycles satisfies the specified number
of idle cycles. The Ti cycles are inserted before the column address output cycle.
While the SDRAM space is accessed in a full access, the CS2 signal is driven low even in an idle
cycle.
The idle cycle insertion is enabled even in a fast-page access in RAS down mode. The specified
number of idle cycles is inserted. Figure 9.101 shows a timing example of the idle cycle insertion
in RAS down mode.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
External space read
T1
T2
T3
DRAM space read
Tp
Tr
Ti
Ti
Tc1
Tc2
Bφ
Address bus
RD
RAS
LLCAS
Data bus
Figure 9.99 Example of DRAM Full Access after External Read (CAST = 0)
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Section 9 Bus Controller (BSC)
External space (area A) read
T1
T2
T3
SDRAM space read
Tp
Tr
Ti
Ti
Tc1
Tcl
Tc2
SDRAMφ
Address bus
CS (area A)
CS (area 2)
RD
RAS
CAS
WE
DQMLL
Data bus
Figure 9.100 Example of SDRAM Full Access after External Read (CAS Latency = 2)
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Section 9 Bus Controller (BSC)
External space read
DRAM space read
Tp
Tr
Tc1
Tc2
T1
T2
T3
DRAM space write
Ti
Tc1
Tc2
Bφ
Address bus
RD
RAS
UCAS, LCAS
Data bus
WR
Idle cycle
Figure 9.101 Example of Idle Cycles in RAS Down Mode (Write after Read)
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Section 9 Bus Controller (BSC)
Table 9.30 Idle Cycles in Mixed Accesses to Normal Space and DRAM/SDRAM Space
Previous
Access
IDLS
Next Access
3
Normal/DRAM/ Normal/DRAM/ 
SDRAM space SDRAM space

read
read
IDLSEL
1
0
7 to 0
1
0
1
0
Idle Cycle

0






Disabled

1

0
0
0


1 cycle inserted
0
1
2 cycles inserted
1
0
3 cycles inserted
1
1
4 cycles inserted


Single address Normal/DRAM/ 0
write
SDRAM space
1
write
0
0 cycle inserted
0
1
2 cycles inserted
1
0
3 cycles inserted
1
1
4 cycles inserted

0





Disabled


1
0
0
0


1 cycle inserted
0
1
2 cycles inserted
1
0
3 cycles inserted
1
1
4 cycles inserted
0
0
0 cycle inserted
0
1
2 cycles inserted
1
0
3 cycles inserted
1
1
4 cycles inserted
0







Disabled
1



0
0


1 cycle inserted
0
1
2 cycles inserted
1
0
3 cycles inserted
1
1
4 cycles inserted








Disabled




0
0


1 cycle inserted
0
1
2 cycles inserted
1
0
3 cycles inserted
1
1
4 cycles inserted
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0

1
Normal/DRAM/ Normal/DRAM/ 
SDRAM space SDRAM space

read
write
IDLCB
2
1
Normal/DRAM/ Normal/DRAM/ 
SDRAM space SDRAM space

read
read
IDLCA
Section 9 Bus Controller (BSC)
9.12.2
Pin States in Idle Cycle
Table 9.31 shows the pin states in an idle cycle.
Table 9.31 Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of following bus cycle
D15 to D0
High impedance
CSn (n = 7 to 0)
High*1
LUCAS, LLCAS*5
High
5
DQMLU, DQMLL*
High*2
AS
High
RD
High
BS
High
RD/WR
High*3
AH
low
LHWR, LLWR
High
LUB, LLB
High
CKE*
5
High
OE*5
RAS*
High
5
High/Low*4
CAS*5
High
WE*
High
5
DACKn (n = 3 to 0)
High
EDACKn (n = 3 to 0) *
5
High
Low when accessing the SDRAM*5 in full access cycle
5
Low when reading the SDRAM* in full access cycle
Low when accessing or writing to the DRAM/SDRAM*5 in full access cycle
The pin state varies depending on the DRAM space access/ area access other than the
DRAM space, or RAS up mode/RAS down mode. For details, see figures 9.98 and
9.100.
5. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Notes: 1.
2.
3.
4.
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Section 9 Bus Controller (BSC)
9.13
Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, the internal bus masters other than the EXDMAC* continue to operate
as long as there is no external access.
In addition, in the external bus released state, the BREQO signal can be driven low to output a bus
request externally.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
9.13.1
Operation
In external extended mode, when the BRLE bit in BCR1 is set to 1, and the ICR bit for the
corresponding pin is set to 1, the bus can be released to the external. Driving the BREQ pin low
issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed
timing, the BACK pin is driven low, and the address bus, data bus, and bus control signals are
placed in the high-impedance state, establishing the external bus released state. For ICR, see
section 13, I/O Ports.
In the external bus released state, the CPU, DTC, DMAC can access the internal space using the
internal bus. When any one of the CPU, DTC, DMAC, and EXDMAC*attempts to accesses the
external address space, it temporarily defers initiation of the bus cycle, and waits for the bus
request from the external bus master to be canceled.
In the external bus released state, certain operations are suspended as follows until the bus request
from the external bus master is canceled:
• When a refresh is requested, refresh control is suspended.
• When the SLEEP instruction is executed to enter software standby mode or all-module clockstop mode, control for software standby mode or all-module clock-stop mode is suspended.
• When SCKCR is written to set the clock frequencies, changing of clock frequencies is
suspended. For SCKCR, see section 26, Clock Pulse Generator.
If the BREQOE bit in BCR1is set to 1, the BREQO pin can be driven low to request cancellation
of the bus request when any of the following requests are issued.
• When any one of the CPU, DTC, DMAC, and EXDMAC* attempts to access the external
address space
• When a refresh* is requested
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Section 9 Bus Controller (BSC)
• When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clock-stop mode
• When SCKCR is written to set the clock frequencies
If an external bus release request, external access, and a refresh* request occur simultaneously, the
order of priority is as follows:
Refresh* > EXDMAC* > External bus release > External access by CPU, DTC, and
DMAC
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
9.13.2
Pin States in External Bus Released State
Table 9.32 shows pin states in the external bus released state.
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Section 9 Bus Controller (BSC)
Table 9.32 Pin States in Bus Released State
Pins
Pin State
A23 to A0
High impedance
D15 to D0
High impedance
BS
High impedance
CSn (n = 7 to 0)
High impedance
AS
High impedance
AH
High impedance
RD/WR
High impedance
LUCAS, LLCAS*
High impedance
RD
High impedance
RAS*
High impedance
CAS*
High impedance
WE
High impedance
DQMLU, DQMLL*
High impedance
CKE*
High impedance
OE*
High impedance
LUB, LLB
High impedance
LHWR, LLWR
High impedance
DACKn (n = 3 to 0)
High
EDACKn (n = 3 to 0)*
High
Note:
*
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.13.3
Transition Timing
Figures 9.102 and 9.103* show the timing of transition to the bus released state.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
External space
access cycle
T1
CPU cycle
External bus released state
T2
Bφ
Hi-Z
Address bus
Hi-Z
Data bus
Hi-Z
CSn
Hi-Z
AS
Hi-Z
RD
Hi-Z
LHWR, LLWR
BREQ
BACK
BREQO
[1]
[2]
[3]
[4]
[7]
[5]
[8]
[6]
[1] A low level of the BREQ signal is sampled at the rising edge of the Bφ signal.
[2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or
more after the low level of the BREQ signal is sampled.
[3] The BACK signal is driven low, releasing bus to the external bus master.
[4] The BREQ signal state sampling is continued in the external bus released state.
[5] A high level of the BREQ signal is sampled.
[6] The external bus released cycles are ended one cycle after the BREQ signal is driven high.
[7] When the external space is accessed by an internal bus master during external bus released while the BREQOE
bit is set to 1, the BREQO signal goes low.
[8] Normally the BREQO signal goes high at the rising edge of the BACK signal.
Figure 9.102 Bus Released State Transition Timing (SRAM Interface is Not Used)
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Section 9 Bus Controller (BSC)
External
access cycle
T1
External bus released state
CPU cycle
T2
SDRAMφ
Hi-Z
Address bus
Hi-Z
Data bus
Hi-Z
Precharge-sel
CS2
Hi-Z
RAS
Hi-Z
CAS
Hi-Z
WE
Hi-Z
CKE
Hi-Z
DQMLU, DQMLL
Hi-Z
BREQ
BACK
BREQO
NOP
[1]
PALL NOP
[2]
[3]
[4]
NOP
[5]
[8]
[6]
[9]
[7]
[1] A low level of the BREQ signal is sampled at the rising edge of the Bφ signal.
[2] The PALL command is issued.
[3] The bus control signals are driven high at the end of the external access cycle. It takes two cycles or
more after the low level of the BREQ signal is sampled.
[4] The BACK signal is driven low, releasing bus to the external bus master.
[5] The BREQ signal state sampling is continued in the external bus released state.
[6] A high level of the BREQ signal is sampled.
[7] The BACK signal is driven high, ending external bus release cycle after one cycle.
[8] When the external space is accessed by an internal bus master or a refresh cycle is requested during external
bus released while the BREQOE bit is set to 1, the BREQO signal goes low.
[9] Normally the BREQO signal goes high at the rising edge of the BACK signal.
Figure 9.103 Bus Released State Transition Timing (SRAM Interface is Used)
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Section 9 Bus Controller (BSC)
9.14
Internal Bus
9.14.1
Access to Internal Address Space
The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and
register space for the on-chip peripheral modules. The number of cycles necessary for access
differs according the space.
Table 9.33 shows the number of access cycles for each on-chip memory space.
Table 9.33 Number of Access Cycles for On-Chip Memory Spaces
Access Space
Access
On-chip ROM space
Read
One Iφ cycle
Write
Three Iφ cycles
Read
One Iφ cycle
Write
One Iφ cycle
On-chip RAM space
Number of Access Cycles
In access to the registers for on-chip peripheral modules, the number of access cycles differs
according to the register to be accessed. When the dividing ratio of the operating clock of a bus
master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0
to n-1 are inserted for register access in the same way as for external bus clock division.
Table 9.34 lists the number of access cycles for registers of on-chip peripheral modules.
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Section 9 Bus Controller (BSC)
Table 9.34 Number of Access Cycles for Registers of On-Chip Peripheral Modules
Number of Cycles
Module to be Accessed
Read
1
Write
Two Iφ
DMAC and EXDMAC* registers
MCU operating mode, clock pulse generator,
Two Iφ
power-down control registers, interrupt controller,
2
bus controller, DTC registers, and LVD*
registers.
Write Data Buffer Function
Disabled
Three Iφ
Disabled
Two Pφ
Three Pφ Disabled
I/O port registers other than PFCR, PORTM* ,and Two Pφ
N,
TPU, PPG0, TMR0, TMR1, SCI0 to SCI4, IIC2_0,
IIC2_1, A/D_0, and D/A registers
Enabled
1
Enabled
I/O port registers of PFCR and WDT
1
I/O port registers of PORTM* , N, TMR2, TMR3,
SCI5, SCI6, IIC2_3, IIC2_4, A/D_1, AD_2, and
PPG1 registers
Three Pφ
Notes: 1. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
2. Supported only by the H8SX/1648L Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.15
Write Data Buffer Function
9.15.1
Write Data Buffer Function for External Data Bus
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables internal accesses in parallel with external writes or DMAC single address
transfers. The write data buffer function is made available by setting the WDBE bit to 1 in BCR1.
Figure 9.104 shows an example of the timing when the write data buffer function is used. When
this function is used, if an external address space write or a DMAC single address transfer
continues for two cycles or longer, and there is an internal access next, an external write only is
executed in the first two cycles. However, from the next cycle onward, internal accesses (on-chip
memory or internal I/O register read/write) and the external address space write rather than
waiting until it ends are executed in parallel.
On-chip memory read
Peripheral module read
External write cycle
Iφ
On-chip
memory 1
Internal
address bus
T1
On-chip
memory 2
T2
Peripheral module address
T3
Bφ
Address bus
Write to
external
space
External address
CSn
LHWR, LLWR
D15 to D0
Figure 9.104 Example of Timing when Write Data Buffer Function is Used
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Section 9 Bus Controller (BSC)
9.15.2
Write Data Buffer Function for Peripheral Modules
This LSI has a write data buffer function for the peripheral module access. Using the write data
buffer function enables peripheral module writes and on-chip memory or external access to be
executed in parallel. The write data buffer function is made available by setting the PWDBE bit in
BCR2 to 1. For details on the on-chip peripheral module registers, see table 9.34, Number of
Access Cycles for Registers of On-Chip Peripheral Modules in section 9.14, Internal Bus.
Figure 9.105 shows an example of the timing when the write data buffer function is used. When
this function is used, if an internal I/O register write continues for two cycles or longer and then
there is an on-chip RAM, an on-chip ROM, or an external access, internal I/O register write only
is performed in the first two cycles. However, from the next cycle onward an internal memory or
an external access and internal I/O register write are executed in parallel rather than waiting until
it ends.
On-chip
memory
read
Peripheral module write
Iφ
Internal
address bus
Pφ
Internal I/O
address bus
Peripheral module address
Internal I/O
data bus
Figure 9.105 Example of Timing when Peripheral Module
Write Data Buffer Function is Used
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Section 9 Bus Controller (BSC)
9.16
Bus Arbitration
This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI
incorporates internal access and external access bus arbiters that can be used and controlled
independently. The internal bus arbiter handles the CPU, DTC, and DMAC accesses. The external
bus arbiter handles the external access by the CPU, DTC, DMAC, and EXDMAC*, refresh*, and
external bus release request (external bus master).
The bus arbiters determine priorities at the prescribed timing, and permit use of the bus by means
of the bus request acknowledge signal.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
9.16.1
Operation
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The priority of the internal bus arbitration:
DMAC > DTC > CPU
The priority of the external bus arbitration:
Refresh* > EXDMAC* > External bus release request > External access by the CPU, DTC, or
DMAC
If the DMAC or DTC accesses continue, the CPU can be given priority over the DMAC or DTC
to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2. In this
case, the priority between the DMAC and DTC does not change. If an external bus release request,
an EXDMAC* access, and a refresh* cycle request continue, an external bus access by the CPU,
DTC, and DMAC can be given priority to execute the bus cycles alternatively between them by
setting the EBCCS bit in BCR2. In this case, the priorities among the refresh*, EXDMAC*, and
external bus release request do not change.
An internal bus access by internal bus masters and an external bus access by an external bus
release request, a refresh* cycle, or an EXDMAC* access can be executed in parallel.
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.16.2
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority over that of the bus
master that has taken control of the bus and is currently operating, the bus is not necessarily
transferred immediately. There are specific timings at which each bus master can release the bus.
(1)
CPU
The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or
DMAC, the bus arbiter transfers the bus to the bus master that issued the request. When the CPU
accesses the external space and a bus request is received from the EXDMAC*, the external bus
arbiter transfer the bus to the EXDMAC*.
The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is
transferred synchronously with the clock.
Note, however, that the bus cannot be transferred in the following cases.
• The word or longword access is performed in some divisions.
• Stack handling is performed in multiple bus cycles.
• Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS
instruction.
(In the block transfer instructions, the bus can be transferred in the write cycle and the
following transfer data read cycle.)
• From the target read to write in the bit manipulation instructions or memory operation
instructions.
(In an instruction that performs no write operation according to the instruction condition, up to
a cycle corresponding the write cycle)
Note: * Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
(2)
DTC
The DTC sends the internal bus arbiter a request for the bus when an activation request is
generated. When the DTC accesses an external bus space, the DTC first takes control of the bus
from the internal bus arbiter and then requests a bus to the external bus arbiter.
Once the DTC takes control of the bus, the DTC continues the transfer processing cycles. If a bus
master whose priority is higher than the DTC requests the bus, the DTC transfers the bus to the
higher priority bus master. If the IBCCS bit in BCR2 is set to 1, the DTC transfers the bus to the
CPU.
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Section 9 Bus Controller (BSC)
Note, however, that the bus cannot be transferred in the following cases.
• During transfer information read
• During the first data transfer
• During transfer information write back
The DTC releases the bus when the consecutive transfer cycles completed.
(3)
DMAC
The DMAC sends the internal bus arbiter a request for the bus when an activation request is
generated. When the DMAC accesses an external bus space, the DMAC first takes control of the
bus from the internal bus arbiter and then requests a bus to the external bus arbiter.
After the DMAC takes control of the bus, it may continue the transfer processing cycles or release
the bus at the end of every bus cycle depending on the conditions.
The DMAC continues transfers without releasing the bus in the following case:
• Between the read cycle in the dual-address mode and the write cycle corresponding to the read
cycle
If no bus master of a higher priority than the DMAC requests the bus and the IBCCS bit in BCR2
is cleared to 0, the DMAC continues transfers without releasing the bus in the following cases:
• During 1-block transfers in the block transfer mode
• During transfers in the burst mode
In other cases, the DMAC transfers the bus at the end of the bus cycle.
(4)
EXDMAC
The EXDMAC sends the external bus arbiter a request for the bus when an activation request is
generated. If an internal bus master accesses the external space, the bus is passed to the EXDMAC
when the bus master can release the bus. Some EXDMAC transfers are continued once it takes
control of the bus. Some EXDMAC transfers are divided and it releases the bus for each transfer
cycle.
• Transfers are continued without bus release between a read cycle and the subsequent write
cycle in dual address mode
• Transfers are continued without bus release in cluster transfer mode
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Section 9 Bus Controller (BSC)
• Transfers are continued without bus release when a bus master with priority over the DMAC is
not requesting the bus, the EBCCS bit in BCR2 is cleared to 0, and either the following
conditions are executed.
 While one block of data is being transferred in block transfer mode
 While data is being transferred in burst mode
A transfer other than the above is stopped and the bus is passed when the bus cycle is completed.
However, the EXDMAC takes control of the bus and EXDMAC transfers are continued when
multiple channels in the EXDMAC request the bus while other bus masters are not requesting the
bus.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
(5)
External Bus Release
When the BREQ pin goes low and an external bus release request is issued while the BRLE bit in
BCR1 is set to 1 with the corresponding ICR bit set to 1, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
(6)
Refresh
When area 2 is specified as the DRAM space or SDRAM space with the RFSHE bit in REFCR set
to 1, RTCNT starts to count up. When the RTCOR value matches RTCNT, a bus request is sent to
the bus arbiter.
A refresh cycle is inserted on completion of the external bus cycle. A refresh cycle is not
consecutively inserted. Once a refresh cycle is inserted, the bus is passed to another bus master.
When the bus is passed, if there is no bus request from other bus masters, NOP cycles are inserted.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
9.17
Bus Controller Operation in Reset
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
9.18
(1)
Usage Notes
Setting Registers
The BSC registers must be specified before accessing the external address space. In on-chip ROM
disabled mode, the BSC registers must be specified before accessing the external address space for
other than an instruction fetch access.
(2)
Mode Settings
The burst read-burst write mode of synchronous DRAM is not supported.
When setting the mode register of synchronous DRAM, the burst read-single write mode must be
selected and the burst length must be 1.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
(3)
External Bus Release Function and All-Module-Clock-Stop Mode
In this LSI, if the ACSE bit in MSTPCRA is set to 1 and a SLEEP instruction is executed to enter
the sleep state after shutting off the clocks to all peripheral modules (MSTPCRA and MSTPCRB
= H'FFFFFFF) or allowing operation of the 8-bit timer module alone (MSTPCRA and MSTPCRB
= H'F[C to F]FFFFFF), the all-module-clock-stop mode is entered in which the clock for the bus
controller and I/O ports is also stopped. For details, see section 27, Power-Down Modes.
In this state, the external bus release function is halted. To use the external bus release function in
sleep mode, the ACSE bit in MSTPCRA must be cleared to 0. Conversely, if a SLEEP instruction
to place the chip in all-module-clock-stop mode is executed in the external bus released state, the
transition to all-module-clock-stop mode is deferred and performed until after the bus is
recovered.
(4)
External Bus Release Function and Software Standby Mode
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
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Section 9 Bus Controller (BSC)
Also, since clock oscillation halts in software standby mode, if the BREQ signal goes low in this
mode, indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby mode.
Note that the BACK and BREQO pins are both in the high-impedance state in software standby
mode.
(5)
External Bus Release Function and CBR-Refresh or Auto-Refresh Cycle
The CBR refresh or auto-refresh cycle cannot be performed while the external bus is released.
When a CBR-refresh or an auto-refresh cycle is requested, the BREQO signal can be output by
setting the BREQOE bit in BCR1 to 1.
(6)
BREQO Output Timing
When the BREQOE bit is set to 1 and the BREQO signal is output, both the BREQO and BACK
signals may go low simultaneously.
This will occur if the next external access request occurs while internal bus arbitration is in
progress after the chip samples a low level of the BREQ signal.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
(7)
Refresh Settings
In single-chip activation mode, the setting of the RFSHE bit in REFCR should be made after
setting the EXPE bit in SYSCR to 1. For SYSCR, see section 3, MCU Operating Modes.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
(8)
Refresh Timer Settings
The setting of bits RTCK2 to RTCK0 in REFCR should be made after RTCNT and RTCOR have
been set. When changing RTCNT and RTCOR, the counter operation should be halted. When
changing bits RTCK2 to RTCK0, external access and external bus release by the EXDMAC
should be prohibited. The write data buffer function should be used after the write data buffer
function is disabled and the external space is read.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
(9)
Switching Between Refresh Timer and Interval Timer
When changing the RFSHE bit in REFCR from 1 to 0, a refresh cycle may be inserted until the bit
change is reflected. After this, when using RTCNT as an interval timer, the compare match flag
(CMF) may be set to 1. Therefore, confirm the state before setting the CMIE bit to 1.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
(10) RAS Down Mode and Software Standby Mode for DRAM Interface
When making a transition to software standby mode with the OPE bit in SBYCR set to 0 without
using the self-refresh mode, the transition should be made in RAS up mode (RCDM = 0). When
RAS down mode (RCDM = 1) is used, execute the SLEEP instruction after setting the RCDM bit
to 0. RAS down mode should be set again after recovery from software standby mode. For
SBYCR, see section 27, Power-Down Modes.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
(11) RAS Down Mode and Clock Frequencies Setting for DRAM/SDRAM
Write access to SCKCR for setting the clock frequencies should be performed in RAS up mode
(RCDM = 0). When RAS down mode (RCDM = 1) is used, set the RCDM bit to 0 before writing
to SCKCR. RAS down mode should be set again after clock frequencies are set. For SCKCR, see
section 26, Clock Pulse Generator.
Note: Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
(12) Cluster Transfer to SDRAM Space
Cluster transfer mode is available for the SDRAM with CAS latency of 2. When the SDRAM is
used in cluster transfer mode, the SDRAM with CAS latency of 2 should be used. In cluster
transfer mode, the write-precharge output delay function by the TRWL bit is not available. The
TRWL bit must be cleared to 0.
Note:
Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
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Section 9 Bus Controller (BSC)
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Section 10 DMA Controller (DMAC)
Section 10 DMA Controller (DMAC)
This LSI includes a 4-channel DMA controller (DMAC).
10.1
Features
• Maximum of 4-G byte address space can be accessed
• Byte, word, or longword can be set as data transfer unit
• Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size
Supports free-running mode in which total transfer size setting is not needed
• DMAC activation methods are auto-request, on-chip module interrupt, and external request.
Auto request:
CPU activates (cycle stealing or burst access can be selected)
On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected
as an activation source
External request:
Low level or falling edge detection of the DACK signal can be
selected. External request is available for all four channels.
• Dual or single address mode can be selected as address mode
Dual address mode: Both source and destination are specified by addresses
Single address mode: Either source or destination is specified by the DACK signal and the
other is specified by address
• Normal, repeat, or block transfer can be selected as transfer mode
Normal transfer mode:
One byte, one word, or one longword data is transferred at a
single transfer request
Repeat transfer mode:
One byte, one word, or one longword data is transferred at a
single transfer request
Repeat size of data is transferred and then a transfer address
returns to the transfer start address
Up to 65536 transfers (65,536 bytes/words/longwords) can be set
as repeat size
Block transfer mode:
One block data is transferred at a single transfer request
Up to 65,536 bytes/words/longwords can be set as block size
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Section 10 DMA Controller (DMAC)
• Extended repeat area function which repeats the addressees within a specified area using the
transfer address with the fixed upper bits (ring buffer transfer can be performed, as an
example) is available
One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as
extended repeat areas
• Address update can be selected from fixed address, offset addition, and increment or
decrement by 1, 2, or 4
Address update by offset addition enables to transfer data at addresses which are not placed
continuously
• Word or longword data can be transferred to an address which is not aligned with the
respective boundary
Data is divided according to its address (byte or word) when it is transferred
• Two types of interrupts can be requested to the CPU
A transfer end interrupt is generated after the number of data specified by the transfer counter
is transferred. A transfer escape end interrupt is generated when the remaining total transfer
size is less than the transfer data size at a single transfer request, when the repeat size of data
transfer is completed, or when the extended repeat area overflows.
• Module stop state can be set.
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Section 10 DMA Controller (DMAC)
A block diagram of the DMAC is shown in figure 10.1.
Internal data bus
Internal address bus
External pins
DREQn
Data buffer
DACKn
TENDn
Interrupt signals
requested to the
CPU by each
channel
Internal activation sources
...
Controller
Address buffer
Operation unit
Operation unit
DOFR_n
DSAR_n
Internal activation
source detector
DMRSR_n
DDAR_n
DMDR_n
DTCR_n
DACR_n
DBSR_n
Module data bus
[Legend]
DSAR_n:
DDAR_n:
DOFR_n:
DTCR_n:
DBSR_n:
DMDR_n:
DACR_n:
DMRSR_n:
DMA source address register
DMA destination address register
DMA offset register
DMA transfer count register
DMA block size register
DMA mode control register
DMA address control register
DMA module request select register
DREQn: DMA transfer request
DACKn: DMA transfer acknowledge
TENDn: DMA transfer end
n = 0 to 3
Figure 10.1 Block Diagram of DMAC
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Section 10 DMA Controller (DMAC)
10.2
Input/Output Pins
Table 10.1 shows the pin configuration of the DMAC.
Table 10.1 Pin Configuration
Channel
Pin Name
Abbr.
I/O
Function
0
DMA transfer request 0
DREQ0
Input
Channel 0 external request
DMA transfer acknowledge 0
DACK0
Output
Channel 0 single address transfer
acknowledge
DMA transfer end 0
TEND0
Output
Channel 0 transfer end
DMA transfer request 1
DREQ1
Input
Channel 1 external request
DMA transfer acknowledge 1
DACK1
Output
Channel 1 single address transfer
acknowledge
DMA transfer end 1
TEND1
Output
Channel 1 transfer end
DMA transfer request 2
DREQ2
Input
Channel 2 external request
DMA transfer acknowledge 2
DACK2
Output
Channel 2 single address transfer
acknowledge
DMA transfer end 2
TEND2
Output
Channel 2 transfer end
DMA transfer request 3
DREQ3
Input
Channel 3 external request
DMA transfer acknowledge 3
DACK3
Output
Channel 3 single address transfer
acknowledge
DMA transfer end 3
TEND3
Output
Channel 3 transfer end
1
2
3
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Section 10 DMA Controller (DMAC)
10.3
Register Descriptions
The DMAC has the following registers.
Channel 0:
•
•
•
•
•
•
•
•
DMA source address register_0 (DSAR_0)
DMA destination address register_0 (DDAR_0)
DMA offset register_0 (DOFR_0)
DMA transfer count register_0 (DTCR_0)
DMA block size register_0 (DBSR_0)
DMA mode control register_0 (DMDR_0)
DMA address control register_0 (DACR_0)
DMA module request select register_0 (DMRSR_0)
Channel 1:
•
•
•
•
•
•
•
•
DMA source address register_1 (DSAR_1)
DMA destination address register_1 (DDAR_1)
DMA offset register_1 (DOFR_1)
DMA transfer count register_1 (DTCR_1)
DMA block size register_1 (DBSR_1)
DMA mode control register_1 (DMDR_1)
DMA address control register_1 (DACR_1)
DMA module request select register_1 (DMRSR_1)
Channel 2:
•
•
•
•
•
•
•
•
DMA source address register_2 (DSAR_2)
DMA destination address register_2 (DDAR_2)
DMA offset register_2 (DOFR_2)
DMA transfer count register_2 (DTCR_2)
DMA block size register_2 (DBSR_2)
DMA mode control register_2 (DMDR_2)
DMA address control register_2 (DACR_2)
DMA module request select register_2 (DMRSR_2)
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Section 10 DMA Controller (DMAC)
Channel 3:
•
•
•
•
•
•
•
•
DMA source address register_3 (DSAR_3)
DMA destination address register_3 (DDAR_3)
DMA offset register_3 (DOFR_3)
DMA transfer count register_3 (DTCR_3)
DMA block size register_3 (DBSR_3)
DMA mode control register_3 (DMDR_3)
DMA address control register_3 (DACR_3)
DMA module request select register_3 (DMRSR_3)
10.3.1
DMA Source Address Register (DSAR)
DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR
updates the transfer source address every time data is transferred. When DDAR is specified as the
destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored.
Although DSAR can always be read from by the CPU, it must be read from in longwords and
must not be written to while data for the channel is being transferred.
Bit
31
30
29
28
27
26
25
24
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 10 DMA Controller (DMAC)
10.3.2
DMA Destination Address Register (DDAR)
DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR
updates the transfer destination address every time data is transferred. When DSAR is specified as
the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored.
Although DDAR can always be read from by the CPU, it must be read from in longwords and
must not be written to while data for the channel is being transferred.
Bit
31
30
29
28
27
26
25
24
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 10 DMA Controller (DMAC)
10.3.3
DMA Offset Register (DOFR)
DOFR is a 32-bit readable/writable register that specifies the offset to update the source and
destination addresses. Although different values are specified for individual channels, the same
values must be specified for the source and destination sides of a single channel.
Bit
31
30
29
28
27
26
25
24
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 10 DMA Controller (DMAC)
10.3.4
DMA Transfer Count Register (DTCR)
DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total
transfer size).
To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register,
it means that the total transfer size is not specified and data is transferred with the transfer counter
stopped (free running mode). When H'FFFFFFFF is set, the total transfer size is 4 Gbytes
(4,294,967,295), which is the maximum size. While data is being transferred, this register
indicates the remaining transfer size. The value corresponding to its data access size is subtracted
every time data is transferred (byte: −1, word: −2, and longword: −4).
Although DTCR can always be read from by the CPU, it must be read from in longwords and
must not be written to while data for the channel is being transferred.
Bit
31
30
29
28
27
26
25
24
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 10 DMA Controller (DMAC)
10.3.5
DMA Block Size Register (DBSR)
DBSR specifies the repeat size or block size. DBSR is enabled in repeat transfer mode and block
transfer mode and is disabled in normal transfer mode.
Bit
Bit Name
31
30
29
28
27
26
25
24
BKSZH31
BKSZH30
BKSZH29
BKSZH28
BKSZH27
BKSZH26
BKSZH25
BKSZH24
Initial Value
R/W
Bit
Bit Name
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
22
21
20
19
18
17
16
BKSZH22
BKSZH21
BKSZH20
BKSZH19
BKSZH18
BKSZH17
BKSZH16
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
BKSZ15
BKSZ14
BKSZ13
BKSZ12
BKSZ11
BKSZ10
BKSZ9
BKSZ8
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
BKSZ7
BKSZ6
BKSZ5
BKSZ4
BKSZ3
BKSZ2
BKSZ1
BKSZ0
Initial Value
R/W
Bit
0
R/W
23
R/W
Bit Name
0
R/W
BKSZH23
Initial Value
Bit Name
0
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Initial
Value
R/W
Description
31 to 16 BKSZH31 to All 0
BKSZH16
R/W
Specify the repeat size or block size.
15 to 0
R/W
BKSZ15 to
BKSZ0
All 0
When H'0001 is set, the repeat or block size is one byte,
one word, or one longword. When H'0000 is set, it
means the maximum value (refer to table 10.1). While
the DMA is in operation, the setting is fixed.
Rev. 2.00 Jul. 31, 2008 Page 392 of 1438
REJ09B0365-0200
Indicate the remaining repeat or block size while the
DMA is in operation. The value is decremented by 1
every time data is transferred. When the remaining size
becomes 0, the value of the BKSZH bits is loaded. Set
the same value as the BKSZH bits.
Section 10 DMA Controller (DMAC)
Table 10.2 Data Access Size, Valid Bits, and Settable Size
Mode
Data Access Size BKSZH Valid Bits BKSZ Valid Bits
Byte
Repeat transfer
and block transfer Word
31 to 16
15 to 0
1 to 65,536
2 to 131,072
Longword
10.3.6
Settable Size
(Byte)
4 to 262,144
DMA Mode Control Register (DMDR)
DMDR controls the DMAC operation.
• DMDR_0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
31
30
29
28
27
26
25
24
DTE
DACKE
TENDE

DREQS
NRD


0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
23
22
21
20
19
18
17
16
ACT



ERRF

ESIF
DTIF
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R/(W)*
R
R/(W)*
R/(W)*
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: *
15
14
13
12
11
10
9
8
DTSZ1
DTSZ0
MDS1
MDS0
TSEIE

ESIE
DTIE
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
7
6
5
4
3
2
1
0
DTF1
DTF0
DTA


DMAP2
DMAP1
DMAP0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Only 0 can be written to this bit after having been read as 1, to clear the flag.
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Section 10 DMA Controller (DMAC)
• DMDR_1 to DMDR_3
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
31
30
29
28
27
26
25
24
DTE
DACKE
TENDE

DREQS
NRD


0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
23
22
21
20
19
18
17
16
ACT





ESIF
DTIF
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R/(W)*
R/(W)*
Bit
Bit Name
15
14
13
12
11
10
9
8
DTSZ1
DTSZ0
MDS1
MDS0
TSEIE

ESIE
DTIE
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: *
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
7
6
5
4
3
2
1
0
DTF1
DTF0
DTA


DMAP2
DMAP1
DMAP0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Only 0 can be written to this bit after having been read as 1, to clear the flag.
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
31
DTE
0
R/W
Data Transfer Enable
Enables/disables a data transfer for the corresponding
channel. When this bit is set to 1, it indicates that the
DMAC is in operation.
Setting this bit to 1 starts a transfer when the autorequest is selected. When the on-chip module interrupt
or external request is selected, a transfer request after
setting this bit to 1 starts the transfer. While data is
being transferred, clearing this bit to 0 stops the
transfer.
In block transfer mode, if writing 0 to this bit while data is
being transferred, this bit is cleared to 0 after the current
1-block size data transfer.
If an event which stops (sustains) a transfer occurs
externally, this bit is automatically cleared to 0 to stop
the transfer.
Operating modes and transfer methods must not be
changed while this bit is set to 1.
0: Disables a data transfer
1: Enables a data transfer (DMA is in operation)
[Clearing conditions]
•
When the specified total transfer size of transfers is
completed
•
When a transfer is stopped by an overflow interrupt
by a repeat size end
•
When a transfer is stopped by an overflow interrupt
by an extended repeat size end
•
When a transfer is stopped by a transfer size error
interrupt
•
When clearing this bit to 0 to stop a transfer
In block transfer mode, this bit changes after the current
block transfer.
•
When an address error or an NMI interrupt is
requested
•
In the reset state or hardware standby mode
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
30
DACKE
0
R/W
DACK Signal Output Enable
Enables/disables the DACK signal output in single
address mode. This bit is ignored in dual address mode.
0: Disables DACK signal output
1: Enables DACK signal output
29
TENDE
0
R/W
TEND Signal Output Enable
Enables/disables the TEND signal output.
0: Disables TEND signal output
1: Enables TEND signal output
28

0
R/W
Reserved
Initial value should not be changed.
27
DREQS
0
R/W
DREQ Select
Selects whether a low level or the falling edge of the
DREQ signal used in external request mode is detected.
0: Low level detection
1: Falling edge detection (the first transfer after a
transfer enabled is detected on a low level)
26
NRD
0
R/W
Next Request Delay
Selects the accepting timing of the next transfer request.
0: Starts accepting the next transfer request after
completion of the current transfer
1: Starts accepting the next transfer request one cycle
after completion of the current transfer
25, 24

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
23
ACT
0
R
Active State
Indicates the operating state for the channel.
0: Waiting for a transfer request or a transfer disabled
state by clearing the DTE bit to 0
1: Active state
22 to 20 
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
19
ERRF
0
R/(W)* System Error Flag
Description
Indicates that an address error or an NMI interrupt has
been generated. This bit is available only in DMDR_0.
Setting this bit to 1 prohibits writing to the DTE bit for all
the channels. This bit is reserved in DMDR_1 to
DMDR_3. It is always read as 0 and cannot be modified.
0: An address error or an NMI interrupt has not been
generated
1: An address error or an NMI interrupt has been
generated
[Clearing condition]
•
When clearing to 0 after reading ERRF = 1
[Setting condition]
•
When an address error or an NMI interrupt has been
generated
However, when an address error or an NMI interrupt has
been generated in DMAC module stop mode, this bit is
not set to 1.
18

0
R
Reserved
This bit is always read as 0 and cannot be modified.
17
ESIF
0
R/(W)* Transfer Escape Interrupt Flag
Indicates that a transfer escape end interrupt has been
requested. A transfer escape end means that a transfer
is terminated before the transfer counter reaches 0.
0: A transfer escape end interrupt has not been
requested
1: A transfer escape end interrupt has been requested
[Clearing conditions]
•
When setting the DTE bit to 1
•
When clearing to 0 before reading ESIF = 1
[Setting conditions]
•
When a transfer size error interrupt is requested
•
When a repeat size end interrupt is requested
•
When a transfer end interrupt by an extended repeat
area overflow is requested
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
16
DTIF
0
R/(W)* Data Transfer Interrupt Flag
Description
Indicates that a transfer end interrupt by the transfer
counter has been requested.
0: A transfer end interrupt by the transfer counter has
not been requested
1: A transfer end interrupt by the transfer counter has
been requested
[Clearing conditions]
•
When setting the DTE bit to 1
•
When clearing to 0 after reading DTIF = 1
[Setting condition]
•
When DTCR reaches 0 and the transfer is
completed
15
DTSZ1
0
R/W
Data Access Size 1 and 0
14
DTSZ0
0
R/W
Select the data access size for a transfer.
00: Byte size (eight bits)
01: Word size (16 bits)
10: Longword size (32 bits)
11: Setting prohibited
13
MDS1
0
R/W
Transfer Mode Select 1 and 0
12
MDS0
0
R/W
Select the transfer mode.
00: Normal transfer mode
01: Block transfer mode
10: Repeat transfer mode
11: Setting prohibited
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
11
TSEIE
0
R/W
Transfer Size Error Interrupt Enable
Enables/disables a transfer size error interrupt.
When the next transfer is requested while this bit is set
to 1 and the contents of the transfer counter is less than
the size of data to be transferred at a single transfer
request, the DTE bit is cleared to 0. At this time, the
ESIF bit is set to 1 to indicate that a transfer size error
interrupt has been requested.
The sources of a transfer size error are as follows:
•
In normal or repeat transfer mode, the total transfer
size set in DTCR is less than the data access size
•
In block transfer mode, the total transfer size set in
DTCR is less than the block size
0: Disables a transfer size error interrupt request
1: Enables a transfer size error interrupt request
10

0
R
Reserved
This bit is always read as 0 and cannot be modified.
9
ESIE
0
R/W
Transfer Escape Interrupt Enable
Enables/disables a transfer escape end interrupt
request. When the ESIF bit is set to 1 with this bit set to
1, a transfer escape end interrupt is requested to the
CPU or DTC. The transfer end interrupt request is
cleared by clearing this bit or the ESIF bit to 0.
0: Disables a transfer escape end interrupt
1: Enables a transfer escape end interrupt
8
DTIE
0
R/W
Data Transfer End Interrupt Enable
Enables/disables a transfer end interrupt request by the
transfer counter. When the DTIF bit is set to 1 with this
bit set to 1, a transfer end interrupt is requested to the
CPU or DTC. The transfer end interrupt request is
cleared by clearing this bit or the DTIF bit to 0.
0: Disables a transfer end interrupt
1: Enables a transfer end interrupt
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
7
DTF1
0
R/W
Data Transfer Factor 1 and 0
6
DTF0
0
R/W
Select a DMAC activation source. When the on-chip
peripheral module setting is selected, the interrupt
source should be selected by DMRSR. When the
external request setting is selected, the sampling
method should be selected by the DREQS bit.
00: Auto request (cycle stealing)
01: Auto request (burst access)
10: On-chip module interrupt
11: External request
5
DTA
0
R/W
Data Transfer Acknowledge
This bit is valid in DMA transfer by the on-chip module
interrupt source. This bit enables or disables to clear the
source flag selected by DMRSR.
0: To clear the source in DMA transfer is disabled.
Since the on-chip module interrupt source is not
cleared in DMA transfer, it should be cleared by the
CPU or DTC transfer.
1: To clear the source in DMA transfer is enabled.
Since the on-chip module interrupt source is cleared
in DMA transfer, it does not require an interrupt by
the CPU or DTC transfer.
4, 3

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
2
DMAP2
0
R/W
DMA Priority Level 2 to 0
1
DMAP1
0
R/W
0
DMAP0
0
R/W
Select the priority level of the DMAC when using the
CPU priority control function over DTC and DMAC.
When the CPU has priority over the DMAC, the DMAC
masks a transfer request and waits for the timing when
the CPU priority becomes lower than the DMAC priority.
The priority levels can be set to the individual channels.
This bit is valid when the CPUPCE bit in CPUPCR is set
to 1.
000: Priority level 0 (low)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (high)
Note:
*
Only 0 can be written to, to clear the flag.
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Section 10 DMA Controller (DMAC)
10.3.7
DMA Address Control Register (DACR)
DACR specifies the operating mode and transfer method.
Bit
Bit Name
Initial Value
31
30
29
28
27
26
25
24
AMS
DIRS



RPTIE
ARS1
ARS0
0
0
0
0
0
0
0
0
R/W
R/W
R
R
R
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
16
Bit Name


SAT1
SAT0


DAT1
DAT0
R/W
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R
R
R/W
R/W
15
14
13
12
11
10
9
8
SARIE


SARA4
SARA3
SARA2
SARA1
SARA0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
DARIE


DARA4
DARA3
DARA2
DARA1
DARA0
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31
AMS
0
R/W
Address Mode Select
Selects address mode from single or dual address
mode. In single address mode, the DACK pin is enabled
according to the DACKE bit.
0: Dual address mode
1: Single address mode
30
DIRS
0
R/W
Single Address Direction Select
Specifies the data transfer direction in single address
mode. This bit s ignored in dual address mode.
0: Specifies DSAR as source address
1: Specifies DDAR as destination address
29 to 27 
0
R/W
Reserved
These bits are always read as 0 and cannot be
modified.
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
26
RPTIE
0
R/W
25
24
ARS1
ARS0
0
0
R/W
R/W
Repeat Size End Interrupt Enable
Enables/disables a repeat size end interrupt request.
In repeat transfer mode, when the next transfer is
requested after completion of a 1-repeat-size data
transfer while this bit is set to 1, the DTE bit in DMDR is
cleared to 0. At this time, the ESIF bit in DMDR is set to
1 to indicate that a repeat size end interrupt is
requested. Even when the repeat area is not specified
(ARS1 = 1 and ARS0 = 0), a repeat size end interrupt
after a 1-block data transfer can be requested.
In addition, in block transfer mode, when the next
transfer is requested after 1-block data transfer while
this bit is set to 1, the DTE bit in DMDR is cleared to 0.
At this time, the ESIF bit in DMDR is set to 1 to indicate
that a repeat size end interrupt is requested.
0: Disables a repeat size end interrupt
1: Enables a repeat size end interrupt
Area Select 1 and 0
Specify the block area or repeat area in block or repeat
transfer mode.
00: Specify the block area or repeat area on the source
address
01: Specify the block area or repeat area on the
destination address
10: Do not specify the block area or repeat area
11: Setting prohibited
23, 22

All 0
R
21
20
SAT1
SAT0
0
0
R/W
R/W
Reserved
These bits are always read as 0 and cannot be
modified.
Source Address Update Mode 1 and 0
Select the update method of the source address
(DSAR). When DSAR is not specified as the transfer
source in single address mode, this bit is ignored.
00: Source address is fixed
01: Source address is updated by adding the offset
10: Source address is updated by adding 1, 2, or 4
according to the data access size
11: Source address is updated by subtracting 1, 2, or 4
according to the data access size
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
19, 18

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
17
DAT1
0
R/W
Destination Address Update Mode 1 and 0
16
DAT0
0
R/W
Select the update method of the destination address
(DDAR). When DDAR is not specified as the transfer
destination in single address mode, this bit is ignored.
00: Destination address is fixed
01: Destination address is updated by adding the offset
10: Destination address is updated by adding 1, 2, or 4
according to the data access size
11: Destination address is updated by subtracting 1, 2,
or 4 according to the data access size
15
SARIE
0
R/W
Interrupt Enable for Source Address Extended Area
Overflow
Enables/disables an interrupt request for an extended
area overflow on the source address.
When an extended repeat area overflow on the source
address occurs while this bit is set to 1, the DTE bit in
DMDR is cleared to 0. At this time, the ESIF bit in
DMDR is set to 1 to indicate an interrupt by an extended
repeat area overflow on the source address is
requested.
When block transfer mode is used with the extended
repeat area function, an interrupt is requested after
completion of a 1-block size transfer. When setting the
DTE bit in DMDR of the channel for which a transfer has
been stopped to 1, the transfer is resumed from the
state when the transfer is stopped.
When the extended repeat area is not specified, this bit
is ignored.
0: Disables an interrupt request for an extended area
overflow on the source address
1: Enables an interrupt request for an extended area
overflow on the source address
14, 13

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
12
SARA4
0
R/W
Source Address Extended Repeat Area
11
SARA3
0
R/W
10
SARA2
0
R/W
9
SARA1
0
R/W
8
SARA0
0
R/W
Specify the extended repeat area on the source address
(DSAR). With the extended repeat area, the specified
lower address bits are updated and the remaining upper
address bits are fixed. The extended repeat area size is
specified from four bytes to 128 Mbytes in units of byte
and a power of 2.
When the lower address is overflowed from the
extended repeat area by address update, the address
becomes the start address and the end address of the
area for address addition and subtraction, respectively.
When an overflow in the extended repeat area occurs
with the SARIE bit set to 1, an interrupt can be
requested. Table 10.3 shows the settings and areas of
the extended repeat area.
7
DARIE
0
R/W
Destination Address Extended Repeat Area Overflow
Interrupt Enable
Enables/disables an interrupt request for an extended
area overflow on the destination address.
When an extended repeat area overflow on the
destination address occurs while this bit is set to 1, the
DTE bit in DMDR is cleared to 0. At this time, the ESIF
bit in DMDR is set to 1 to indicate an interrupt by an
extended repeat area overflow on the destination
address is requested.
When block transfer mode is used with the extended
repeat area function, an interrupt is requested after
completion of a 1-block size transfer. When setting the
DTE bit in DMDR of the channel for which the transfer
has been stopped to 1, the transfer is resumed from the
state when the transfer is stopped.
When the extended repeat area is not specified, this bit
is ignored.
0: Disables an interrupt request for an extended area
overflow on the destination address
1: Enables an interrupt request for an extended area
overflow on the destination address
6, 5

All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
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Section 10 DMA Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
4
DARA4
0
R/W
Destination Address Extended Repeat Area
3
DARA3
0
R/W
2
DARA2
0
R/W
1
DARA1
0
R/W
0
DARA0
0
R/W
Specify the extended repeat area on the destination
address (DDAR). With the extended repeat area, the
specified lower address bits are updated and the
remaining upper address bits are fixed. The extended
repeat area size is specified from four bytes to 128
Mbytes in units of byte and a power of 2.
When the lower address is overflowed from the
extended repeat area by address update, the address
becomes the start address and the end address of the
area for address addition and subtraction, respectively.
When an overflow in the extended repeat area occurs
with the DARIE bit set to 1, an interrupt can be
requested. Table 10.3 shows the settings and areas of
the extended repeat area.
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Section 10 DMA Controller (DMAC)
Table 10.3 Settings and Areas of Extended Repeat Area
SARA4 to
SARA0 or
DARA4 to
DARA0
Extended Repeat Area
00000
Not specified
00001
2 bytes specified as extended repeat area by the lower 1 bit of the address
00010
4 bytes specified as extended repeat area by the lower 2 bits of the address
00011
8 bytes specified as extended repeat area by the lower 3 bits of the address
00100
16 bytes specified as extended repeat area by the lower 4 bits of the address
00101
32 bytes specified as extended repeat area by the lower 5 bits of the address
00110
64 bytes specified as extended repeat area by the lower 6 bits of the address
00111
128 bytes specified as extended repeat area by the lower 7 bits of the address
01000
256 bytes specified as extended repeat area by the lower 8 bits of the address
01001
512 bytes specified as extended repeat area by the lower 9 bits of the address
01010
1 Kbyte specified as extended repeat area by the lower 10 bits of the address
01011
2 Kbytes specified as extended repeat area by the lower 11 bits of the address
01100
4 Kbytes specified as extended repeat area by the lower 12 bits of the address
01101
8 Kbytes specified as extended repeat area by the lower 13 bits of the address
01110
16 Kbytes specified as extended repeat area by the lower 14 bits of the address
01111
32 Kbytes specified as extended repeat area by the lower 15 bits of the address
10000
64 Kbytes specified as extended repeat area by the lower 16 bits of the address
10001
128 Kbytes specified as extended repeat area by the lower 17 bits of the address
10010
256 Kbytes specified as extended repeat area by the lower 18 bits of the address
10011
512 Kbytes specified as extended repeat area by the lower 19 bits of the address
10100
1 Mbyte specified as extended repeat area by the lower 20 bits of the address
10101
2 Mbytes specified as extended repeat area by the lower 21 bits of the address
10110
4 Mbytes specified as extended repeat area by the lower 22 bits of the address
10111
8 Mbytes specified as extended repeat area by the lower 23 bits of the address
11000
16 Mbytes specified as extended repeat area by the lower 24 bits of the address
11001
32 Mbytes specified as extended repeat area by the lower 25 bits of the address
11010
64 Mbytes specified as extended repeat area by the lower 26 bits of the address
11011
128 Mbytes specified as extended repeat area by the lower 27 bits of the address
111××
Setting prohibited
[Legend]
×: Don't care
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Section 10 DMA Controller (DMAC)
10.3.8
DMA Module Request Select Register (DMRSR)
DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source.
The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no
interrupt source. For the vector numbers of the interrupt sources, refer to table 10.5.
Bit
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Initial Value
R/W
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Section 10 DMA Controller (DMAC)
10.4
Transfer Modes
Table 10.4 shows the DMAC transfer modes. The transfer modes can be specified to the
individual channels.
Table 10.4 Transfer Modes
Address Register
Address
Mode
Transfer mode
Dual
address
•
Normal transfer
•
Repeat transfer
•
Activation Source
Common Function
Source
Destination
•
•
DSAR
DDAR
On-chip module
interrupt
Total transfer
size: 1 to 4
Gbytes or not
specified
•
Offset addition
External request
•
Extended repeat
area function
DSAR/
DACK
DACK/
DDAR
Block transfer
Repeat or block size •
= 1 to 65,536 bytes,
1 to 65,536 words, or •
1 to 65,536
longwords
Single
address
Auto request
(activated by
CPU)
•
Instead of specifying the source or destination address
registers, data is directly transferred from/to the external
device using the DACK pin
•
The same settings as above are available other than address
register setting (e.g., above transfer modes can be specified)
•
One transfer can be performed in one bus cycle (the types of
transfer modes are the same as those of dual address modes)
When the auto request setting is selected as the activation source, the cycle stealing or burst access
can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer
counter is stopped and the transfer is continued without the limitation of the transfer count.
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Section 10 DMA Controller (DMAC)
10.5
Operations
10.5.1
Address Modes
(1)
Dual Address Mode
In dual address mode, the transfer source address is specified in DSAR and the transfer destination
address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data
bus width is less than the data access size or the access address is not aligned with the boundary of
the data access size, the number of bus cycles are needed more than two because one bus cycle is
divided into multiple bus cycles).
In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data
is written to the transfer destination address.
The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters,
refresh cycle, and external bus release cycle) are not generated between read and write cycles.
The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is
output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is
also output in the idle cycle. The DACK signal is not output.
Figure 10.2 shows an example of the signal timing in dual address mode and figure 10.3 shows the
operation in dual address mode.
DMA read
cycle
DMA write
cycle
DSAR
DDAR
Bφ
Address bus
RD
WR
TEND
Figure 10.2 Example of Signal Timing in Dual Address Mode
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Section 10 DMA Controller (DMAC)
Transfer
Address TA
Address TB
Address update setting is as follows:
Source address increment
Fixed destination address
Address BA
Figure 10.3 Operations in Dual Address Mode
(2)
Single Address Mode
In single address mode, data between an external device and an external memory is directly
transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in
one bus cycle. In this mode, the data bus width must be the same as the data access size. For
details on the data bus width, see section 9, Bus Controller (BSC).
The DMAC accesses an external device as the transfer source or destination by outputting the
strobe signal (DACK) to the external device with DACK and accesses the other transfer target by
outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 10.4
shows an example of a transfer between an external memory and an external device with the
DACK pin. In this example, the external device outputs data on the data bus and the data is written
to the external memory in the same bus cycle.
The transfer direction is decided by the DIRS bit in DACR which specifies an external device with
the DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an
external memory (DSAR) to an external device with the DACK pin. When DIRS = 1, data is
transferred from an external device with the DACK pin to an external memory (DDAR). The
settings of registers which are not used as the transfer source or destination are ignored.
The DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The
DACK signal is low active.
The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is
output in one bus cycle. When an idle cycle is inserted before the bus cycle, the TEND signal is
also output in the idle cycle.
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Section 10 DMA Controller (DMAC)
Figure 10.5 shows an example of timing charts in single address mode and figure 10.6 shows an
example of operation in single address mode.
External
address
bus
External
data
bus
LSI
External
memory
DMAC
Data flow
External device
with DACK
DACK
DREQ
Figure 10.4 Data Flow in Single Address Mode
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Section 10 DMA Controller (DMAC)
Transfer from external memory to external device with DACK
DMA cycle
Bφ
Address bus
Address for external memory space
DSAR
RD
RD signal for external memory space
WR
High
DACK
Data output by external memory
Data bus
TEND
Transfer from external device with DACK to external memory
DMA cycle
Bφ
Address bus
RD
Address for external memory space
DDAR
High
WR
WR signal for external memory space
DACK
Data output by external device with DACK
Data bus
TEND
Figure 10.5 Example of Signal Timing in Single Address Mode
Address T
DACK
Transfer
Address B
Figure 10.6 Operations in Single Address Mode
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Section 10 DMA Controller (DMAC)
10.5.2
(1)
Transfer Modes
Normal Transfer Mode
In normal transfer mode, one data access size of data is transferred at a single transfer request. Up
to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer
mode.
The TEND signal is output only in the last DMA transfer. The DACK signal is output every time a
transfer request is received and a transfer starts.
Figure 10.7 shows an example of the signal timing in normal transfer mode and figure 10.8 shows
the operation in normal transfer mode.
Auto request transfer in dual address mode:
Bus cycle
DMA transfer
cycle
Last DMA
transfer cycle
Read
Read
Write
Write
TEND
External request transfer in single address mode:
DREQ
Bus cycle
DMA
DMA
DACK
Figure 10.7 Example of Signal Timing in Normal Transfer Mode
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Section 10 DMA Controller (DMAC)
Transfer
Address TA
Address TB
Total transfer
size (DTCR)
Address BA
Address BB
Figure 10.8 Operations in Normal Transfer Mode
(2)
Repeat Transfer Mode
In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up
to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in
DBSR up to 65536 × data access size.
The repeat area can be specified for the source or destination address side by bits ARS1 and ARS0
in DACR. The address specified as the repeat area returns to the transfer start address when the
repeat size of transfers is completed. This operation is repeated until the total transfer size
specified in DTCR is completed. When H'00000000 is specified in DTCR, it is regarded as the
free running mode and repeat transfer is continued until the DTE bit in DMDR is cleared to 0.
In addition, a DMA transfer can be stopped and a repeat size end interrupt can be requested to the
CPU or DTC when the repeat size of transfers is completed. When the next transfer is requested
after completion of a 1-repeat size data transfer while the RPTIE bit is set to 1, the DTE bit in
DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1 to complete the transfer. At this time,
an interrupt is requested to the CPU or DTC when the ESIE bit in DMDR is set to 1.
The timings of the TEND and DACK signals are the same as in normal transfer mode.
Figure 10.9 shows the operation in repeat transfer mode while dual address mode is set.
When the repeat area is specified as neither source nor destination address side, the operation is
the same as the normal transfer mode operation shown in figure 10.8. In this case, a repeat size
end interrupt can also be requested to the CPU when the repeat size of transfers is completed.
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Section 10 DMA Controller (DMAC)
Transfer
Address TA
Address TB
Repeat size =
BKSZH ×
data access size
Total transfer
size (DTCR)
Address BA
Operation when the repeat area is specified
to the source side
Address BB
Figure 10.9 Operations in Repeat Transfer Mode
(3)
Block Transfer Mode
In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4
Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR
up to 65536 × data access size.
While one block of data is being transferred, transfer requests from other channels are suspended.
When the transfer is completed, the bus is released to the other bus master.
The block area can be specified for the source or destination address side by bits ARS1 and ARS0
in DACR. The address specified as the block area returns to the transfer start address when the
block size of data is completed. When the block area is specified as neither source nor destination
address side, the operation continues without returning the address to the transfer start address. A
repeat size end interrupt can be requested.
The TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle.
When an interrupt request by an extended repeat area overflow is used in block transfer mode,
settings should be selected carefully. For details, see section 10.5.5, Extended Repeat Area
Function.
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Section 10 DMA Controller (DMAC)
Figure 10.10 shows an example of the DMA transfer timing in block transfer mode. The transfer
conditions are as follows:
• Address mode: single address mode
• Data access size: byte
• 1-block size: three bytes
The block transfer mode operations in single address mode and in dual address mode are shown in
figures 10.11 and 10.12, respectively.
DREQ
Transfer cycles for one block
Bus cycle
CPU
CPU
DMAC
DMAC
DMAC
CPU
No CPU cycle generated
TEND
Figure 10.10 Operations in Block Transfer Mode
Address T
Transfer
Block
BKSZH ×
data access size
DACK
Address B
Figure 10.11 Operation in Single Address Mode in Block Transfer Mode
(Block Area Specified)
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Section 10 DMA Controller (DMAC)
Address TB
Address TA
Transfer
First block
First block
BKSZH ×
data access size
Second block
Second block
Total transfer
size (DTCR)
Nth block
Nth block
Address BB
Address BA
Figure 10.12 Operation in Dual Address Mode in Block Transfer Mode
(Block Area Not Specified)
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Section 10 DMA Controller (DMAC)
10.5.3
Activation Sources
The DMAC is activated by an auto request, an on-chip module interrupt, and an external request.
The activation source is specified by bits DTF1 and DTF0 in DMDR.
(1)
Activation by Auto Request
The auto request activation is used when a transfer request from an external device or an on-chip
peripheral module is not generated such as a transfer between memory and memory or between
memory and an on-chip peripheral module which does not request a transfer. A transfer request is
automatically generated inside the DMAC. In auto request activation, setting the DTE bit in
DMDR starts a transfer. The bus mode can be selected from cycle stealing and burst modes.
(2)
Activation by On-Chip Module Interrupt
An interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is
used as a transfer request. When a DMA transfer is enabled (DTE = 1), the DMA transfer is
started by an on-chip module interrupt.
The activation source of the on-chip module interrupt is selected by the DMA module request
select register (DMRSR). The activation sources are specified to the individual channels. Table
10.5 is a list of on-chip module interrupts for the DMAC. The interrupt request selected as the
activation source can generate an interrupt request simultaneously to the CPU or DTC. For details,
refer to section 7, Interrupt Controller.
The DMAC receives interrupt requests by on-chip peripheral modules independent of the interrupt
controller. Therefore, the DMAC is not affected by priority given in the interrupt controller.
When the DMAC is activated while DTA = 1, the interrupt request flag is automatically cleared by
a DMA transfer. If multiple channels use a single transfer request as an activation source, when
the channel having priority is activated, the interrupt request flag is cleared. In this case, other
channels may not be activated because the transfer request is not held in the DMAC.
When the DMAC is activated while DTA = 0, the interrupt request flag is not cleared by the
DMAC and should be cleared by the CPU or DTC transfer.
When an activation source is selected while DTE = 0, the activation source does not request a
transfer to the DMAC. It requests an interrupt to the CPU or DTC.
In addition, make sure that an interrupt request flag as an on-chip module interrupt source is
cleared to 0 before writing 1 to the DTE bit.
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Section 10 DMA Controller (DMAC)
Table 10.5 List of On-chip module interrupts to DMAC
On-Chip Module Interrupt Source
On-Chip
Module
DMRSR
(Vector
Number)
ADI0 (conversion end interrupt for A/D converter unit 0)
A/D_0
86
TGI0A (TGI0A input capture/compare match)
TPU_0
88
TGI1A (TGI1A input capture/compare match)
TPU_1
93
TGI2A (TGI2A input capture/compare match)
TPU_2
97
TGI3A (TGI3A input capture/compare match)
TPU_3
101
TGI4A (TGI4A input capture/compare match)
TPU_4
106
TGI5A (TGI5A input capture/compare match)
TPU_5
110
RXI0 (receive data full interrupt for SCI channel 0)
SCI_0
145
TXI0 (transmit data empty interrupt for SCI channel 0)
SCI_0
146
RXI1 (receive data full interrupt for SCI channel 1)
SCI_1
149
TXI1 (transmit data empty interrupt for SCI channel 1)
SCI_1
150
RXI2 (receive data full interrupt for SCI channel 2)
SCI_2
153
TXI2 (transmit data empty interrupt for SCI channel 2)
SCI_2
154
RXI3 (receive data full interrupt for SCI channel 3)
SCI_3
157
TXI3 (transmit data empty interrupt for SCI channel 3)
SCI_3
158
RXI4 (receive data full interrupt for SCI channel 4)
SCI_4
161
TXI4 (transmit data empty interrupt for SCI channel 4)
SCI_4
162
TGI6A (TGI6A input capture/compare match)
TPU_6
164
TGI7A (TGI7A input capture/compare match)
TPU_7
169
TGI8A (TGI8A input capture/compare match)
TPU_8
173
TGI9A (TGI9A input capture/compare match)
TPU_9
177
TGI10A (TGI10A input capture/compare match)
TPU_10
182
TGI11A (TGI11A input capture/compare match)
TPU_11
188
RXI5 (receive data full interrupt for SCI channel 5)
SCI_5
220
TXI5 (transmit data empty interrupt for SCI channel 5)
SCI_5
221
RXI6 (receive data full interrupt for SCI channel 6)
SCI_6
224
TXI6 (transmit data empty interrupt for SCI channel 6)
SCI_6
225
ADI2 (conversion end interrupt for A/D converter unit 2)
A/D_2
232
ADI1 (conversion end interrupt for A/D converter unit 1)
A/D_1
237
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Section 10 DMA Controller (DMAC)
(3)
Activation by External Request
A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA
transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. When a DMA
transfer between on-chip peripheral modules is performed, select an activation source from the
auto request and on-chip module interrupt (the external request cannot be used).
A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling
edge or low level. Whether the falling edge or low level detection is used is selected by the
DREQS bit in DMDR.
When an external request is selected as an activation source, clear the DDR bit to 0 and set the
ICR bit to 1 for the corresponding pin. For details, see section 13, I/O Ports.
10.5.4
Bus Access Modes
There are two types of bus access modes: cycle stealing and burst.
When an activation source is the auto request, the cycle stealing or burst mode is selected by bit
DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request,
the cycle stealing mode is selected.
(1)
Cycle Stealing Mode
In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word,
longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC
obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This
operation is continued until the transfer end condition is satisfied.
When a transfer is requested to another channel during a DMA transfer, the DMAC releases the
bus and then transfers data for the requested channel. For details on operations when a transfer is
requested to multiple channels, see section 10.5.8, Priority of Channels.
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Section 10 DMA Controller (DMAC)
Figure 10.13 shows an example of timing in cycle stealing mode. The transfer conditions are as
follows:
• Address mode: Single address mode
• Sampling method of the DREQ signal: Low level detection
DREQ
Bus cycle
CPU
CPU
DMAC
CPU
DMAC
CPU
Bus released temporarily for the CPU
Figure 10.13 Example of Timing in Cycle Stealing Mode
(2)
Burst Access Mode
In burst mode, once it takes the bus, the DMAC continues a transfer without releasing the bus until
the transfer end condition is satisfied. Even if a transfer is requested from another channel having
priority, the transfer is not stopped once it is started. The DMAC releases the bus in the next cycle
after the transfer for the channel in burst mode is completed. This is similarly to operation in cycle
stealing mode. However, setting the IBCCS bit in BCR2 of the bus controller makes the DMAC
release the bus to pass the bus to another bus master.
In block transfer mode, the burst mode setting is ignored (operation is the same as that in burst
mode during one block of transfers). The DMAC is always operated in cycle stealing mode.
Clearing the DTE bit in DMDR stops a DMA transfer. A transfer requested before the DTE bit is
cleared to 0 by the DMAC is executed. When an interrupt by a transfer size error, a repeat size
end, or an extended repeat area overflow occurs, the DTE bit is cleared to 0 and the transfer ends.
Figure 10.14 shows an example of timing in burst mode.
Bus cycle
CPU
CPU
DMAC
DMAC
DMAC
CPU
No CPU cycle generated
Figure 10.14 Example of Timing in Burst Mode
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CPU
Section 10 DMA Controller (DMAC)
10.5.5
Extended Repeat Area Function
The source and destination address sides can be specified as the extended repeat area. The contents
of the address register repeat addresses within the area specified as the extended repeat area. For
example, to use a ring buffer as the transfer target, the contents of the address register should
return to the start address of the buffer every time the contents reach the end address of the buffer
(overflow on the ring buffer address). This operation can automatically be performed using the
extended repeat area function of the DMAC.
The extended repeat areas can be specified independently to the source address register (DSAR)
and destination address register (DDAR).
The extended repeat area on the source address is specified by bits SARA4 to SARA0 in DACR.
The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in
DACR. The extended repeat area sizes for each side can be specified independently.
A DMA transfer is stopped and an interrupt by an extended repeat area overflow can be requested
to the CPU when the contents of the address register reach the end address of the extended repeat
area. When an overflow on the extended repeat area set in DSAR occurs while the SARIE bit in
DACR is set to 1, the ESIF bit in DMDR is set to 1 and the DTE bit in DMDR is cleared to 0 to
stop the transfer. At this time, if the ESIE bit in DMDR is set to 1, an interrupt by an extended
repeat area overflow is requested to the CPU. When the DARIE bit in DACR is set to 1, an
overflow on the extended repeat area set in DDAR occurs, meaning that the destination side is a
target. During the interrupt handling, setting the DTE bit in DMDR resumes the transfer.
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Section 10 DMA Controller (DMAC)
Figure 10.15 shows an example of the extended repeat area operation.
...
When the area represented by the lower three bits of DSAR (eight bytes)
is specified as the extended repeat area (SARA4 to SARA0 = B'00011)
External memory
Area specified
by DSAR
H'23FFFE
H'23FFFF
H'240000
H'240000
H'240001
H'240001
H'240002
H'240002
H'240003
H'240003
H'240004
H'240004
H'240005
H'240005
H'240006
H'240006
H'240007
H'240007
H'240008
Repeat
An interrupt request by extended repeat area
overflow can be generated.
...
H'240009
Figure 10.15 Example of Extended Repeat Area Operation
When an interrupt by an extended repeat area overflow is used in block transfer mode, the
following should be taken into consideration.
When a transfer is stopped by an interrupt by an extended repeat area overflow, the address
register must be set so that the block size is a power of 2 or the block size boundary is aligned with
the extended repeat area boundary. When an overflow on the extended repeat area occurs during a
transfer of one block, the interrupt by the overflow is suspended and the transfer overruns.
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Section 10 DMA Controller (DMAC)
Figure 10.16 shows examples when the extended repeat area function is used in block transfer
mode.
...
When the are represented by the lower three bits (eight bytes) of DSAR are specified as the extended
repeat area (SARA4 to SARA0 = 3) and the block size in block transfer mode is specified to 5 (bits 23
to 16 in DTCR = 5).
External memory Area specified
1st block
2nd block
by DSAR
transfer
transfer
H'23FFFE
H'23FFFF
H'240000
H'240000
H'240000
H'240000
H'240001
H'240001
H'240001
H'240001
H'240002
H'240002
H'240002
H'240003
H'240003
H'240003
H'240004
H'240004
H'240004
H'240005
H'240005
H'240005
H'240006
H'240006
H'240006
H'240007
H'240007
H'240007
H'240008
Block transfer
continued
...
H'240009
Interrupt
request
generated
Figure 10.16 Example of Extended Repeat Area Function in Block Transfer Mode
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Section 10 DMA Controller (DMAC)
10.5.6
Address Update Function using Offset
The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or
offset addition. When the offset addition is selected, the offset specified by the offset register
(DOFR) is added to the address every time the DMAC transfers the data access size of data. This
function realizes a data transfer where addresses are allocated to separated areas.
Figure 10.17 shows the address update method.
External memory
External memory
±0
External memory
±1, 2, or 4
+ offset
Address not
updated
(a) Address fixed
Data access size
added to or subtracted
from address (addresses
are continuous)
(b) Increment or decrement
by 1, 2, or 4
Offset is added to address
(addresses are not
continuous)
(c) Offset addition
Figure 10.17 Address Update Method
In item (a), Address fixed, the transfer source or destination address is not updated indicating the
same address.
In item (b), Increment or decrement by 1, 2, or 4, the transfer source or destination address is
incremented or decremented by the value according to the data access size at each transfer. Byte,
word, or longword can be specified as the data access size. The value of 1 for byte, 2 for word, and
4 for longword is used for updating the address. This operation realizes the data transfer placed in
consecutive areas.
In item (c), Offset addition, the address update does not depend on the data access size. The offset
specified by DOFR is added to the address every time the DMAC transfers data of the data access
size.
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Section 10 DMA Controller (DMAC)
The address is calculated by the offset set in DOFR and the contents of DSAR and DDAR.
Although the DMAC calculates only addition, an offset subtraction can be realized by setting the
negative value in DOFR. In this case, the negative value must be 2's complement.
(1)
Basic Transfer Using Offset
Figure 10.18 shows a basic operation of a transfer using the offset addition.
Data 1
Address A1
Transfer
Offset
Data 2
Data 1
Data 2
Data 3
Data 4
Data 5
:
Address B1
Address B2 = Address B1 + 4
Address B3 = Address B2 + 4
Address B4 = Address B3 + 4
Address B5 = Address B4 + 4
Address A2
= Address A1 + Offset
:
:
:
Offset
Data 3
Address A3
= Address A2 + Offset
Offset
Data 4
Transfer source:
Offset addition
Transfer destination: Increment by 4 (longword)
Address A4
= Address A3 + Offset
Offset
Data 5
Address A5
= Address A4 + Offset
Figure 10.18 Operation of Offset Addition
In figure 10.18, the offset addition is selected as the transfer source address update and increment
or decrement by 1, 2, or 4 is selected as the transfer destination address. The address update means
that data at the address which is away from the previous transfer source address by the offset is
read from. The data read from the address away from the previous address is written to the
consecutive area in the destination side.
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Section 10 DMA Controller (DMAC)
(2)
XY Conversion Using Offset
Figure 10.19 shows the XY conversion using the offset addition in repeat transfer mode.
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
1st transfer
Offset
Offset
Offset
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Data 16
1st transfer
2nd transfer
Transfer
3rd transfer
4th transfer
2nd transfer Transfer source 3rd transfer
addresses
changed
by CPU
Data 1
Data 1
Data 5
Data 5
Address
initialized Data 9
Data 9
Address
initialized Data 13
Data 13
Data 2
Data 2
Data 6
Data 6
Data 10
Data 10
Data 14
Data 14
Data 3
Data 3
Data 7
Data 7
Data 11
Data 11
Data 15
Data 15
Data 4
Data 4
Data 8
Data 8
Interrupt
request
Data 12
Data 12
Interrupt
generated
request
Data 16
Data 16
generated
Data 1
Data 2
Data 5
Data 9
Data 6
Data 10
Data 3
Data 7
Data 11
Data 4
Data 8
Data 12
Data 13
Data 14
Data 15
Data 16
Transfer
Transfer source
addresses
changed
by CPU
Interrupt
request
generated
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Data 16
1st transfer
2nd transfer
3rd transfer
4th transfer
Figure 10.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode
In figure 10.19, the source address side is specified to the repeat area by DACR and the offset
addition is selected. The offset value is set to 4 × data access size (when the data access size is
longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 × data access
size (when the data access size is longword, the repeat size is set to 4 × 4 = 16 bytes, as an
example). The increment by 1, 2, or 4 is specified as the transfer destination address. A repeat size
end interrupt is requested when the repeat size of transfers is completed.
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Section 10 DMA Controller (DMAC)
When a transfer starts, the transfer source address is added to the offset every time data is
transferred. The transfer data is written to the destination continuous addresses. When data 4 is
transferred meaning that the repeat size of transfers is completed, the transfer source address
returns to the transfer start address (address of data 1 on the transfer source) and a repeat size end
interrupt is requested. While this interrupt stops the transfer temporarily, the contents of DSAR are
written to the address of data 5 by the CPU (when the data access size is longword, write the data
1 address + 4). When the DTE bit in DMDR is set to 1, the transfer is resumed from the state when
the transfer is stopped. Accordingly, operations are repeated and the transfer source data is
transposed to the destination area (XY conversion).
Figure 10.20 shows a flowchart of the XY conversion.
Start
Set address and transfer count
Set repeat transfer mode
Enable repeat escape interrupt
Set DTE bit to 1
Receives transfer request
Transfers data
Decrements transfer count
and repeat size
No
Transfer count = 0?
No
Yes
Repeat size = 0?
Yes
Initializes transfer source address
Generates repeat size end
interrupt request
Set transfer source address + 4
(Longword transfer)
End
: User operation
: DMAC operation
Figure 10.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode
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Section 10 DMA Controller (DMAC)
(3)
Offset Subtraction
When setting the negative value in DOFR, the offset value must be 2's complement. The 2's
complement is obtained by the following formula.
2's complement of offset = 1 + ~offset (~: bit inversion)
Example:
2's complement of H'0001FFFF
= H'FFFE0000 + H'00000001
= H'FFFE0001
The value of 2's complement can be obtained by the NEG.L instruction.
10.5.7
Register during DMA Transfer
The DMAC registers are updated by a DMA transfer. The value to be updated differs according to
the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits
BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR.
(1)
DMA Source Address Register
When the transfer source address set in DSAR is accessed, the contents of DSAR are output and
then are updated to the next address.
The increment or decrement can be specified by bits SAT1 and SAT0 in DACR. When SAT1 and
SAT0 = B'00, the address is fixed. When SAT1 and SAT0 = B'01, the address is added with the
offset. When SAT1 and SAT0 = B'10, the address is incremented. When SAT1 and SAT0 = B'11,
the address is decremented. The size of increment or decrement depends on the data access size.
The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0
= B'00, the data access size is byte and the address is incremented or decremented by 1. When
DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or
decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the
address is incremented or decremented by 4. Even if the access data size of the source address is
word or longword, when the source address is not aligned with the word or longword boundary,
the read bus cycle is divided into byte or word cycles. While data of one word or one longword is
being read, the size of increment or decrement is changing according to the actual data access size,
for example, +1 or +2 for byte or word data. After one word or one longword of data is read, the
address when the read cycle is started is incremented or decremented by the value according to
bits SAT1 and SAT0.
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Section 10 DMA Controller (DMAC)
In block or repeat transfer mode, when the block or repeat size of data transfers is completed while
the block or repeat area is specified to the source address side, the source address returns to the
transfer start address and is not affected by the address update.
When the extended repeat area is specified to the source address side, operation follows the
setting. The upper address bits are fixed and is not affected by the address update.
While data is being transferred, DSAR must be accessed in longwords. If the upper word and
lower word are read separately, incorrect data may be read from since the contents of DSAR
during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the
channel being transferred must not be written to.
(2)
DMA Destination Address Register
When the transfer destination address set in DDAR is accessed, the contents of DDAR are output
and then are updated to the next address.
The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1
and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with
the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 =
B'11, the address is decremented. The incrementing or decrementing size depends on the data
access size.
The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0
= B'00, the data access size is byte and the address is incremented or decremented by 1. When
DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or
decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the
address is incremented or decremented by 4. Even if the access data size of the destination address
is word or longword, when the destination address is not aligned with the word or longword
boundary, the write bus cycle is divided into byte and word cycles. While one word or one
longword of data is being written, the incrementing or decrementing size is changing according to
the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one
longword of data is written, the address when the write cycle is started is incremented or
decremented by the value according to bits SAT1 and SAT0.
In block or repeat transfer mode, when the block or repeat size of data transfers is completed while
the block or repeat area is specified to the destination address side, the destination address returns
to the transfer start address and is not affected by the address update.
When the extended repeat area is specified to the destination address side, operation follows the
setting. The upper address bits are fixed and is not affected by the address update.
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Section 10 DMA Controller (DMAC)
While data is being transferred, DDAR must be accessed in longwords. If the upper word and
lower word are read separately, incorrect data may be read from since the contents of DDAR
during the transfer may be updated regardless of the access by the CPU. Moreover, DDAR for the
channel being transferred must not be written to.
(3)
DMA Transfer Count Register (DTCR)
A DMA transfer decrements the contents of DTCR by the transferred bytes. When byte data is
transferred, DTCR is decremented by 1. When word data is transferred, DTCR is decremented by
2. When longword data is transferred, DTCR is decremented by 4. However, when DTCR = 0, the
contents of DTCR are not changed since the number of transfers is not counted.
While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in
longwords. If the upper word and lower word are read separately, incorrect data may be read from
since the contents of DTCR during the transfer may be updated regardless of the access by the
CPU. Moreover, DTCR for the channel being transferred must not be written to.
When a conflict occurs between the address update by DMA transfer and write access by the CPU,
the CPU has priority. When a conflict occurs between change from 1, 2, or 4 to 0 in DTCR and
write access by the CPU (other than 0), the CPU has priority in writing to DTCR. However, the
transfer is stopped.
(4)
DMA Block Size Register (DBSR)
DBSR is enabled in block or repeat transfer mode. Bits 31 to 16 in DBSR function as BKSZH and
bits 15 to 0 in DBSR function as BKSZ. The BKSZH bits (16 bits) store the block size and repeat
size and its value is not changed. The BKSZ bits (16 bits) function as a counter for the block size
and repeat size and its value is decremented every transfer by 1. When the BKSZ value is to
change from 1 to 0 by a DMA transfer, 0 is not stored but the BKSZH value is loaded into the
BKSZ bits.
Since the upper 16 bits of DBSR are not updated, DBSR can be accessed in words.
DBSR for the channel being transferred must not be written to.
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Section 10 DMA Controller (DMAC)
(5)
DTE Bit in DMDR
Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is
automatically cleared to 0 according to the DMA transfer state by the DMAC.
The conditions for clearing the DTE bit by the DMAC are as follows:
•
•
•
•
•
•
•
•
•
When the total size of transfers is completed
When a transfer is completed by a transfer size error interrupt
When a transfer is completed by a repeat size end interrupt
When a transfer is completed by an extended repeat area overflow interrupt
When a transfer is stopped by an NMI interrupt
When a transfer is stopped by and address error
Reset state
Hardware standby mode
When a transfer is stopped by writing 0 to the DTE bit
Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited
(except for the DTE bit). When changing the register settings after writing 0 to the DTE bit,
confirm that the DTE bit has been cleared to 0.
Figure 10.21 show the procedure for changing the register settings for the channel being
transferred.
Changing register settings
of channel during operation
[1] Write 0 to the DTE bit in DMDR.
[2] Read the DTE bit.
Write 0 to DTE bit
[1]
Read DTE bit
[2]
[3] Confirm that DTE = 0. DTE = 1
indicates that DMA is transferring.
[4] Write the desired values to the
registers.
[3]
DTE = 0?
No
Yes
Change register settings
[4]
End of changing
register settings
Figure 10.21 Procedure for Changing Register Setting For Channel being Transferred
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Section 10 DMA Controller (DMAC)
(6)
ACT Bit in DMDR
The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0
or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the
DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0
and the transfer is not completed, the ACT bit retains 1.
In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to
completion of a 1-block size transfer.
In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE
bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA
transfer.
(7)
ERRF Bit in DMDR
When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the
channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an
address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in
operation.
(8)
ESIF Bit in DMDR
When an interrupt by an transfer size error, a repeat size end, or an extended repeat area overflow
is requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a
transfer escape interrupt is requested to the CPU or DTC.
The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus
cycle of the interrupt source is completed.
The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is
resumed by setting the DTE bit to 1 during interrupt handling.
For details on interrupts, see section 10.8, Interrupt Sources.
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Section 10 DMA Controller (DMAC)
(9)
DTIF Bit in DMDR
The DTIF bit in DMDR is set to 1 after the total transfer size of transfers is completed. When both
the DTIF and DTIE bits in DMDR are set to 1, a transfer end interrupt by the transfer counter is
requested to the CPU or DTC.
The DTIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus
cycle is completed.
The DTIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is
resumed by setting the DTE bit to 1 during interrupt handling.
For details on interrupts, see section 10.8, Interrupt Sources.
10.5.8
Priority of Channels
The channels of the DMAC are given following priority levels: channel 0 > channel 1 >
channel 2 > channel3. Table 10.6 shows the priority levels among the DMAC channels.
Table 10.6 Priority among DMAC Channels
Channel
Priority
Channel 0
High
Channel 1
Channel 2
Channel 3
Low
The channel having highest priority other than the channel being transferred is selected when a
transfer is requested from other channels. The selected channel starts the transfer after the channel
being transferred releases the bus. At this time, when a bus master other than the DMAC requests
the bus, the cycle for the bus master is inserted.
In a burst transfer or a block transfer, channels are not switched.
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Section 10 DMA Controller (DMAC)
Figure 10.22 shows a transfer example when multiple transfer requests from channels 0 to 2.
Channel 1 transfer
Channel 0 transfer
Channel 2 transfer
Bφ
Address bus
DMAC
operation
Channel 0
Wait
Channel 0
Channel 1
Channel 2
Bus
released
Channel 1
Channel 0
Channel 1
Bus
released
Channel 2
Request cleared
Request cleared
Request Selected
retained
Request Not
Request
retained selected retained
Selected
Request cleared
Figure 10.22 Example of Timing for Channel Priority
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Channel 2
Wait
Section 10 DMA Controller (DMAC)
10.5.9
DMA Basic Bus Cycle
Figure 10.23 shows an examples of signal timing of a basic bus cycle. In figure 10.23, data is
transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When
the bus mastership is passed from the DMAC to the CPU, data is read from the source address and
it is written to the destination address. The bus is not released between the read and write cycles
by other bus requests. DMAC bus cycles follows the bus controller settings.
DMAC cycle (one word transfer)
CPU cycle
T1
T2
T1
T2
T3
T1
CPU cycle
T2
T3
Bφ
Source address
Destination address
Address bus
RD
LHWR
High
LLWR
Figure 10.23 Example of Bus Timing of DMA Transfer
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Section 10 DMA Controller (DMAC)
10.5.10 Bus Cycles in Dual Address Mode
(1)
Normal Transfer Mode (Cycle Stealing Mode)
In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one
word, or one longword) is completed. One bus cycle or more by the CPU or DTC are executed in
the bus released cycles.
In figure 10.24, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer
mode by cycle stealing.
DMA read
cycle
DMA read
cycle
DMA write
cycle
DMA write
cycle
DMA read
cycle
DMA write
cycle
Bφ
Address bus
RD
LHWR, LLWR
TEND
Bus
released
Bus
released
Bus
released
Last transfer cycle
Bus
released
Figure 10.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing
In figures 10.25 and 10.26, the TEND signal output is enabled and data is transferred in longwords
from the external 16-bit 2-state access space to the 16-bit 2-state access space in normal transfer
mode by cycle stealing.
In figure 10.25, the transfer source (DSAR) is not aligned with a longword boundary and the
transfer destination (DDAR) is aligned with a longword boundary.
In figure 10.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer
destination (DDAR) is not aligned with a longword boundary.
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Section 10 DMA Controller (DMAC)
DMA byte
read cycle
DMA word
read cycle
DMA byte
read cycle
DMA word
write cycle
DMA word
write cycle
DMA byte
read cycle
DMA word
read cycle
DMA byte
read cycle
DMA word
write cycle
DMA word
write cycle
4m + 1
4m + 2
4m + 4
4n
4n +2
4m + 5
4m + 6
4m + 8
4n + 4
4n + 6
Bφ
Address
bus
RD
LHWR
LLWR
TEND
Last transfer cycle
Bus
released
Bus
released
Bus
released
m and n are integers.
Figure 10.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing
(Transfer Source DSAR = Odd Address and Source Address Increment)
DMA word
read cycle
DMA word
read cycle
DMA byte
write cycle
DMA word
write cycle
DMA byte
write cycle
DMA word
read cycle
DMA word
read cycle
DMA byte
write cycle
DMA word
write cycle
DMA byte
write cycle
4m + 2
4n + 5
4n + 6
4n + 8
4m + 4
4m + 6
4n + 1
4n + 2
4n + 4
Bφ
Address
bus
4m
RD
LHWR
LLWR
TEND
Bus
released
Bus
released
Last transfer cycle
Bus
released
m and n are integers.
Figure 10.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing
(Transfer Destination DDAR = Odd Address and Destination Address Decrement)
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Section 10 DMA Controller (DMAC)
(2)
Normal Transfer Mode (Burst Mode)
In burst mode, one byte, one word, or one longword of data continues to be transferred until the
transfer end condition is satisfied.
When a burst transfer starts, a transfer request from a channel having priority is suspended until
the burst transfer is completed.
In figure 10.27, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer
mode by burst access.
DMA read cycle DMA write cycle
DMA read cycle
DMA write cycle DMA read cycle
DMA write cycle
Bφ
Address bus
RD
LHWR, LLWR
TEND
Last transfer cycle
Bus
released
Burst transfer
Figure 10.27 Example of Transfer in Normal Transfer Mode by Burst Access
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Bus
released
Section 10 DMA Controller (DMAC)
(3)
Block Transfer Mode
In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer
request is completed.
In figure 10.28, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer
mode.
DMA read
cycle
DMA write
cycle
DMA read
cycle
DMA write
cycle
DMA read
cycle
DMA write
cycle
DMA read
cycle
DMA write
cycle
Bφ
Address bus
RD
LHWR, LLWR
TEND
Bus
released
Block transfer
Bus
released
Last block transfer cycle
Bus
released
Figure 10.28 Example of Transfer in Block Transfer Mode
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Section 10 DMA Controller (DMAC)
(4)
Activation Timing by DREQ Falling Edge
Figure 10.29 shows an example of normal transfer mode activated by the DREQ signal falling
edge.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If
a high level of the DREQ signal has been detected until completion of the DMA write cycle,
receiving the next transfer request resumes and then a low level of the DREQ signal is detected.
This operation is repeated until the transfer is completed.
DMA read
cycle
Bus released
DMA write
cycle
DMA read
cycle
Bus released
DMA write
cycle
Bus released
Bφ
DREQ
Address bus
DMA
operation
Transfer source Transfer destination
Read
Wait
Read
Wait
Duration of transfer
request disabled
Request
Channel
Write
Transfer source Transfer destination
Request
[2]
Wait
Duration of transfer
request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
Write
[3]
[4]
[5]
Transfer request enable resumed
[6]
[7]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the
DREQ signal.
[4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
[1]
Figure 10.29 Example of Transfer in Normal Transfer Mode Activated
by DREQ Falling Edge
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Section 10 DMA Controller (DMAC)
Figure 10.30 shows an example of block transfer mode activated by the DREQ signal falling edge.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If
a high level of the DREQ signal has been detected until completion of the DMA write cycle,
receiving the next transfer request resumes and then a low level of the DREQ signal is detected.
This operation is repeated until the transfer is completed.
1-block transfer
1-block transfer
DMA read
cycle
Bus released
DMA write
cycle
DMA read
cycle
Bus released
DMA write
cycle
Bus released
Bφ
DREQ
Address bus
DMA
operation
Channel
Transfer source Transfer destination
Read
Wait
Write
Read
Wait
Duration of transfer
request disabled
Request
Transfer source Transfer destination
[2]
Wait
Duration of transfer
request disabled
Request
Min. of 3 cycles
Min. of 3 cycles
[1]
Write
[3]
[4]
[5]
[6]
Transfer request enable resumed
[7]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the
DREQ signal.
[4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
[1]
Figure 10.30 Example of Transfer in Block Transfer Mode Activated
by DREQ Falling Edge
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Section 10 DMA Controller (DMAC)
(5)
Activation Timing by DREQ Low Level
Figure 10.31 shows an example of normal transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Bus released
DMA read
cycle
DMA write
cycle
Transfer
source
Transfer
destination
DMA read
cycle
Bus released
DMA write
cycle
Bus released
Bφ
DREQ
Address bus
DMA
operation
Channel
Wait
Read
Write
Wait
Duration of transfer
request disabled
Request
Transfer
source
Read
Request
[2]
Write
Wait
Duration of transfer
request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
Transfer
destination
[3]
[4]
[5]
Transfer request enable resumed
[6]
[7]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
[1]
Figure 10.31 Example of Transfer in Normal Transfer Mode Activated
by DREQ Low Level
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Section 10 DMA Controller (DMAC)
Figure 10.32 shows an example of block transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
1-block transfer
1-block transfer
DMA read
cycle
Bus released
DMA write
cycle
DMA write
cycle
DMA read
cycle
Bus released
Bus released
Bφ
DREQ
Transfer
source
Address bus
DMA
operation
Channel
Wait
Read
Request
Transfer
destination
Transfer
source
Wait
Write
Read
Duration of transfer
request disabled
[1]
[2]
Write
Wait
Duration of transfer
request disabled
Request
Min. of 3 cycles
Transfer
destination
Min. of 3 cycles
[3]
[4]
[5]
[6]
Transfer request enable resumed
[7]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
[1]
Figure 10.32 Example of Transfer in Block Transfer Mode Activated
by DREQ Low Level
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Section 10 DMA Controller (DMAC)
Activation Timing by DREQ Low Level with NRD = 1
(6)
When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is
delayed for one cycle.
Figure 10.33 shows an example of normal transfer mode activated by the DREQ signal low level
with NRD = 1.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
DMA read
cycle
Bus released
DMA read
cycle
DMA read
cycle
Bus released
DMA read
cycle
Bus released
Bφ
DREQ
Transfer
source
Address bus
Channel
Request
Duration of transfer
request disabled
Transfer
destination
Transfer
source
Duration of transfer request
disabled which is extended
by NRD
Request
Min. of 3 cycles
[1]
[2]
Transfer
destination
Duration of transfer
request disabled
Duration of transfer request
disabled which is extended
by NRD
Min. of 3 cycles
[3]
[4]
[5]
Transfer request enable resumed
[6]
[7]
Transfer request enable resumed
[1]
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed one cycle after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Figure 10.33 Example of Transfer in Normal Transfer Mode Activated
by DREQ Low Level with NRD = 1
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Section 10 DMA Controller (DMAC)
10.5.11 Bus Cycles in Single Address Mode
(1)
Single Address Mode (Read and Cycle Stealing)
In single address mode, one byte, one word, or one longword of data is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU or DTC are executed in the bus released cycles.
In figure 10.34, the TEND signal output is enabled and data is transferred in bytes from the
external 8-bit 2-state access space to the external device in single address mode (read).
DMA read
cycle
DMA read
cycle
DMA read
cycle
DMA read
cycle
Bφ
Address bus
RD
DACK
TEND
Bus
released
Bus
released
Bus
released
Bus
Last transfer Bus
released
released
cycle
Figure 10.34 Example of Transfer in Single Address Mode (Byte Read)
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Section 10 DMA Controller (DMAC)
(2)
Single Address Mode (Write and Cycle Stealing)
In single address mode, data of one byte, one word, or one longword is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU or DTC are executed in the bus released cycles.
In figure 10.35, the TEND signal output is enabled and data is transferred in bytes from the
external 8-bit 2-state access space to the external device in single address mode (write).
DMA write
cycle
DMA write
cycle
DMA write
cycle
DMA write
cycle
Bφ
Address bus
LLWR
DACK
TEND
Bus
released
Bus
released
Bus
released
Last transfer Bus
Bus
cycle released
released
Figure 10.35 Example of Transfer in Single Address Mode (Byte Write)
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Section 10 DMA Controller (DMAC)
Activation Timing by DREQ Falling Edge
(3)
Figure 10.36 shows an example of single address mode activated by the DREQ signal falling edge.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If
a high level of the DREQ signal has been detected until completion of the single cycle, receiving
the next transfer request resumes and then a low level of the DREQ signal is detected. This
operation is repeated until the transfer is completed.
Bus
released
DMA single
cycle
Bus
released
DMA single
cycle
Bus
released
Bφ
DREQ
Transfer source/
Transfer destination
Transfer source/
Transfer destination
Address bus
DACK
DMA
operation
Channel
Single
Wait
Request
Single
Wait
Duration of transfer
request disabled
[1]
[2]
Duration of transfer
request disabled
Request
Min. of 3 cycles
Wait
Min. of 3 cycles
[3]
[4]
Transfer request
enable resumed
[5]
[6]
[7]
Transfer request
enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the
DREQ signal.
[4][7] When a high level of the DREQ signal has been detected, transfer enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
[1]
Figure 10.36 Example of Transfer in Single Address Mode Activated
by DREQ Falling Edge
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Section 10 DMA Controller (DMAC)
Activation Timing by DREQ Low Level
(4)
Figure 10.37 shows an example of normal transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the single cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Bus
released
DMA single
cycle
Bus
released
DMA single
cycle
Bus
released
Bφ
DREQ
Transfer source/
Transfer destination
Address bus
Transfer source/
Transfer destination
DACK
DMA
Wait
operation
Single
Request
Channel
Single
Wait
Duration of transfer
request disabled
[1]
[2]
Duration of transfer
request disabled
Request
Min. of 3 cycles
Wait
Min. of 3 cycles
[3]
[4]
Transfer request
enable resumed
[5]
[6]
[7]
Transfer request
enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the single cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
[1]
Figure 10.37 Example of Transfer in Single Address Mode Activated
by DREQ Low Level
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Section 10 DMA Controller (DMAC)
Activation Timing by DREQ Low Level with NRD = 1
(5)
When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is
delayed for one cycle.
Figure 10.38 shows an example of single address mode activated by the DREQ signal low level
with NRD = 1.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after one cycle of the transfer
request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the
DREQ signal is detected. This operation is repeated until the transfer is completed.
DMA single
cycle
Bus
released
DMA single
cycle
Bus
released
Bus
released
Bφ
DREQ
Channel
Transfer source/
Transfer destination
Transfer source/
Transfer destination
Address bus
Request
Min. of 3 cycles
[1]
[2]
Duration of transfer request
disabled which is extended
by NRD
Duration of transfer
request disabled
Duration of transfer request
disabled which is extended
by NRD
Duration of transfer
Request
request disabled
Min. of 3 cycles
[3]
[4]
[5]
Transfer request
enable resumed
[6]
[7]
Transfer request
enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed one cycle after completion of the single cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
[1]
Figure 10.38 Example of Transfer in Single Address Mode Activated
by DREQ Low Level with NRD = 1
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Section 10 DMA Controller (DMAC)
10.6
DMA Transfer End
Operations on completion of a transfer differ according to the transfer end condition. DMA
transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0.
(1)
Transfer End by DTCR Change from 1, 2, or 4, to 0
When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The
DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the
DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When
the DTCR value is 0 before the transfer, the transfer is not stopped.
(2)
Transfer End by Transfer Size Error Interrupt
When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer
size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMDR is cleared
to 0 and the ESIF bit in DMDR is set to 1.
• In normal transfer mode and repeat transfer mode, when the next transfer is requested while a
transfer is disabled due to the DTCR value less than the data access size
• In block transfer mode, when the next transfer is requested while a transfer is disabled due to
the DTCR value less than the block size
When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0.
A transfer size error is not generated. Operation in each transfer mode is shown below.
• In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data
access size, data is transferred in bytes
• In block transfer mode, when the DTCR value is less than the block size, the specified size of
data in DTCR is transferred instead of transferring the block size of data. The transfer is
performed in bytes.
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Section 10 DMA Controller (DMAC)
(3)
Transfer End by Repeat Size End Interrupt
In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data
transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When
the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the
ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer.
In block transfer mode, when the next transfer is requested after completion of a 1-block size data
transfer, a repeat size end interrupt can be requested.
(4)
Transfer End by Interrupt on Extended Repeat Area Overflow
When an overflow on the extended repeat area occurs while the extended repeat area is specified
and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area
overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE
bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1.
In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a
read cycle, the following write cycle is performed.
In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1block transfer, the remaining data is transferred. The transfer is not terminated by an extended
repeat area overflow interrupt unless the current transfer is complete.
(5)
Transfer End by Clearing DTE Bit in DMDR
When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current
DMA cycle and a DMA cycle in which the transfer request is accepted are completed.
In block transfer mode, a DMA transfer is completed after 1-block data is transferred.
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Section 10 DMA Controller (DMAC)
(6)
Transfer End by NMI Interrupt
When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the
ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the
transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the
ERRF bit to 0 and then set the DTE bits for the channels to 1.
The transfer end timings after an NMI interrupt is requested are shown below.
(a)
Normal Transfer Mode and Repeat Transfer Mode
In dual address mode, a DMA transfer is completed after completion of the write cycle for one
transfer unit.
In single address mode, a DMA transfer is completed after completion of the bus cycle for one
transfer unit.
(b)
Block Transfer Mode
A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is
not guaranteed.
In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar
to (a) in normal transfer mode.
(7)
Transfer End by Address Error
When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit
in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is
forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0
and then set the DTE bits for the channels.
The transfer end timing after an address error is the same as that after an NMI interrupt.
(8)
Transfer End by Hardware Standby Mode or Reset
The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA
transfer is not guaranteed.
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Section 10 DMA Controller (DMAC)
10.7
Relationship among DMAC and Other Bus Masters
10.7.1
CPU Priority Control Function Over DMAC
The CPU priority control function over DMAC can be used according to the CPU priority control
register (CPUPCR) setting. For details, see section 7.7, CPU Priority Control Function Over DTC,
DMAC, and EXDMAC.
The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for
each channel.
The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to
CPUP0 is updated according to the exception handling priority.
If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority
over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not
activated. When another channel has priority over or the same as the CPU, a transfer request is
received regardless of the priority between channels and the transfer is activated.
The transfer request masked by the CPU priority control function is suspended. When the transfer
channel is given priority over the CPU by changing priority levels of the CPU or channel, the
transfer request is received and the transfer is resumed. Writing 0 to the DTE bit clears the
suspended transfer request.
When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority.
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Section 10 DMA Controller (DMAC)
10.7.2
Bus Arbitration among DMAC and Other Bus Masters
When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be
inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to
other bus masters.
The consecutive DMA transfer cycles may not be divided according to the transfer mode settings
to achieve high-speed access.
The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release,
and on-chip bus master (CPU, DTC, or EXDMAC*) cycles are not inserted between the read and
write cycles of a DMA transfer.
In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA
transfer are consecutively performed. For this duration, since the DMAC has priority over the
CPU and DTC, accesses to the external space are suspended (the IBCCS bit in the bus control
register 2 (BCR2) is cleared to 0).
When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles
of the DMAC and on-chip bus master are performed alternatively.
When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the
IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated.
For details, see section 9, Bus Controller (BSC).
A conflict may occur among the external space access of a DMAC, refresh cycle*, an EXDMAC
cycle*, and an external bus release cycle. Even if a burst or block transfer is performed by the
DMAC, the transfer is stopped temporarily and the refresh cycle*, EXDMAC cycle*, and external
bus release cycle are inserted by the BSC according to the external bus priority (when the CPU
external access and the DTC external access do not have priority over a DMAC transfer, the
transfers are not operated until the DMAC releases the bus).
In dual address mode, the DMAC releases the external bus after the external space write cycle.
Since the read and write cycles are not separated, the bus is not released.
An internal space (on-chip memory and internal I/O registers) access of the DMAC and a refresh
cycle, an EXDMAC cycle, and an external bus release cycle may be performed at the same time.
Note: * Supported only by the H8S/1648G Group and H8S/1648H Group.
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Section 10 DMA Controller (DMAC)
10.8
Interrupt Sources
The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer
escape end interrupt which is generated when a transfer is terminated before the transfer counter
reaches 0. Table 10.7 shows interrupt sources and priority. For details, see section 7, Interrupt
Controller.
Table 10.7 Interrupt Sources and Priority
Abbr.
Interrupt Sources
Priority
DMTEND0
Transfer end interrupt by channel 0 transfer counter
High
DMTEND1
Transfer end interrupt by channel 1 transfer counter
DMTEND2
Transfer end interrupt by channel 2 transfer counter
DMTEND3
Transfer end interrupt by channel 3 transfer counter
DMEEND0
Interrupt by channel 0 transfer size error
Interrupt by channel 0 repeat size end
Interrupt by channel 0 extended repeat area overflow on source address
Interrupt by channel 0 extended repeat area overflow on destination address
DMEEND1
Interrupt by channel 1 transfer size error
Interrupt by channel 1 repeat size end
Interrupt by channel 1 extended repeat area overflow on source address
Interrupt by channel 1 extended repeat area overflow on destination address
DMEEND2
Interrupt by channel 2 transfer size error
Interrupt by channel 2 repeat size end
Interrupt by channel 2 extended repeat area overflow on source address
Interrupt by channel 2 extended repeat area overflow on destination address
DMEEND3
Interrupt by channel 3 transfer size error
Interrupt by channel 3 repeat size end
Interrupt by channel 3 extended repeat area overflow on source address
Interrupt by channel 3 extended repeat area overflow on destination address
Low
Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding
channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in
DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in
DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels is
decided by the interrupt controller and it is shown in table 10.7. For details, see section 7, Interrupt
Controller.
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Section 10 DMA Controller (DMAC)
Each interrupt source is specified by the interrupt enable bit in the register for the corresponding
channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat
size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an
interrupt by an extended repeat area overflow on the destination address are enabled or disabled by
the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR,
and the DARIE bit in DACR, respectively.
A transfer end interrupt by the transfer counter is generated when the DTIF bit in DMDR is set to
1. The DTIF bit is set to 1 when DTCR becomes 0 by a transfer while the DTIE bit in DMDR is
set to 1.
An interrupt other than the transfer end interrupt by the transfer counter is generated when the
ESIF bit in DMDR is set to 1. The ESIF bit is set to 1 when the conditions are satisfied by a
transfer while the enable bit is set to 1.
A transfer size error interrupt is generated when the next transfer cannot be performed because the
DTCR value is less than the data access size, meaning that the data access size of transfers cannot
be performed. In block transfer mode, the block size is compared with the DTCR value for
transfer error decision.
A repeat size end interrupt is generated when the next transfer is requested after completion of the
repeat size of transfers in repeat transfer mode. Even when the repeat area is not specified in the
address register, the transfer can be stopped periodically according to the repeat size. At this time,
when a transfer end interrupt by the transfer counter is generated, the ESIF bit is set to 1.
An interrupt by an extended repeat area overflow on the source and destination addresses is
generated when the address exceeds the extended repeat area (overflow). At this time, when a
transfer end interrupt by the transfer counter, the ESIF bit is set to 1.
Figure 10.39 is a block diagram of interrupts and interrupt flags. To clear an interrupt, clear the
DTIF or ESIF bit in DMDR to 0 in the interrupt handling routine or continue the transfer by
setting the DTE bit in DMDR after setting the register. Figure 10.40 shows procedure to resume
the transfer by clearing an interrupt.
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Section 10 DMA Controller (DMAC)
TSIE bit
DTIE bit
DMAC is activated in
transfer size error state
Transfer end
interrupt
DTIF bit
RPTIE bit
[Setting condition]
When DTCR becomes 0
and transfer ends
DMAC is activated
after BKSZ bits are
changed from 1 to 0
SARIE bit
ESIE bit
Extended repeat area
overflow occurs in
source address
Transfer escape
end interrupt
ESIF bit
DARIE bit
Setting condition is satisfied
Extended repeat area
overflow occurs in
destination address
Figure 10.39 Interrupt and Interrupt Sources
Transfer end interrupt
handling routine
Transfer resumed after
interrupt handling routine
Consecutive transfer
processing
Registers are specified
[1]
DTIF and ESIF bits are
cleared to 0
[4]
DTE bit is set to 1
[2]
Interrupt handling routine
ends
[5]
Interrupt handling routine
ends (RTE instruction
executed)
[3]
Registers are specified
[6]
DTE bit is set to 1
[7]
Transfer resume
processing end
Transfer resume
processing end
[1] Specify the values in the registers such as transfer counter and address register.
[2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or
ESIF bit in DMDR to 0 and an interrupt source is cleared.
[3] End the interrupt handling routine by the RTE instruction.
[4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit.
[5] Complete the interrupt handling routine and clear the interrupt mask.
[6] Specify the values in the registers such as transfer counter and address register.
[7] Set the DTE bit to 1 to resume DMA operation.
Figure 10.40 Procedure Example of Resuming Transfer by Clearing Interrupt Source
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Section 10 DMA Controller (DMAC)
10.9
Usage Notes
1. DMAC Register Access During Operation
Except for clearing the DTE bit in DMDR, the settings for channels being transferred
(including waiting state) must not be changed. The register settings must be changed during
the transfer prohibited state.
2. Settings of Module Stop Function
The DMAC operation can be enabled or disabled by the module stop control register. The
DMAC is enabled by the initial value.
Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC
enters the module stop state. However, when a transfer for a channel is enabled or when an
interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the
DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13.
When the clock is stopped, the DMAC registers cannot be accessed. However, the following
register settings are valid in the module stop state. Disable them before entering the module
stop state, if necessary.
 TENDE bit in DMDR is 1 (the TEND signal output enabled)
 DACKE bit in DMDR is 1 (the DACK signal output enabled)
3. Activation by DREQ Falling Edge
The DREQ falling edge detection is synchronized with the DMAC internal operation.
A. Activation request waiting state: Waiting for detecting the DREQ low level. A transition to
2. is made.
B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made.
C. Transfer prohibited state: Waiting for detecting the DREQ high level. A transition to 1. is
made.
After a DMAC transfer enabled, a transition to 1. is made. Therefore, the DREQ signal is
sampled by low level detection at the first activation after a DMAC transfer enabled.
4. Acceptation of Activation Source
At the beginning of an activation source reception, a low level is detected regardless of the
setting of DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven
low before setting DMDR, the low level is received as a transfer request.
When the DMAC is activated, clear the DREQ signal of the previous transfer.
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Section 11 EXDMA Controller (EXDMAC)
Section 11 EXDMA Controller (EXDMAC)
EXDMAC is supported both by the H8SX/1648G Group and H8SX/1648H Group but neither by
the H8SX/1648 Group, H8SX/1648A Group, nor the H8SX/1648L Group.
This LSI has an on-chip four-channel external bus transfer DMA controller (EXDMAC). The
EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external
devices and external memory. Also, the EXDMAC allows external bus transfer in parallel with the
internal CPU operation when there is no external bus request from a controller other than the
EXDMAC.
11.1
Features
• Up to 4-Gbyte address space accessible
• Selection of byte, word, or longword transfer data length
• Total transfer size of up to 4 Gbytes (4,294,967,295 bytes)
Selection of free-running mode (with no total transfer size specified)
• Selection of auto-requests or external requests for activating the EXDMAC
Auto-request: Activation from the CPU (Cycle steal mode or burst mode can be selected.)
External request: Low level sensing or falling edge sensing for the EDREQ signal can be
selected.
All of four channels can accept external requests.
• Selection of dual address mode or single address mode
Dual address mode: Both the transfer source and destination addresses are specified to transfer
data.
Single address mode: The EDACK signal is used to access the transfer source or destination
peripheral device and the address of the other device is specified to transfer data.
• Normal, repeat, block, or cluster transfer (only for the EXDMAC) can be selected as transfer
mode
Normal transfer mode: One byte, one word, or one longword data is transferred at a single
transfer request
Repeat transfer mode: One byte, one word, or one longword data is transferred at a single
transfer request
Repeat size of data is transferred and then a transfer address returns to
the transfer start address
Up to 64-kbyte transfers can be set as repeat size (65,536
bytes/words/longwords)
Block transfer mode: One block data is transferred at a single transfer request
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Section 11 EXDMA Controller (EXDMAC)
•
•
•
•
•
•
•
Up to 64-kbyte data can be set as block size (65,536
bytes/words/longwords)
Cluster transfer mode: One cluster data is transferred at a single transfer request
Up to 32-byte data can be set as cluster size
Selection of extended repeat area function (to transfer data such as ring buffer data by fixing
the upper bit value in the transfer address register and repeating the address values in a
specified range)
For the extended repeat area, 1 bit (2 bytes) to 27 bits (128 Mbytes) can be set independently
for the transfer source or destination.
Selection of address update methods: Increment/decrement by 1, 2 or 4, fixed, or offset
addition
When offset addition is used to update addresses, the mid-addresses can be skipped during data
transfer.
Transfer of word or longword data to addresses beyond each data boundary
Data can be divided into an optimal data size (byte or word) according to addresses when
transferring data.
Two kinds of interrupts requested to the CPU
Transfer end interrupt: Requested after the number of data set by the transfer counter has been
completely transferred
Transfer escape end interrupt: Requested when the remaining transfer size is smaller than the
size set for a single transfer request, after a repeat-size transfer is completed, or when an
extended repeat area overflow occurs.
Acceptance of a transfer request can be reported to an external device via the EDRAK pin
(only for the EXDMAC).
Operation of EXDMAC, connected to a dedicated bus, in parallel with a bus master such as the
CPU, DTC, or DMAC (only for the EXDMAC).
Module stop state can be set.
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Section 11 EXDMA Controller (EXDMAC)
Figure 11.1 shows a block diagram of the EXDMAC.
Internal data bus
Internal address bus
External pins
EDREQn
Data buffer
EDACKn
ETENDn
EDRAKn
Control unit
CLSBR0
Address buffer
Interrupt request
signals to CPU
for individual channels
CLSBR1
Processor
CLSBR2
Processor
EDOFR_n
.
.
.
EDSAR_n
CLSBR7
EDDAR_n
EDMDR_n
EDTCR_n
EDACR_n
EDBSR_n
Module data bus
[Legend]
EDSAR_n:
EDDAR_n:
EDOFR_n:
EDTCR_n:
EDBSR_n:
EDMDR_n:
EDACR_n:
CLSBR0 to CLSBR7:
EXDMA source address register
EXDMA destination address register
EXDMA offset register
EXDMA transfer count register
EXDMA block size register
EXDMA mode control register
EXDMA address control register
Cluster buffer registers 0 to 7
EDREQn:
EDACKn:
ETENDn:
EDRAKn:
(n: 0 to 3)
EXDMA transfer request
EXDMA transfer acknowledge
EXDMA transfer end
EDREQ acceptance acknowledge
Figure 11.1 Block Diagram of EXDMAC
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Section 11 EXDMA Controller (EXDMAC)
11.2
Input/Output Pins
Table 11.1 shows the EXDMAC pin configuration.
Table 11.1 Pin Configuration
Channel
Name
Abbr.
I/O
Function
0
EXDMA transfer request 0
EDREQ0
Input
Channel 0 external request
EXDMA transfer
acknowledge 0
EDACK0
Output
Channel 0 single address transfer
acknowledge
EXDMA transfer end 0
ETEND0
Output
Channel 0 transfer end
EDREQ0 acceptance
acknowledge
EDRAK0
Output
Notification to external device of
channel 0 external request
acceptance and start of execution
EXDMA transfer request 1
EDREQ1
Input
Channel 1 external request
EXDMA transfer
acknowledge 1
EDACK1
Output
Channel 1 single address transfer
acknowledge
EXDMA transfer end 1
ETEND1
Output
Channel 1 transfer end
EDREQ1 acceptance
acknowledge
EDRAK1
Output
Notification to external device of
channel 1 external request
acceptance and start of execution
EXDMA transfer request 2
EDREQ2
Input
Channel 2 external request
EXDMA transfer
acknowledge 2
EDACK2
Output
Channel 2 single address transfer
acknowledge
EXDMA transfer end 2
ETEND2
Output
Channel 2 transfer end
EDREQ2 acceptance
acknowledge
EDRAK2
Output
Notification to external device of
channel 2 external request
acceptance and start of execution
EXDMA transfer request 3
EDREQ3
Input
Channel 3 external request
EXDMA transfer
acknowledge 3
EDACK3
Output
Channel 3 single address transfer
acknowledge
EXDMA transfer end 3
ETEND3
Output
Channel 3 transfer end
EDREQ3 acceptance
acknowledge
EDRAK3
Output
Notification to external device of
channel 3 external request
acceptance and start of execution
1
2
3
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Section 11 EXDMA Controller (EXDMAC)
11.3
Registers Descriptions
The EXDMAC has the following registers.
Channel 0
•
•
•
•
•
•
•
EXDMA source address register_0 (EDSAR_0)
EXDMA destination address register_0 (EDDAR_0)
EXDMA offset register_0 (EDOFR_0)
EXDMA transfer count register_0 (EDTCR_0)
EXDMA block size register_0 (EDBSR_0)
EXDMA mode control register_0 (EDMDR_0)
EXDMA address control register_0 (EDACR_0)
Channel 1
•
•
•
•
•
•
•
EXDMA source address register_1 (EDSAR_1)
EXDMA destination address register_1 (EDDAR_1)
EXDMA offset register_1 (EDOFR_1)
EXDMA transfer count register_1 (EDTCR_1)
EXDMA block size register_1 (EDBSR_1)
EXDMA mode control register_1 (EDMDR_1)
EXDMA address control register_1 (EDACR_1)
Channel 2
•
•
•
•
•
•
•
EXDMA source address register_2 (EDSAR_2)
EXDMA destination address register_2 (EDDAR_2)
EXDMA offset register_2 (EDOFR_2)
EXDMA transfer count register_2 (EDTCR_2)
EXDMA block size register_2 (EDBSR_2)
EXDMA mode control register_2 (EDMDR_2)
EXDMA address control register_2 (EDACR_2)
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Section 11 EXDMA Controller (EXDMAC)
Channel 3
•
•
•
•
•
•
•
EXDMA source address register_3 (EDSAR_3)
EXDMA destination address register_3 (EDDAR_3)
EXDMA offset register_3 (EDOFR_3)
EXDMA transfer count register_3 (EDTCR_3)
EXDMA block size register_3 (EDBSR_3)
EXDMA mode control register_3 (EDMDR_3)
EXDMA address control register_3 (EDACR_3)
Common register
• Cluster buffer registers 0 to 7 (CLSBR0 to CLSBR7)
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Section 11 EXDMA Controller (EXDMAC)
11.3.1
EXDMA Source Address Register (EDSAR)
EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address
update function is provided that updates the register contents to the next transfer source address
each time transfer processing is performed. In single address mode, the EDSAR value is ignored
when the address specified by EDDAR is transferred as a destination address (DIRS = 1 in
EDACR).
EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDSAR for a channel on which EXDMA transfer is in progress.
Bit
31
30
29
28
27
26
25
24
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 2.00 Jul. 31, 2008 Page 467 of 1438
REJ09B0365-0200
Section 11 EXDMA Controller (EXDMAC)
11.3.2
EXDMA Destination Address Register (EDDAR)
EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An
address update function is provided that updates the register contents to the next transfer
destination address each time transfer processing is performed. In single address mode, the
EDDAR value is ignored when the address specified by EDSAR is transferred as a source address
(DIRS = 0 in EDACR).
EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDDAR for a channel on which EXDMA transfer is in progress.
Bit
31
30
29
28
27
26
25
24
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 2.00 Jul. 31, 2008 Page 468 of 1438
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Section 11 EXDMA Controller (EXDMAC)
11.3.3
EXDMA Offset Register (EDOFR)
EDOFR is a 32-bit readable/writable register that sets the offset value when offset addition is
selected for updating source or destination addresses. This register can be set independently for
each channel, but the same offset value must be used for the source and destination addresses on
the same channel.
Bit
31
30
29
28
27
26
25
24
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 2.00 Jul. 31, 2008 Page 469 of 1438
REJ09B0365-0200
Section 11 EXDMA Controller (EXDMAC)
11.3.4
EXDMA Transfer Count Register (EDTCR)
EDTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total
transfer size).
When EDTCR is set to H'00000001, the total transfer size is 1 byte. When EDTCR is set to
H'00000000, the total transfer size is not specified and the transfer counter is halted (free-running
mode). In this case, no transfer end interrupt by the transfer counter is generated. When EDTCR is
set to H'FFFFFFFF, up to 4 Gbytes (4,294,967,295 bytes) of the total transfer size is set. When the
EXDMA is active, EDTCR indicates the remaining transfer size. The value according to the data
access size (byte: −1, word: −2, longword: −4) is decremented each time of a data transfer.
EDTCR can be read at all times by the CPU. When reading EDTCR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDTCR for a channel on which EXDMA transfer is in progress.
Bit
31
30
29
28
27
26
25
24
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit Name
Initial Value
R/W
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 2.00 Jul. 31, 2008 Page 470 of 1438
REJ09B0365-0200
Section 11 EXDMA Controller (EXDMAC)
11.3.5
EXDMA Block Size Register (EDBSR)
EDBSR sets the repeat size, block size, or cluster size. EDBSR is enabled in repeat transfer, block
transfer, and cluster transfer modes. EDBSR is disabled in normal transfer mode.
When BKSZH and BKSZ are set to H'0001 in cluster transfer mode (dual address mode), the
EXDMAC operates in block transfer mode (dual address mode).
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
31
30
29
28
27
26
25
24
BKSZH31
BKSZH30
BKSZH29
BKSZH28
BKSZH27
BKSZH26
BKSZH25
BKSZH24
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
BKSZH23
BKSZH22
BKSZH21
BKSZH20
BKSZH19
BKSZH18
BKSZH17
BKSZH16
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
BKSZ15
BKSZ14
BKSZ13
BKSZ12
BKSZ11
BKSZ10
BKSZ9
BKSZ8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
BKSZ7
BKSZ6
BKSZ5
BKSZ4
BKSZ3
BKSZ2
BKSZ1
BKSZ0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
31 to 16
BKSZH31
to
BKSZH16
15 to 0
Initial
value
R/W
Description
All 0
R/W
Sets the repeat size, block size, or cluster size.
BKSZ15 to All 0
BKSZ0
When these bits are set to H'0001, one byte-, one
word-, or one longword-size is set. When these bits are
set to H'0000, the maximum values are set (see table
11.2). These bits are always fixed during an EXDMA
operation.
R/W
In an EXDMA operation, the remaining repeat size,
block size, or cluster size is indicated. The value is
decremented by one each time of a data transfer. When
the remaining size becomes zero, the BKSZH value is
loaded. Set the same initial value as for the BKSZH bit
when writing.
Rev. 2.00 Jul. 31, 2008 Page 471 of 1438
REJ09B0365-0200
Section 11 EXDMA Controller (EXDMAC)
Table 11.2 Data Access Size, Enable Bit, and Allowable Size
Mode
Data
BKSZH
Access Size enable bit
BKSZ
enable bit
Allowable size (in bytes)
Repeat transfer mode
Byte
15 to 0
1 to 65,536
Block transfer mode
Word
2 to 131,072
Longword
4 to 262,144
Cluster transfer mode
11.3.6
31 to 16
Byte
20 to 16
4 to 0
1 to 32
Word
19 to 16
3 to 0
2 to 32
Longword
18 to 16
2 to 0
4 to 32
EXDMA Mode Control Register (EDMDR)
EDMDR controls EXDMAC operations.
• EDMDR_0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
31
30
29
28
27
26
25
24
DTE
EDACKE
ETENDE
EDRAKE
EDREQS
NRD


0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
23
22
21
20
19
18
17
16
ACT



ERRF

ESIF
DTIF
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R/(W)*
R
R/(W)*
R/(W)*
Bit
Bit Name
15
14
13
12
11
10
9
8
DTSZ1
DTSZ0
MDS1
MDS0
TSEIE

ESIE
DTIE
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: *
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
7
6
5
4
3
2
1
0
DTF1
DTF0



EDMAP2
EDMAP1
EDMAP0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Only 0 can be written to this bit after having been read as 1, to clear the flag.
Rev. 2.00 Jul. 31, 2008 Page 472 of 1438
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Section 11 EXDMA Controller (EXDMAC)
• EDMDR_1 to EDMDR_3
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
31
30
29
28
27
26
25
24
DTE
EDACKE
ETENDE
EDRAKE
DREQS
NRD


0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
23
22
21
20
19
18
17
16
ACT





ESIF
DTIF
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R/(W)*
R/(W)*
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: *
15
14
13
12
11
10
9
8
DTSZ1
DTSZ0
MDS1
MDS0
TSEIE

ESIE
DTIE
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
7
6
5
4
3
2
1
0
DTF1
DTF0



EDMAP2
EDMAP1
EDMAP0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Only 0 can be written to this bit after having been read as 1, to clear the flag.
Rev. 2.00 Jul. 31, 2008 Page 473 of 1438
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
31
DTE
0
R/W
Data Transfer Enable
Enables or disables data transfer on the corresponding
channel. When this bit is set to 1, this indicates that an
EXDMA operation is in progress.
When auto-request mode is specified, transfer
processing begins when this bit is set to 1. With
external requests, transfer processing begins when a
transfer request is issued after this bit has been set to
1. When this bit is cleared to 0 during an EXDMA
operation, transfer is halted.
If this bit is cleared to 0 during an EXDMA operation in
block transfer mode, this bit is cleared to 0 on
completion of the currently executing one-block
transfer. When this bit is cleared to 0 during an EXDMA
operation in cluster transfer mode, this bit is cleared to
0 on completion of the currently executing one-cluster
transfer.
If an external source that ends (aborts) transfer occurs,
this bit is automatically cleared to 0 and transfer is
terminated.
Do not change the operating mode, transfer method, or
other parameters while this bit is set to 1.
0: Data transfer disabled
1: Data transfer enabled (during an EXDMA operation)
[Clearing conditions]
•
•
•
•
•
•
•
Rev. 2.00 Jul. 31, 2008 Page 474 of 1438
REJ09B0365-0200
When transfer of the total transfer size specified
ends
When operation is halted by a repeat size end
interrupt
When operation is halted by an extended repeat
area overflow interrupt
When operation is halted by a transfer size error
interrupt
When 0 is written to terminate transfer
In block transfer mode, the value written is effective
after one-block transfer ends.
In cluster transfer mode, the value written is
effective after one-cluster transfer ends.
When an address error or NMI interrupt occurs
Reset, hardware standby mode
Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
30
EDACKE
0
R/W
EDACK Pin Output Enable
In single address mode, enables or disables output
from the EDACK pin. In dual address mode, the
specification by this bit is ignored.
0: EDACK pin output disabled
1: EDACK pin output enabled
29
ETENDE
0
R/W
ETEND Pin Output Enable
Enables or disables output from the ETEND pin.
0: ETEND pin output disabled
1: ETEND pin output enabled
28
EDRAKE
0
R/W
EDRAK Pin Output Enable
Enables or disables output from the EDRAK pin.
0: EDRAK pin output disabled
1: EDRAK pin output enabled
27
EDREQS
0
R/W
EDREQ Select
Selects whether a low level or the falling edge of the
EDREQ signal used in external request mode is
detected.
0: Low-level detection
1: Falling edge detection (the first transfer is detected
on a low level after a transfer is enabled.)
26
NRD
0
R/W
Next Request Delay
Selects the timing of the next transfer request to be
accepted.
0: Next transfer request starts to be accepted after
transfer of the bus cycle in progress ends.
1: Next transfer request starts to be accepted after one
cycle of Bφ from the completion of the bus cycle in
progress.
25, 24

All 0
R
Reserved
They are always read as 0 and cannot be modified.
Rev. 2.00 Jul. 31, 2008 Page 475 of 1438
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
23
ACT
0
R
Active State
Indicates the operation state of the corresponding
channel.
0: Transfer request wait state or transfer disabled state
(DTE = 0)
1: Active state
22 to 20

All 0
R
Reserved
They are always read as 0 and cannot be modified.
19
ERRF
0
R/(W)*
System Error Flag
Flag that indicates the occurrence of an address error
or NMI interrupt. This bit is only enabled in EDMDR_0.
When this bit is set to 1, write to the DTE bit for all
channels is disabled. This bit is reserved in EDMDR_1
to EDMDR_3. They are always read as 0 and cannot
be modified.
0: Address error or NMI interrupt is not generated
1: Address error or NMI interrupt is generated
[Clearing condition]
•
Writing 0 to ERRF after reading ERRF = 1
[Setting condition]
•
When an address error or NMI interrupt occurred
However, when an address error or an NMI interrupt
has been generated in EXDMAC module stop mode,
this bit is not set to 1.
18

0
R
Reserved
They are always read as 0 and cannot be modified.
Rev. 2.00 Jul. 31, 2008 Page 476 of 1438
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
17
ESIF
0
R/(W)*
Transfer Escape Interrupt Flag
Flag indicating that a transfer escape end interrupt
request has occurred before the transfer counter
becomes 0 and transfer escape has ended.
0: Transfer escape end interrupt request is not
generated
1: Transfer escape end interrupt request is generated
[Clearing conditions]
•
Writing 1 to the DTE bit
•
Writing 0 to ESIF while reading ESIF = 1
[Setting conditions]
16
DTIF
0
R/(W)*
•
Transfer size error interrupt request is generated
•
Repeat size end interrupt request is generated
•
Extended repeat area overflow end interrupt request
is generated
Data Transfer Interrupt Flag
Flag indicating that a transfer end interrupt request has
occurred by the transfer counter.
0: Transfer end interrupt request is not generated by
the transfer counter
1: Transfer end interrupt request is generated by the
transfer counter
[Clearing conditions]
•
Writing 1 to the DTE bit
•
Writing 0 to DTIF while reading DTIF = 1
[Setting condition]
•
When EDTCR becomes 0 and transfer has ended
15
DTSZ1
0
R/W
Data Access Size 1 and 0
14
DTSZ0
0
R/W
Selects the data access size.
00: Byte-size (8 bits)
01: Word-size (16 bits)
10: Longword-size (32 bits)
11: Setting prohibited
Rev. 2.00 Jul. 31, 2008 Page 477 of 1438
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
13
MDS1
0
R/W
Transfer Mode Select 1 and 0
12
MDS0
0
R/W
Selects the transfer mode.
00: Normal transfer mode
01: Block transfer mode
10: Repeat transfer mode
11: Cluster transfer mode
11
TSEIE
0
R/W
Transfer Size Error Interrupt Enable
Enables or disables a transfer size error interrupt
request.
When this bit is set to 1 and the transfer counter value
becomes smaller than the data access size for one
transfer request by EXDMAC transfer, the DTE bit is
cleared to 0 by the next transfer request. At the same
time, the ESIF bit is set to 1 to indicate that a transfer
size error interrupt request is generated.
When cluster transfer read/write address mode is
specified, this bit should be set to 1.
Transfer size error interrupt request occurs in the
following conditions:
•
In normal transfer and repeat transfer modes, the
total transfer size set in EDTCR is smaller than the
data access size
•
In block transfer mode, the total transfer size set in
EDTCR is smaller than the block size
•
In cluster transfer mode, the total transfer size set in
EDTCR is smaller than the cluster size
0: Transfer size error interrupt request disabled
1: Transfer size error interrupt request enabled
10

0
R
Reserved
They are always read as 0 and cannot be modified.
Rev. 2.00 Jul. 31, 2008 Page 478 of 1438
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
9
ESIE
0
R/W
Transfer Escape Interrupt Enable
Enables or disables a transfer escape end interrupt
request occurred during EXDMA transfer. When this bit
is set to 1, and the ESIF bit is set to 1, a transfer
escape end interrupt is requested to the CPU or DTC.
The transfer escape end interrupt request is canceled
by clearing this bit or the ESIF bit to 0.
0: Transfer escape interrupt request disabled
1: Transfer escape interrupt request enabled
8
DTIE
0
R/W
Data Transfer Interrupt Enable
Enables or disables a transfer end interrupt request by
the transfer counter. When this bit is set to 1 and the
DTIF bit is set to 1, a transfer end interrupt is requested
to the CPU or DTC. The transfer end interrupt request
is canceled by clearing this bit or the DTIF bit to 0.
0: Transfer end interrupt request disabled
1: Transfer end interrupt request enabled
7
DTF1
0
R/W
Data Transfer Factor 1 and 0
6
DTF0
0
R/W
Selects a source to activate EXDMAC. For external
requests, a sampling method is selected by the
EDREQS bit.
00: Auto-request (cycle steal mode)
01: Auto-request (burst mode)
10: Setting prohibited
11: External request
5

0
R/W
Reserved
The initial value should not be changed.
Rev. 2.00 Jul. 31, 2008 Page 479 of 1438
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
4, 3

All 0
R
Reserved
They are always read as 0 and cannot be modified.
2
EDMAP2
0
R/W
EXDMA Priority Levels 2 to 0
1
EDMAP1
0
R/W
0
EDMAP0
0
R/W
Selects the EXDMAC priority level when using the CPU
priority control function over DTC and EXDMAC. When
the EXDMAC priority level is lower than the CPU
priority level, EXDMAC masks the acceptance of
transfer source and waits until the CPU priority level
becomes low. The priority level can be set
independently for each channel. This bit is enabled
when the CPUPCE bit in CPUPCR is 1.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
Note:
*
Only 0 can be written to these bits after 1 is read to clear the flag.
Rev. 2.00 Jul. 31, 2008 Page 480 of 1438
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Section 11 EXDMA Controller (EXDMAC)
11.3.7
EXDMA Address Control Register (EDACR)
EDACR sets the operating modes and transfer methods.
Bit
Bit Name
Initial Value
31
30
29
28
27
26
25
24
AMS
DIRS



RPTIE
ARS1
ARS0
0
0
0
0
0
0
0
0
R/W
R/W
R
R
R
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
16
Bit Name


SAT1
SAT0


DAT1
DAT0
R/W
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R
R
R/W
R/W
15
14
13
12
11
10
9
8
SARIE


SARA4
SARA3
SARA2
SARA1
SARA0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
DARIE


DARA4
DARA3
DARA2
DARA1
DARA0
0
0
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial
value
R/W
Description
31
AMS
0
R/W
Address Mode Select
Selects single address mode or dual address mode.
When single address mode is selected, EDACK pin is
valid due to the EDACKE bit setting in EDMDR.
0: Dual address mode
1: Single address mode
30
DIRS
0
R/W
Single Address Direction Select
Specifies the data transfer direction in single address
mode. In dual address mode, the specification by this
bit is ignored.
In cluster transfer mode, the internal cluster buffer will
be the source or destination in place of the external
device with DACK.
0: EDSAR transferred as a source address
1: EDDAR transferred as a destination address
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
29 to 27

All 0
R
Reserved
They are always read as 0 and cannot be modified.
26
RPTIE
0
R/W
Repeat Size End Interrupt Enable
Enables or disables a repeat size end interrupt request.
When this bit is set to 1 and the next transfer source is
generated at the end of a repeat-size transfer in repeat
transfer mode, the DTE bit in EDMDR is cleared to 0. At
the same time, the ESIF bit in EDMDR is set to 1 to
indicate that a repeat size end interrupt is requested.
Even if the repeat area is not specified (ARS1, ARS0 =
B'10), the repeat size end interrupt can be requested at
the end of a repeat-size transfer.
When this bit is set to 1 and the next transfer source is
generated at the end of a block- or cluster-size transfer
in block transfer or cluster transfer mode, the DTE bit in
EDMDR is cleared to 0. At the same time, the ESIF bit
in EDMDR is set to 1 to indicate that the repeat size
end interrupt is requested.
0: Repeat size end interrupt request disabled
1: Repeat size end interrupt request enabled
25
ARS1
0
R/W
Area Select 1 and 0
24
ARS0
0
R/W
Select the block area or repeat area in block transfer,
repeat transfer or cluster transfer mode.
00: Block area/repeat area on the source address side
01: Block area/repeat area on the destination address
side
10: Block area/repeat area not specified
11: Setting prohibited
23, 22

All 0
R
Reserved
They are always read as 0 and cannot be modified.
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
21
SAT1
0
R/W
Source Address Update Mode 1 and 0
20
SAT0
0
R/W
These bits specify incrementing/decrementing of the
transfer source address (EDSAR). When the transfer
source is not specified in EDSAR in single address
mode, the specification by these bits is ignored.
00: Fixed
01: Offset added
10: Incremented (+1, +2, or +4 according to the data
access size)
11: Decremented (−1, −2, or −4 according to the data
access size)
19, 18

All 0
R
Reserved
They are always read as 0 and cannot be modified.
17
DAT1
0
R/W
Destination Address Update Mode 1 and 0
16
DAT0
0
R/W
These bits specify incrementing/decrementing of the
transfer destination address (EDDAR). When the
transfer source is not specified in EDDAR in single
address mode, the specification by these bits is
ignored.
00: Fixed
01: Offset added
10: Incremented (+1, +2, or +4 according to the data
access size)
11: Decremented (−1, −2, or −4 according to the data
access size)
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
15
SARIE
0
R/W
Source Address Extended Repeat Area Overflow
Interrupt Enable
Enables or disables the source address extended
repeat area overflow interrupt request.
When this bit is set to 1, in the event of source address
extended repeat area overflow, the DTE bit is cleared to
0 in EDMDR. At the same time, the ESIF bit is set to 1
in EDMDR to indicate that the source address extended
repeat area overflow interrupt is requested.
When used together with block transfer mode, an
interrupt is requested at the end of a block-size transfer.
If the DTE bit is set to 1 in EDMDR for the channel on
which transfer is terminated by an interrupt, transfer can
be resumed from the state in which it ended.
If a source address extended repeat area is not
designated, the specification by this bit is ignored.
0: Source address extended repeat area overflow
interrupt request disabled
1: Source address extended repeat area overflow
interrupt request enabled
14, 13

All 0
R
Reserved
They are always read as 0 and cannot be modified.
12
SARA4
0
R/W
Source Address Extended Repeat Area
11
SARA3
0
R/W
10
SARA2
0
R/W
9
SARA1
0
R/W
8
SARA0
0
R/W
These bits specify the source address (EDSAR)
extended repeat area. The extended repeat area
function updates the specified lower address bits,
leaving the remaining upper address bits always the
same. An extended repeat area size of 4 bytes to 128
Mbytes can be specified. The setting interval is a
power-of-two number of bytes.
When extended repeat area overflow results from
incrementing or decrementing an address, the lower
address is the start address of the extended repeat
area in the case of address incrementing, or the last
address of the extended repeat area in the case of
address decrementing.
If SARIE bit is set to 1, an interrupt can be requested
when an extended repeat area overflow occurs.
Table 11.3 shows the settings and ranges of the
extended repeat area.
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Section 11 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial
value
R/W
Description
7
DARIE
0
R/W
Destination Address Extended Repeat Area Overflow
Interrupt Enable
Enables or disables a destination address extended
repeat area overflow interrupt request.
When this bit is set to 1, in the event of destination
address extended repeat area overflow, the DTE bit in
EDMDR is cleared to 0. At the same time, the ESIF bit
in EDMDR is set to 1 to indicate that a destination
address extended repeat area overflow interrupt is
requested.
When used together with block transfer mode, an
interrupt is requested at the end of a block-size transfer.
If DTE bit is set to 1 in EDMDR for the channel on
which transfer is terminated by an interrupt, transfer can
be resumed from the state in which it ended. If a
destination address extended repeat area is not
designated, the specification by this bit is ignored.
0: Destination address extended repeat area overflow
interrupt request disabled
1: Destination address extended repeat area overflow
interrupt request enabled
6, 5

All 0
R
Reserved
They are always read as 0 and cannot be modified.
4
DARA4
0
R/W
Destination Address Extended Repeat Area
3
DARA3
0
R/W
2
DARA2
0
R/W
These bits specify the destination address (EDDAR)
extended repeat area.
1
DARA1
0
R/W
0
DARA0
0
R/W
The extended repeat area function updates the
specified lower address bits, leaving the remaining
upper address bits always the same. An extended
repeat area size of 4 bytes to 128 Mbytes can be
specified. The setting interval is a power-of-two number
of bytes.
When extended repeat area overflow results from
incrementing or decrementing an address, the lower
address is the start address of the extended repeat
area in the case of address incrementing, or the last
address of the extended repeat area in the case of
address decrementing.
If the DARIE bit is set to 1, an interrupt can be
requested when an extended repeat area overflow
occurs.
Table 11.3 shows the settings and ranges of the
extended repeat area.
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Section 11 EXDMA Controller (EXDMAC)
Table 11.3 Settings and Ranges of Extended Repeat Area
Value of SARA4 to SARA0/
DARA4 to DARA0
Range of Extended Repeat Area
00000
Not designated as extended repeat area
00001
Lower 1 bit (2-byte area) designated as extended repeat area
00010
Lower 2 bit (4-byte area) designated as extended repeat area
00011
Lower 3 bit (8-byte area) designated as extended repeat area
00100
Lower 4 bit (16-byte area) designated as extended repeat area
00101
Lower 5 bit (32-byte area) designated as extended repeat area
00110
Lower 6 bit (64-byte area) designated as extended repeat area
00111
Lower 7 bit (128-byte area) designated as extended repeat area
01000
Lower 8 bit (256-byte area) designated as extended repeat area
01001
Lower 9 bit (512-byte area) designated as extended repeat area
01010
Lower 10 bit (1-kbyte area) designated as extended repeat area
01011
Lower 11 bit (2-kbyte area) designated as extended repeat area
01100
Lower 12 bit (4-kbyte area) designated as extended repeat area
01101
Lower 13 bit (8-kbyte area) designated as extended repeat area
01110
Lower 14 bit (16-kbyte area) designated as extended repeat area
01111
Lower 15 bit (32-kbyte area) designated as extended repeat area
10000
Lower 16 bit (64-kbyte area) designated as extended repeat area
10001
Lower 17 bit (128-kbyte area) designated as extended repeat area
10010
Lower 18 bit (256-kbyte area) designated as extended repeat area
10011
Lower 19 bit (512-kbyte area) designated as extended repeat area
10100
Lower 20 bit (1-Mbyte area) designated as extended repeat area
10101
Lower 21 bit (2-Mbyte area) designated as extended repeat area
10110
Lower 22 bit (4-Mbyte area) designated as extended repeat area
10111
Lower 23 bit (8-Mbyte area) designated as extended repeat area
11000
Lower 24 bit (16-Mbyte area) designated as extended repeat area
11001
Lower 25 bit (32-Mbyte area) designated as extended repeat area
11010
Lower 26 bit (64-Mbyte area) designated as extended repeat area
11011
Lower 27 bit (128-Mbyte area) designated as extended repeat area
111XX
Setting prohibited
[Legend] X: Don't care
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Section 11 EXDMA Controller (EXDMAC)
11.3.8
Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7)
CLSBR0 to CLSBR7 are 32-bit readable/writable registers that store the transfer data. The transfer
data is stored in order from CLSBR0 to CLSBR7 in cluster transfer mode. The data stored in
cluster transfer mode or by the CPU write operation is held until the next cluster transfer or CPU
write operation is performed.
When reading the data stored in cluster transfer mode by the CPU, check the completion of cluster
transfer and then perform only a cluster-size read specified for the cluster transfer. Data with
another size is undefined.
In cluster transfer mode, the same CLSBR is used for all channels. When the CPU write operation
to CLSBR conflicts with cluster transfer, the contents of transferred data are not guaranteed. When
cluster transfer read/write address mode is specified and if another channel is set for cluster
transfer, the transferred data may be overwritten.
Bit
31
30
29
28
27
26
25
24
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
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Section 11 EXDMA Controller (EXDMAC)
11.4
Transfer Modes
11.4.1
Ordinary Modes
The ordinary modes of EXDMAC are summarized in table 11.4. The transfer mode can be set
independently for each channel.
Table 11.4 Ordinary Modes
Address
Mode
Dual
address
mode
Address Register
Transfer Mode
Activation Source
Common Function
Source
Destination
•
•
•
EDSAR
EDDAR
Direct data transfer to/from external devices using EDACK pin
EDSAR/
EDACK/
instead of source or destination address register
EDACK
EDDAR
Normal transfer
•
•
•
External request
Block transfer
mode
Total transfer size:
1 to 4 Gbytes,
CPU)
Repeat transfer
mode
Auto-request
(activated by the
mode
or no specification
•
Offset addition
•
Extended repeat
area function
(Repeat size/
block size
= 1 to 65,536 bytes/
word/longword)
Single
address
mode
•
•
Above transfer mode can be specified in addition to address
register setting
•
One transfer possible in one bus cycle
(Transfer mode variations are the same as in dual address mode.)
When the activation source is an auto-request, cycle steal mode or burst mode can be selected.
When the total transfer size is not specified (EDTCR = H'00000000), the transfer counter is halted
and the transfer count is not restricted, allowing continuous transfer.
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Section 11 EXDMA Controller (EXDMAC)
11.4.2
Cluster Transfer Modes
Table 11.5 shows cluster transfer modes. Cluster transfer mode can be set independently for each
channel. The cluster buffer is common to all channels.
Table 11.5 Cluster Transfer Mode
Cluster
Buffer
Function
Transfer
Destination
Address Mode
Activation Source
Common Function
Transfer
Source
Cluster transfer
•
•
EDSAR
Read from
the transfer
source and
written to
the transfer
destination
EDDAR
EDSAR
Read from
the transfer
source


Written to
the transfer
destination
EDDAR
Dual address mode
•
Auto-request
One access size
the CPU)
(byte/word/longword)
to 32 bytes
External
request
•
specification
Read address mode
Cluster transfer
Total transfer size
1 to 4 Gbytes, or no
Cluster transfer
(DIRS = 0)
Cluster size
(activated by
•
Offset addition
•
Extended repeat
Write address mode
area function
(DIRS = 1)
In cluster transfer mode, the specified cluster size is transferred in response to a single transfer
request. The cluster size can be from one access size (byte, word, or longword) to 32 bytes. Within
a cluster, a cluster-size transfer is performed in burst transfer mode. With a cluster-size access in
cluster transfer mode (dual address mode), block transfer mode (dual address mode) is used.
With auto-requests, cycle steal mode is set.
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Section 11 EXDMA Controller (EXDMAC)
11.5
Mode Operation
11.5.1
Address Modes
(1)
Dual Address Mode
In dual address mode, the transfer source address is set in EDSAR, and the transfer destination
address is set in EDDAR. One transfer operation is executed in two bus cycles. (When the data
bus width is smaller than the data access size or when the address to be accessed is not at the data
boundary of the data access size, the bus cycle is divided, resulting more than two bus cycles.)
In a transfer operation, the data on the transfer source address is read in the first bus cycle, and is
written to the transfer destination address in the next bus cycle.
These consecutive read and write cycles are indivisible: another bus cycle (external access by
another bus master, refresh cycle, or external bus release cycle) does not occur between these two
cycles.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for two consecutive bus cycles. When an idle cycle is inserted before the bus cycle, the
ETEND signal is also output in the idle cycle. The EDACK signal is not output.
Figure 11.2 shows an example of the timing in dual address mode and figure 11.3 shows the dual
address mode operation.
EXDMA read
cycle
EXDMA write
cycle
EDSAR
EDDAR
Bφ
Address bus
RD
WR
ETEND
Figure 11.2 Example of Timing in Dual Address Mode
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Section 11 EXDMA Controller (EXDMAC)
Address TB
Transfer
Address TA
Address BA
Address update setting
The source address incremented
The destination adderss is fixed
Figure 11.3 Dual Address Mode Operation
(2)
Single Address Mode
In single address mode, the EDACK pin is used instead of EDSAR or EDDAR to transfer data
directly between an external device and external memory. One transfer operation is executed in
one bus cycle.
In this mode, the data bus width must be the same as the data access size. For details on the data
bus width, see section 9, Bus Controller (BSC).
In this mode, the EXDMAC accesses the transfer source or transfer destination external device by
outputting the strobe signal (EDACK) for the external device with DACK, and at the same time
accesses the other external device in the transfer by outputting an address. In this way, EXDMA
transfer can be executed in one bus cycle. In the example of transfer between external memory and
an external device with DACK shown in figure 11.4, data is output to the data bus by the external
device and written to external memory in the same bus cycle.
The transfer direction, that is whether the external device with DACK is the transfer source or
transfer destination, can be specified with the DIRS bit in EDACR. Transfer is performed from the
external memory (EDSAR) to the external device with DACK when DIRS = 0, and from the
external device with DACK to the external memory (EDDAR) when DIRS = 1. The setting in the
source or destination address register not used in the transfer is ignored.
The EDACK pin output is valid by the setting of EDACKE bit in EDMDR when single address
mode is selected. The EDACK pin output is active-low.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for one bus cycle. When an idle cycle is inserted before the bus cycle, the ETEND signal
is also output in the idle cycle.
Figure 11.5 shows an example of the timing in single address mode and figure 11.6 shows the
single address mode operation.
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Section 11 EXDMA Controller (EXDMAC)
External
address bus
External
data bus
LSI
External
memory
EXDMAC
Data flow
External device
with DACK
EDACK
EDREQ
Figure 11.4 Data Flow in Single Address Mode
Transfer from external memory to external device with DACK
EXDMA cycle
Bφ
Address bus
EDSAR
RD
Address for external memory space
RD signal to external memory space
WR
High
EDACK
Data output by external memory
Data bus
ETEND
Transfer from external device with DACK to external memory
EXDMA cycle
Bφ
Address bus
RD
EDDAR
Address for external memory space
High
WR
WR signal to external memory space
EDACK
Data bus
Data output from external device with DACK
ETEND
Figure 11.5 Example of Timing in Single Address Mode
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Section 11 EXDMA Controller (EXDMAC)
Address T
EDACK
Transfer
Address B
Figure 11.6 Single Address Mode Operation
11.5.2
(1)
Transfer Modes
Normal Transfer Mode
In normal transfer mode, transfer of one data access size unit is processed in response to one
transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. EDBSR is invalid
in normal transfer mode.
The ETEND signal is output only for the last EXDMA transfer. The EDRAK signal is output each
time a transfer request is accepted and transfer processing is started.
Figure 11.7 shows examples of transfer timing in normal transfer mode and figure 11.8 shows the
normal transfer mode operation in dual address mode.
Transfer conditions: Dual address mode, auto-request mode
EXDMA transfer
cycle
Bus cycle
Read
Write
Last EXDMA
transfer cycle
Read
Write
ETEND
Transfer conditions: Single address mode, external request mode
EDREQ
EDRAK
Bus cycle
EXDMA
EXDMA
EDACK
Figure 11.7 Examples of Timing in Normal Transfer Mode
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Section 11 EXDMA Controller (EXDMAC)
Transfer
Address TA
Address TB
Total transfer
size (EDTCR)
Address BA
Address BB
Figure 11.8 Normal Transfer Mode Operation
(2)
Repeat Transfer Mode
In repeat transfer mode, transfer of one data access size unit is processed in response to one
transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. The repeat size of
up to 64 kbytes × data access size can be set by EDBSR.
The ARS1 and ARS0 bits in EDACR specify the repeat area on the source address or destination
address side. The address specified for the repeat area is restored to the transfer start address at the
end of a repeat-size transfer. This operation continues until transfer of total transfer size set in
EDTCR ends. EDTCR specified with H'00000000 is assumed as free-running mode and the repeat
transfer continues until the DTE bit in EDMDR is cleared to 0.
At the end of a repeat-size transfer, the EXDMA transfer is halted temporarily and a repeat size
end interrupt is requested to the CPU or DTC. When the RPTIE bit in EDACR is set to 1 and the
next transfer request is generated at the end of a repeat-size transfer, the ESIF bit in EDMDR is set
to 1 and the DTE bit in EDMDR is cleared to 0 to terminate the transfer. At this time, an interrupt
is requested to the CPU or DTC when the ESIE bit in EDMDR is set to 1.
The timing of EXDMA transfer including the ETEND or EDRAK output is the same as for
normal transfer mode.
Figure 11.9 shows the repeat transfer mode operation in dual address mode.
The operation without specifying a repeat area on the source or destination address side is the
same as for the normal transfer mode operation shown in figure 11.8. In this case, a repeat size end
interrupt can also be generated at the end of a repeat-size transfer.
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Section 11 EXDMA Controller (EXDMAC)
Address TA
Transfer
Address TB
Repeat size
(BKSZH ×
data access size)
Total transfer
size (EDTCR)
Address BA
Operation with the repeat area
specified on the source address side
Address BB
Figure 11.9 Repeat Transfer Mode Operation
(3)
Block Transfer Mode
In block transfer mode, transfer of one block size unit is processed in response to one transfer
request. The total transfer size of up to 4 Gbytes can be set by EDTCR. The block size of up to 64
kbytes × data access size can be set by EDBSR.
A transfer request from another channel is held pending during one block transfer. When oneblock transfer is completed, the bus mastership is released for another bus master.
A block area can be specified by the ARS1 or ARS0 bit in EDACR on the source or destination
address side. The address specified for the block area is restored to the transfer start address each
time one-block transfer completes. When no repeat area is specified on the source and destination
address sides, the address is not restored to the transfer start address and the operation proceeds to
the next sequence. A repeat size end interrupt can be generated.
The ETEND signal is output for each block transfer in the EXDMA transfer cycle in which the
block ends. The EDRAK signal is output once for one transfer request (for transfer of one block).
Caution is required when setting the extended repeat area overflow interrupt in block transfer
mode. For details, see section 11.5.5, Extended Repeat Area Function.
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Section 11 EXDMA Controller (EXDMAC)
Figure 11.10 shows an example of EXDMA transfer timing in block transfer mode. The transfer
conditions are as follows:
Address mode: Single address mode
Data access size: In bytes
One block size: 3 bytes
Figure 11.11 shows the block transfer mode operation in single address mode and figure 11.12
shows the block transfer mode operation in dual address mode.
EDREQ
EDRAK
Bus cycle
One-block transfer cycle
CPU
CPU
EXDMAC
EXDMAC
EXDMAC
CPU
CPU cycle not generated
ETEND
Figure 11.10 Example of Block Transfer Mode
Address T
Block
Transfer
EDACK
BKSZH ×
data access size
Address B
Figure 11.11 Block Transfer Mode Operation in Single Address Mode
(with Block Area Specified)
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Section 11 EXDMA Controller (EXDMAC)
Address TA
First block
Address TB
Transfer
First block
BKSZH ×
data access size
Second block
Second block
Total transfer
size (EDTCR)
Nth block
Nth block
Address BB
Address BA
Figure 11.12 Block Transfer Mode Operation in Dual Address Mode (without Block Area
Specified)
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Section 11 EXDMA Controller (EXDMAC)
11.5.3
Activation Sources
The EXDMAC is activated by an auto request or an external request. This activation source is
selected by the DTF1 or DTF0 bit in EDMDR.
(1)
Activation by Auto-Request
The transfer request signal is automatically generated in EXDMAC with auto-request activation
when no transfer request signal is generated from external or peripheral modules, incase of
transfer among memory or between memory and peripheral modules that cannot generate the
transfer request signal. The transfer starts when the DTE bit in EDMDR is set to 1 with autorequest activation. The bus mode can be selected from cycle steal mode and burst mode with autorequest activation.
(2)
Activation by External Request
Transfer is started by the transfer request signal (EDREQ) from the external device for activation
by an external request. When the EXDMA transfer is enabled (DTE = 1), the EXDMA transfer
starts by EDREQ input.
The transfer request signal is accepted by the EDREQ pin. The EDREQS bit in EDMDR selects
whether the EDREQ is detected by falling edge sensing or low level sensing.
When the EDRAKE bit in EDMDR is set to 1, the signal notifying transfer request acceptance is
output from the EDRAK pin. The EDRAK signal is accepted for one external request and is
output when transfer processing starts.
When specifying an external request as an activation source, set the DDR bit to 0 and the ICR bit
to 1 on the corresponding pin in advance. For details, see section 13, I/O Ports.
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Section 11 EXDMA Controller (EXDMAC)
11.5.4
Bus Mode
There are two bus modes: cycle steal mode and burst mode.
For auto-request activation, either cycle steal mode or burst mode can be selected by the DTF0 bit
in EDMDR. When the activation source is an external request, cycle steal mode is used.
(1)
Cycle Steal Mode
In cycle steal mode, the EXDMAC releases the bus mastership at the end of each transfer of a
transfer unit (byte, word, longword, one block size, or one cluster size). If there is a subsequent
transfer request, the EXDMAC takes back the bus mastership, performs another transfer-unit
transfer, and then releases the bus mastership again at the end of the transfer. This procedure is
repeated until the transfer end condition is satisfied.
If a transfer request occurs in another channel during EXDMA transfer, the bus mastership is
temporarily released for another bus master, then transfer is performed on the channel for which
the transfer request was issued. For details on the operation when there are transfer requests for a
number of channels, see section 11.5.8, Channel Priority Order.
Figure 11.13 shows an example of the timing in cycle steal mode. The transfer conditions are as
follows:
• Address mode: Single address mode
• Sampling method on the EDREQ pin: Low level sensing
• CPU internal bus master is operating in external space
EDREQ
EDRAK
Bus cycle
CPU
CPU
EXDMAC
CPU
EXDMAC
CPU
Bus mastership returned temporarily to CPU
Figure 11.13 Example of Timing in Cycle Steal Mode
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Section 11 EXDMA Controller (EXDMAC)
(2)
Burst Mode
In burst mode, once the EXDMAC acquires the bus mastership, it continues transferring data,
without releasing the bus mastership, until the transfer end condition is satisfied. In burst mode,
once transfer is started it is not interrupted even if there is a transfer request for another channel
with higher priority. When the burst mode channel finishes its transfer, it releases the bus
mastership in the next cycle in the same way as in cycle steal mode. However, when the EBCCS
bit in BCR2 of the bus controller is set to 1, the EXDMAC can temporarily release the bus
mastership for another bus master when an external access request is generated from another bus
master.
In block transfer mode and cluster transfer mode, the setting of burst mode is invalid (one-block or
one-cluster transfer is processed in the same way as in burst mode). The EXDMAC always
operates in cycle steal mode.
When the DTE bit is cleared to 0 in EDMDR, EXDMA transfer is halted. However, EXDMA
transfer is executed for all transfer requests generated within the EXDMAC until the DTE bit is
cleared to 0. If a transfer size error interrupt, a repeat size end interrupt, or extended repeat area
overflow interrupt is generated, the DTE bit is cleared to 0 and transfer is terminated.
Figure 11.14 shows an example of the timing in burst mode.
Bus cycle
CPU
CPU
EXDMAC
EXDMAC
EXDMAC
CPU
CPU
CPU cycle not generated
Figure 11.14 Example of Timing in Burst Mode
11.5.5
Extended Repeat Area Function
The EXDMAC has a function for designating an extended repeat area for source addresses and/or
destination addresses. When an extended repeat area is designated, the address register values
repeat within the range specified as the extended repeat area. Normally, when a ring buffer is
involved in a transfer, an operation is required to restore the address register value to the buffer
start address each time the address register value becomes the last address in the buffer (i.e. when
ring buffer address overflow occurs). However, if the extended repeat area function is used, the
operation that restores the address register value to the buffer start address is processed
automatically within the EXDMAC.
The extended repeat area function can be set independently for the source address register
(EDSAR) and the destination address register (EDDAR).
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The source address extended repeat area is specified by bits SARA4 to SARA0 in EDACR, and
the destination address extended repeat area by bits DARA4 to DARA0 in EDACR. The size of
each extended repeat area can be specified independently.
When the address register value is the last address in the extended repeat area and extended repeat
area overflow occurs, EXDMA transfer can be temporarily halted and an extended repeat area
overflow interrupt request can be generated for the CPU. If the SARIE bit in EDACR is set to 1,
and the EDSAR extended repeat area overflows, the ESIF bit is set to 1 and the DTE bit cleared to
0 in EDMDR, and transfer is terminated. If the ESIE bit is set to 1 in EDMDR, an extended repeat
area overflow interrupt is requested to the CPU. If the DARIE bit in EDACR is set to 1, the above
applies to the destination address register. If the DTE bit in EDMDR is set to 1 during interrupt
generation, transfer is resumed.
Figure 11.15 illustrates the operation of the extended repeat area function.
When lower 3 bits (8-byte area) of EDSAR are designated
as extended repeat area (SARA4 to SARA0 = B'00011)
...
External memory
Range of
EDSAR values
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
Repeat
Extended repeat area overflow
interrupt can be requested
...
H'23FFFE
H'23FFFF
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
H'240008
H'240009
Figure 11.15 Example of Extended Repeat Area Function Operation
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Section 11 EXDMA Controller (EXDMAC)
Caution is required when the extended repeat area overflow interrupt is used together with block
transfer mode. If transfer is always terminated when extended repeat area overflow occurs in block
transfer mode, the block size must be a power of two, or alternatively, the address register value
must be set so that the end of a block coincides with the end of the extended repeat area range. If
extended repeat area overflow occurs during a block-size transfer in block transfer mode, the
extended repeat area overflow interrupt request is held pending until the end of the block, and
transfer overrun will occur.
The same caution is required when the extended repeat area overflow interrupt is used together
with cluster transfer mode.
Figure 11.16 shows an example in which block transfer mode is used together with the extended
repeat area function.
External memory
Range of
EDSAR values
H'23FFFE
H'23FFFF
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
H'240008
H'240009
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
First block
transfer
H'240000
H'240001
H'240002
H'240003
H'240004
Second block
transfer
H'240000
H'240001
H'240005
H'240006
H'240007
Interrupt
requested
Block transfer in progress
...
...
When lower 3 bits (8-byte area) of EDSAR are designated as extended repeat area (SARA4 to
SARA0 = 3), and block size of 5 (bits 23 to 16 in EDTCR = 5) is set in block transfer mode.
Figure 11.16 Example of Extended Repeat Area Function Operation in Block Transfer
Mode
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Section 11 EXDMA Controller (EXDMAC)
11.5.6
Address Update Function Using Offset
There are the following update methods for transfer destination and source addresses: Fixed,
increment/decrement by 1, 2 or 4, and offset addition. With the offset addition method, the offset
specified by the offset register (EDOFR) is added each time the EXDMAC performs a dataaccess-size transfer. This function allows the mid-addresses being skipped during data transfer.
Figure 11.17 shows the address update methods.
External memory
External memory
±0
External memory
±1, 2, or 4
+ Offset
Address not
updated
Value, that corresponds
to data access size,
incremented, decremented
to/from the address
(Successive addresses)
Offset value added to the address
(Insuccessive addresses)
(a) Fixed
(b) Increment/decrement
by 1, 2 or 4
(c) Offset addition
Figure 11.17 Address Update Method
For the fixed method (a), the same address is always indicated without the transfer destination or
source address being updated.
For the method of increment/decrement by 1, 2 or 4 (b), the value corresponding to the data access
size is incremented or decremented to or from the transfer destination or source address each time
the data is transferred. A byte, word, or longword can be specified for the data access size. The
value used for increment or decrement of an address is 1 for a byte-size , 2 for a word-size , and 4
for a longword-size transfer. This function allows continuous address transfer of EXDMAC.
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For the offset addition method (c), address operation is not performed based on the data access
size. The EXDMAC adds the value set by EDOFR to the transfer destination or source address for
each time the data is transferred.
The EXDMAC sets the offset value in EDOFR and operates using EDSAR or EDDAR. The
EXDMAC can only add the offset value, but subtraction of the offset value is also possible by
setting a negative value in EDOFR. Specify a twos complement for a negative offset value.
(1)
Basic transfer using offset
Figure 11.18 shows the basic operation of transfer using an offset.
Data 1
Address A1
Transfer
Offset value
Data 2
Data 1
Data 2
Data 3
Data 4
Data 5
:
Address B1
Address B2 = Address B1 + 4
Address B3 = Address B2 + 4
Address B4 = Address B3 + 4
Address B5 = Address B4 + 4
Address A2
= Address A1 + Offset
:
:
:
Offset value
Data 3
Address A3
= Address A2 + Offset
Data 4
Address A4
= Address A3 + Offset
Offset value
Offset value
Data 5
Address A5
= Address A4 + Offset
Transfer source:
Offset added
Transfer destination: Incremented by 4
(with a longword-size selected)
Figure 11.18 Address Update Function Using Offset
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In figure 11.18, the offset addition method is set for updating the transfer source address, and the
method of increment/decrement 1, 2 or 4 is set for updating the transfer destination address. For
updating the second and subsequent transfer source addresses, the data of the address for which
the offset value is added to the previous transfer address is read. This data is written to the
successive area on the transfer destination.
(2)
Example of XY conversion using offset
Figure 11.19 shows the XY conversion by combining the repeat transfer mode and offset
addition.
Data 1
Data 2
Data 3
Data 4
Data 5 Data 9 Data 13
Data 6 Data 10 Data 14
Data 7 Data 11 Data 15
Data 8 Data 12 Data 16
1st transfer
Transfer
First cycle
Second cycle
Third cycle
First cycle
Data 1
Data 5
Data 9
Data 13
Data 2 Data 3
Data 6 Data 7
Data 10 Data 11
Data 14 Data 15
Data 4
Data 8
Data 12
Data 16
2nd transfer Transfer source 3rd transfer
address
overwritten
by CPU
Offset value
Offset value
Offset value
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Address
restored
Interrupt
requested
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Address
restored
Interrupt
requested
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Transfer
Transfer source
address
overwritten
by CPU
Interrupt
requested
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Data 16
First cycle
Second cycle
Third cycle
Fourth cycle
Figure 11.19 XY Conversion by Combining Repeat Transfer Mode and Offset Addition
In figure 11.19, the source address side is set as a repeat area in EDACR and the offset addition is
set in EDACR. The offset value is the address that corresponds to 4 × data access size (example:
for a longword-size transfer, H'00000010 is specified in EDOFR). The repeat size is 4 × data
access size (example: for a longword-size transfer, 4 × 4 = 16 bytes are specified as a repeat size).
The increment by 1, 2 or 4 is set for the transfer destination. The RPTIE bit in EDACR is set to 1
to generate a repeat size end interrupt request at the end of a repeat-size transfer.
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When transfer starts, the offset value is added to the transfer source address and the data is
transferred. The data is aligned in the order of transfer in the transfer destination. After up to data
4 is transferred, the EXDMAC assumes that a repeat-size transfer completed, and restores the
transfer source address to the transfer start address (address of transfer source data 1). At the same
time, a repeat size end interrupt is requested. This interrupt request aborts the transfer temporarily.
Overwrite the EDSAR value to the data 5 address by accessing the I/O register via the CPU. (For
longword transfer, add 4 to the address of data 1.) When the DTE bit in EDMDR is set to 1,
transfer is resumed from the state in which the transfer is aborted. The transfer source data is XYconverted and transferred to the transfer destination by repeating the above processing.
Figure 11.20 shows the XY conversion flow.
Start
Set address and transfer count
Set repeat transfer mode
Enable repeat cancel interrupt
Set DTE bit to 1
Transfer request accepted
No
Data transfer
Repeat size = 0
Yes
Transfer counter and
repeat size decremented
Transfer source address restored
End of repeat size
Interrupt requested
No
Transfer count = 0
Yes
Set transfer source address + 4
(For longword transfer)
End
: User side
:EXDMAC side
Figure 11.20 Flow of XY Conversion Combining Repeat Transfer Mode and Offset
Addition
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Section 11 EXDMA Controller (EXDMAC)
(3)
Offset subtraction specification
To set a negative value in EDOFR, specify a twos complement as an offset value. A twos
complement is derived by the following expression:
[Twos complement expression for negative offset value] = −[offset value] + 1 (−: bit reverse)
Example: Twos complement expression of H'0001FFFF
= H'FFFE0000 + H'00000001
= H'FFFE0001
A twos complement can be derived by the NEG.L instruction of the CPU.
11.5.7
Registers during EXDMA Transfer Operation
EXDMAC register values are updated as EXDMA transfer processing is performed. The updated
values depend on various settings and the transfer status. The following registers and bits are
updated: EDSAR, EDDAR, EDTCR, bits BKSZH and BKSZ in EDBSR, and bits DTE, ACT,
ERRF, ESIF and DTIF in EDMDR.
(1)
EXDMA Source Address Register (EDSAR)
When the EDSAR address is accessed as the transfer source, the EDSAR value is output, and then
EDSAR is updated with the address to be accessed next.
Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed
when SAT1 and SAT0 = B′00, incremented by offset register value when SAT1 and SAT0 =
B′01, incremented when SAT1 and SAT0 = B′10, and decremented when SAT1 and SAT0 =
B′11. (The increment or decrement value is determined by the data access size.)
The DTSZ1 and DTSZ0 bits in EDMDR set the data access size. When DTSZ1 and DTSZ0 =
B′00, the data is byte-size and the address is incremented or decremented by 1. When DTSZ1 and
DTSZ0 = B′01, the data is word-size and the address is incremented or decremented by 2. When
DTSZ1and DTSZ0 = B′10, the data is longword-size and the address is incremented or
decremented by 4. When a word-size or longword-size is specified but the source address is not at
the word or longword boundary, the data is divided into bytes or words for reading. When a word
or longword is divided for reading, the address is incremented or decremented by 1 or 2 according
to an actual byte-or word-size read. After a word-size or longword-size read, the address is
incremented or decremented to or from the read start address according to the setting of SAT1 and
SAT0.
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Section 11 EXDMA Controller (EXDMAC)
When a block area (repeat area) is set for the source address in block transfer mode (or repeat
transfer mode), the source address is restored to the transfer start address at the end of block-size
(repeat-size) transfer and is not affected by address updating.
When an extended repeat area is set for the source address, the operation conforms to that setting.
The upper addresses set for the extended repeat area is fixed, and is not affected by address
updating.
When EDSAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. Do not write to
EDSAR for a channel on which a transfer operation is in progress.
(2)
EXDMA Destination Address Register (EDDAR)
When the EDDAR address is accessed as the transfer destination, the EDDAR value is output, and
then EDDAR is updated with the address to be accessed next.
Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The address is fixed
when DAT1 and DAT0 = B′00, incremented by offset register value when DAT1 and DAT0 =
B′01, incremented when DAT1 and DAT0 = B′10, and decremented when DAT1 and DAT0 =
B′11. (The increment or decrement value is determined by the data access size.)
The DTSZ1 and DTSZ0 bits in EDMDR set the data access size. When DTSZ1 and DTSZ0 =
B′00, the data is byte-size and the address is incremented or decremented by 1. When DTSZ1 and
DTSZ0 = B′01, the data is word-size and the address is incremented or decremented by 2. When
DTSZ1 and DTSZ0 = B′10, the data is longword-size and the address is incremented or
decremented by 4. When a word-size or longword-size is specified but the destination address is
not at the word or longword boundary, the data is divided into bytes or words for writing. When a
word or a longword is divided for writing, the address is incremented or decremented by 1 or 2
according to an actual byte- or word-size written. After a word-size or longword-size write, the
address is incremented or decremented to or from the write start address according to the setting of
SAT1 and SAT0.
When a block area (repeat area) is set for the destination address in block transfer mode (or repeat
transfer mode), the destination address is restored to the transfer start address at the end of blocksize (repeat-size) transfer and is not affected by address updating.
When an extended repeat area is set for the destination address, the operation conforms to that
setting. The upper addresses set for the extended repeat area is fixed, and is not affected by
address updating.
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Section 11 EXDMA Controller (EXDMAC)
When EDDAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. Do not write to
EDDAR for a channel on which a transfer operation is in progress.
(3)
EXDMA Transfer Count Register (EDTCR)
When an EXDMA transfer is performed, the value in EDTCR is decremented by the number of
bytes transferred. When a byte is transferred, the value is decremented by 1; when a word is
transferred, the value is decremented by 2; when a longword is transferred, the value is
decremented by 4. However, when the EDTCR value is 0, transfers are not counted and the
EDTCR value does not change.
All of the bits of EDTCR may change, so when EDTCR is read by the CPU during EXDMA
transfer, a longword access must be used. During a transfer operation, EDTCR may be updated
without regard to accesses from the CPU, and the correct values may not be read if the upper and
lower words are read separately. Do not write to EDTCR for a channel on which a transfer
operation is in progress.
If there is conflict between an address update associated with EXDMA transfer and a write by the
CPU, the CPU write has priority.
In the event of conflict between an EDTCR update from 1, 2, or 4 to 0 and a write (of a nonzero
value) by the CPU, the CPU write value has priority as the EDTCR value, but transfer is
terminated.
(4)
EXDMA Block Size Register (EDBSR)
EDBSR is valid in block transfer or repeat transfer mode. EDBSR31 and EDBSR16 are used as
BKSZH and EDBSR15 and EDBSR0 for BKSZ. The 16 bits of BKSZH holds a block size and
repeat size and their values do not change. The 16 bits of BKSZ functions as a block size or repeat
size counter, the value of which is decremented by 1 when one data transfer is performed. When
the BKSZ value is determined as 0 during EXDMA transfer, the EXDMAC does not store 0 in
BKSZ and stores the BKSZH value.
The upper 16 bits of EDBSR is never updated, allowing a word-size access.
Do not write to EDBSR for a channel on which a transfer operation is in progress.
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Section 11 EXDMA Controller (EXDMAC)
(5)
DTE Bit in EDMDR
The DTE bit in EDMDR is written to by the CPU to control enabling and disabling of data
transfer, but may be cleared to 0 automatically by the EXDMAC due to the EXDMA transfer
status.
Conditions for DTE bit clearing by the EXDMAC include the following:
•
•
•
•
•
•
•
•
•
When the specified total transfer size is completely transferred
A transfer size error interrupt is requested, and transfer ends
A repeat size end interrupt is requested, and transfer ends
When an extended repeat area overflow interrupt is requested, and transfer ends
When an NMI interrupt is generated, and transfer halts
When an address error is generated, and transfer halts
A reset
Hardware standby mode
When 0 is written to the DTE bit, and transfer halts
Writes (except to the DTE bit) are prohibited to registers of a channel for which the DTE bit is set
to 1. When changing register settings after a 0-write to the DTE bit, it is necessary to confirm that
the DTE bit has been cleared to 0.
Figure 11.21 shows the procedure for changing register settings in an operating channel.
Changing register settings
in operating channel
Write 0 to DTE bit
[1]
Read DTE bit
[2]
DTE bit = 0
No
[1] Write 0 to the DTE bit in EDMDR
[2] Read DTE bit.
[3] Confirm that DTE bit = 0. If DTE bit = 1,
this indicates that EXDMA transfer is in progress.
[4] Write the required set values to the registers.
[3]
Yes
Change register settings
[4]
Register setting
changes completed
Figure 11.21 Procedure for Changing Register Settings in Operating Channel
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Section 11 EXDMA Controller (EXDMAC)
(6)
ACT bit in EDMDR
The ACT bit in EDMDR indicates whether the EXDMAC is in standby or active state. When DTE
= 0 and DTE = 1 (transfer request wait status) are specified, the ACT bit is set to 0. In another case
(EXDMAC in the active state), the ACT bit is set to 1. The ACT bit is held to 1 during EXDMA
transfer even if 0 is written to the DTE bit to halt transfer.
In block transfer mode, a block-size transfer is not halted even if 0 is written to the DTE bit to halt
transfer. The ACT bit is held to 1 until a block-size transfer completes after 0 is written to the
DTE bit.
In burst mode, transfer is halted after up to three times of EXDMA transfers are performed since
the bus cycle in which 0 is written to the DTE bit has been processed. The ACT bit is held to 1
between termination of the last EXDMA cycle and 0-write in the DTE bit.
(7)
ERRF bit in EDMDR
This bit specifies termination of transfer by EXDMAC clearing the DTE bit to 0 for all channels if
an address error or NMI interrupt is generated. The EXDMAC also sets 1 to the ERRF bit of
EDMDR_0 regardless of the EXDMAC operation to indicate that an address error or NMI
interrupt is generated. However, when an address error or an NMI interrupt has been generated in
EXDMAC module stop mode, the ERRF bit is not set to 1.
(8)
ESIF bit in EDMDR
The ESIF bit in EDMDR is set to 1 when a transfer size interrupt, repeat size end interrupt, or an
extended repeat area overflow interrupt is requested. When the ESIF bit is set to 1 and the ESIE
bit in EDMDR is set to 1, a transfer escape interrupt is requested to the CPU or DTC.
The timing that the ESIF bit is set to 1 is when the EXDMA transfer bus cycle (the source of an
interrupt request) terminates, the ACT bit in EDMDR is set to 0, and transfer is terminated.
When the DTE bit is set to 1 to resume transfer during interrupt processing, the ESIF bit is
automatically cleared to 0 to cancel the interrupt request.
For details on interrupts, see section 11.9, Interrupt Sources.
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Section 11 EXDMA Controller (EXDMAC)
(9)
DTIF bit in EDMDR
The DTIF bit in EDMDR is set to 1 after the data of total transfer size is transferred completely by
EXDMA transfer. When the DTIF bit is set to 1 and the DTIE bit in EDMDR is set to 1, a transfer
end interrupt by the transfer counter is requested to the CPU or DTC.
The timing that the DTIF bit is set to 1 is when the EXDMA transfer bus cycle is terminated, the
ACT bit in EDMDR is set to 0, and the transfer is terminated.
When the DTE bit is set to 1 to resume transfer during interrupt processing, the DTIF bit is
automatically cleared to 0 to cancel the interrupt request.
For details on interrupts, see section 11.9, Interrupt Sources.
11.5.8
Channel Priority Order
The priority order of the EXDMAC channels is: channel 0 > channel 1 > channel 2 > channel 3.
Table 11.6 shows the EXDMAC channel priority order.
Table 11.6 EXDMAC Channel Priority Order
Channel
Channel Priority
Channel 0
High
Channel 1
Channel 2
Channel 3
Low
If transfer requests occur simultaneously for a number of channels, the highest-priority channel
according to the priority order is selected for transfer. Transfer starts after the channel in progress
releases the bus. If a bus request is issued from another bus master other than EXDMAC during a
transfer operation, another bus master cycle is initiated.
Channels are not switched during burst transfer, a block-size transfer in block transfer mode or a
cluster-size transfer in cluster transfer mode.
Figure 11.22 shows an example of the transfer timing when transfer requests occur simultaneously
for channels 0, 1, and 2.
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Section 11 EXDMA Controller (EXDMAC)
Channel 1 transfer
Channel 0 transfer
Channel 2 transfer
Bφ
Address bus
Channel 0
Idle
EXDMAC
control
Channel 0
Request cleared
Channel 1
Request Selected
held
Channel 2
Request Not
Request
selected held
held
Idle
Channel 2
Channel 1
Channel 0
Channel 2
Channel 1
Request cleared
Selected
Request cleared
Figure 11.22 Example of Channel Priority Timing
11.5.9
Basic Bus Cycles
An example of the basic bus cycle timing is shown in figure 11.23. In this example, word-size
transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus
mastership is transferred from the CPU to the EXDMAC, a source address read and destination
address write are performed. The bus is not released in response to another bus request, etc.,
between these read and write operations. As like CPU cycles, EXDMAC cycles conform to the
bus controller settings.
CPU cycle
EXDMAC cycle (one word transfer)
T1
T2
T1
T2
T3
T1
T2
CPU cycle
T3
Bφ
Source address
Destination address
Address bus
RD
LHWR
High
LLWR
Figure 11.23 Example of EXDMA Transfer Bus Timing
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11.5.10 Bus Cycles in Dual Address Mode
(1)
Normal Transfer Mode (Cycle Steal Mode)
In cycle steal mode, the bus is released after one byte, word, or longword has been transferred.
While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated.
Figure 11.24 shows an example of transfer when ETEND output is enabled, and word-size, normal
transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
EXDMA read EXDMA write
EXDMA read EXDMA write
EXDMA read EXDMA write
Bφ
Address bus
RD
LHWR, LLWR
ETEND
Bus
release
Bus
release
Bus
release
Last transfer cycle
Bus
release
Figure 11.24 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer
Figures 10.25 and 10.26 show examples of transfer when ETEND output is enabled, and
longword-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state
access space to external 16-bit, 2-state access space.
In figure 11.25, the transfer source (SAR) address is not at a longword boundary and the transfer
destination (DAR) address is at the longword boundary.
In figure 11.26, the transfer source (SAR) address is at the longword boundary and the transfer
destination (DAR) address is not at the longword boundary.
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Section 11 EXDMA Controller (EXDMAC)
EXDMA byte EXDMA word EXDMA byte EXDMA word EXDMA word
read cycle
read cycle
read cycle
write cycle
write cycle
EXDMA byte EXDMA word EXDMA byte EXDMA word EXDMA word
read cycle
read cycle
read cycle
write cycle
write cycle
Bφ
Address
bus
4m + 1
4m + 2
4m + 4
4n
4n + 2
4m + 5
4m + 6
4m + 8
4n + 4
4n + 6
RD
LHWR
LLWR
TEND
Bus
released
Bus
released
Last transfer cycle
Bus
released
m and n are integers.
Figure 11.25 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer
(Transfer Source EDSAR = Odd Address, Source Address Incremented)
EXDMA word EXDMA word EXDMA byte EXDMA word EXDMA byte
read cycle
read cycle
write cycle
write cycle
write cycle
EXDMA word EXDMA word EXDMA byte EXDMA word EXDMA byte
read cycle
read cycle
write cycle
write cycle
write cycle
Bφ
Address
bus
4m
4m + 2
4n + 5
4n + 6
4n + 8
4m + 4
4m + 6
4n + 1
4n + 2
4n + 4
RD
LHWR
LLWR
ETEND
Bus
released
Bus
released
Last transfer cycle
Bus
released
m and n are integers.
Figure 11.26 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer
(Transfer Destination EDDAR = Odd Address, Destination Address Decremented)
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Section 11 EXDMA Controller (EXDMAC)
(2)
Normal Transfer Mode (Burst Mode)
In burst mode, one-byte, one-word, or one-longword transfer is executed continuously until the
transfer end condition is satisfied.
Once burst transfer starts, requests from other channels, even of higher priority, are held pending
until burst transfer ends.
Figure 11.27 shows an example of transfer when ETEND output is enabled, and word-size, normal
transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space.
EXDMA read EXDMA write
EXDMA read
EXDMA write EXDMA read
EXDMA write
Bφ
Address bus
RD
LHWR, LLWR
ETEND
Last transfer cycle Bus
release
Bus
release
Burst transfer
Figure 11.27 Example of Normal Transfer Mode (Burst Mode) Transfer
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Section 11 EXDMA Controller (EXDMAC)
(3)
Block Transfer Mode
In block transfer mode, one block is transferred in response to one transfer request, and after the
transfer, the bus is released.
Figure 11.28 shows an example of transfer when ETEND output is enabled, and word-size, block
transfer mode is performed from external 16-bit, 2-state access space to external 16-bit, 2-state
access space.
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Bφ
Address
bus
RD
LHWR,
LLWR
ETEND
Bus
release
Block transfer
Bus
release
Last block transfer cycle
Bus
release
Figure 11.28 Example of Block Transfer Mode Transfer
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Section 11 EXDMA Controller (EXDMAC)
(4)
EDREQ Pin Falling Edge Activation Timing
Figure 11.29 shows an example of normal transfer mode transfer activated by the EDREQ pin
falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing
is started. If EDREQ pin high level sampling is completed by the end of the EXDMA write cycle,
acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is
performed again. This sequence of operations is repeated until the end of the transfer.
Bus release
EXDMA read
EXDMA write
Bus release
EXDMA read EXDMA write
Bus release
Bφ
EDREQ
Transfer
source
Address bus
EXDMA
control
Read
Idle
Request
Channel
Transfer
destination
Transfer
source
Write
Request clearance period
Request
[2]
Write
Idle
Request clearance period
Minimum 3 cycles
Minimum 3 cycles
[1]
Read
Idle
Transfer
destination
[3]
[4]
[5]
Acceptance resumed
[6]
[7]
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts; EDREQ pin high level sampling is started at rise of Bφ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.29 Example of Normal Transfer Mode Transfer Activated
by EDREQ Pin Falling Edge
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Section 11 EXDMA Controller (EXDMAC)
Figure 11.30 shows an example of block transfer mode transfer activated by the EDREQ pin
falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing
is started. If EDREQ pin high level sampling is completed by the end of the EXDMA write cycle,
acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is
performed again. This sequence of operations is repeated until the end of the transfer.
One block transfer
One block transfer
EXDMA
read
Bus release
EXDMA
write
Bus release
EXDMA
read
EXDMA
write
Transfer
source
Transfer
destination
Bus release
Bφ
EDREQ
Transfer
source
Address bus
EXDMA
control
Channel
Idle
Request
Read
Transfer
destination
Request clearance period
[2]
Write
Idle
Request clearance period
Request
Minimum 3 cycles
[1]
Read
Idle
Write
Minimum 3 cycles
[3]
[4]
[5]
[6]
Acceptance resumed
[7]
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts; EDREQ pin high level sampling is started at rise of Bφ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bf, and request is held.)
Figure 11.30 Example of Block Transfer Mode Transfer Activated
by EDREQ Pin Falling Edge
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Section 11 EXDMA Controller (EXDMAC)
(5)
EDREQ Pin Low Level Activation Timing
Figure 11.31 shows an example of normal transfer mode transfer activated by the EDREQ pin low
level.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the write cycle, acceptance resumes
and EDREQ pin low level sampling is performed again. This sequence of operations is repeated
until the end of the transfer.
Bus release
EXDMA read EXDMA write
Bus release
EXDMA read
EXDMA write
Transfer
source
Transfer
destination
Bus release
Bφ
EDREQ
Address
bus
Transfer
source
EXDMA
control
Channel
Idle
Read
Request
Transfer
destination
Write
Duration of transfer
request disabled
[2]
Write
Idle
Duration of transfer
request disabled
Request
Minimum 3 cycles
[1]
Read
Idle
Minimum 3 cycles
[3]
[4]
[5]
Transfer request enable resumed
[6]
[7]
Transfer request enable resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.31 Example of Normal Transfer Mode Transfer Activated
by EDREQ Pin Low Level
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Section 11 EXDMA Controller (EXDMAC)
Figure 11.32 shows an example of block transfer mode transfer activated by the EDREQ pin low
level.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the write cycle, acceptance resumes
and EDREQ pin low level sampling is performed again. This sequence of operations is repeated
until the end of the transfer.
One block transfer
One block transfer
EXDMA read EXDMA write
Bus release
Bus release
EXDMA read
EXDMA write
Transfer
source
Transfer
destination
Bus release
Bφ
EDREQ
Transfer
source
Address bus
EXDMA
control
Channel
Idle
Read
Request
Transfer
destination
Write
Request clearance period
[2]
Idle
Write
Request clearance period
Request
Minimum 3 cycles
[1]
Read
Idle
Minimum 3 cycles
[3]
[4]
[5]
Acceptance resumed
[6]
[7]
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.32 Example of Block Transfer Mode Transfer Activated
by EDREQ Pin Low Level
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Section 11 EXDMA Controller (EXDMAC)
(6)
EDREQ Pin Low Level Activation Timing with NRD = 1 Specified
When the NRD bit is set to 1 in EDMDR, the acceptance timing of the next transfer request can be
delayed one cycle later.
Figure 11.33 shows an example of normal transfer mode transfer activated by the EDREQ pin low
level with NRD = 1 specified.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the write cycle, acceptance resumes
when one cycle of the request clearance period specified by NRD = 1 expires and EDREQ pin low
level sampling is performed again. This sequence of operations is repeated until the end of the
transfer.
EXDMA read EXDMA write
Bus release
EXDMA read EXDMA write
Bus release
Bus release
Bφ
EDREQ
Address
bus
Channel
Transfer
source
Transfer
destination
Transfer
source
Transfer
destination
Extended request
clearance period
specified by NRD
Request
Request clearance period
Minimum 3 cycles
[1]
[2]
Request
Request clearance period
Extended request
clearance period
specified by NRD
Minimum 3 cycles
[3]
[4]
[5]
Acceptance resumed
[6]
[7]
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of write cycle plus one cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.33 Example of Normal Transfer Mode Transfer Activated
by EDREQ Pin Low Level with NRD = 1 Specified
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Section 11 EXDMA Controller (EXDMAC)
11.5.11 Bus Cycles in Single Address Mode
(1)
Single Address Mode (Read in Cycle Steal Mode)
In single address mode, the bus is released after one byte, word, or longword has been transferred
in response to one transfer request. While the bus is released, one or more CPU, DMAC, or DTC
bus cycles are initiated.
Figure 11.34 shows an example of transfer when ETEND output is enabled, and byte-size, single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
EXDMA read
EXDMA read
EXDMA read
EXDMA read
Bφ
Address bus
RD
EDACK
ETEND
Bus
released
Bus
release
Bus
release
Bus
Last transfer Bus
release
release
cycle
Figure 11.34 Example of Single Address Mode (Byte Read) Transfer
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Section 11 EXDMA Controller (EXDMAC)
(2)
Single Address Mode (Write in Cycle Steal Mode)
In single address mode, the bus is released after one byte, word, or longword has been transferred
in response to one transfer request. While the bus is released, one or more CPU, DMAC, or DTC
bus cycles are initiated.
Figure 11.35 shows an example of transfer when ETEND output is enabled, and byte-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
EXDMA write
EXDMA write
EXDMA write
EXDMA write
Bφ
Address bus
LLWR
EDACK
ETEND
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer Bus
release
cycle
Figure 11.35 Example of Single Address Mode (Byte Write) Transfer
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Section 11 EXDMA Controller (EXDMAC)
(3)
EDREQ Pin Falling Edge Activation Timing
Figure 11.36 shows an example of single address mode transfer activated by the EDREQ pin
falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing
is started. If EDREQ pin high level sampling is completed by the end of the EXDMA single cycle,
acceptance resumes after the end of the single cycle, and EDREQ pin low level sampling is
performed again. This sequence of operations is repeated until the end of the transfer.
Bus
release
Bus
release
EXDMA single
Bus
EXDMA single release
Bφ
EDREQ
Transfer source/
Transfer destination
Transfer source/
Transfer destination
Address bus
EDACK
EXDMA control
Single
Idle
Request
Channel
Single
Idle
Request clearance period
Request
Minimum 3 cycles
[1]
[2]
Idle
Request clearance period
Minimum 3 cycles
[3]
[4]
[5]
Acceptance resumed
[6]
[7]
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts; EDREQ pin high level sampling is started at rise of Bφ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.36 Example of Single Address Mode Transfer Activated
by EDREQ Pin Falling Edge
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Section 11 EXDMA Controller (EXDMAC)
(4)
EDREQ Pin Low Level Activation Timing
Figure 11.37 shows an example of single address mode transfer activated by the EDREQ pin low
level.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the single cycle, acceptance resumes
and EDREQ pin low level sampling is performed again. This sequence of operations is repeated
until the end of the transfer.
Bus
release
Bus
release
EXDMA single
EXDMA single
Bus
release
Bφ
EDREQ
Transfer source/
Transfer destination
Address bus
Transfer source/
Transfer destination
EDACK
EXDMA control Idle
Single
Request clearance period
Request
Channel
Minimum 3 cycles
[1]
Single
Idle
[2]
Idle
Request clearance period
Request
Minimum 3 cycles
[3]
[4]
[5]
Acceptance resumed
[6]
[7]
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of single cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.37 Example of Single Address Mode Transfer Activated
by EDREQ Pin Low Level
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Section 11 EXDMA Controller (EXDMAC)
(5)
EDREQ Pin Low Level Activation Timing with NRD = 1 Specified
When the NRD bit is set to 1 in EDMDR, the acceptance timing of the next transfer request can be
delayed one cycle later.
Figure 11.38 shows an example of single address mode transfer activated by the EDREQ pin low
level with NRD = 1 specified.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the single cycle, acceptance resumes
when one cycle of the request clearance period specified by NRD = 1 expires and EDREQ pin low
level sampling is performed again. This sequence of operations is repeated until the end of the
transfer.
Bus
release
Bus
release
EXDMA single
EXDMA single
Bus
release
Bφ
EDREQ
Transfer source/
Transfer destination
Transfer source/
Transfer destination
Address bus
Extended request clearance
period specified by NRD
Channel
Request
Request clearance period
Request
Minimum 3 cycles
[1]
[2]
Extended request clearance
period specified by NRD
Request clearance period
Minimum 3 cycles
[3]
[4]
[5]
Acceptance resumed
[6]
[7]
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of write cycle plus one cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.38 Example of Single Address Mode Transfer Activated
by EDREQ Pin Low Level with NRD = 1 Specified
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Section 11 EXDMA Controller (EXDMAC)
11.5.12 Operation Timing in Each Mode
This section describes examples of operation timing in each mode. The CPU external bus cycle is
shown as an example of conflict with another bus master.
(1)
Auto-Request/Normal Transfer Mode/Cycle Steal Mode
With auto-request (in cycle steal mode), when the DTE bit is set to 1 in EDMDR, an EXDMA
transfer cycle is started a minimum of three cycles later. If there is a transfer request for another
channel of higher priority, the transfer request by the original channel is held pending, and transfer
is performed on the higher-priority channel from the next transfer. Transfer on the original channel
is resumed on completion of the higher-priority channel transfer.
Figures 10.39 and 10.40 show operation timing examples for various conditions.
3 cycles
3 cycles
3 cycles
Bφ
Last transfer cycle
Bus cycle
Bus release
CPU operation
EXDMA
read
EXDMA
write
DTE 1
write
Bus
release
EXDMA
read
EXDMA
write
Bus
release
EXDMA
read
EXDMA
write
Bus
release
Internal bus space cycles
ETEND
DTE bit
0
1
Figure 11.39 Auto-Request/Normal Transfer Mode/Cycle Steal Mode
(No Conflict/Dual Address Mode)
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0
Section 11 EXDMA Controller (EXDMAC)
Bφ
One bus cycle
CPU cycle
Bus cycle
CPU operation
External
space
EXDMA single
transfer cycle
Last transfer cycle
EXDMA single
transfer cycle
CPU cycle
External space
CPU cycle
EXDMA single
transfer cycle
External space
CPU cycle
External space
EDACK
ETEND
Figure 11.40 Auto-Request/Normal Transfer Mode/Cycle Steal Mode
(CPU Cycles/Single Address Mode)
(2)
Auto-Request/Normal Transfer Mode/Burst Mode
With auto-request (in burst mode), when the DTE bit is set to 1 in EDMDR, an EXDMA transfer
cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst)
until the transfer end condition is satisfied. Transfer requests for other channels are held pending
until the end of transfer on the current channel.
Figures 10.41 to 10.43 show operation timing examples for various conditions.
Bφ
Last transfer cycle
Bus cycle
CPU operation
CPU cycle
CPU cycle
External
space
External
space
EXDMAC
read
EXDMAC
write
EXDMAC
read
EXDMAC
write
Repeated
EXDMAC
read
EXDMAC
write
CPU cycle
External space
ETEND
DTE bit
1
0
Figure 11.41 Auto-Request/Normal Transfer Mode/Burst Mode
(CPU Cycles/Dual Address Mode)
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Section 11 EXDMA Controller (EXDMAC)
Bφ
Last transfer cycle
Bus cycle
Bus release
EXDMAC single
transfer cycle
EXDMAC single
transfer cycle
EXDMAC single
transfer cycle
EXDMAC cycle of
another channel
Bus
release
EDACK of
current channel
ETEND of
current channel
Transfer request of
another channel
EDREQ
Figure 11.42 Auto-Request/Normal Transfer Mode/Burst Mode
(Conflict with Another Channel/Single Address Mode)
Bus cycle
EXDMA
CPU operation Internal space
EXDMA
CPU
External space
EXDMA
CPU
External space
EXDMA
EXDMA
Internal space
Figure 11.43 External Bus Master Cycle Steal Function (Auto-Request/Normal Transfer
Mode/Burst Mode with CPU Cycles/Single Address Mode/EBCCS = 1)
(3)
External Request/Normal Transfer Mode/Cycle Steal Mode
In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a
transfer request is accepted. The next transfer request is accepted after the end of a one-transferunit EXDMA cycle. For external bus space CPU cycles, at least one bus cycle is generated before
the next EXDMA cycle.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next EXDMA cycle.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
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Section 11 EXDMA Controller (EXDMAC)
Figures 10.44 to 10.47 show operation timing examples for various conditions.
Bφ
EDREQ
EDRAK
3 cycles
Bus cycle
Bus release
EXDMA
read
EXDMA
write
Last transfer cycle
Bus release
EXDMA
read
EXDMA
write
Bus release
ETEND
0
1
DTE bit
Figure 11.44 External Request/Normal Transfer Mode/Cycle Steal Mode
(No Conflict/Dual Address Mode/Low Level Sensing)
Bφ
EDREQ
EDRAK
One bus cycle
Bus cycle
CPU operation
CPU cycle
CPU cycle
External
space
External
space
EXDMAC single
transfer cycle
CPU cycle
External space
Last transfer cycle
EXDMAC single
transfer cycle
CPU cycle
External space
EDACK
ETEND
Figure 11.45 External Request/Normal Transfer Mode/Cycle Steal Mode
(CPU Cycles/Single Address Mode/Low Level Sensing)
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Section 11 EXDMA Controller (EXDMAC)
Bφ
EDREQ
EDRAK
EDREQ
acceptance
internal
processing
state
Start of transfer by
Start of transfer by
Start of high level sensing internal edge
Start of high level sensing
internal edge
confirmation
confirmation
Bus release
CPU
operation
EXDMAC single
transfer cycle
Bus release
EXDMAC single
transfer cycle
Start of transfer by
internal edge
Start of high level sensing
confirmation
Bus release
EXDMAC single
transfer cycle
EDACK
Figure 11.46 External Request/Normal Transfer Mode/Cycle Steal Mode (No
Conflict/Single Address Mode/Falling Edge Sensing)
Bφ
EDREQ of
current channel
EDRAK of
current channel
3 cycles
Bus cycle
EXDMAC
transfer cycle
Bus release
EXDMA
read
EXDMA
write
Transfer cycles of another channel
EXDMA
read
EDREQ of
another channel
EDRAK of
another channel
Figure 11.47 External Request/Normal Transfer Mode/Cycle Steal Mode
(Conflict with Another Channel/Dual Address Mode/Low Level Sensing)
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EXDMA
write
Section 11 EXDMA Controller (EXDMAC)
(4)
External Request/Block Transfer Mode/Cycle Steal Mode
In block transfer mode, transfer of one block is performed continuously in the same way as in
burst mode. The timing of the start of the next block transfer is the same as in normal transfer
mode.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next block transfer.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 10.48 to 10.52 show operation timing examples for various conditions.
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Rev. 2.00 Jul. 31, 2008 Page 534 of 1438
DTE bit
ETEND
Bus cycle
EDRAK
EDREQ
Bφ
Bus release
EXDMA
read
EXDMA
write
1
EXDMA
read
EXDMA
write
One block size transfer period
Repeated
EXDMA
read
EXDMA
write
End of block
Bus release
3 cycles
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
0
Bus release
EXDMA
write
Last transfer cycle
Last block
Section 11 EXDMA Controller (EXDMAC)
Figure 11.48 External Request/Block Transfer Mode/Cycle Steal Mode
(No Conflict/Dual Address Mode/Low Level Sensing)
ETEND
EDACK
Bus cycle
EDRAK
EDREQ
Bφ
Bus release
EXDMA single
transfer cycle
EXDMA single
transfer cycle
One block size transfer period
Repeated
EXDMA single
transfer cycle
End of block
Bus release
3 cycles
EXDMA single
transfer cycle
Repeated
EXDMA single
transfer cycle
Last transfer cycle
Last block
Bus
release
Section 11 EXDMA Controller (EXDMAC)
Figure 11.49 External Request/Block Transfer Mode/Cycle Steal Mode
(No Conflict/Single Address Mode/Falling Edge Sensing)
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ETEND
EDACK
External
space
CPU
operation
External
space
CPU cycle
Bus cycle CPU cycle
EDRAK
EDREQ
Bφ
EXDMA single
transfer cycle
External
space
Repeated
EXDMA single
transfer cycle
End of block
One block size transfer period
CPU cycle
Bus cycle
EXDMA single
transfer cycle
External
space
Repeated
EXDMA single
transfer cycle
Last block
One block size transfer period
CPU cycle
Section 11 EXDMA Controller (EXDMAC)
Figure 11.50 External Request/Block Transfer Mode/Cycle Steal Mode
(CPU Cycles/Single Address Mode/Low Level Sensing)
EDRAK of
another channel
EDREQ of
another channel
ETEND
Bus cycle
EDRAK
EDREQ
Bφ
Bus release
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
EXDMA
write
End of block
One block size transfer period
EXDMA cycle of another channel
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
EXDMA
write
Last block
One block size transfer period
Section 11 EXDMA Controller (EXDMAC)
Figure 11.51 External Request/Block Transfer Mode/Cycle Steal Mode
(Conflict with Another Channel/Dual Address Mode/Low Level Sensing)
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ETEND
EDACK
CPU
operation
Bus
cycle
EDRAK
EDREQ
Bφ
External
space
CPU
cycle
External
space
CPU cycle
EXDMA single
transfer cycle
External
space
Repeated
EXDMA single
transfer cycle
End of block
One block size transfer period
CPU cycle
Bus cycle
EXDMA single
transfer cycle
External
space
Repeated
EXDMA single
transfer cycle
Last block
One block size transfer period
CPU
cycle
Section 11 EXDMA Controller (EXDMAC)
Figure 11.52 External Request/Block Transfer Mode/Cycle Steal Mode
(CPU Cycles/EBCCS = 1/Single Address Mode/Low Level Sensing)
Section 11 EXDMA Controller (EXDMAC)
11.6
Operation in Cluster Transfer Mode
In cluster transfer mode, transfer is performed by the consecutive read and write operations of 1 to
32 bytes using the cluster buffer. A part of the cluster transfer mode function differs from the
ordinary transfer mode functions (normal transfer, repeat transfer, and block transfer modes).
11.6.1
(1)
Address Mode
Cluster Transfer Dual Address Mode (AMS = 0)
In this mode, both the transfer source and destination addresses are specified for transfer in the
EXDMAC internal registers. The transfer source address is set in the source address register
(EDSAR), and the transfer destination address is set in the destination address register (EDDAR).
The transfer is processed by performing the consecutive read of a cluster-size from the transfer
source address and then the consecutive write of that data to the transfer destination address. One
data access size to 32 bytes can be specified as a cluster size. When one data access size is
specified as a cluster size, block transfer mode (dual address mode) is used.
The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another
bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for the last write cycle. The EDACK signal is not output.
Figure 11.53 shows the data flow in the cluster transfer mode (dual address mode), figure 11.54
shows an example of the timing in cluster transfer dual address mode, and figure 11.55 shows the
cluster transfer dual address mode operation.
LSI
Transfer source: External memory
Transfer destination: External device
EDDAR acces
EDSAR access
Read Read
Read
Write Write
Read
Write
Write
Cluster buffer
One cluster size
One cluster size
Consecutive
read
Consecutive
write
Figure 11.53 Data Flow in Cluster Transfer Dual Address Mode
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Section 11 EXDMA Controller (EXDMAC)
EXDMA write cycle
EXDMA read cycle
Bφ
Address bus
EDSAR
EDSAR
EDSAR
EDDAR
EDDAR
EDDAR
RD
WR
ETEND
Figure 11.54 Timing in Cluster Transfer Dual Address Mode
Address TA
First cluster
Transfer
Address TB
First cluster
Cluster size:
BKSZH ×
Data accsess size
Second cluster
Second cluster
Nth cluster
Nth cluster
Address BA
Address BB
Figure 11.55 Cluster Transfer Dual Address Mode Operation
When a word or longword is specified as a data access size but the source or destination address is
not at the word or longword boundary, use the appropriate data access size for efficient data
transfer.
In an example shown in figure 11.56, a longword-size transfer is performed with 4-longword
specified as a cluster size in the cluster transfer dual address mode from the lower two bits of B'11
to B'10.
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Section 11 EXDMA Controller (EXDMAC)
The cluster size is decremented regardless of the read or write operation in the consecutive write
sequences.
Transfer source memory
MSB
Cluster buffer
Transfer destination memory
LSB
CLSBR0
1
2
CLSBR1
2
3
CLSBR2
3
4
CLSBR3
4
Byte 1
H'AA0000
H'AA0004
Long Word 2
H'AA0008
Long Word 3
H'AA000C
Long Word 4
H'AA0010
Word 5
5
H'BB0000
6
Byte 6
Long Word
H'BB0008
Long Word
H'BB000C
H'BB0010
CLSBR4
Word
H'BB0004
Long Word
Word
CLSBR5
CLSBR6
CLSBR7
Figure 11.56 Odd Address Transfer
(2)
Cluster Transfer Read Address Mode (AMS = 1, DIRS = 0)
In this mode, the transfer source address is specified in the source address register (EDSAR) and
data is read from the transfer source and transferred to the cluster buffer. In this mode, the TSEIE
bit in the mode control register (EDMDR) must be set to 1.
Two data access size to 32 bytes can be specified as a cluster size for the consecutive read
operation.
The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another
bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for the last read cycle. When an idle cycle is inserted before the last read cycle, the
ETEND signal is also output in the idle cycle.
In this mode, the EDACKE bit in EDMDR must be set to 0 to disable the EDACK pin output.
Figure 11.57 shows the data flow in the cluster transfer read address mode (from the external
memory to the cluster buffer), and figure 11.58 shows an example of the timing in cluster transfer
read address mode.
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Section 11 EXDMA Controller (EXDMAC)
LSI
Address bus
Cluster buffer
EDSAR access
Transfer source
external memory
External data bus
CPU
Register read
Figure 11.57 Data Flow in Cluster Transfer Read Address Mode (
from External Memory to Cluster Buffer)
EXDMA read cycle
Bφ
Address bus
EDSAR
EDSAR
EDSAR
RD
High
WR
ETEND
Figure 11.58 Timing in Cluster Transfer Read Address Mode
(from External Memory to Cluster Buffer)
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Section 11 EXDMA Controller (EXDMAC)
(3)
Cluster Transfer Write Address Mode (AMS = 1, DIRS = 1)
In this mode, the transfer destination address is specified in the destination address register
(EDDAR) and data in the cluster butter is written to the transfer destination. In this mode, the
TSEIE bit in the mode control register (EDMDR) must be set to 1.
One data access size to 32 bytes can be specified as a cluster size for the consecutive write
operation. When one data access size is specified as a cluster size, the cluster transfer write
address mode is used.
The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another
bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for the last write cycle. When an idle cycle is inserted before the last write cycle, the
ETEND signal is also output in the idle cycle.
In this mode, the EDACKE bit in EDMCR must be set to 0 to disable the EDACK pin output.
Figure 11.59 shows the data flow in the cluster transfer write address mode (from the cluster
buffer to the external memory), and figure 11.60 shows an example of the timing in cluster
transfer write address mode.
LSI
Address bus
Cluster buffer
EDDAR access
External data bus
Transfer
destination
external
memory
When initializing an area by the specified data, write the specified data from cluster buffer 0 into a register
sequentially. Then, specify the buffer size written in the register as a cluster size and the area to be initialized
as DAR, and then execute transfer in this mode.
Figure 11.59 Data Flow in Cluster Transfer Write Address Mode
(from Cluster Buffer to External Memory)
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Section 11 EXDMA Controller (EXDMAC)
EXDMA write cycle
Bφ
Address bus
RD
EDDAR
EDDAR
EDDAR
High
WR
ETEND
Figure 11.60 Timing in Cluster Transfer Write Address Mode
(from Cluster Buffer to External Memory)
11.6.2
Setting of Address Update Mode
The cluster transfer mode transfer is restricted by the address update mode function. There are the
following four address update methods: increment, decrement, fixed, and offset addition.
When the address increment method is specified and if the specified address is not at the address
boundary for the data access size (odd address for a word-size transfer, address beyond the 4n
boundary for a longword-size transfer), the bus cycle is divided for transfer until the address
becomes at the address boundary. When the address matches the boundary, transfer is processed in
units of data access sizes. At the end of transfer, the bus cycle is divided again to transfer the
remaining data in cluster transfer mode.
With address decrement, fixed, or offset addition method, specify the address, that matches the
address boundary for the data access size, in EDSAR and EDDAR. When specifying the address,
that is not at the address boundary for the data access size, in EDSAR and EDDAR, fix the lower
bit to 0 (lower one bit for a word-size transfer, and lower two bits for a longword-size transfer) in
the address register so that the transfer is processed in units of data access sizes. The block transfer
mode must be used for transfer of data by dividing the bus cycle according to the address
boundary.
When the EDTCR value is smaller than the cluster size, a transfer size error occurs. In this case,
when the TSEIE bit in EDMDR is cleared to 0, the cluster transfer mode is switched to the block
transfer mode to process the remaining data. With the decrement, fixed, or offset addition method,
transfer is performed without fixing the lower bit to 0.
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Section 11 EXDMA Controller (EXDMAC)
11.6.3
Caution for Combining with Extended Repeat Area Function
As with the block transfer mode, the address register value must be set in cluster transfer mode, so
that the end of the cluster size coincides with the end of the extended repeat area range.
When an extended repeat area overflow occurs during a cluster-size transfer in the cluster transfer
mode, the extended repeat area overflow interrupt request is held pending until the end of a
cluster-size transfer, and transfer overrun will occur.
11.6.4
(1)
Bus Cycles in Cluster Transfer Dual Address Mode
Cluster transfer mode
In cluster transfer mode, a cluster-size transfer is processed in response to one transfer request.
In an example shown in figure 11.61, the ETEND pin output is enabled, and word-size transfer is
performed with 4-byte cluster size in cluster transfer mode from the external 16-bit, 2-state access
space to the external 16-bit, 2-state access space.
EXDMA read
EXDMA write
Bus
release
EXDMA read
EXDMA write
Bφ
Address bus
RD
LHWR,
LLWR
ETEND
Figure 11.61 Example of Cluster Transfer Mode Transfer
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Section 11 EXDMA Controller (EXDMAC)
(2)
EDREQ Pin Falling Edge Activation Timing
Figure 11.62 shows an example of cluster transfer mode transfer activated by the EDREQ pin
falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing
is started. If EDREQ pin high level sampling is completed by the end of the last cluster write
cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is
performed again. This sequence of operations is repeated until the end of the transfer.
One cluster transfer
Bus release
One cluster transfer
Bus release
Bφ
EDREQ
Address bus
Transfer source
EXDMA control
Channel
Consecutive read
Request
[1]
[1]
[2] [5]
[3] [6]
[4] [7]
Minimum 3 cycles
[2]
Transfer destination
Consecutive read
Consecutive write
Request clearance period
[3]
Transfer source
Request
[4]
Minimum 3 cycles
[5]
Transfer destination
Consecutive write
Request clearance period
[6]
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle starts; EDREQ pin high level sampling is started at rise of Bφ.
When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.62 Example of Cluster Transfer Mode Transfer Activated
by EDREQ Pin Falling Edge
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[7]
Section 11 EXDMA Controller (EXDMAC)
(3)
EDREQ Pin Low Level Activation Timing
Figure 11.63 shows an example of cluster transfer mode transfer activated by the EDREQ pin low
level.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. At the end of the last cluster write cycle, acceptance
resumes and EDREQ pin low level sampling is performed again. This sequence of operations is
repeated until the end of the transfer.
When NRD bit = 0 in EDMDR, acceptance resumes at the end of the last cluster write cycle and
EDREQ pin low level sampling is performed again. This sequence of operations is repeated until
the end of the transfer.
When NRD bit = 1 in EDMDR, acceptance resumes after one cycle from the end of the last cluster
write cycle, and EDREQ pin low level sampling is performed again. This sequence of operations
is repeated until the end of the transfer.
Bus release
One cluster transfer
Bus release
One cluster transfer
Bφ
EDREQ
Address bus
Transfer source
EXDMA control
Consecutive read
Channel
Transfer destination
Consecutive write
Consecutive read
Request clearance period
Request
Request
Minimum 3 cycles
[1]
[1]
[2] [5]
[3] [6]
[4] [7]
[2]
Transfer source
Transfer destination
Consecutive write
Request clearance period
Minimum 3 cycles
[3]
[4]
[5]
[6]
[7]
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
Request is cleared at the end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle stars.
Acceptance is resumed after completion of wite cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
Figure 11.63 Example of Cluster Transfer Mode Transfer Activated
by EDREQ Pin Low Level
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Section 11 EXDMA Controller (EXDMAC)
11.6.5
Operation Timing in Cluster Transfer Mode
This section describes examples of operation timing in cluster transfer mode. The CPU external
bus cycle is shown as an example of conflict with another bus master.
(1)
Auto-Request/Cluster Transfer Mode/Cycle Steal Mode
With auto-request (in cycle steal mode), when the DTE bit is set to 1 in EDMDR, a continuous
EXDMA transfer cycle is started a minimum of three cycles later. If there is a transfer request for
another channel of higher priority, the transfer request by the original channel is held pending, and
transfer is performed on the higher-priority channel from the next transfer. Transfer on the original
channel is resumed on completion of the higher-priority channel transfer.
The cluster transfer mode (read address mode and write address mode) can not be used with the
cluster transfer mode (dual address mode) among more than one channel at the same time. When
using the cluster transfer mode (read address mode and write address mode), do not set the cluster
transfer mode for another channel.
Figures 10.64 to 10.66 show operation timing examples for various conditions.
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DTE bit
ETEND
CPU operation
Bus cycle
Bφ
0
DTE
= 1 write
Consecutive
EXDMA write
One cluster transfer
Consecutive
EXDMA read
Internal bus space cycles
Bus release
3 cycles
Bus release
3 cycles
1
Consecutive
EXDMA read
Consecutive
EXDMA write
One cluster transfer
Bus release
3 cycles
Consecutive
EXDMA read
Consecutive
EXDMA write
Last cluster cycle
0
Section 11 EXDMA Controller (EXDMAC)
Figure 11.64 Auto-Request/Cluster Transfer Mode/Cycle Steal Mode
(No Confict/Dual Address Mode)
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DTE bit
ETEND
CPU operation
Bus cycle
Bφ
External space
CPU cycle
0
DTE = 1 write
CPU cycle
Consecutive
EXDMA write
External space
Consecutive
EXDMA read
One cluster transfer
CPU cycle
1
External space
Consecutive
EXDMA write
One cluster transfer
Consecutive
EXDMA read
CPU cycle
External space
Consecutive
EXDMA write
Last cluster cycle
Consecutive
EXDMA read
0
Section 11 EXDMA Controller (EXDMAC)
Figure 11.65 Auto-Request/Cluster Transfer Mode/Cycle Steal Mode
(CPU Cycles/Dual Address Mode)
Transfer
request from
another
channel
(EDREQ)
Bus cycle
Bφ
Consecutive
EXDMA read
Consecutive
EXDMA write
One cluster transfer
Bus release
Consecutive
EXDMA read
Consecutive
EXDMA write
One cluster transfer
EXDMA single transfer cycle of
another channel with higher priority
Consecutive
EXDMA read
Consecutive
EXDMA write
Last cluster transfer
Section 11 EXDMA Controller (EXDMAC)
Figure 11.66 Auto-Request/Cluster Transfer Mode/Cycle Steal Mode
(Conflict with Another Channel/Dual Address Mode)
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Section 11 EXDMA Controller (EXDMAC)
(2)
External Request/Cluster Transfer Mode/Cycle Steal Mode
With external requests, a cluster-size transfer is performed continuously. The start timing of the
next cluster transfer is the same as for normal transfer mode.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next cluster transfer.
The cluster transfer mode (read address mode and write address mode) can not be used with the
cluster transfer mode (dual address mode) among more than one channel at the same time. When
using the cluster transfer mode (read address mode and write address mode), do not set the cluster
transfer mode for another channel.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 10.67 to 10.69 show operation timing examples for various conditions.
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DTE bit
ETEND
Bus cycle
EDRAK
EDREQ
Bφ
Bus release
EXDMA read
1
EXDMA read
EXDMA write
EXDMA write
One cluster transfer
Consecutive read
Consecutive write
Bus release
3 cycles
EXDMA read
EXDMA read
Consecutive read
EXDMA write
EXDMA write
Last cluster
Consecutive write
0
Section 11 EXDMA Controller (EXDMAC)
Figure 11.67 External Request/Cluster Transfer Mode/Cycle Steal Mode
(No Conflict/Dual Address Mode/Low Level Sensing)
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CPU cycle
External space
EXDMA write
EXDMA read
External space
External space
CPU operation
Bus cycle
EDRAK
EDREQ
Bφ
CPU cycle
CPU cycle
EXDMA read
One cluster size transfer period
EXDMA write
CPU cycle
CPU cycle
Section 11 EXDMA Controller (EXDMAC)
Figure 11.68 External Request/Cluster Transfer Mode/Cycle Steal Mode
(CPU Cycles/Dual Address Mode/Low Level Sensing)
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EDRAK of
another channel
EDREQ of
another channel
ETEND
Bus cycle
EDRAK
EDREQ
Bφ
CPU cycle
CPU cycle
Consecutive
EXDMA read
Consecutive
EXDMA write
One cluster size transfer period
EXDMA cycle of
another channel
Consecutive
EXDMA read
Consecutive
EXDMA write
One cluster size transfer period
(Last cluster transfer)
Section 11 EXDMA Controller (EXDMAC)
Figure 11.69 External Request/Cluster Transfer Mode/Cycle Steal Mode
(Conflict with Another Channel/Dual Address Mode/Low Level Sensing)
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Section 11 EXDMA Controller (EXDMAC)
11.7
Ending EXDMA Transfer
The operation for ending EXDMA transfer depends on the transfer end conditions. When
EXDMA transfer ends, the DTE bit and the ACT bit in EDMDR change from 1 to 0, indicating
that EXDMA transfer has ended.
(1)
Transfer End by EDTCR Change from 1, 2, or 4 to 0
When the value of EDTCR changes from 1, 2, or 4 to 0, EXDMA transfer ends on the
corresponding channel. The DTE bit in EDMDR is cleared to 0, and the DTIF bit in EDMDR is
set to 1. If the DTIE bit in EDMDR is set to 1 at this time, a transfer end interrupt request is
generated by the transfer counter. EXDMA transfer does not end if the EDTCR value has been 0
since before the start of transfer.
(2)
Transfer End by Transfer Size Error Interrupt
When the following conditions are satisfied while the TSEIE bit in EDMDR is set to 1, a transfer
size error occurs and an EXDMA transfer is terminated. At this time, the DTE bit in EDMDR is
cleared to 0 and the ESIF bit in EDMDR is set to 1.
• In normal transfer mode and repeat transfer mode, when the next transfer is requested while a
transfer is disabled due to the EDTCR value less than the data access size.
• In block transfer mode, when the next transfer is requested while a transfer is disabled due to
the EDTCR value less than the block size.
• In cluster transfer mode, when the next transfer is requested while a transfer is disabled due to
the EDTCR value less than the cluster size.
When the TSEIE bit in EDMDR is cleared to 0, data is transferred until the EDTCR value reaches
0. A transfer size error is not generated. Operation in each transfer mode is described below.
• In normal transfer mode and repeat mode, when the EDTCR value is less than the data access
size, data is transferred in bytes.
• In block transfer mode, when the EDTCR value is less than the block size, the specified size of
data in EDTCR is transferred instead of transferring the block size of data. When the EDTCR
value is less than the data access size, data is transferred in bytes.
• In cluster transfer mode, when the EDTCR value is less than the cluster size, the specified size
of data in EDTCR is transferred instead of transferring the cluster size of data. When the
EDTCR value is less than the data access size, data is transferred in bytes.
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Section 11 EXDMA Controller (EXDMAC)
(3)
Transfer End by Repeat Size End Interrupt
In repeat transfer mode, when the RPTIE bit in EDACR is set to 1 and the next transfer request is
generated on completion of a repeat-size transfer, a repeat size end interrupt request is generated.
The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR is cleared to 0, and the
ESIF bit in EDMDR is set to 1 at the same time. If the DTE bit is set to 1 in this state, transfer
resumes.
In block transfer or cluster transfer mode, a repeat size end interrupt request can be generated. In
block transfer mode, if the next transfer request is generated at the end of a block-size transfer, a
repeat size end interrupt request is generated. In cluster transfer mode, if the next transfer request
is generated at the end of a cluster-size transfer, a repeat size end interrupt request is generated.
(4)
Transfer End by Extended Repeat Area Overflow Interrupt
If an address overflows the extended repeat area when an extended repeat area specification has
been made and the SARIE or DARIE bit in EDACR is set to 1, an extended repeat area overflow
interrupt is requested. The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR
is cleared to 0, and the ESIF bit in EDMDR is set to 1 at the same time.
In dual address mode, if an extended repeat area overflow interrupt is requested during a read
cycle, the following write cycle processing is still executed.
In block transfer mode, if an extended repeat area overflow interrupt is requested during transfer
of a block, transfer continues to the end of the block. Transfer end by means of an extended repeat
area overflow interrupt occurs between block-size transfers.
In cluster transfer mode, if an extended repeat area overflow interrupt is requested during transfer
of a cluster, transfer continues to the end of the cluster. Transfer end by means of an extended
repeat area overflow interrupt occurs between cluster-size transfers.
(5)
Transfer End by 0-Write to DTE Bit in EDMDR
When 0 is written to the DTE bit in EDMDR by the CPU, etc., transfer ends after completion of
the EXDMA cycle in which transfer is in progress or a transfer request was accepted.
In block transfer mode, EXDMA transfer ends after completion of one-block-size transfer in
progress.
In cluster transfer mode, EXDMA transfer ends after completion of one-cluster-size transfer in
progress.
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Section 11 EXDMA Controller (EXDMAC)
(6)
Transfer End by NMI Interrupt
If an NMI interrupt occurs, the EXDMAC clears the DTE bit to 0 in all channels and sets the
ERRF bit in EDMDR_0 to 1. EXDMA transfer is aborted when an NMI interrupt is generated
during EXDMA transfer. To perform EXDMA transfer after an NMI interrupt occurs, clear the
ERRF bit to 0 and then set the DTE bit to 1 in all channels.
The following explains the transfer end timing in each mode after an NMI interrupt is detected.
(a)
Normal transfer mode and repeat transfer mode
In dual address mode, EXDMA transfer ends at the end of the EXDMA transfer write cycle in
units of transfers.
In single address mode, EXDMA transfer ends at the end of the EXDMA transfer bus cycle in
units of transfers.
(b)
Block transfer mode
A block size EXDMA transfer is aborted. A block size transfer is not correctly executed, thus
matching between the actual transfer and the transfer request is not guaranteed.
In dual address mode, a write cycle corresponding to a read cycle is executed as well as in the
normal transfer mode.
(c)
Cluster transfer mode
A cluster size EXDMA transfer is aborted. If transfer is aborted in a read cycle, the read data is not
guaranteed. If transfer is aborted in a write cycle, the data not transferred is not guaranteed.
Matching between the transfer counter and the address register is not guaranteed since the transfer
processing cannot be controlled.
(7)
Transfer End by Address Error
If an address error occurs, the EXDMAC clears the DTE bit to 0 in all channels, and set the ERRF
bit in EDMDR_0 to 1. An address error during EXDMA transfer forcibly terminates the transfer.
To perform EXDMA transfer after an address error occurs, clear the ERRF bit to 0 and then set
the DTE bit to 1 in each channel.
The transfer end timing after address error detection is the same as for the one when an NMI
interrupt occurs.
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Section 11 EXDMA Controller (EXDMAC)
(8)
Transfer End by Hardware Standby Mode and Reset Input
The EXDMAC is initialized in hardware standby mode and by a reset. EXDMA transfer is not
guaranteed in these cases.
11.8
Relationship among EXDMAC and Other Bus Masters
11.8.1
CPU Priority Control Function Over EXDMAC
The EXDMAC priority level control function can be used for the CPU by setting the CPU priority
control register (CPUPCR). For details, see section 7.7, CPU Priority Control Function Over DTC,
DMAC, and EXDMAC.
The EXDMAC priority level can be set independently for each channel by the EDMAP2 to
EDMAP0 bits in EDMDR.
The CPU priority level, which corresponds to the priority level of exception handling, can be set
by updating the values of the CPUP2 to CPUP0 bits in CPUPCR with the interrupt mask bit
values.
When the CPUPCE bit in CPUPCR is set to 1 to enable the CPU priority level control and the
EXDMAC priority level is lower than the CPU priority level, the transfer request of the
corresponding channel is masked and the channel activation is disabled. When the priority level of
another channel is the same or higher than the CPU priority level, the transfer request for another
channel is accepted and transfer is enabled regardless of the priority levels of channels.
The CPU priority level control function holds pending the transfer source, which masked the
transfer request. When the CPU priority level becomes lower than the channel priority level by
updating one of them, the transfer request is accepted and transfer starts. The transfer request held
pending is cleared by writing 0 to the DTE bit.
When the CPUPCE bit is cleared to 0, the lowest CPU priority level is assumed.
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Section 11 EXDMA Controller (EXDMAC)
11.8.2
Bus Arbitration with Another Bus Master
A cycle of another bus master may (or not) be inserted among consecutive EXDMA transfer bus
cycles. The EXDMAC bus mastership can be set so that it is released and transferred to another
bus master.
Some of the consecutive EXDMA transfer bus cycles may be indivisible due to the transfer mode
specification, may be consecutive bus cycles for high-speed access due to the transfer mode
specification, or may be consecutive bus cycles because another bus master does not request the
bus mastership.
These consecutive EXDMA read and write cycles are indivisible: refresh cycle, external bus
release cycle, or external space access cycle by internal bus master (CPU, DTC, DMAC) does not
occur between a read cycle and a write cycle.
In cluster transfer mode, the transfer cycle in one cluster is indivisible.
In block transfer mode and auto-request burst mode, the EXDMA transfer bus cycles continues. In
this period, the bus priority level of the internal bus master is lower than the EXDMAC so that the
external space access is held pending (when EBCCS = 0 in the bus control register 2 (BCR2)).
When switching to another channel, or in the auto-request cycle steal mode, the EXDMA transfer
cycles and internal bus master cycles are alternatively executed. When the internal bus master is
not issuing an external space access cycle, the EXDMA transfer bus cycles are continuously
executed in the allowable range.
When the EBCCS bit in BCR2 is set to 1 to enable the arbitration function between the EXDMAC
and the internal bus master, the bus mastership is released, except for indivisible bus cycles, and
transferred between the EXDMAC and the internal bus master alternatively. For details, see
section 9, Bus Controller (BSC).
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Section 11 EXDMA Controller (EXDMAC)
11.9
Interrupt Sources
EXDMAC interrupt sources are a transfer end by the transfer counter, and an escape end interrupt
which is caused by the transfer counter not becoming 0. Table 11.7 shows the interrupt sources
and their priority order.
Table 11.7 Interrupt Sources and Priority Order
Interrupt
Interrupt Source
Interrupt
Priority
EXDMTEND0
Transfer end indicated by channel 0 transfer counter
High
EXDMTEND1
Transfer end indicated by channel 1 transfer counter
EXDMTEND2
Transfer end indicated by channel 2 transfer counter
EXDMTEND3
Transfer end indicated by channel 3 transfer counter
EXDMEEND0
Channel 0 transfer size error
Channel 0 repeat size end
Channel 0 source address extended repeat area overflow
Channel 0 destination address extended repeat area overflow
EXDMEEND1
Channel 1 transfer size error
Channel 1 repeat size end
Channel 1 source address extended repeat area overflow
Channel 1 destination address extended repeat area overflow
EXDMEEND2
Channel 2 transfer size error
Channel 2 repeat size end
Channel 2 source address extended repeat area overflow
Channel 2 destination address extended repeat area overflow
EXDMEEND3
Channel 3 transfer size error
Channel 3 repeat size end
Channel 3 source address extended repeat area overflow
Channel 3 destination address extended repeat area overflow
Low
Interrupt source can be enabled or disabled by setting the DTIE and ESIE bits in EDMDR for the
relevant channels. The DTIE bit can be combined with the DTIF bit in EDMDR to generate an
EXDMTEND interrupt. The ESIE bit can be combined with the ESIF bit in EDMDR to generate
an EXDMEEND interrupt. Interrupt sources in EXDMEEND are not identified as common
interrupts. The interrupt priority order among channels is determined by the interrupt controller as
shown in table 11.8. For detains, see section 7, Interrupt Controller.
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Section 11 EXDMA Controller (EXDMAC)
Interrupt source settings are made individually with the interrupt enable bits in the registers for the
relevant channels. The transfer counter's transfer end interrupt is enabled or disabled by means of
the DTIE bit in EDMDR, the transfer size error interrupt by means of the TSEIE bit in EDMDR,
the repeat size end interrupt by means of the RPTIE bit in EDACR, the source address extended
repeat area overflow interrupt by means of the SARIE bit in EDACR, and the destination address
extended repeat area overflow interrupt by means of the DARIE bit in EDACR.
The transfer end interrupt by the transfer counter occurs when the DTIE bit in EDMDR is set to 1,
the EDTCR becomes 0 by transfer, and then the DTIF bit in EDMDR is set to 1.
Interrupts other than the transfer end interrupt by the transfer counter occurs when the
corresponding interrupt enable bit is set to 1, the condition for that interrupt is satisfied, and then
the ESIF bit in EDMDR is set to 1.
The transfer size error interrupt occurs when the EDTCR value is smaller than the data access size
and a data-access-size transfer for one request cannot be performed for a transfer request. In block
transfer mode, the block size is compared to the EDTCR value to determine a transfer size error.
In cluster transfer mode, the cluster size is compared to the EDTCR value to determine a transfer
size error.
The repeat size end interrupt occurs when the next transfer request is generated after the end of a
repeat size transfer in repeat transfer mode. When the repeat area is not set in the address register,
transfer can be aborted periodically based on the set repeat size value. If the transfer end interrupt
by the transfer counter occurs at the same time, the ESIF bit is set to 1.
The source/destination address extended repeat area overflow interrupt occurs when the addresses
overflow the specified extended repeat area. If the transfer end interrupt by the transfer counter
occurs at the same time, the ESIF bit is set to 1.
Figure 11.70 shows the block diagram of various interrupts and their interrupt flags. The transfer
end interrupt can be cleared either by clearing the DTIF or ESIF bit to 0 in EDMDR within the
interrupt handling routine, or by re-setting the address registers and then setting the DTE bit to 1
in EDMDR to perform transfer continuation processing. An example of the procedure for clearing
the transfer end interrupt and restarting transfer is shown in figure 11.71.
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Section 11 EXDMA Controller (EXDMAC)
TSEIE bit
DTIE bit
Activation source occurred
in the transfer size error state
DTIF bit
RPTIE bit
Transfer
end interrupt
Condition to set DTIF bit to 1: DTCR
is set to 0 and transfer ends.
Activation source occurred
after BKSZ changed from 1 to 0
SARIE bit
ESIE bit
Source address extended
repeat area overflow occurred
ESIF bit
Transfer escape
end interrupt
Condition to set ESIF bit to 1
DARIE bit
Destination address extended
repeat area overflow occurred
Figure 11.70 Interrupts and Interrupt Sources
Transfer end interrupt of
exception handling routine
Transfer restart after end of
interrupt handling routine
Transfer continuation processing
Change register settings
[1]
Write 1 to DTE bit
[2]
End of interrupt handling routine
(RTE instruction execution)
[3]
Clear DTIF or ESIF bit to 0
[4]
End of interrupt handling routine
[5]
Change register settings
[6]
Write 1 to DTE bit
[7]
End of transfer restart processing
End of transfer restart processing
[1] Write set values to the registers
(transfer counter, address registers, etc.)
[2] Write 1 to the DTE bit in EDMDR to restart
EXDMA operation. When 1 is written to
the DTE bit, the DTIF or ESIF bit in EDMDR is
automatically cleared to 0 and the interrupt
source is cleared.
[3] The interrupt handling routine is
ended with an RTE instruction, etc.
[4] Write 0 to the DTIF or ESIF bit
in EDMDR by first reading 1 from it.
[5] After the interrupt handling routine is
ended with an RTE instruction, etc.,
interrupt masking is cleared.
[6] Write set values to the registers
(transfer counter, address registers, etc.).
[7] Write 1 to the DTE bit in EDMDR
to restart EXDMA operation.
Figure 11.71 Procedure for Clearing Transfer End Interrupt and Restarting Transfer
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Section 11 EXDMA Controller (EXDMAC)
11.10
Usage Notes
1. EXDMAC Register Access during Operation
Except for clearing the DTE bit to 0 in EDMDR, settings should not be changed for a channel
in operation (including the transfer standby state). Transfer must be disabled before changing a
setting for an operational channel.
2. Module Stop State
The EXDMAC operation can be enabled or disabled by the module stop control register. The
initial value is "enabled".
When the MSTPA14 bit is set to 1 in MSTPCRA, the EXDMAC clock stops and the
EXDMAC enters the module stop state. However, 1 cannot be written to the MSTPA14 bit
when any of the EXDMAC's channels is enabled for transfer, or when an interrupt is being
requested. Before setting the MSTPA14 bit, first clear the DTE bit in EDMDR to 0, then clear
the DTIF or DTIE bit in EDMDR to 0.
When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The
following EXDMAC register settings remain valid in the module stop state, and so should be
disabled, if necessary, before making the module stop transition.
• ETENDE = 1 in EDMDR (ETEND pin enable)
• EDRAKE = 1 in EDMDR (EDRAK pin enable)
• EDACKE = 1 in EDMDR (EDACK pin enable)
3. EDREQ Pin Falling Edge Activation
Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC
internal operations, as indicated below.
1. Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to
[2].
2. Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to
[3].
3. Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to
[1].
After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is
used for the initial activation after transfer is enabled.
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Section 11 EXDMA Controller (EXDMAC)
4. Activation Source Acceptance
At the start of activation source acceptance, low level sensing is used for both falling edge
sensing and low level sensing on the EDREQ. Therefore, a request is accepted in the case of a
low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the
transfer-enabled state.
At EXDMAC activation, low level on the EDREQ pin must not remain at the end of the
previous transfer.
5. Conflict in Cluster Transfer
In cluster transfer mode, the same cluster buffer is used for all channels. When more than one
cluster transfer conflicts, the cluster buffer register holds the value of the last cluster transfer.
When the transfer between the transfer source/destination and the cluster buffer conflicts with
another cluster transfer, the transferred data in the cluster buffer may be overwritten by another
channel cluster transfer. Therefore, in the cluster transfer mode (single address mode), do not
set the cluster transfer mode for any other channels.
6. Cluster Transfer Mode and Endian
In cluster transfer mode, only a transfer to the areas in the big endian format is supported.
When cluster transfer mode is specified, do not specify the areas in the little endian format for
EDSAR and EDDAR. For details on the endian, see section 9, Bus Controller (BSC).
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Section 11 EXDMA Controller (EXDMAC)
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Section 12 Data Transfer Controller (DTC)
Section 12 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by
an interrupt request.
12.1
Features
• Transfer possible over any number of channels:
Multiple data transfer enabled for one activation source (chain transfer)
Chain transfer specifiable after data transfer (when the counter is 0)
• Three transfer modes
Normal/repeat/block transfer modes selectable
Transfer source and destination addresses can be selected from increment/decrement/fixed
• Short address mode or full address mode selectable
 Short address mode
Transfer information is located on a 3-longword boundary
The transfer source and destination addresses can be specified by 24 bits to select a 16Mbyte address space directly
 Full address mode
Transfer information is located on a 4-longword boundary
The transfer source and destination addresses can be specified by 32 bits to select a 4Gbyte address space directly
• Size of data for data transfer can be specified as byte, word, or longword
The bus cycle is divided if an odd address is specified for a word or longword transfer.
The bus cycle is divided if address 4n + 2 is specified for a longword transfer.
• A CPU interrupt can be requested for the interrupt that activated the DTC
A CPU interrupt can be requested after one data transfer completion
A CPU interrupt can be requested after the specified data transfer completion
• Read skip of the transfer information specifiable
• Writeback skip executed for the fixed transfer source and destination addresses
• Module stop state specifiable
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Section 12 Data Transfer Controller (DTC)
Figure 12.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus
connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC
transfer information.
Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR
must be set to 1.
DTC
Interrupt controller
On-chip
ROM
MRA
DTC activation request
vector number
Register
control
SAR
DAR
CRA
Activation
control
8
CPU interrupt request
Interrupt source clear
request
External bus
Bus interface
External device
(memory mapped)
Bus controller
REQ
DTCVBR
ACK
[Legend]
DTC mode registers A, B
DTC source address register
DTC destination address register
DTC transfer count registers A, B
DTC enable registers A to H
DTC control register
DTC vector base register
Figure 12.1 Block Diagram of DTC
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CRB
Interrupt
control
External
memory
MRA, MRB:
SAR:
DAR:
CRA, CRB:
DTCERA to DTCERH:
DTCCR:
DTCVBR:
MRB
DTC internal bus
On-chip
peripheral
module
Peripheral bus
On-chip
RAM
DTCCR
Internal bus (32 bits)
DTCERA
to DTCERF
Section 12 Data Transfer Controller (DTC)
12.2
Register Descriptions
DTC has the following registers.
•
•
•
•
•
•
DTC mode register A (MRA)
DTC mode register B (MRB)
DTC source address register (SAR)
DTC destination address register (DAR)
DTC transfer count register A (CRA)
DTC transfer count register B (CRB)
These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the
CPU. The contents of these registers are stored in the data area as transfer information. When a
DTC activation request occurs, the DTC reads a start address of transfer information that is stored
in the data area according to the vector address, reads the transfer information, and transfers data.
After the data transfer, it writes a set of updated transfer information back to the data area.
• DTC enable registers A to F (DTCERA to DTCERF)
• DTC control register (DTCCR)
• DTC vector base register (DTCVBR)
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Section 12 Data Transfer Controller (DTC)
12.2.1
DTC Mode Register A (MRA)
MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU.
Bit
7
6
5
4
3
2
1
0
MD1
MD0
Sz1
Sz0
SM1
SM0


Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined








R/W
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial
Value
7
MD1
Undefined 
DTC Mode 1 and 0
6
MD0
Undefined 
Specify DTC transfer mode.
Description
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
5
Sz1
Undefined 
DTC Data Transfer Size 1 and 0
4
Sz0
Undefined 
Specify the size of data to be transferred.
00: Byte-size transfer
01: Word-size transfer
10: Longword-size transfer
11: Setting prohibited
3
SM1
Undefined 
Source Address Mode 1 and 0
2
SM0
Undefined 
Specify an SAR operation after a data transfer.
0x: SAR is fixed
(SAR writeback is skipped)
10: SAR is incremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
11: SAR is decremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
1, 0

Undefined 
Reserved
The write value should always be 0.
[Legend]
x: Don't care
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Section 12 Data Transfer Controller (DTC)
12.2.2
DTC Mode Register B (MRB)
MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.
Bit
7
6
5
4
3
2
1
0
CHNE
CHNS
DISEL
DTS
DM1
DM0


Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined








R/W
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial
Value
7
CHNE
Undefined 
Description
DTC Chain Transfer Enable
Specifies the chain transfer. For details, see section
12.7.2, Chain Transfer. The chain transfer condition is
selected by the CHNS bit.
0: Disables the chain transfer
1: Enables the chain transfer
6
CHNS
Undefined 
DTC Chain Transfer Select
Specifies the chain transfer condition. If the following
transfer is a chain transfer, the completion check of the
specified transfer count is not performed and activation
source flag or DTCER is not cleared.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
5
DISEL
Undefined 
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends. When
this bit is set to 0, a CPU interrupt request is only
generated when the specified number of data transfer
ends.
4
DTS
Undefined 
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area
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Section 12 Data Transfer Controller (DTC)
Bit
Bit Name
Initial
Value
3
DM1
Undefined 
Destination Address Mode 1 and 0
2
DM0
Undefined 
Specify a DAR operation after a data transfer.
R/W
Description
0X: DAR is fixed
(DAR writeback is skipped)
10: DAR is incremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
11: SAR is decremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
1, 0

Undefined 
Reserved
The write value should always be 0.
[Legend]
x: Don't care
12.2.3
DTC Source Address Register (SAR)
SAR is a 32-bit register that designates the source address of data to be transferred by the DTC.
In full address mode, 32 bits of SAR are valid. In short address mode, the lower 24 bits of SAR is
valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of
bit 23.
If a word or longword access is performed while an odd address is specified in SAR or if a
longword access is performed while address 4n + 2 is specified in SAR, the bus cycle is divided
into multiple cycles to transfer data. For details, see section 12.5.1, Bus Cycle Division.
SAR cannot be accessed directly from the CPU.
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Section 12 Data Transfer Controller (DTC)
12.2.4
DTC Destination Address Register (DAR)
DAR is a 32-bit register that designates the destination address of data to be transferred by the
DTC.
In full address mode, 32 bits of DAR are valid. In short address mode, the lower 24 bits of DAR is
valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of
bit 23.
If a word or longword access is performed while an odd address is specified in DAR or if a
longword access is performed while address 4n + 2 is specified in DAR, the bus cycle is divided
into multiple cycles to transfer data. For details, see section 12.5.1, Bus Cycle Division.
DAR cannot be accessed directly from the CPU.
12.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the
activation source is cleared and then an interrupt is requested to the CPU when the count reaches
H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536
when CRA = H'0000.
In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower
eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit
transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the
contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when
CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL =
H'00.
In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower
eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size
counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte
(word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the
count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01,
255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or
longwords) when CRAH = CRAL =H'00.
CRA cannot be accessed directly from the CPU.
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Section 12 Data Transfer Controller (DTC)
12.2.6
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source
is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The
transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536 when CRB =
H'0000.
CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU.
12.2.7
DTC enable registers A to H (DTCERA to DTCERH)
DTCER, which is comprised of eight registers, DTCERA to DTCERH, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 12.1. Use bit manipulation instructions such as BSET and BCLR to read or write a
DTCE bit. If all interrupts are masked, multiple activation sources can be set at one time (only at
the initial setting) by writing data after executing a dummy read on the relevant register.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
14
13
12
11
10
9
8
DTCE15
DTCE14
DTCE13
DTCE12
DTCE11
DTCE10
DTCE9
DTCE8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 12 Data Transfer Controller (DTC)
Bit
Bit Name
Initial
Value
R/W
Description
15
DTCE15
0
R/W
DTC Activation Enable 15 to 0
14
DTCE14
0
R/W
13
DTCE13
0
R/W
Setting this bit to 1 specifies a relevant interrupt source to
a DTC activation source.
12
DTCE12
0
R/W
[Clearing conditions]
11
DTCE11
0
R/W
•
When writing 0 to the bit to be cleared after reading 1
10
DTCE10
0
R/W
•
9
DTCE9
0
R/W
When the DISEL bit is 1 and the data transfer has
ended
8
DTCE8
0
R/W
•
When the specified number of transfers have ended
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
0
DTCE0
0
R/W
12.2.8
DTC Control Register (DTCCR)
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended
DTCCR specifies transfer information read skip.
Bit
7
6
5
4
3
2
1
0
Bit Name



RRS
RCHNE


ERR
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R
R/(W)*
R/W
Note: * Only 0 can be written to clear the flag.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 12 Data Transfer Controller (DTC)
Bit
Bit Name
Initial
Value
R/W
Description
4
RRS
0
R/W
DTC Transfer Information Read Skip Enable
Controls the vector address read and transfer
information read. A DTC vector number is always
compared with the vector number for the previous
activation. If the vector numbers match and this bit is
set to 1, the DTC data transfer is started without
reading a vector address and transfer information. If the
previous DTC activation is a chain transfer, the vector
address read and transfer information read are always
performed.
0: Transfer read skip is not performed.
1: Transfer read skip is performed when the vector
numbers match.
3
RCHNE
0
R/W
Chain Transfer Enable After DTC Repeat Transfer
Enables/disables the chain transfer while transfer
counter (CRAL) is 0 in repeat transfer mode.
In repeat transfer mode, the CRAH value is written to
CRAL when CRAL is 0. Accordingly, chain transfer may
not occur when CRAL is 0. If this bit is set to 1, the
chain transfer is enabled when CRAH is written to
CRAL.
0: Disables the chain transfer after repeat transfer
1: Enables the chain transfer after repeat transfer

2, 1
All 0
R
Reserved
These are read-only bits and cannot be modified.
0
ERR
0
R/(W)* Transfer Stop Flag
Indicates that an address error or an NMI interrupt
occurs. If an address error or an NMI interrupt occurs,
the DTC stops.
0: No interrupt occurs
1: An interrupt occurs
[Clearing condition]
•
Note:
*
When writing 0 after reading 1
Only 0 can be written to clear this flag.
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Section 12 Data Transfer Controller (DTC)
12.2.9
DTC Vector Base Register (DTCVBR)
DTCVBR is a 32-bit register that specifies the base address for vector table address calculation.
Bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. The initial value of DTCVBR is
H'00000000.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit Name
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
Initial Value
R/W
12.3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Activation Sources
The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC
activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt
source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer
(or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or
corresponding DTCER bit is cleared.
12.4
Location of Transfer Information and DTC Vector Table
Locate the transfer information in the data area. The start address of transfer information should be
located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored
during access ([1:0] = B'00.) Transfer information can be located in either short address mode
(three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies
either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see
section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is
shown in figure 12.2
The DTC reads the start address of transfer information from the vector table according to the
activation source, and then reads the transfer information from the start address. Figure 12.3 shows
correspondences between the DTC vector address and transfer information.
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Section 12 Data Transfer Controller (DTC)
Transfer information
in short address mode
Transfer information
in full address mode
Lower addresses
Start
address
0
MRA
MRB
Chain
transfer
CRA
1
2
Lower addresses
Start
address
3
SAR
DAR
CRB
MRA
SAR
MRB
DAR
CRA
CRB
Transfer information
for one transfer
(3 longwords)
Transfer information
for the 2nd transfer
in chain transfer
(3 longwords)
0
1
2
MRA MRB
3
Reserved
(0 write)
Transfer
information
for one transfer
(4 longwords)
SAR
Chain
transfer
DAR
CRA
CRB
MRA MRB
Reserved
(0 write)
Transfer
information
for the 2nd
transfer
in chain transfer
(4 longwords)
SAR
DAR
4 bytes
CRA
CRB
4 bytes
Figure 12.2 Transfer Information on Data Area
Upper: DTCVBR
Lower: H'400 + vector number × 4
DTC vector
address
+4
Vector table
Transfer information (1)
Transfer information (1)
start address
Transfer information (2)
start address
Transfer information (2)
:
:
:
+4n
Transfer information (n)
start address
:
:
:
4 bytes
Transfer information (n)
Figure 12.3 Correspondence between DTC Vector Address and Transfer Information
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Section 12 Data Transfer Controller (DTC)
Table 12.1 shows correspondence between the DTC activation source and vector address.
Table 12.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of
Activation
Activation Source Source
Vector
Number
DTC Vector
Address Offset
DTCE*
Priority
External pin
IRQ0
64
H'500
DTCEA15
High
IRQ1
65
H'504
DTCEA14
IRQ2
66
H'508
DTCEA13
IRQ3
67
H'50C
DTCEA12
IRQ4
68
H'510
DTCEA11
IRQ5
69
H'514
DTCEA10
IRQ6
70
H'518
DTCEA9
IRQ7
71
H'51C
DTCEA8
IRQ8
72
H'520
DTCEA7
IRQ9
73
H'524
DTCEA6
IRQ10
74
H'528
DTCEA5
IRQ11
75
H'52C
DTCEA4
IRQ12
76
H'530
DTCEA3
IRQ13
77
H'534
DTCEA2
IRQ14
78
H'538
DTCEA1
IRQ15
79
H'53C
DTCEA0
A/D_0
ADI0 (A/D_0
conversion
end)
86
H'558
DTCEB15
TPU_0
TGI0A
88
H'560
DTCEB13
TGI0B
89
H'564
DTCEB12
TGI0C
90
H'568
DTCEB11
TPU_1
TPU_2
TPU_3
TGI0D
91
H'56C
DTCEB10
TGI1A
93
H'574
DTCEB9
TGI1B
94
H'578
DTCEB8
TGI2A
97
H'584
DTCEB7
TGI2B
98
H'588
DTCEB6
TGI3A
101
H'594
DTCEB5
TGI3B
102
H'598
DTCEB4
TGI3C
103
H'59C
DTCEB3
TGI3D
104
H'5A0
DTCEB2
Low
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Section 12 Data Transfer Controller (DTC)
Origin of
Activation
Activation Source Source
Vector
Number
DTC Vector
Address Offset
DTCE*
Priority
TPU_4
106
H'5A8
DTCEB1
High
TGI4A
TGI4B
107
H'5AC
DTCEB0
TPU_5
TGI5A
110
H'5B8
DTCEC15
TGI5B
111
H'5BC
DTCEC14
TMR_0
CMI0A
116
H'5D0
DTCEC13
CMI0B
117
H'5D4
DTCEC12
TMR_1
CMI1A
119
H'5DC
DTCEC11
CMI1B
120
H'5E0
DTCEC10
TMR_2
CMI2A
122
H'5E8
DTCEC9
CMI2B
123
H'5EC
DTCEC8
TMR_3
CMI3A
125
H'5F4
DTCEC7
CMI3B
126
H'5F8
DTCEC6
DMAC
DMTEND0
128
H'600
DTCEC5
DMTEND1
129
H'604
DTCEC4
DMTEND2
130
H'608
DTCEC3
DMTEND3
131
H'60C
DTCEC2
EXDMTEND0 132
H'610
DTCEC1
EXDMAC*2
DMAC
EXDMAC*2
EXDMTEND1 133
H'614
DTCEC0
EXDMTEND2 134
H'618
DTCED15
EXDMTEND3 135
H'61C
DTCED14
DMEEND0
136
H'620
DTCED13
DMEEND1
137
H'624
DTCED12
DMEEND2
138
H'628
DTCED11
DMEEND3
139
H'62C
DTCED10
EXDMEEND0 140
H'630
DTCED9
EXDMEEND1 141
H'634
DTCED8
EXDMEEND2 142
H'638
DTCED7
EXDMEEND3 143
H'63C
DTCED6
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Low
Section 12 Data Transfer Controller (DTC)
Origin of
Activation
Activation Source Source
Vector
Number
DTC Vector
Address Offset
DTCE*
Priority
SCI_0
RXI0
145
H'644
DTCED5
High
TXI0
146
H'648
DTCED4
SCI_1
RXI1
149
H'654
DTCED3
TXI1
150
H'658
DTCED2
SCI_2
RXI2
153
H'664
DTCED1
TXI2
154
H'668
DTCED0
SCI_3
RXI3
157
H'674
DTCED15
TXI3
158
H'678
DTCED14
SCI_4
RXI4
161
H'684
DTCEE13
TPU_6
TPU_7
TPU_8
TPU_9
TPU_10
TPU_11
TXI4
162
H'688
DTCEE12
TGI6A
164
H'690
DTCEE11
TGI6B
165
H'694
DTCEE10
TGI6C
166
H'698
DTCEE9
TGI6D
167
H'69C
DTCEE8
TGI7A
169
H'6A4
DTCEE7
TGI7B
170
H'6A8
DTCEE6
TGI8A
173
H'6B4
DTCEE5
TGI8B
174
H'6B8
DTCEE4
TGI9A
177
H'6C4
DTCEE3
TGI9B
178
H'6C8
DTCEE2
TGI9C
179
H'6CC
DTCEE1
TGI9D
180
H'6D0
DTCEE0
TGI10A
182
H'6D8
DTCEF15
TGI10B
183
H'6DC
DTCEF14
TGI10V
186
H'6E8
DTCEF11
TGI11A
188
H'6F0
DTCEF10
TGI11B
189
H'6F4
DTCEF9
Low
Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should
always be 0. To leave software standby mode or all-module-clock-stop mode with an
interrupt, write 0 to the corresponding DTCE bit.
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
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Section 12 Data Transfer Controller (DTC)
12.5
Operation
The DTC stores transfer information in the data area. When activated, the DTC reads transfer
information that is stored in the data area and transfers data on the basis of that transfer
information. After the data transfer, it writes updated transfer information back to the data area.
Since transfer information is in the data area, it is possible to transfer data over any required
number of channels. There are three transfer modes: normal, repeat, and block.
The DTC specifies the source address and destination address in SAR and DAR, respectively.
After a transfer, SAR and DAR are incremented, decremented, or fixed independently.
Table 12.2 shows the DTC transfer modes.
Table 12.2 DTC Transfer Modes
Transfer
Mode
Size of Data Transferred at
One Transfer Request
Memory Address Increment or
Decrement
Transfer
Count
Normal
1 byte/word/longword
Incremented/decremented by 1, 2, or 4, 1 to 65536
or fixed
Repeat*1
1 byte/word/longword
Incremented/decremented by 1, 2, or 4, 1 to 256*3
or fixed
Block*2
Block size specified by CRAH (1 Incremented/decremented by 1, 2, or 4, 1 to 65536
to 256 bytes/words/longwords) or fixed
Notes: 1. Either source or destination is specified to repeat area.
2. Either source or destination is specified to block area.
3. After transfer of the specified transfer count, initial state is recovered to continue the
operation.
Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a
single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have
chain transfer performed only when the transfer counter value is 0.
Figure 12.4 shows a flowchart of DTC operation, and table 12.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
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Section 12 Data Transfer Controller (DTC)
Start
Match &
RRS = 1
Vector number
comparison
Not match | RRS = 0
Read DTC vector
Next transfer
Read transfer
information
Transfer data
Update transfer
information
Update the start address
of transfer information
Write transfer information
CHNE = 1
Yes
No
Transfer counter = 0
or DISEL = 1
Yes
No
CHNS = 0
Yes
No
Transfer counter = 0
Yes
No
DISEL = 1
Yes
No
Clear activation
source flag
Clear DTCER/request an interrupt
to the CPU
End
Figure 12.4 Flowchart of DTC Operation
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Section 12 Data Transfer Controller (DTC)
Table 12.3 Chain Transfer Conditions
1st Transfer
2nd Transfer
Transfer
CHNE CHNS DISEL Counter*1
0

0
Transfer
CHNE CHNS DISEL Counter*1 DTC Transfer
0
Not 0




Ends at 1st transfer

0
2




Ends at 1st transfer
0

1




Interrupt request to CPU
1
0

0

0
Not 0
Ends at 2nd transfer
0

0
2
0*
Ends at 2nd transfer
1

Interrupt request to CPU

Ends at 1st transfer
1
1
1
1
0
1

1
1
0*

Not 0
2
0*
Not 0
0



0

0
Not 0
Ends at 2nd transfer
0

0
0*2
Ends at 2nd transfer
0

1



Interrupt request to CPU

Ends at 1st transfer
Interrupt request to CPU
Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer
mode
2. When the contents of the CRAH is written to the CRAL in repeat transfer mode
12.5.1
Bus Cycle Division
When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus
cycle is divided and the transfer data is read from or written to in bytes. Similarly, when the
transfer data size is longword and the SAR and DAR values are not a multiple of 4, the bus cycle
is divided and the transfer data is read from or written to in words.
Table 12.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and
access data size. Figure 12.5 shows the bus cycle division example.
Table 12.4 Number of Bus Cycle Divisions and Access Size
Specified Data Size
SAR and DAR Values
Byte (B)
Word (W)
Longword (LW)
Address 4n
1 (B)
1 (W)
1 (LW)
Address 2n + 1
1 (B)
2 (B-B)
3 (B-W-B)
Address 4n + 2
1 (B)
1 (W)
2 (W-W)
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Section 12 Data Transfer Controller (DTC)
[Example 1: When an odd address and even address are specified in SAR and DAR, respectively, and when the data size of transfer is specified as word]
Clock
DTC activation
request
DTC request
W
R
Address
B
Vector read
B
W
Transfer information Data transfer Transfer information
read
write
[Example 2: When an odd address and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword]
Clock
DTC activation
request
DTC request
W
R
Address
B
Vector read
Transfer information
read
W
B
Data transfer
L
Transfer information
write
[Example 3: When address 4n + 2 and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword]
Clock
DTC activation
request
DTC request
W
R
Address
W
Vector read
W
L
Transfer information Data transfer Transfer information
read
write
Figure 12.5 Bus Cycle Division Example
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Section 12 Data Transfer Controller (DTC)
12.5.2
Transfer Information Read Skip Function
By setting the RRS bit of DTCCR, the vector address read and transfer information read can be
skipped. The current DTC vector number is always compared with the vector number of previous
activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without
reading the vector address and transfer information. If the previous activation is a chain transfer,
the vector address read and transfer information read are always performed. Figure 12.6 shows the
transfer information read skip timing.
To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the
vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is
cleared to 0, the stored vector number is deleted, and the updated vector table and transfer
information are read at the next activation.
Clock
DTC activation (1)
request
(2)
DTC request
Transfer
information
read skip
Address
R
Vector read
W
Transfer information Data Transfer information
read
transfer
write
R
W
Data Transfer information
transfer
write
Note: Transfer information read is skipped when the activation sources of (1) and (2) (vector numbers) are the same while RRS = 1.
Figure 12.6 Transfer Information Read Skip Timing
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Section 12 Data Transfer Controller (DTC)
12.5.3
Transfer Information Writeback Skip Function
By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer
information will not be written back. This function is performed regardless of short or full address
mode. Table 12.5 shows the transfer information writeback skip condition and writeback skipped
registers. Note that the CRA and CRB are always written back regardless of the short or full
address mode. In addition in full address mode, the writeback of the MRA and MRB are always
skipped.
Table 12.5 Transfer Information Writeback Skip Condition and Writeback Skipped
Registers
SM1
DM1
SAR
DAR
0
0
Skipped
Skipped
0
1
Skipped
Written back
1
0
Written back
Skipped
1
1
Written back
Written back
12.5.4
Normal Transfer Mode
In normal transfer mode, one operation transfers one byte, one word, or one longword of data.
From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be
specified as incremented, decremented, or fixed. When the specified number of transfers ends, an
interrupt can be requested to the CPU.
Table 12.6 lists the register function in normal transfer mode. Figure 12.7 shows the memory map
in normal transfer mode.
Table 12.6 Register Function in Normal Transfer Mode
Register
Function
Written Back Value
SAR
Source address
Incremented/decremented/fixed*
DAR
Destination address
Incremented/decremented/fixed*
CRA
Transfer count A
CRA − 1
CRB
Transfer count B
Not updated
Note:
*
Transfer information writeback is skipped.
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Section 12 Data Transfer Controller (DTC)
Transfer source data area
Transfer destination data area
SAR
DAR
Transfer
Figure 12.7 Memory Map in Normal Transfer Mode
12.5.5
Repeat Transfer Mode
In repeat transfer mode, one operation transfers one byte, one word, or one longword of data. By
the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to
256 transfers can be specified. When the specified number of transfers ends, the transfer counter
and address register specified as the repeat area is restored to the initial state, and transfer is
repeated. The other address register is then incremented, decremented, or left fixed. In repeat
transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when
CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU
interrupt cannot be requested when DISEL = 0.
Table 12.7 lists the register function in repeat transfer mode. Figure 12.8 shows the memory map
in repeat transfer mode.
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Section 12 Data Transfer Controller (DTC)
Table 12.7 Register Function in Repeat Transfer Mode
Written Back Value
Register Function
CRAL is not 1
SAR
Incremented/decremented/fixed DTS =0: Incremented/
*
decremented/fixed*
Source address
CRAL is 1
DTS = 1: SAR initial value
DAR
Destination address Incremented/decremented/fixed DTS = 0: DAR initial value
*
DTS =1: Incremented/
decremented/fixed*
CRAH
Transfer count
storage
CRAH
CRAH
CRAL
Transfer count A
CRAL − 1
CRAH
CRB
Transfer count B
Not updated
Not updated
Note:
*
Transfer information writeback is skipped.
Transfer source data area
(specified as repeat area)
Transfer destination data area
SAR
DAR
Transfer
Figure 12.8 Memory Map in Repeat Transfer Mode
(When Transfer Source is Specified as Repeat Area)
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Section 12 Data Transfer Controller (DTC)
12.5.6
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area by the DTS bit in MRB.
The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one
block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR
when DTS = 0) specified as the block area is restored to the initial state. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When
the specified number of transfers ends, an interrupt is requested to the CPU.
Table 12.8 lists the register function in block transfer mode. Figure 12.9 shows the memory map
in block transfer mode.
Table 12.8 Register Function in Block Transfer Mode
Register Function
Written Back Value
SAR
DTS =0: Incremented/decremented/fixed*
Source address
DTS = 1: SAR initial value
DAR
Destination address
DTS = 0: DAR initial value
DTS =1: Incremented/decremented/fixed*
CRAH
Block size storage
CRAH
CRAL
Block size counter
CRAH
CRB
Block transfer counter
CRB − 1
Note:
*
Transfer information writeback is skipped.
Transfer source data area
SAR
1st block
:
:
Transfer destination data area
(specified as block area)
Transfer
Block area
Nth block
Figure 12.9 Memory Map in Block Transfer Mode
(When Transfer Destination is Specified as Block Area)
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DAR
Section 12 Data Transfer Controller (DTC)
12.5.7
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB
set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB,
MRA, and MRB, which define data transfers, can be set independently. Figure 12.10 shows the
chain transfer operation.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source
flag for the activation source and DTCER are not affected.
In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB
to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed.
Data area
Transfer source data (1)
Vector table
Transfer information
stored in user area
Transfer destination data (1)
DTC vector
address
Transfer information
start address
Transfer information
CHNE = 1
Transfer information
CHNE = 0
Transfer source data (2)
Transfer destination data (2)
Figure 12.10 Operation of Chain Transfer
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Section 12 Data Transfer Controller (DTC)
12.5.8
Operation Timing
Figures 10.11 to 10.14 show the DTC operation timings.
Clock
DTC activation
request
DTC request
Address
R
Vector read
Transfer
information
read
W
Data transfer
Transfer
information
write
Figure 12.11 DTC Operation Timing
(Example of Short Address Mode in Normal Transfer Mode or Repeat Transfer Mode)
Clock
DTC activation
request
DTC request
R
Address
Vector read
Transfer
information
read
W
R
Data transfer
W
Transfer
information
write
Figure 12.12 DTC Operation Timing
(Example of Short Address Mode in Block Transfer Mode with Block Size of 2)
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Section 12 Data Transfer Controller (DTC)
Clock
DTC activation
request
DTC request
Address
R
Vector
read
Transfer
information
read
W
R
Data
transfer
Transfer
information
write
Transfer
information
read
W
Data
transfer
Transfer
information
write
Figure 12.13 DTC Operation Timing (Example of Short Address Mode in Chain Transfer)
Clock
DTC activation
request
DTC request
Address
R
Vector read
Transfer information
read
W
Data Transfer information
transfer
write
Figure 12.14 DTC Operation Timing
(Example of Full Address Mode in Normal Transfer Mode or Repeat Transfer Mode)
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Section 12 Data Transfer Controller (DTC)
12.5.9
Number of DTC Execution Cycles
Table 12.9 shows the execution status for a single DTC data transfer, and table 12.10 shows the
number of cycles required for each execution.
Table 12.9 DTC Execution Status
Mode
Vector
Read
I
Transfer
Information
Write
L
Transfer
Information
Read
J
Data Read
L
Internal
Operation
N
Data Write
M
Normal 1
0*1
4*2
3*3
0*1
3*2.3 2*4
1*5
3*6
2*7
1
3*6
2*7
1
1
0*1
Repeat 1
0*1
4*2
3*3
0*1
3*2.3 2*4
1*5
3*6
2*7
1
3*6
2*7
1
1
0*1
Block 1
transfer
0*1
4*2
3*3
0*1
3*2.3 2*4
1*5
3•P
6
*
2•P* 1•P 3•P
6
*
2•P* 1•P 1
0*1
7
7
[Legend]
P: Block size (CRAH and CRAL value)
Note: 1. When transfer information read is skipped
2. In full address mode operation
3. In short address mode operation
4. When the SAR or DAR is in fixed mode
5. When the SAR and DAR are in fixed mode
6. When a longword is transferred while an odd address is specified in the address
register
7. When a word is transferred while an odd address is specified in the address register or
when a longword is transferred while address 4n + 2 is specified
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Section 12 Data Transfer Controller (DTC)
Table 12.10 Number of Cycles Required for Each Execution State
On-Chip On-Chip
On-Chip I/O
Registers
External Devices
Object to be Accessed
RAM
ROM
Bus width
32
32
8
16
32
Access cycles
1
1
2
2
2
2
3
2
3
Execution Vector read SI
1
1



8
12 + 4m
4
6 + 2m
Transfer information read SJ 1
1



8
12 + 4m
4
6 + 2m
Transfer information write Sk 1
1



8
12 + 4m
4
6 + 2m
Byte data read SL
1
2
2
2
2
3+m
2
3+m
status
1
8
16
Word data read SL
1
1
4
2
2
4
4 + 2m
2
3+m
Longword data read SL
1
1
8
4
2
8
12 + 4m
4
6 + 2m
Byte data write SM
1
1
2
2
2
2
3+m
2
3+m
Word data write SM
1
1
4
2
2
4
4 + 2m
2
3+m
Longword data write SM
1
1
8
4
2
8
12 + 4m
4
6 + 2m
Internal operation SN
1
[Legend]
m: Number of wait cycles 0 to 7 (For details, see section 9, Bus Controller (BSC).)
The number of execution cycles is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution cycles = I • SI + Σ (J • SJ + K • SK + L • SL + M • SM) + N • SN
12.5.10 DTC Bus Release Timing
The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The
DTC releases the bus after a vector read, transfer information read, a single data transfer, or
transfer information writeback. The DTC does not release the bus during transfer information
read, single data transfer, or transfer information writeback.
12.5.11 DTC Priority Level Control to the CPU
The priority of the DTC activation sources over the CPU can be controlled by the CPU priority
level specified by bits CPUP2 to CPUP0 in CPUPCR and the DTC priority level specified by bits
DTCP2 to DTCP0. For details, see section 7, Interrupt Controller.
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Section 12 Data Transfer Controller (DTC)
12.6
DTC Activation by Interrupt
The procedure for using the DTC with interrupt activation is shown in figure 12.15.
DTC activation by interrupt
Clear RRS bit in DTCCR to 0
[1]
Set transfer information
(MRA, MRB, SAR, DAR,
CRA, CRB)
[2]
Set starts address of transfer
information in DTC vector table
[3]
Set RRS bit in DTCCR to 1
[4]
[1] Clearing the RRS bit in DTCCR to 0 clears the read skip flag
of transfer information. Read skip is not performed when the
DTC is activated after clearing the RRS bit. When updating
transfer information, the RRS bit must be cleared.
[2] Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer
information in the data area. For details on setting transfer
information, see section 12.3, Register Descriptions. For details
on location of transfer information, see section 12.4, Location of
Transfer Information and DTC Vector Table.
[3] Set the start address of the transfer information in the DTC
vector table. For details on setting DTC vector table, see section
12.4, Location of Transfer Information and DTC Vector Table.
Set corresponding bit in
DTCER to 1
[5]
Set enable bit of interrupt
request for activation source
to 1
[6]
[4] Setting the RRS bit to 1 performs a read skip of second time or
later transfer information when the DTC is activated consecutively by the same interrupt source. Setting the RRS bit to 1 is
always allowed. However, the value set during transfer will be
valid from the next transfer.
[5] Set the bit in DTCER corresponding to the DTC activation
interrupt source to 1. For the correspondence of interrupts and
DTCER, refer to table 12.1. The bit in DTCER may be set to 1 on
the second or later transfer. In this case, setting the bit is not
needed.
Interrupt request generated
[6] Set the enable bits for the interrupt sources to be used as the
activation sources to 1. The DTC is activated when an interrupt
used as an activation source is generated. For details on the
settings of the interrupt enable bits, see the corresponding
descriptions of the corresponding module.
DTC activated
Determine
clearing method of
activation source
Clear
activation
source
[7]
Clear corresponding
bit in DTCER
[7] After the end of one data transfer, the DTC clears the activation
source flag or clears the corresponding bit in DTCER and
requests an interrupt to the CPU. The operation after transfer
depends on the transfer information. For details, see section
12.3, Register Descriptions and figure 12.4.
Corresponding bit in DTCER
cleared or CPU interrupt
requested
Transfer end
Figure 12.15 DTC with Interrupt Activation
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Section 12 Data Transfer Controller (DTC)
12.7
Examples of Use of the DTC
12.7.1
Normal Transfer Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The
DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0,
DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where
the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
2. Set the start address of the transfer information for an RXI interrupt at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the receive
end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation
will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination
processing should be performed in the interrupt handling routine.
12.7.2
Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain
transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of transfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
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Section 12 Data Transfer Controller (DTC)
1. Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz1 = 0, Sz0 = 1). Set the source side as a repeat area (DTS = 1). Set
MRB to chain transfer mode (CHNE = 1, CHNS = 0, DISEL = 0). Set the data table start
address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL.
CRB can be set to any value.
2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0
= 0), and word size (Sz1 = 0, Sz0 = 1). Set the data table start address in SAR, the TGRA
address in DAR, and the data table size in CRA. CRB can be set to any value.
3. Locate the TPU transfer information consecutively after the NDR transfer information.
4. Set the start address of the NDR transfer information to the DTC vector address.
5. Set the bit corresponding to the TGIA interrupt in DTCER to 1.
6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
interrupt with TIER.
7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
8. Set the CST bit in TSTR to 1, and start the TCNT count operation.
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the
set value of the next output trigger period is transferred to TGRA. The activation source TGFA
flag is cleared.
10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the
CPU. Termination processing should be performed in the interrupt handling routine.
12.7.3
Chain Transfer when Counter = 0
By executing a second data transfer and performing re-setting of the first data transfer only when
the counter value is 0, it is possible to perform 256 or more repeat transfers.
An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed
to have been set to start at lower address H'0000. Figure 12.16 shows the chain transfer when the
counter value is 0.
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Section 12 Data Transfer Controller (DTC)
1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source
address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0.
2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first
data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at
addresses H'200000 to H'21FFFF, prepare H'21 and H'20.
3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for resetting the transfer destination address for the first data transfer. Use the upper eight bits of
DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0.
If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter
for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits
of the transfer source address for the first data transfer to H'21. The lower 16 bits of the
transfer destination address of the first data transfer and the transfer counter are H'0000.
5. Next, execute the first data transfer the 65536 times specified for the first data transfer by
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper eight bits of the transfer source address for the first data
transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer
and the transfer counter are H'0000.
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
no interrupt request is sent to the CPU.
Input circuit
Transfer information
located on the on-chip memory
Input buffer
1st data transfer
information
Chain transfer
(counter = 0)
2nd data transfer
information
Upper 8 bits of DAR
Figure 12.16 Chain Transfer when Counter = 0
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Section 12 Data Transfer Controller (DTC)
12.8
Interrupt Sources
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and priority level control in the interrupt controller.
12.9
Usage Notes
12.9.1
Module Stop State Setting
Operation of the DTC can be disabled or enabled using the module stop control register. The
initial setting is for operation of the DTC to be enabled. Register access is disabled by setting the
module stop state. The module stop state cannot be set while the DTC is activated. For details,
refer to section 27, Power-Down Modes.
12.9.2
On-Chip RAM
Transfer information can be located in on-chip RAM. In this case, the RAME bit in SYSCR must
not be cleared to 0.
12.9.3
DMAC Transfer End Interrupt
When the DTC is activated by a DMAC transfer end interrupt, the DTE bit of DMDR is not
controlled by the DTC but its value is modified with the write data regardless of the transfer
counter value and DISEL bit setting. Accordingly, even if the DTC transfer counter value
becomes 0, no interrupt request may be sent to the CPU in some cases.
When the DTC is activated by a DMAC transfer end interrupt, even if DISEL=0, an automatic
clearing of the relevant activation source flag is not automatically cleared by the DTC. Therefore,
write 1 to the DTE bit by the DTC transfer and clear the activation source flag to 0.
12.9.4
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
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Section 12 Data Transfer Controller (DTC)
12.9.5
Chain Transfer
When chain transfer is used, clearing of the activation source or DTCER is performed when the
last of the chain of data transfers is executed. At this time, SCI and A/D converter
interrupt/activation sources, are cleared when the DTC reads or writes to the relevant register.
Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the
relevant register is not included in the last chained data transfer, the interrupt or activation source
will be retained.
12.9.6
Transfer Information Start Address, Source Address, and Destination Address
The transfer information start address to be specified in the vector table should be address 4n. If an
address other than address 4n is specified, the lower 2 bits of the address are regarded as 0s.
The source and destination addresses specified in SAR and DAR, respectively, will be transferred
in the divided bus cycles depending on the address and data size.
12.9.7
Transfer Information Modification
When IBCCS = 1 and the DMAC is used, clear the IBCCS bit to 0 and then set to 1 again before
modifying the DTC transfer information in the CPU exception handling routine initiated by a DTC
transfer end interrupt.
12.9.8
Endian Format
The DTC supports big and little endian formats. The endian formats used when transfer
information is written to and when transfer information is read from by the DTC must be the
same.
12.9.9
Points for Caution when Overwriting DTCER.
When overwriting of the DTC-transfer enable register (DTCER) and the generation of an interrupt
that is a source for DTC activation are in competition, activation of the DTC and interrupt
exception processing by the CPU will both proceed at the same time. Depending on the conditions
at this time, doubling of interrupts may occur. If there is a possibility of competition between
overwriting of the DTCER and generation of an interrupt that is a source for DTC activation,
proceed with overwriting of the DTCER according to the relevant procedure given below.
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Section 12 Data Transfer Controller (DTC)
In the case of
interrupt-control mode 0
In the case of
interrupt-control mode 2
Back-up the value of the CCR.
Back-up the value of the EXR.
Set the interrupt-mask bit to 1
(corresponding bit = 1 in the CCR).
Set the interrupt-request masking level to 7
(in the EXR, I2, I1, I0 = b'111).
Overwrite the DTCER.
Overwrite the DTCER.
Interrupts are
masked
Dummy-read the DTCER.
Dummy-read the DTCER.
Restore the original value of the
interrupt-mask bit.
Restore the original value of the
interrupt-request masking level.
END
END
Figure 12.17 Example of Procedures for Overwriting the DTCER
Rev. 2.00 Jul. 31, 2008 Page 602 of 1438
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Section 13 I/O Ports
Section 13 I/O Ports
Table 13.1 summarizes the port functions. The pins of each port also have other functions such as
input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port
includes a data direction register (DDR) that controls input/output, a data register (DR) that stores
output data, a port register (PORT) used to read the pin states, and an input buffer control register
(ICR) that controls input buffer on/off. Ports 4, and 5 do not have a DR or a DDR register.
Ports D to F and H to K have internal input pull-up MOSs and a pull-up MOS control register
(PCR) that controls the on/off state of the input pull-up MOSs.
Ports 2 and F include an open-drain control register (ODR) that controls on/off of the output
buffer PMOSs.
Port N supports 5-V input and functions as an NMOS open-drain output pin.
All of the I/O ports can drive a single TTL load with a capacitive component of up to 30 pF and
drive Darlington transistors when functioning as output ports.
Pins on ports 2, 3, J, and K have Schmitt-trigger inputs. Schmitt-trigger input is enabled for pins of
other ports when they are used as IRQ, TPU, TMR, or IIC2 inputs.
Table 13.1 Port Functions
SchmittTrigger
Input*1
Input Pullup MOS
Function
OpenDrain
Output
Function


Function
Port
Description
Bit
I/O
Input
Output
Port 1
General I/O port
function
multiplexed with
interrupt input,
SCI I/O, DMAC
I/O, EXDMAC
I/O*7, A/D
converter input,
TPU input, and
IIC2 I/O
7
P17/SCL0
IRQ7-A/
TCLKD-B/
ADTRG1-A
EDRAK1-A*7
IRQ7-A,
TCLKD-B,
SCL0
6
P16/SDA0/SCK3
IRQ6-A/
TCLKC-B
DACK1-A
EDACK1-A*7
IRQ6-A,
TCLKC-B,
SDA0
5
P15/SCL1
IRQ5-A/
TCLKB-B/
RxD3
TEND1-A
ETEND1-A*7
IRQ5-A,
TCLKB-B,
SCL1
4
P14/SDA1
DREQ1-A/
IRQ4-A/
TCLKA-B/
EDREQ1-A*7
TxD3
IRQ4-A,
TCLKA-B,
SDA1
3
P13
ADTRG0-A/
IRQ3-A
EDRAK0-A*7
IRQ3-A
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Section 13 I/O Ports
SchmittTrigger
Input*1
Input Pullup MOS
Function
OpenDrain
Output
Function



O
Function
Port
Port 1
Description
Bit
I/O
Input
Output
General I/O port
2
P12/SCK2
IRQ2-A
DACK0-A/
EDACK0-A*7
IRQ2-A
1
P11
RxD2/
TEND0-A/
IRQ1-A
IRQ1-A
ETEND0-A*7
DREQ0-A/
TxD2
IRQ0-A
PO7
All input
function
multiplexed with
interrupt input,
SCI I/O, DMAC
I/O, A/D
0
P10
IRQ0-A/
converter input,
EDREQ0-A*7
TPU input, and
IIC2 I/O
Port 2
General I/O port
7
function
multiplexed with
interrupt input,
6
TIOCA5/
IRQ15-A*6
P26/
IRQ14-A
TIOCA5
PPG output,
TPU I/O, TMR
P27/
TIOCB5
5
I/O, and SCI I/O
functions
PO6/TMO1/
All input
TxD1
functions
PO5
P25,
P25/
TMCI1/
TIOCA4
RxD1/
TIOCA4,
IRQ13-A
TMCI1,
IRQ13-A
4
P24/
TIOCA4/
TIOCB4/
TMRI1/
PO4
P24,
TIOCB4,
SCK1
IRQ12-A
TIOCA4,
TMRI1,
IRQ12-A
3
2
P23/
IRQ11-A/
TIOCD3
TIOCC3
P22/
IRQ10-A
TIOCC3
1
PO3
All input
functions
PO2/TMO0/
All input
TxD0
functions
PO1
P21,
P21/
TMCI0/
TIOCA3
RxD0/
TIOCA3,
IRQ9-A
TMCI0,
IRQ9-A
0
P20/
TIOCA3/
TIOCB3/
TMRI0/
PO0
P20,
TIOCB3,
SCK0
IRQ8-A
TIOCA3,
TMRI0,
IRQ8-A
Rev. 2.00 Jul. 31, 2008 Page 604 of 1438
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Section 13 I/O Ports
Input Pullup MOS
Function
OpenDrain
Output
Function




Function
Port
Description
Bit
I/O
Input
Output
SchmittTrigger
Input*1
Port 3
General I/O port
7
P37/
TIOCA2/
PO15
All input
TIOCB2
TCLKD-A
EDRAK3*7
functions
P36/

PO14
All input
EDRAK2*7
functions
function
multiplexed with
PPG output,
6
TIOCA2
7
EXDMAC I/O* ,
DMAC I/O, and
5
TPU I/O
4
P35/
TIOCA1/
PO13/
All input
TIOCB1
TCLKC-A
EDACK3*7
functions
P34/

PO12/
All input
ETEND3*7
functions
PO11
All input
TIOCA1
3
P33/
TIOCC0/
TIOCD0
TCLKB-A/
functions
EDREQ3*7
2
P32/
TCLKA-A
TIOCC0
1
P31/
TIOCA0
TIOCB0
All input
functions
PO9/
All input
ETEND2*7
functions
PO8
All input
P30/
DREQ0-B
TIOCA0
EDREQ2*7
7

P47/AN11

6

P46/AN10

A/D converter
5

P45/AN9

input
4

P44/AN8

3



2



1



0



0
Port 4
PO10/
EDACK2*7
General I/O port
function
multiplexed with
functions

Rev. 2.00 Jul. 31, 2008 Page 605 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Input Pullup MOS
Function
OpenDrain
Output
Function


Function
Port
Description
Bit
I/O
Input
Output
SchmittTrigger
Input*1
Port 5
General input
7

P57/AN7/
DA1
IRQ7-B
DA0
IRQ6-B

IRQ5-B

IRQ4-B

IRQ3-B

IRQ2-B

IRQ1-B

IRQ0-B
IRQ7-B
port function
multiplexed with
interrupt input,
6

IRQ6-B
A/D converter
input, and D/A
P56/AN6/
5

P55/AN5/
IRQ5-B
converter output
4

P54/AN4/
IRQ4-B
3

P53/AN3/
IRQ3-B
2

P52/AN2/
IRQ2-B
1

P51/AN1/
IRQ1-B
0

P50/AN0/
IRQ0-B
Rev. 2.00 Jul. 31, 2008 Page 606 of 1438
REJ09B0365-0200
Section 13 I/O Ports
SchmittTrigger
Input*1
Input Pullup MOS
Function
OpenDrain
Output
Function




Function
Port
Description
Bit
I/O
Input
Output
Port 6
General I/O port
7
P67
IRQ15-B
EDRAK1-B*7
IRQ15-B
6
P66

EDRAK0-B*

5
P65/SCK6
TCK/
TMO3/
IRQ13-B,
IRQ13-B
DACK3/
TCK
function
multiplexed with
TMR I/O, SCI
I/O,
EDACK1-B*7
EXDMAC I/O*7,
DMAC I/O,
7
TMCI3/TDI/
TEND3/
TMCI3/
H-UDI input, and
IRQ12-B/
ETEND1-B*7
IRQ12-B,
interrupt input
RxD6
4
3
P64
P63
TMRI3/
TDI
TxD6
TMRI3,
DREQ3/
IRQ11-B,
IRQ11-B/
TMS
TMS/
EDREQ1-B*7
2
P62/SCK4
IRQ10-B/
TMO2/
IRQ10-B,
TRST
DACK2
TRST
EDACK0-B*7
1
P61
TMCI2/
TEND2/
TMCI2,
RxD4/
ETEND0-B*7
IRQ9-B
IRQ9-B
0
P60
TMRI2/
TxD4
TMRI2,
IRQ8-B
DREQ2/
IRQ8-B/
EDREQ0-B*7
Port A
General I/O port
function
multiplexed with
7

PA7
Bφ
6
PA6

AS/AH/

BS-B
system clock
output and bus
5
PA5

RD
control I/O
4
PA4

LHWR/LUB
3
PA3

LLWR/LLB
2
PA2
BREQ/

WAIT-A
1
PA1

BACK/
(RD/WR-A)
0
PA0

BREQO/
BS-A
Rev. 2.00 Jul. 31, 2008 Page 607 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Input Pullup MOS
Function
OpenDrain
Output
Function
Function
Port
Description
Bit
I/O
Input
Output
SchmittTrigger
Input*1
Port B
General I/O port
7
PB7

CS7-D/






SDRAMφ*7
function
multiplexed with
bus control
6
PB6
ADTRG0-B
CS6-D
(RD/WR-B)
output
5
PB5

CS5-D/OE*7/
CKE*7
4
PB4

CS4-B/WE*7
3
PB3

CS3-A/
CS7-A
CAS*7
2
PB2

CS2-A/
CS6-A/
RAS*7
1
PB1

CS1/
CS2-B/
CS5-A/
CS6-B/
CS7-B
0
PB0

CS0/
CS4-A/
CS5-B
Port C
7



6



bus control I/O
5
PC5


and A/D
4
PC4
ADTRG2

3
PC3

LLCAS*7/
General I/O port
function
multiplexed with
converter input
DQMLL*7
2
PC2

LUCAS*7/
DQMLU*7
1
PC1

CS4-C/
CS5-C/
CS6-C/
CS7-C
0
PC0
WAIT-B/
ADTRG1-B
Rev. 2.00 Jul. 31, 2008 Page 608 of 1438
REJ09B0365-0200
CS3-B
Section 13 I/O Ports
Input Pullup MOS
Function
OpenDrain
Output
Function
Function
Port
Description
Bit
I/O
Input
Output
SchmittTrigger
Input*1
Port D*3
General I/O port
7
PD7

A7

O

6
PD6

A6
5
PD5

A5
4
PD4

A4
3
PD3

A3
2
PD2

A2
1
PD1

A1
0
PD0

A0
7
PE7

A15

O

6
PE6

A14
5
PE5

A13
4
PE4

A12
3
PE3

A11
2
PE2

A10
1
PE1

A9
0
PE0

A8
7
PF7/SCK5

A23

O
O
6
PF6
RxD5/IrRxD
A22
5
PF5

A21/
function
multiplexed with
address output
3
Port E*
General I/O port
function
multiplexed with
address output
Port F
General I/O port
function
multiplexed with
address output
TxD5/
and SCI I/O
IrTXD/
4
PF4

A20
3
PF3

A19
2
PF2

A18
1
PF1

A17
0
PF0

A16
Rev. 2.00 Jul. 31, 2008 Page 609 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Input Pullup MOS
Function
OpenDrain
Output
Function
Function
Port
Description
Bit
I/O
Input
Output
SchmittTrigger
Input*1
Port H
General I/O port
7
PH7/D7*2



O

6
2


2


2


2


2


1
2
PH1/D1*


0
PH0/D0*2


7
2



O

2


2


2


2


2
All input
O

function
PH6/D6*
multiplexed with
bi-directional
data bus
5
4
3
2
Port I
General I/O port
function
multiplexed with
bi-directional
data bus
6
5
4
3
General I/O port
J*4
function
multiplexed with
PPG and TPU
PH4/D4*
PH3/D3*
PH2/D2*
PI7/D15*
PI6/D14*
PI5/D13*
PI4/D12*
PI3/D11*


1
2
PI1/D9*


0
PI0/D8*2


PO23
2
Port
PH5/D5*
7
6
PI2/D10*
PJ7/
TIOCA8/
TIOCB8
TCLKH
PJ6/

functions
PO22
TIOCA8
I/O
5
4
functions
PJ5/
TIOCA7/
TIOCB7
TCLKG
PJ4/

PO21
2
PO20
PJ3/
TIOCC6/
TIOCD6
TCLKF
PJ2/
TCLKE
PJ1/
PO19
PJ0/
TIOCA6
Rev. 2.00 Jul. 31, 2008 Page 610 of 1438
REJ09B0365-0200
All input
functions
PO18
All input
functions
TIOCA6
PO17
TIOCB6
0
All input
functions
TIOCC6
1
All input
functions
TIOCA7
3
All input
All input
functions

PO16
All input
functions
Section 13 I/O Ports
Input Pullup MOS
Function
OpenDrain
Output
Function
O



Function
Port
Description
Bit
I/O
Input
Output
SchmittTrigger
Input*1
Port
General I/O port
7
PK7/
TIOCA11
PO31
All input
K*4
function
multiplexed with
PPG and TPU
TIOCB11
6
functions

PK6/
PO30
TIOCA11
All input
functions
I/O
5
PK5/
TIOCA10
PO29
TIOCB10
4
functions

PK4/
PO28
TIOCA10
3
PK3/
TIOCC9
PO27
PO26
TIOCC9
1
PK1/
TIOCA9
PO25
PO24
TIOCA9
7
Port M*
General I/O port



6



5



7


7


7


1
7
PM1*


0
PM0*7


3
2
PM4*
PM3*
PM2*
All input
functions
7
4
All input
functions

PK0/
All input
functions
TIOCB9
0
All input
functions

PK2/
All input
functions
TIOCD9
2
All input

Rev. 2.00 Jul. 31, 2008 Page 611 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Input Pullup MOS
Function
OpenDrain
Output
Function

O
Function
Port
Description
Bit
I/O
Input
Output
SchmittTrigger
Input*1
Port N*5
General I/O port
7




6



5



4



3
PN3/SCL3


SCL3
2
PN2/SDA3


SDA3
1
PN1/SCL2


SCL2
0
PN0/SDA2


SDA2
function
multiplexed with
IIC2 I/O
Notes:
1. Pins without Schmitt-trigger input buffer have CMOS input buffer.
2. Addresses are also output when accessing to the address/data multiplexed I/O space.
3. Ports D and E are disabled when PCJKE = 1.
4. Ports J and K are disabled when PCJKE = 0.
5. Output on the pins of port N is always NMOS open-drain output.
6. Supported only by the H8SX/1648 Group, H8SX/1648A Group, and H8SX/1648L Group.
7. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 612 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.1
Register Descriptions
Table 13.2 lists each port registers.
Table 13.2 Register Configuration in Each Port
Registers
Port
Number of
Pins
DDR
DR
PORT
ICR
PCR
ODR
Port 1
8
O
O
O
O


Port 2
8
O
O
O
O

O
Port 3
8
O
O
O
O


Port 4
4


O
O


Port 5
8


O
O


Port 6
8
O
O
O
O


Port A
8
O
O
O
O


8
O
O
O
O


Port C*
1
6
O
O
O
O


Port D*
2
8
O
O
O
O
O

Port E*
2
8
O
O
O
O
O

Port F
8
O
O
O
O
O
O
Port B
Port H
8
O
O
O
O
O

Port I
8
O
O
O
O
O

8
O
O
O
O
O

8
O
O
O
O
O

Port M*
5
O
O
O
O


Port N
4
O
O
O
O


Port J*
3
3
Port K*
4
[Legend]
O:
Register exists
:
No register exists
Notes: 1. Write the initial value to any of bits in port C registers.
2. Do not access port D or E registers when PCJKE = 1.
3. Do not access port J or K registers when PCJKE = 0.
4. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 613 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.1.1
Data Direction Register (PnDDR) (n = 1, 2, 3, 6, A, to F, H to K, M*, and N)
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from
the DDR is invalid and DDR is always read as an undefined value.
When the general I/O port function is selected, the corresponding pin functions as an output port
by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by
clearing the corresponding DDR bit to 0.
The initial DDR values are shown in table 13.3.
Bit
7
6
5
4
3
2
1
0
Pn7DDR
Pn6DDR
Pn5DDR
Pn4DDR
Pn3DDR
Pn2DDR
Pn1DDR
Pn0DDR
Initial Value
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Bit Name
Notes: The lower six bits of port C registers are effective while the upper two bits are reserved.
The lower five bits of port M registers are effective while the upper three bits are reserved.
The lower four bits of port N registers are effective while the upper four bits are reserved.
Do not access port J or port K registers when PCJKE = 0.
Do not access port D or port E registers when PCJKE = 1.
Table 13.3 Startup Mode and Initial Value
Startup Mode
Port
External Extended Mode
Single-Chip Mode
Port A
H'80
H'00
Other ports
H'00
H'00
Rev. 2.00 Jul. 31, 2008 Page 614 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.1.2
Data Register (PnDR) (n = 1, 2, 3, 6, A, to F, H to K, M*, and N)
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the
general output port.
The initial value of DR is H'00.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
Pn7DR
Pn6DR
Pn5DR
Pn4DR
Pn3DR
Pn2DR
Pn1DR
Pn0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: The lower six bits of port C registers are effective while the upper two bits are reserved.
The lower five bits of port M registers are effective while the upper three bits are reserved.
The lower four bits of port N registers are effective while the upper four bits are reserved.
Do not access port J or port K registers when PCJKE = 0.
Do not access port D or port E registers when PCJKE = 1.
13.1.3
Port Register (PORTn) (n = 1 to 6, A to F, H to K, M*, and N)
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
PORT is an 8-bit read-only register that reflects the port pin state. A write to PORT is invalid.
When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and
the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the
ICR value.
The initial value of PORT is undefined and is determined based on the port pin state.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
Pn7
Pn6
Pn5
Pn4
Pn3
Pn2
Pn1
Pn0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R
R
R
R
R
R
R
R
Notes: The upper four bits of port 4 registers are effective while the lower four bits are reserved.
The lower six bits of port C registers are effective while the upper two bits are reserved.
The lower five bits of port M registers are effective while the upper three bits are reserved.
The lower four bits of port N registers are effective while the upper four bits are reserved.
Do not access port J or port K registers when PCJKE = 0.
Do not access port D or port E registers when PCJKE = 1.
Rev. 2.00 Jul. 31, 2008 Page 615 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.1.4
Input Buffer Control Register (PnICR) (n = 1 to 6, A to F, H to K, M*, and N)
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
ICR is an 8-bit readable/writable register that controls the port input buffers.
For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR
cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed
high.
When the pin functions as an input for the peripheral modules, the corresponding bits should be
set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input
or is used as an analog input/output pin.
When PORT is read, the pin state is always read regardless of the ICR value. When the ICR value
is cleared to 0 at this time, the read pin state is not reflected in a corresponding on-chip peripheral
module.
If ICR is modified, an internal edge may occur depending on the pin state. Accordingly, ICR
should be modified when the corresponding input pins are not used. For example, an IRQ input,
modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the
interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the
ICR setting, the edge should be cancelled.
The initial value of ICR is H'00.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
Pn7ICR
Pn6ICR
Pn5ICR
Pn4ICR
Pn3ICR
Pn2ICR
Pn1ICR
Pn0ICR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: The upper four bits of port 4 registers are effective while the lower four bits are reserved.
The lower six bits of port C registers are effective while the upper two bits are reserved.
The lower five bits of port M registers are effective while the upper three bits are reserved.
The lower four bits of port N registers are effective while the upper four bits are reserved.
Do not access port J or port K registers when PCJKE = 0.
Do not access port D or port E registers when PCJKE = 1.
Rev. 2.00 Jul. 31, 2008 Page 616 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.1.5
Pull-Up MOS Control Register (PnPCR) (n = D to F and H to K)
PCR is an 8-bit readable/writable register that controls on/off of the port input pull-up MOS.
If a bit in PCR is set to 1 while the pin is in input state, the input pull-up MOS corresponding to
the bit in PCR is turned on. Table 13.4 shows the input pull-up MOS status. The initial value of
PCR is H'00.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
Pn7PCR
Pn6PCR
Pn5PCR
Pn4PCR
Pn3PCR
Pn2PCR
Pn1PCR
Pn0PCR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 13.4 Input Pull-Up MOS State
Port
Pin State
Reset
Hardware
Software
Standby Mode Standby Mode
Other
Operation
Port D
Address output
Port output
Port input
Address output
Port output
Port input
Address output
Peripheral module output
Port output
Port input
Data input/output
Port output
Port input
Data input/output
Port output
Port input
Peripheral module output
Port output
Port input
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON/OFF
OFF
OFF
ON/OFF
OFF
OFF
OFF
ON/OFF
OFF
OFF
ON/OFF
OFF
OFF
ON/OFF
OFF
OFF
ON/OFF
Port E
Port F
Port H
Port I
Port J
OFF
OFF
ON/OFF
OFF
OFF
ON/OFF
OFF
OFF
OFF
ON/OFF
OFF
OFF
ON/OFF
OFF
OFF
ON/OFF
OFF
OFF
ON/OFF
Rev. 2.00 Jul. 31, 2008 Page 617 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Port
Pin State
Reset
Hardware
Standby Mode
Software
Standby Mode
Other
Operation
Port K
Peripheral module output
Port output
Port input
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON/OFF
OFF
OFF
ON/OFF
[Legend]
OFF:
ON/OFF:
13.1.6
The input pull-up MOS is always off.
If PCR is set to 1, the input pull-up MOS is on; if PCR is cleared to 0, the input pull-up
MOS is off.
Open-Drain Control Register (PnODR) (n = 2 and F)
ODR is an 8-bit readable/writable register that selects the open-drain output function.
If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS opendrain output. If a bit in ODR is cleared to 0, the pin corresponding to that bit in ODR functions as
a CMOS output.
The initial value of ODR is H'00.
Bit
Bit Name
Initial Value
R/W
13.2
7
6
5
4
3
2
1
0
Pn7ODR
Pn6ODR
Pn5ODR
Pn4ODR
Pn3ODR
Pn2ODR
Pn1ODR
Pn0ODR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Buffer Control
This section describes the output priority of each pin.
The name of each peripheral module pin is followed by "_OE". This (for example: TIOCA4_OE)
indicates whether the output of the corresponding function is valid (1) or if another setting is
specified (0). Table 13.5 lists each port output signal's valid setting. For details on the
corresponding output signals, see the register description of each peripheral module. If the name
of each peripheral module pin is followed by A or B, the pin function can be modified by the port
function control register (PFCR). For details, see section 13.3, Port Function Controller.
For a pin whose initial value changes according to the activation mode, "Initial value E" indicates
the initial value when the LSI is started up in external extended mode and "Initial value S"
indicates the initial value when the LSI is started in single-chip mode.
Rev. 2.00 Jul. 31, 2008 Page 618 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.1
(1)
Port 1
P17/IRQ7-A/TCLKD-B/SCL0/ADTRG1-A/ EDRAK1-A*
The pin function is switched as shown below according to the combination of the EXDMAC* and
IIC2 register setting and P17DDR bit setting.
Setting
Module Name
Pin Function
EXDMAC*
IIC2
I/O Port
EDRAK1A_OE*
SCL0_OE
P17DDR
EXDMAC*
EDRAK1-A*
1


IIC2
SCL0 input/output
0
1

I/O port
P17 output
0
0
1
P17 input
(initial setting)
0
0
0
Note:
(2)
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
P16/DACK1-A/IRQ6-A/TCLKC-B/SDA0/SCK3/EDACK1-A*
The pin function is switched as shown below according to the combination of the EXDMAC*,
DMAC, SCI, and IIC2 register setting and P16DDR bit setting.
Setting
EXDMAC*
Module
Name
DMAC
SCI
IIC2
I/O Port
Pin Function
EDACK1A_OE* DACK1A_OE SCK3_OE SDA0_OE P16DDR
EXDMAC*
EDACK1-A
output*
1

DMAC
DACK1-A
output
0
1


—
SCI
SCK3 output
0
0
1


IIC2
SDA0
input/output
0
0
0
1

I/O port
P16 output
0
0
0
0
1
P16 input
(initial setting)
0
0
0
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 619 of 1438
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Section 13 I/O Ports
(3)
P15/RxD3/TEND1-A/IRQ5-A/TCLKB-B/SCL1/ ETEND1-A*
The pin function is switched as shown below according to the combination of the EXDMAC*,
DMAC and IIC2 register setting and P15DDR bit setting.
Setting
EXDMAC*
DMAC
IIC2
I/O Port
Module Name
Pin Function ETEND1A_OE* TEND1A_OE SCL1_OE
P15DDR
EXDMAC*
ETEND1-A
output*
1



DMAC
TEND1-A
output
0
1

—
IIC2
SCL1
input/output
0
0
1

I/O port
P15 output
0
0
0
1
P15 input
0
(initial setting)
0
0
0
Note:
(4)
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
P14/TxD3/DREQ1-A/EDREQ1-A*/IRQ4-A/TCLKA-B/SDA1
The pin function is switched as shown below according to the combination of the SCI and IIC2
register setting and P14DDR bit setting.
Setting
Module Name
Pin Function
SCI
IIC2
I/O Port
TxD3_OE
SDA1_OE
P14DDR
SCI
TxD3 output
1
—
—
IIC2
SDA1 input/output
0
1
—
I/O port
P14 output
0
0
1
P14 input
(initial setting)
0
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 620 of 1438
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Section 13 I/O Ports
(5)
P13/ADTRG0-A/IRQ3-A/ EDRAK0-A*
The pin function is switched as shown below according to the EXDMAC* register setting and
P13DDR bit setting.
Setting
EXDMAC*
I/O Port
Module Name
Pin Function
EDRAK0A_OE*
P13DDR
EXDMAC*
EDRAK0-A output*
1
—
I/O port
P13 output
0
1
P13 input (initial setting)
0
0
Note:
(6)
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
P12/SCK2/DACK0-A/IRQ2-A/ EDACK0-A*
The pin function is switched as shown below according to the combination of the EXDMAC*,
DMAC and SCI register settings and P12DDR bit setting.
Setting
EXDMAC*
DMAC
SCI
Module Name
Pin Function
EDACK0A_OE* DACK0A_OE SCK2_OE
EXDMAC*
EDACK0-A
output*
1
DMAC
I/O Port
P12DDR



DACK0-A output 0
1


SCI
SCK2 output
0
0
1

I/O port
P12 output
0
0
0
1
P12 input
(initial setting)
0
0
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 621 of 1438
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Section 13 I/O Ports
(7)
P11/RxD2/TEND0-A/IRQ1-A/ ETEND0-A*
The pin function is switched as shown below according to the combination of the EXDMAC* and
DMAC register settings and P11DDR bit setting.
Setting
EXDMAC*
DMAC
I/O Port
Module Name
Pin Function
ETEND0A_OE* TEND0A_OE
EXDMAC*
ETEND0-A output*
1


DMAC
TEND0-A output
10
1

I/O port
P11 output
0
0
1
P11 input
(initial setting)
0
0
0
Note:
(8)
*
P11DDR
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
P10/TxD2/DREQ0-A/IRQ0-A/EDERQ0-A*
The pin function is switched as shown below according to the combination of the SCI register
setting and P10DDR bit setting.
Setting
SCI
I/O Port
Module Name
Pin Function
TxD2_OE
P10DDR
SCI
TxD2 output
1

I/O port
P10 output
0
1
P10 input
(initial setting)
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 622 of 1438
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Section 13 I/O Ports
13.2.2
(1)
Port 2
P27/PO7/TIOCA5/TIOCB5/IRQ15-A
The pin function is switched as shown below according to the combination of the TPU and PPG
register settings and P27DDR bit setting.
Setting
TPU
PPG
I/O Port
Module Name
Pin Function
TIOCB5_OE
PO7_OE
P27DDR
TPU
TIOCB5 output
1
—
—
PPG
PO7 output
0
1
—
P27 output
0
0
1
P27 input
(initial setting)
0
0
0
I/O port
(2)
P26/PO6/TIOCA5/TMO1/TxD1/IRQ14-A
The pin function is switched as shown below according to the combination of the TPU, TMR,
SCI, and PPG register settings and P26DDR bit setting.
Setting
TPU
TMR
SCI
PPG
I/O Port
TxD1_OE
PO6_OE
P26DDR



Module Name
Pin Function
TIOCA5_OE TMO1_OE
TPU
TIOCA5 output
1

TMR
TMO1 output
0
1



SCI
TxD1 output
0
0
1


PPG
PO6 output
0
0
0
1

I/O port
P26 output
0
0
0
0
1
P26 input
(initial setting)
0
0
0
0
0
Rev. 2.00 Jul. 31, 2008 Page 623 of 1438
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Section 13 I/O Ports
(3)
P25/PO5/TIOCA4/TMCI1/RxD1/IRQ13-A
The pin function is switched as shown below according to the combination of the TPU and PPG
register settings and P25DDR bit setting.
Setting
TPU
PPG
I/O Port
Module Name
Pin Function
TIOCA4_OE
PO5_OE
P25DDR
TPU
TIOCA4 output
1


PPG
PO5 output
0
1

I/O port
P25 output
0
0
1
P25 input
(initial setting)
0
0
0
(4)
P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1/IRQ12-A
The pin function is switched as shown below according to the combination of the TPU, SCI, and
PPG register settings and P24DDR bit setting.
Setting
TPU
SCI
PPG
I/O Port
PO4_OE
P24DDR
Module Name
Pin Function
TIOCB4_OE SCK1_OE
TPU
TIOCB4 output
1



SCI
SCK1 output
0
1


PPG
PO4 output
0
0
1

P24 output
0
0
0
1
P24 input
(initial setting)
0
0
0
0
I/O port
Rev. 2.00 Jul. 31, 2008 Page 624 of 1438
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Section 13 I/O Ports
(5)
P23/PO3/TIOCC3/TIOCD3/IRQ11-A
The pin function is switched as shown below according to the combination of the TPU and PPG
register settings and P23DDR bit setting.
Setting
TPU
PPG
I/O Port
Module Name
Pin Function
TIOCD3_OE
PO3_OE
P23DDR
TPU
TIOCD3 output
1
—
—
PPG
PO3 output
0
1
—
I/O port
P23 output
0
0
1
P23 input
(initial setting)
0
0
0
(6)
P22 /PO2/TIOCC3/TMO0/TxD0/IRQ10-A
The pin function is switched as shown below according to the combination of the TPU, TMR,
SCI, and PPG register settings and P22DDR bit setting.
Setting
TPU
TMR
SCI
PPG
I/O Port
Module Name
Pin Function
TIOCC3_OE
TMO0_OE TxD0_OE
PO2_OE
P22DDR
TPU
TIOCC3 output
1




TMR
TMO0 output
0
1



SCI
TxD0 output
0
0
1


PPG
PO2 output
0
0
0
1

I/O port
P22 output
0
0
0
0
1
P22 input
(initial setting)
0
0
0
0
0
Rev. 2.00 Jul. 31, 2008 Page 625 of 1438
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Section 13 I/O Ports
(7)
P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A
The pin function is switched as shown below according to the combination of the TPU and PPG
register settings and P21DDR bit setting.
Setting
TPU
PPG
I/O Port
Module Name
Pin Function
TIOCA3_OE
PO1_OE
P21DDR
TPU
TIOCA3 output
1


PPG
PO1 output
0
1

I/O port
P21 output
0
0
1
P21 input
(initial setting)
0
0
0
(8)
P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A
The pin function is switched as shown below according to the combination of the TPU, SCI, and
PPG register settings and P20DDR bit setting.
Setting
TPU
SCI
PPG
I/O Port
PO0_OE
P20DDR
Module Name
Pin Function
TIOCB3_OE SCK0_OE
TPU
TIOCB3 output
1



SCI
SCK0 output
0
1


PPG
PO0 output
0
0
1

P20 output
0
0
0
1
P20 input
(initial setting)
0
0
0
0
I/O port
Rev. 2.00 Jul. 31, 2008 Page 626 of 1438
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Section 13 I/O Ports
13.2.3
(1)
Port 3
P37/PO15/TIOCA2/TIOCB2/TCLKD-A/EDRAK3*
The pin function is switched as shown below according to the combination of the EXDMAC*,
TPU and PPG register settings and P37DDR bit setting.
Setting
EXDMAC*
TPU
PPG
I/O Port
EDRAK3 _OE*
TIOCB2_OE PO15_OE
P37DDR
Module Name
Pin Function
EXDMAC*
EDRAK3 output* 1
—
—
—
TPU
TIOCB2 output
0
1
—
—
PPG
PO15 output
0
0
1
—
I/O port
P37 output
0
0
0
1
P37 input
(initial setting)
0
0
0
0
Note:
(2)
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
P36/PO14/TIOCA2/ EDRAK2*
The pin function is switched as shown below according to the combination of the EXDMAC*,
TPU and PPG register settings and P36DDR bit setting.
Setting
EXDMAC*
TPU
PPG
I/O Port
EDRAK2 _OE*
TIOCA2_OE PO14_OE
P36DDR
Module Name
Pin Function
EXDMAC*
EDRAK2 output* 1
—
—
—
TPU
TIOCA2 output
0
1
—
—
PPG
PO14 output
0
0
1
—
I/O port
P36 output
0
0
0
1
P36 input
(initial setting)
0
0
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 627 of 1438
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Section 13 I/O Ports
(3)
P35/PO13/TIOCA1/TIOCB1/TCLKC-A/DACK1-B/ EDACK3*
The pin function is switched as shown below according to the combination of the EXDMAC*,
DMAC, TPU, and PPG register settings and P35DDR bit setting.
Setting
Module
Name
EXDMAC*
DMAC
TPU
PPG
I/O Port
Pin Function EDACK3 _OE* DACK1B _OE TIOCB2_OE PO14_OE P36DDR
EXDMAC* EDACK3
output*
1
—
—
—
—
DMAC
DACK1-B
output
0
1
—
—
—
TPU
TIOCB1
output
0
0
1
—
—
PPG
PO13 output
0
0
0
1
—
I/O port
P35 output
0
0
0
0
1
P35 input
0
(initial setting)
0
0
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 628 of 1438
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Section 13 I/O Ports
(4)
P34/PO12/TIOCA1/TEND1-B/ETEND3*
The pin function is switched as shown below according to the combination of the EXDMAC*,
DMAC, TPU, and PPG register settings and P34DDR bit setting.
Setting
Module
Name
EXDMAC*
DMAC
Pin Function ETEND3 _OE* TEND1B_OE
EXDMAC* ETEND3
output*
TPU
PPG
I/O Port
TIOCA1_OE PO12_OE P34DDR
1
—
—
—
—
DMAC
TEND1-B
output
0
1
—
—
—
TPU
TIOCA1
output
0
0
1
—
—
PPG
PO12 output
0
0
0
1
—
I/O port
P34 output
0
0
0
0
1
P34 input
0
(initial setting)
0
0
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 629 of 1438
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Section 13 I/O Ports
(5)
P33/PO11/TIOCC0/TIOCD0/TCLKB-A/DREQ1-B/EDREQ3*
The pin function is switched as shown below according to the combination of the TPU and PPG
register settings and P33DDR bit setting.
Setting
TPU
PPG
I/O Port
Module Name
Pin Function
TIOCD0_OE
PO11_OE
P33DDR
TPU
TIOCD0 output
1
—
—
PPG
PO11 output
0
1
—
I/O port
P33 output
0
0
1
P33 input
(initial setting)
0
0
0
Note:
(6)
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
P32/PO10/TIOCC0/TCLKA-A/DACK0-B/EDACK2*
The pin function is switched as shown below according to the combination of the EXDMAC*,
DMAC, TPU, and PPG register settings and P32DDR bit setting.
Setting
Module
Name
EXDMAC*
DMAC
Pin Function EDACK2_OE* DACK0B_OE
EXDMAC* EDACK2
output*
TPU
PPG
I/O Port
TIOCC0_OE PO10_OE P32DDR
1
—
—
—
—
DMAC
DACK0-B
output
0
1
—
—
—
TPU
TIOCA1
output
0
0
1
—
—
PPG
PO12 output
0
0
0
1
—
I/O port
P34 output
0
0
0
0
1
P34 input
0
(initial setting)
0
0
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 630 of 1438
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Section 13 I/O Ports
(7)
P31/PO9/TIOCA0/TIOCB0/TEND0-B/ETEND2*
The pin function is switched as shown below according to the combination of the EXDMAC*,
DMAC, TPU, and PPG register settings and P31DDR bit setting.
Setting
Module
Name
EXDMAC*
DMAC
Pin Function ETEND2_OE* TEND0B_OE
EXDMAC* ETEND2
output*
TPU
PPG
I/O Port
TIOCB0_OE PO9_OE
P31DDR
1
—
—
—
—
DMAC
TEND0-B
output
0
1
—
—
—
TPU
TIOCB0
output
0
0
1
—
—
PPG
PO9 output
0
0
0
1
—
I/O port
P31 output
0
0
0
0
1
P31 input
0
(initial setting)
0
0
0
0
Note:
(8)
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
P30/PO8/TIOCA0/DREQ0-B/EDREQ2*
The pin function is switched as shown below according to the combination of the TPU and PPG
register settings and P33DDR bit setting.
Setting
TPU
PPG
I/O Port
Module Name
Pin Function
TIOCA0_OE
PO8_OE
P30DDR
TPU
TIOCA0 output
1


PPG
PO8 output
0
1

I/O port
P30 output
0
0
1
P30 input
(initial setting)
0
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 631 of 1438
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Section 13 I/O Ports
13.2.4
(1)
Port 5
P57/AN7/DA1/IRQ7-B
Module Name
Pin Function
D/A converter
DA1 output
(2)
P56/AN6/DA0/IRQ6-B
Module Name
Pin Function
D/A converter
DA0 output
13.2.5
(1)
Port 6
P67/IRQ15-B/EDRAK1-B*
• H8SX/1648 Group
The pin function is switched as shown below according to the combination of the SCI register
setting and P67DDR bit setting.
Setting
Module Name
Pin Function
I/O port
P67 output
P67 input (initial setting)
SCI
I/O Port
SCK6_OE
P67DDR

1
1
0
0
0
• H8SX/1648A Group and H8SX/1648L Group
The pin function is switched as shown below according to the combination of the P67DDR bit
setting.
Setting
I/O Port
Module Name
Pin Function
P67DDR
I/O port
P67 output
1
P67 input (initial setting)
0
Rev. 2.00 Jul. 31, 2008 Page 632 of 1438
REJ09B0365-0200
Section 13 I/O Ports
• H8SX/1648G Group, H8SX/1648H Group
The pin function is switched as shown below according to the combination of the EXDMAC*
register setting and P67DDR bit setting.
Setting
EXDMAC*
I/O Port
Module Name
Pin Function
EDRAK1B_OE*
P67DDR
EXDMAC*
EDRAK1-B output*
1
0
I/O Port
P67 output
0
1
P67 input (initial setting)
0
0
Note:
(2)
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
P66/EDRAK-0-B*
• H8SX/1648 Group
The pin function is switched as shown below according to the combination of the SCI register
setting and P66DDR bit setting.
Setting
SCI
I/O Port
Module Name
Pin Function
TXD6_OE
P66DDR
I/O port
P66 output

1
1
0
0
0
P66 input (initial setting)
• H8SX/1648A Group and H8SX/1648L Group
The pin function is switched as shown below according to the combination of the P66DDR bit
setting.
Setting
I/O Port
Module Name
Pin Function
P66DDR
I/O port
P66 output
1
P66 input (initial setting)
0
Rev. 2.00 Jul. 31, 2008 Page 633 of 1438
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Section 13 I/O Ports
• H8SX/1648G Group, H8SX/1648H Group
The pin function is switched as shown below according to the combination of the EXDMAC*
register setting and P66DDR bit setting.
Setting
EXDMAC*
I/O Port
Module Name
Pin Function
EDRAK0B_OE*
P66DDR
EXDMAC*
EDRAK0-B output*
1
0
I/O Port
P66 output
0
1
P66 input (initial setting)
0
0
Note:
(3)
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
P65/TMO3/DACK3/EDACK1-B*2/TCK/SCK6/IRQ13-B
The pin function is switched as shown below according to the combination of operation mode, the
EXDMAC*2, DMAC, TMR, and SCI register settings and P65DDR bit setting.
Setting
Module
Name
SCI
EXDMAC*2 DMAC
MCU
TMR
Operating
SCK6_ EDACK1B_
TMO3_
Mode
OE
OE*2
DACK3_OE OE
Pin Function
I/O Port
P65DDR
1




EXDMAC*2 EDACK1-B
output*2
0
1
0


DMAC
SCI
0
0
1


TMR
SCK6 output Modes
other than
the
boundary
DACK3
scan
output
enabled
1
TMO3 output mode*
0
0
0
1

I/O port
P65 output
0
0
0
0
1
P65 input
(initial setting)
0
0
0
0
0
Notes: 1. These pins are boundary scan dedicated input pins during boundary scan enabled
mode.
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 634 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(4)
P64/TMCI3/TEND3/ETEND1-B*2/TDI/RxD6/IRQ12-B
The pin function is switched as shown below according to the combination of operation mode, the
EXDMAC*2, DMAC register setting and P64DDR bit setting.
Setting
Module
Name
Pin Function
EXDMAC*2 ETEND1-B
output*2
DMAC
TEND3 output
I/O port
P64 output
MCU Operating
Mode
EXDMAC*
2
DMAC
ETEND1B_OE*
2
I/O Port
TEND3_OE P64DDR


Modes other than 1
the boundary
scan enabled
0
mode*1
0
1

0
1
0
0
0
P64 input
(initial setting)
Notes: 1. These pins are boundary scan dedicated input pins during boundary scan enabled
mode.
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
(5)
P63/TMRI3/DREQ3/ EDREQ1-B*2/IRQ11-B/TxD6/TMS
The pin function is switched as shown below according to the combination of operation mode, the
SCI register setting and P63DDR bit setting.
Setting
Module
Name
Pin Function
SCI
TxD6 output
I/O port
P63 output
P63 input
(initial setting)
MCU Operating
Mode
SCI
I/O Port
TxD6_OE
P63DDR
Modes other than the 1
boundary scan
0
1
enabled mode*
0

1
0
Notes: 1. These pins are boundary scan dedicated input pins during boundary scan enabled
mode.
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 635 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(6)
P62/TMO2/SCK4/DACK2/ EDACK0-B*2/IRQ10-B/TRST
The pin function is switched as shown below according to the combination of the EXDMAC*2,
DMAC, TMR, and SCI register settings and P62DDR bit setting.
Setting
2
MCU
EXDMAC*
Operating
Pin Function Mode
EDACK0B_OE*
Module
Name
2
DMAC
TMR
SCI
I/O Port
DACK2_OE
TMO2_OE SCK4_OE
P62DDR
EXDMAC* EDACK0-B
output*2
1




DMAC
0
1



0
0
1


0
0
0
1

P62 output
0
0
0
0
1
P62 input
(initial setting)
0
0
0
0
0
2
TMR
SCI
I/O port
Modes
other than
the
DACK2
boundary
output
scan
TMO2 output enabled
1
SCK4 output mode*
Notes: 1. These pins are boundary scan dedicated input pins during boundary scan enabled
mode.
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
(7)
P61/TMCI2/RxD4/TEND2/ ETEND0-B*/IRQ9-B
The pin function is switched as shown below according to the combination of the EXDMAC*,
DMAC register setting and P61DDR bit setting.
Setting
EXDMAC*
DMAC
I/O Port
Module Name
Pin Function
ETEND0B_OE*
TEND2-OE
P61DDR
EXDMAC*
ETEND0-B
output*
1


DMAC
TEND2 output
0
1

I/O port
P61 output
0
0
1
P61 input
(initial setting)
0
0
0
Note:
*
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 636 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(8)
P60/TMRI2/TxD4/DREQ2/ EDREQ0-B*/IRQ8-B
The pin function is switched as shown below according to the combination of the SCI register
setting and P60DDR bit setting.
Setting
SCI
I/O Port
Module Name
Pin Function
TxD4_OE
P60DDR
SCI
TxD4 output
1

I/O port
P60 output
0
1
P60 input
(initial setting)
0
0
Note:
*
13.2.6
(1)
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Port A
PA7/Bφ
The pin function is switched as shown below according to the PA7DDR bit setting.
Setting
I/O Port
Module Name
Pin Function
PA7DDR
I/O port
Bφ output
(initial setting E)
PA7 input
(initial setting S)
1
[Legend]
Initial setting E:
Initial setting S:
0
Initial setting in external extended mode
Initial setting in single-chip mode
Rev. 2.00 Jul. 31, 2008 Page 637 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(2)
PA6/AS/AH/BS-B
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, port function control register (PFCR), and the PA6DDR bit
settings.
Setting
Bus
Controller
I/O Port
Module Name
Pin Function
AH_OE
BS-B_OE
AS_OE
PA6DDR
Bus controller
AH output*
BS-B output*
AS output*
(initial setting E)
PA6 output
PA6 input
(initial setting S)
1
0
0

1
0


1



0
0
0
0
0
0
1
0
I/O port
[Legend]
Initial setting E: Initial setting in external extended mode
Initial setting S: Initial setting in single-chip mode
Note: * Valid in external extended mode (EXPE = 1)
(3)
PA5/RD
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, and the PA5DDR bit settings.
Setting
MCU Operating Mode
I/O Port
EXPE
PA5DDR
Module Name
Pin Function
Bus controller
RD output*
(Initial setting E)
1

I/O port
PA5 output
0
1
PA5 input
(initial setting S)
0
0
[Legend]
Initial setting E: Initial setting in external extended mode
Initial setting S: Initial setting in single-chip mode
Note: * Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 638 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(4)
PA4/LHWR/LUB
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, port function control register (PFCR), and the PA4DDR bit
settings.
Setting
Bus Controller
Module Name
Pin Function
Bus controller
LUB output*
LUB_OE*
I/O Port
LHWR_OE*
2
PA4DDR
1


LHWR output*
(initial setting E)

1

PA4 output
0
0
1
PA4 input
(initial setting S)
0
0
0
1
1
I/O port
2
[Legend]
Initial setting E: Initial setting in external extended mode
Initial setting S: Initial setting in single-chip mode
Notes: 1. Valid in external extended mode (EXPE = 1)
2. When the byte control SRAM space is accessed while the byte control SRAM space is
specified or while LHWR_OE = 1, this pin functions as the LUB output; otherwise, the
LHWR output.
Rev. 2.00 Jul. 31, 2008 Page 639 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(5)
PA3/LLWR/LLB
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, and the PA3DDR bit settings.
Setting
Bus Controller
I/O Port
Module Name
Pin Function
LLB_OE*
LLWR_OE*
PA3DDR
Bus controller
LLB output*1
1


LLWR output*
(initial setting E)

1

PA3 output
0
0
1
PA3 input
(initial setting S)
0
0
0
2
1
I/O port
2
[Legend]
Initial setting E: Initial setting in external extended mode
Initial setting S: Initial setting in single-chip mode
Notes: 1. Valid in external extended mode (EXPE = 1)
2. If the byte control SRAM space is accessed, this pin functions as the LLB output;
otherwise, the LLWR.
(6)
PA2/BREQ/WAIT-A
The pin function is switched as shown below according to the combination of the bus controller
register setting and the PA2DDR bit setting.
Setting
Bus Controller
I/O Port
Module Name
Pin Function
BCR_BRLE
BCR_WAITE
PA2DDR
Bus controller
BREQ input
1


WAIT-A input
0
1

PA2 output
0
0
1
PA2 input
(initial setting)
0
0
0
I/O port
Rev. 2.00 Jul. 31, 2008 Page 640 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(7)
PA1/BACK/(RD/WR-A)
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, port function control register (PFCR), and the PA1DDR bit
settings.
Setting
Bus Controller
I/O Port
Module Name
Pin Function
BACK_OE
Byte control
SRAM
Selection
Bus controller
BACK output*
1



1


RD/WR –A output* 0
I/O port
Note:
(8)
*
(RD/WR)-A_OE PA1DDR
0
0
1

PA1 output
0
0
0
1
PA1 input
(initial setting)
0
0
0
0
Valid in external extended mode (EXPE = 1)
PA0/BREQO/BS-A
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, port function control register (PFCR), and the PA0DDR bit
settings.
Setting
I/O Port
Bus Controller
I/O Port
Module Name
Pin Function
BS-A_OE
BREQO_OE
PA0DDR
Bus controller
BS-A output*
1


BREQO output*
0
1

PA0 output
0
0
1
PA0 input
(initial setting)
0
0
0
I/O port
Note:
*
Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 641 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.7
(1)
Port B
PB7/CS7-D/SDφ*3
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, port function control register (PFCR), and PB7DDR bit settings.
Setting
Module Name
Pin Function
MCU
Operating
Mode
Bus
Controller
I/O Port
SDRAM
CS7D_OE
PB7DDR
Clock Pulse
Generator
SDφ output* *
1


Bus controller
CS7-D output*2
0
1

I/O port
PB7 output
0
0
1
PB7 input
(initial setting)
0
0
0
1
3
Notes: 1. Valid in SDRAM mode
2. Valid in external extended mode (EXPE = 1)
3. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
(2)
PB6/CS6-D/(RD/WR-B)/ADTRG0-B
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, port function control register (PFCR), and PB6DDR bit settings.
Rev. 2.00 Jul. 31, 2008 Page 642 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Setting
I/O Port
Module Name
Pin Function
Byte control
SRAM
Selection
Bus controller
RD/WR-B output*
1



0
1


I/O port
Note:
(3)
*
(RD/WR)B_OE
CS6D_OE
PB6DDR
CS6-D output*
0
0
1

PB6 output
0
0
0
1
PB6 input
(initial setting)
0
0
0
0
Valid in external extended mode (EXPE = 1)
PB5/CS5-D/OE*2/CKE*2
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, port function control register (PFCR), and PB5DDR bit.
Setting
Bus Controller
Module Name
Bus controller
Pin Function
1
2
CKE output* *
OE output* *
1
2
CS5-D output*
I/O port
1
I/O Port
CKE_OE
OE-OE
CS5D_OE
PB5DDR
1



0
1



0
0
PB5 output
0
0
1
1
PB5 input
(initial setting)
0
0
0
0
Notes: 1. Valid in external extended mode (EXPE = 1)
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 643 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(4)
PB4/CS4-B/WE*2
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, port function control register (PFCR), and PB4DDR bit settings.
Setting
Bus Controller
I/O Port
Bus Controller
WE_OE
CS4B_OE
PB4DDR
1


0
1

PB4 output
0
0
1
PB4 input
(initial setting)
0
0
0
Module Name
Pin Function
Bus controller
WE output* *
1
2
CS4-B output*
I/O port
1
Notes: 1. Valid in external extended mode (EXPE = 1)
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
(5)
PB3/CS3-A/CS7-A/CAS*2
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, port function control register (PFCR), and the PB3DDR bit settings.
Setting
Bus Controller
Module Name
Pin Function
Bus controller
CAS output* *
I/O port
I/O Port
CAS_OE
CS3A_OE
CS7A_OE
PB3DDR
1



CS3-A output*
1

1


CS7-A output*
1


1

PB3 output
0
0
0
1
PB3 input
(initial setting)
0
0
0
0
1
2
Notes: 1. Valid in external extended mode (EXPE = 1)
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 644 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(6)
PB2/CS2-A/CS6-A/RAS*2
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, port function control register (PFCR), and the PB2DDR bit
settings.
Setting
Bus Controller
Module Name
Pin Function
Bus controller
RAS output* *
I/O port
I/O Port
RAS_OE
CS2A_OE
CS6A_OE
PB3DDR
1



CS2-A output*
1
0
1


CS6-A output*
1
0
0
1

PB2 output
0
0
0
1
PB2 input
(initial setting)
0
0
0
0
1
2
Notes: 1. Valid in external extended mode (EXPE = 1)
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
(7)
PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, port function control register (PFCR), and the PB1DDR bit settings.
Setting
I/O Port
Module Name
Pin Function
CS1_OE
CS2B_OE
CS5A_OE
CS6B_OE
CS7B_OE
PB1DDR
Bus controller
CS1 output*
1





CS2-B output*

1




CS5-A output*


1



CS6-B output*



1


CS7-B output*




1

PB1 output
0
0
0
0
0
1
PB1 input
(initial setting)
0
0
0
0
0
0
I/O port
Note:
*
Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 645 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(8)
PB0/CS0/CS4-A/CS5-B
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, port function control register (PFCR), and the PB0DDR bit settings.
Setting
I/O Port
Module Name
Pin Function
CS0_OE
CS4A_OE
CS5B_OE
PB0DDR
Bus controller
CS0 output
(initial setting E)
1



CS4-A output

1


I/O port
[Legend]
Initial setting E:
Initial setting S:
CS5-B output


1

PB0 output
0
0
0
1
PB0 input
(initial setting S)
0
0
0
0
Initial setting in on-chip ROM disabled external extended mode
Initial setting in other modes
Rev. 2.00 Jul. 31, 2008 Page 646 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.8
(1)
Port C
PC5, PC4/ADTRG2
The pin function is switched as shown below according to the PCnDDR bit setting.
Setting
I/O Port
Module Name
I/O port
Pin Function
PCnDDR
PCn output
1
PCn input
(initial setting)
0
[Legend]
n:
4 to 5
(2)
PC3/LLCAS*2/DQMLL*2
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, and PC3DDR bit settings.
Setting
Bus Controller
LLCAS_OE
DQMLL_OE
PC3DDR
1


DQMLL output* *

1

PC3 output*
0
0
1
PC3 input (initial
setting)
0
0
0
Module Name
Pin Function
Bus controller
LLCAS output* *
1
1
I/O port
I/O Port
2
2
Notes: 1. Valid in external extended mode (EXPE = 1)
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 647 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(3)
PC2/LUCAS*2-/DQMLU*2
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, bus controller register, and PC2DDR bit settings.
Setting
Bus Controller
LUCAS_OE
DQMLU_OE
PC2DDR
1


DQMLU output* *

1

PC2 output
0
0
1
PC2 input (initial
setting)
0
0
0
Module Name
Pin Function
Bus controller
LUCAS output* *
1
1
I/O port
I/O Port
2
2
Notes: 1. Valid in external extended mode (EXPE = 1)
2. Supported only by the H8SX/1648G Group and H8SX/1648H Group.
(4)
PC1/CS4-C/CS5-C/CS6-C/CS7-C
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, port function control register (PFCR), and the PC1DDR bit settings.
Setting
I/O Port
Module Name
Pin Function
CS4C_OE
CS5C_OE CS6C_OE CS7C_OE
PB1DDR
Bus controller
CS4-C output*
1




CS5-C output*

1



CS6-C output*


1


CS7-C output*



1

PC1 output
0
0
0
0
1
PC1 input
(initial setting)
0
0
0
0
0
I/O port
Note:
*
Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 648 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(5)
PC0/CS3-B/WAIT-B/ADTRG1-B
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, port function control register (PFCR), and PC1DDR bit settings.
Setting
Bus Controller
I/O Port
Module Name
Pin Function
WAITE bit in BCR
CS3B_OE
PC0DDR
Bus controller
WAIT-B input*
1


CS3-B*
0
1

PC0 output
0
0
1
PC0 input
(initial setting)
0
0
0
I/O port
Note:
*
Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 649 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.9
Port D
The pin function of port D can be switched with that of port J according to the combination of
operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port D can be
switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not
change the setting of the PCJKE bit in external extended mode. For details, see section 13.3.12,
Port Function Control Register D (PFCRD).
(1)
PD7/A7, PD6/A6, PD5/A5, PD4/A4, PD3/A3, PD2/A2, PD1/A1, PD0/A0
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, and the PDnDDR bit settings.
Setting
I/O Port
Module Name
Pin Function
MCU Operating Mode
PDnDDR
Bus controller
Address output
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode

1
I/O port
PDn output
PDn input
(initial setting)
Single-chip mode*
Modes other than on-chip ROM
disabled extended mode
1
0
[Legend]
n:
0 to 7
Note: * Address output is enabled by setting PDnDDR = 1 in external extended mode
(EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 650 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.10 Port E
The pin function of port E can be switched with that of port K according to the combination of
operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port E can be
switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not
change the setting of the PCJKE bit in external extended mode. For detail, see section 13.3.12,
Port Function Control Register D (PFCRD).
(1)
PE7/A15, PE6/A14, PE5/A13, PE4/A12, PE3/A11, PE2/A10, PE1/A9, PE0/A8
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, and the PEnDDR bit settings.
Setting
I/O Port
Module Name
Pin Function
MCU Operating Mode
PEnDDR
Bus controller
Address output
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode

1
I/O port
PEn output
PEn input
(initial setting)
Single-chip mode*
Modes other than on-chip ROM
disabled extended mode
1
0
[Legend]
n:
0 to 7
Note: * Address output is enabled by setting PDnDDR = 1 in external extended mode
(EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 651 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.11 Port F
(1)
PF7/A23/SCK5
The pin function is switched as shown below according to the combination of SCI register,
operating mode, EXPE bit, port function control register (PFCR), and PF7DDR bit settings.
Setting
SCI
I/O Port
Module Name
Pin Function
SCK5_OE
A23_OE
PF7DDR
SCI
SCK5 output
1


Bus controller
A23 output*
0
1

PF7 output
0
0
1
PF7 input
(initial setting)
0
0
0
I/O port
Note:
(2)
*
Valid in external extended mode (EXPE = 1)
PF6/A22/RxD5/IrRXD
The pin function is switched as shown below according to the combination of operating mode,
EXPE bit, port function control register (PFCR), and PF6DDR bit settings.
Setting
I/O Port
I/O Port
PF6DDR
Module Name
Pin Function
A22_OE
Bus controller
A22 output*
1

I/O port
PF6 output
0
1
PF6 input
(initial setting)
0
0
Note:
*
Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 652 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(3)
PF5/A21/TxD5/IrTXD
The pin function is switched as shown below according to the combination of SCI and IrDA
registers, operating mode, EXPE bit, port function control register (PFCR), and PF5DDR bit
settings.
Setting
SCI
IrDA
I/O port
Module Name
Pin Function
TxD5_OE
IrTXD_OE
A21_OE
PF5DDR
SCI
TxD5 output
1



IrDA
IrTXD output
0
1


Bus controller
A21 output*
0
0
1

I/O port
PF5 output
0
0
0
1
PF5 input
(initial setting)
0
0
0
0
Note:
(4)
*
Valid in external extended mode (EXPE = 1)
PF4/A20
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, port function control register (PFCR), and the PF4DDR bit settings.
Setting
MCU
Operating Mode
I/O Port
Module Name
Pin Function
A20_OE
PF4DDR
On-chip ROM
disabled extended
mode
Bus controller
A20 output


Modes other than
on-chip ROM
disabled extended
mode
Bus controller
A20 output*
1

I/O port
PF4 output
0
1
PF4 input
(initial setting)
0
0
Note:
*
Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 653 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(5)
PF3/A19
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, port function control register (PFCR), and the PF3DDR bit settings.
Setting
MCU
Operating Mode
I/O Port
Module Name
Pin Function
A19_OE
PF3DDR
On-chip ROM
disabled extended
mode
Bus controller
A19 output


Modes other than
on-chip ROM
disabled extended
mode
Bus controller
A19 output*
1

I/O port
PF3 output
0
1
PF3 input
(initial setting)
0
0
Note:
(6)
*
Valid in external extended mode (EXPE = 1)
PF2/A18
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, port function control register (PFCR), and the PF2DDR bit settings.
Setting
MCU
Operating Mode
I/O Port
Module Name
Pin Function
A18_OE
PF2DDR
On-chip ROM
disabled extended
mode
Bus controller
A18 output


Modes other than
on-chip ROM
disabled extended
mode
Bus controller
A18 output*
1

I/O port
PF2 output
0
1
PF2 input
(initial setting)
0
0
Note:
*
Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 654 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(7)
PF1/A17
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, port function control register (PFCR), and the PF1DDR bit settings.
Setting
MCU
Operating Mode
I/O Port
Module Name
Pin Function
A17_OE
PF1DDR
On-chip ROM
disabled extended
mode
Bus controller
A17 output


Modes other than
on-chip ROM
disabled extended
mode
Bus controller
A17 output*
1

I/O port
PF1 output
0
1
PF1 input
(initial setting)
0
0
Note:
(8)
*
Valid in external extended mode (EXPE = 1)
PF0/A16
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, port function control register (PFCR), and the PF0DDR bit settings.
Setting
MCU
Operating Mode
I/O Port
Module Name
Pin Function
A16_OE
PF0DDR
On-chip ROM
disabled extended
mode
Bus controller
A16 output


Modes other than
on-chip ROM
disabled extended
mode
Bus controller
A16 output*
1

I/O port
PF0 output
0
1
PF0 input
(initial setting)
0
0
Note:
*
Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 655 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.12 Port H
(1)
PH7/D7, PH6/D6, PH5/D5, PH4/D4, PH3/D3, PH2/D2, PH1/D1, PH0/D0
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, and the PHnDDR bit settings.
Setting
MCU Operating Mode
I/O Port
Module Name
Pin Function
EXPE
PHnDDR
Bus controller
Data I/O*
(initial setting E)
1

I/O port
PHn output
0
1
PHn input
(initial setting S)
0
0
[Legend]
Initial setting E: Initial setting in external extended mode
Initial setting S: Initial setting in single-chip mode
n:
0 to 7
Note: * Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 656 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.13 Port I
(1)
PI7/D15, PI6/D14, PI5/D13, PI4/D12, PI3/D11, PI2/D10, PI1/D9, PI0/D8
The pin function is switched as shown below according to the combination of operating mode, bus
mode, the EXPE bit, and the PInDDR bit settings.
Setting
Bus Controller
I/O Port
Module Name
Pin Function
16-Bit Bus Mode
PInDDR
Bus controller
Data I/O*
(initial setting E)
PIn output
PIn input
(initial setting S)
1

0
0
1
0
I/O port
[Legend]
Initial setting E: Initial setting in external extended mode
Initial setting S: Initial setting in single-chip mode
n:
0 to 7
Note: * Valid in external extended mode (EXPE = 1)
Rev. 2.00 Jul. 31, 2008 Page 657 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.14 Port J
The pin function of port J can be switched with that of port D according to the combination of
operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port J can be
switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not
change the setting of the PCJKE bit in external extended mode. For detail, see section 13.3.12,
Port Function Control Register D (PFCRD).
(1)
PJ7/TIOCA8/TIOCB8/TCLKH/PO23
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and PJ7DDR bit settings.
Setting
PPG
TPU
I/O Port
PO23_OE
TIOCB8_OE
PD7DDR
Module Name
Pin Function
PPG
PO23 output*
1


TPU
TIOCB8 output*
0
1

I/O port
PJ7 output*
0
0
1
PJ7 input*
0
0
0
Note:
(2)
*
Valid when PCJKE = 1
PJ6/TIOCA8/PO22
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PJ6DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO22_OE
TIOCA8_OE
PJ6DDR
PPG
PO22 output*
1


TPU
TIOCA8 output*
0
1

I/O port
PJ6 output*
0
0
1
PJ6 input*
0
0
0
Note:
*
Valid when PCJKE = 1
Rev. 2.00 Jul. 31, 2008 Page 658 of 1438
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Section 13 I/O Ports
(3)
PJ5/TIOCA7/TIOCB7/TCLKG/PO21
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PJ5DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO21_OE
TIOCB7_OE
PJ5DDR
PPG
PO21 output*
1


TPU
TIOCB7 output*
0
1

I/O port
PJ5 output*
0
0
1
PJ5 input*
0
0
0
Note:
(4)
*
Valid when PCJKE = 1
PJ4/TIOCA7/PO20
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PJ4DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO20_OE
TIOCA7_OE
PJ4DDR
PPG
PO20 output*
1


TPU
TIOCA7 output*
0
1

I/O port
PJ4 output*
0
0
1
PJ4 input*
0
0
0
Note:
*
Valid when PCJKE = 1
Rev. 2.00 Jul. 31, 2008 Page 659 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(5)
PJ3/PO19/TIOCC6/TIOCD6/TCLKF
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PJ3DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO19_OE
TIOCD6_OE
PJ3DDR
PPG
PO19 output*
1


TPU
TIOCD6 output*
0
1

I/O port
PJ3 output*
0
0
1
PJ3 input*
0
0
0
Note:
(6)
*
Valid when PCJKE = 1
PJ2/PO18/TIOCC6/TCLKE
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PJ2DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO18_OE
TIOCC6_OE
PJ2DDR
PPG
PO18 output*
1


TPU
TIOCC6 output*
0
1

I/O port
PJ2 output*
0
0
1
PJ2 input*
0
0
0
Note:
*
Valid when PCJKE = 1
Rev. 2.00 Jul. 31, 2008 Page 660 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(7)
PJ1/PO17/TIOCA6/TIOCB6
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PJ1DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO17_OE
TIOCB6_OE
PJ1DDR
PPG
PO17 output*
1


TPU
TIOCB6 output*
0
1

I/O port
PJ1 output*
0
0
1
PJ1 input*
0
0
0
Note:
(8)
*
Valid when PCJKE = 1
PJ0/PO16/TIOCA6
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PJ0DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO16_OE
TIOCA6_OE
PJ0DDR
PPG
PO16 output*
1


TPU
TIOCA6 output*
0
1

I/O port
PJ0 output*
0
0
1
PJ0 input*
0
0
0
Note:
*
Valid when PCJKE = 1
Rev. 2.00 Jul. 31, 2008 Page 661 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.15 Port K
The pin function of port K can be switched with that of port E according to the combination of
operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port K can be
switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not
change the setting of the PCJKE bit in external extended mode. For detail, see section 13.3.12,
Port Function Control Register D (PFCRD).
(1)
PK7/PO31/TIOCA11/TIOCB11
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PK7DDR bit settings.
Setting
PPG
TPU
I/O Port
PO31_OE
TIOCB11_OE
PK7DDR
Module Name
Pin Function
PPG
PO31 output*
1


TPU
TIOCB11 output*
0
1

I/O port
PK7 output*
0
0
1
PK7 input*
0
0
0
Note:
(2)
*
Valid when PCJKE = 1
PK6/PO30/TIOCA11
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PK6DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO30_OE
TIOCA11_OE
PK6DDR
PPG
PO30 output*
1


TPU
TIOCA11 output*
0
1

I/O port
PK6 output*
0
0
1
PK6 input*
0
0
0
Note:
*
Valid when PCJKE = 1
Rev. 2.00 Jul. 31, 2008 Page 662 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(3)
PK5/PO29/TIOCA10/TIOCB10
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PK5DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO29_OE
TIOCB10_OE
PK5DDR
PPG
PO29 output*
1


TPU
TIOCB10 output*
0
1

I/O port
PK5 output*
0
0
1
PK5 input*
0
0
0
Note:
(4)
*
Valid when PCJKE = 1
PK4/PO28/TIOCA10
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PK4DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO28_OE
TIOCA10_OE
PK4DDR
PPG
PO28 output*
1


TPU
TIOCA10 output*
0
1

I/O port
PK4 output*
0
0
1
PK4 input*
0
0
0
Note:
*
Valid when PCJKE = 1
Rev. 2.00 Jul. 31, 2008 Page 663 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(5)
PK3/PO27/TIOCC9/TIOCD9
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PK3DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO27_OE
TIOCD9_OE
PK3DDR
PPG
PO27 output*
1


TPU
TIOCD9 output*
0
1

I/O port
PK3 output*
0
0
1
PK3 input*
0
0
0
Note:
(6)
*
Valid when PCJKE = 1
PK2/PO26/TIOCC9
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PK2DDR bit settings.
Setting
PPG
TPU
I/O Port
PO26_OE
TIOCC9_OE
PK2DDR
Module Name
Pin Function
PPG
PO26 output*
1


TPU
TIOCC9 output*
0
1

I/O port
PK2 output*
0
0
1
PK2 input*
0
0
0
Note:
*
Valid when PCJKE = 1
Rev. 2.00 Jul. 31, 2008 Page 664 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(7)
PK1/PO25/TIOCA9/TIOCB9
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PK1DDR bit settings.
Setting
PPG
TPU
I/O Port
Module Name
Pin Function
PO25_OE
TIOCB9_OE
PK1DDR
PPG
PO25 output*
1


TPU
TIOCB9 output*
0
1

I/O port
PK1 output*
0
0
1
PK1 input*
0
0
0
Note:
(8)
*
Valid when PCJKE = 1
PK0/PO24/TIOCA9
The pin function is switched as shown below according to the combination of the PPG register,
TPU register, port function control register (PFCR), and the PK0DDR bit settings.
Setting
PPG
TPU
I/O Port
PO24_OE
TIOCA9_OE
PK0DDR
Module Name
Pin Function
PPG
PO24 output*
1


TPU
TIOCA9 output*
0
1

I/O port
PK0 output*
0
0
1
PK0 input*
0
0
0
Note:
*
Valid when PCJKE = 1
Rev. 2.00 Jul. 31, 2008 Page 665 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.2.16 Port M*
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
(1) PM4
The pin function is switched as shown below according to the PM4DDR bit setting.
Setting
I/O Port
Module Name
I/O port
(2)
Pin Function
PM4DDR
PM4 output
1
PM4 input
(initial setting)
0
PM3
The pin function is switched as shown below according to the PM3DDR bit setting.
Setting
I/O Port
PM3DDR
Module Name
Pin Function
I/O port
PM3 output
1
PM3 input
(initial setting)
0
(3)
PM2
The pin function is switched as shown below according to the PM2DDR bit setting.
Setting
I/O Port
PM2DDR
Module Name
Pin Function
I/O port
PM2 output
1
PM2 input
(initial setting)
0
Rev. 2.00 Jul. 31, 2008 Page 666 of 1438
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Section 13 I/O Ports
(4)
PM1
The pin function is switched as shown below according to the PM1DDR bit setting.
Setting
I/O Port
PM1DDR
Module Name
Pin Function
I/O port
PM1 output
1
PM1 input
(initial setting)
0
(5)
PM0
The pin function is switched as shown below according to the PM0DDR bit setting.
Setting
I/O Port
PM0DDR
Module Name
Pin Function
I/O port
PM0 output
1
PM0 input
(initial setting)
0
13.2.17 Port N
(1)
PN3/SCL3
The pin function is switched as shown below according to the combination of the IIC2 register
setting and the PN3DDR bit setting.
Setting
IIC2
I/O Port
Module Name
Pin Function
SCL3_OE
PN3DDR
IIC2
SCL3 I/O
1

I/O port
PN3 output
0
(open-drain output)
1
PN3 input
(initial setting)
0
0
Rev. 2.00 Jul. 31, 2008 Page 667 of 1438
REJ09B0365-0200
Section 13 I/O Ports
(2)
PN2/SDA3
The pin function is switched as shown below according to the combination of the IIC2 register
setting and the PN2DDR bit setting.
Setting
IIC2
I/O Port
Module Name
Pin Function
SDA3_OE
PN2DDR
IIC2
SDA3 I/O
1

I/O port
PN2 output
0
(open-drain output)
1
PN2 input
(initial setting)
0
(3)
0
PN1/SCL2
The pin function is switched as shown below according to the combination of the IIC2 register
setting and the PN1DDR bit setting.
Setting
IIC2
I/O Port
Module Name
Pin Function
SCL2_OE
PN1DDR
IIC2
SCL2 I/O
1

I/O port
PN1 output
0
(open-drain output)
1
PN1 input
(initial setting)
0
Rev. 2.00 Jul. 31, 2008 Page 668 of 1438
REJ09B0365-0200
0
Section 13 I/O Ports
(4)
PN0/SDA2
The pin function is switched as shown below according to the combination of the IIC2 register
setting and the PN0DDR bit setting.
Setting
IIC2
I/O Port
Module Name
Pin Function
SDA2_OE
PN0DDR
IIC2
SDA2 I/O
1

I/O port
PN0 output
(open drain output)
0
1
PN0 input
(initial setting)
0
0
Rev. 2.00 Jul. 31, 2008 Page 669 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Table 13.5 Available Output Signals and Settings in Each Port
Output
Specification
Signal Name
Port
P1
7
5
4
Signal Selection Register
Settings
Peripheral Module Settings
EDRAK1A_OE* EDRAK1* PFCR8.EDMAS1[A,B] = 00 SYSCR.EXPE=1, EDMDR_1.EDRAKE=1
SCL0_OE
6
Output
Signal
Name
SCL0
ICCRA.ICE = 1
EDACK1A_OE* EDACK1* PFCR8.EDMAS1[A,B] = 00 SYSCR.EXPE=1, EDACR_1.AMS=1,
EDMDR_1.EDACKE=1
DACK1A_OE
DACK1
SCK3_OE
SCK3
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE[1,0] = 01 or
while SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1 while
SMR.C/A = 0, SCR.CKE[1,0] = 01 or
while SMR.C/A = 1, SCR.CKE1 = 0
SDA0_OE
SDA0
ICCRA.ICE = 1
ETEND1A_OE*
ETEND1* PFCR8.EDMAS1[A,B] = 00 SYSCR.EXPE=1, EDMDR_1.ETENDE =
1
TEND1A_OE
TEND1
PFCR7.DMAS1[A,B] = 00
PFCR7.DMAS1[A,B] = 00
DMAC.DACR_1.AMS = 1,
DMDR_1.DACKE = 1
DMDR_1.TENDE = 1
SCL1_OE
SCL1
ICCRA.ICE = 1
TxD3_OE
TxD3
SCR.TE = 1
SDA1_OE
SDA1
ICCRA.ICE = 1
3
EDRAK0A_OE* EDRAK0* PFCR8.EDMAS0[A,B] = 00 SYSCR.EXPE=1, EDMDR_0.EDRAKE =
1
2
EDACK0A_OE* EDACK0* PFCR8.EDMAS0[A,B] = 00 SYSCR.EXPE=1, EDACR_0.AMS = 1,
EDMDR_0.EDACKE=1
DACK0A_OE
DACK0
PFCR7.DMAS0[A,B] = 00
Rev. 2.00 Jul. 31, 2008 Page 670 of 1438
REJ09B0365-0200
DMAC_0.DACR.AMS = 1,
DMDR_0.DACKE = 1
Section 13 I/O Ports
Output
Specification
Signal Name
Output
Signal
Name
2
SCK2_OE
SCK2
1
ETEND0A_OE*
ETEND0
PFCR8.EDMAS0[A,B] = 00 SYSCR.EXPE=1, EDMDR_0.TENDE = 1
TEND0A_OE
TEND0
PFCR7.DMAS0[A,B] = 00
0
TxD2_OE
TxD2
SCR.TE = 1
7
TIOCB5_OE
TIOCB5
TPU.TIOR_5.IOB3 = 0,
TPU.TIOR_5.IOB[1,0] = 01/10/11
PO7_OE
PO7
NDERL.NDER7 = 1
TIOCA5_OE
TIOCA5
TPU.TIOR_5.IOA3 = 0,
TPU.TIOR_5.IOA [1,0] = 01/10/11
TMO1_OE
TMO1
TMR.TCSR_1,.OS3,2 = 01/10/11 or
TMR.TCSR_1, OS[1,0] = 01/10/11
TxD1_OE
TxD1
SCR.TE = 1
PO6_OE
PO6
NDERL.NDER6 = 1
TIOCA4_OE
TIOCA4
TPU.TIOR_4.IOA3 = 0,
TPU.TIOR_4.IOA[1,0] = 01/10/11
PO5_OE
PO5
NDERL.NDER5 = 1
TIOCB4_OE
TIOCB4
TPU.TIOR_4.IOB3 = 0,
TPU.TIOR_4.IOB[1,0] = 01/10/11
SCK1_OE
SCK1
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE [1, 0] = 01 or
while SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1 while
SMR.C/A = 0, SCR.CKE [1, 0] = 01 or
while SMR.C/A = 1, SCR.CKE 1 = 0
PO4_OE
PO4
NDERL.NDER4 = 1
Port
P1
P2
6
5
4
Signal Selection Register
Settings
Peripheral Module Settings
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE[1, 0] = 01 or
while SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1 while
SMR.C/A = 0, SCR.CKE[1, 0] = 01 or
while SMR.C/A = 1, SCR.CKE1 = 0
DMDR_0.TENDE= 1
Rev. 2.00 Jul. 31, 2008 Page 671 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Port
P2
3
2
1
0
P3
7
6
Output
Specification
Signal Name
Output
Signal
Name
TIOCD3_OE
TIOCD3
TPU.TMDR.BFB = 0,
TPU.TIORL_3.IOD3 = 0,
TPU.TIORL_3.IOD[1,0] = 01/10/11
PO3_OE
PO3
NDERL.NDER3 = 1
TIOCC3_OE
TIOCC3
TPU.TMDR.BFA = 0,
TPU.TIORL_3.IOC3 = 0,
TPU.TIORL_3.IOD[1,0] = 01/10/11
TMO0_OE
TMO0
TMR.TCSR_0.OS[3,2] = 01/10/11 or
TMR.TCSR_0.OS[1,0] = 01/10/11
TxD0_OE
TxD0
SCR.TE = 1
PO2_OE
PO2
NDERL.NDER2 = 1
TIOCA3_OE
TIOCA3
TPU.TIORH_3.IOA3 = 0,
TPU.TIORH_3.IOA[1,0] = 01/10/11
PO1_OE
PO1
NDERL.NDER1 = 1
TIOCB3_OE
TIOCB3
TPU.TIORH_3.IOB3 = 0,
TPU.TIORH_3.IOB[1,0] = 01/10/11
SCK0_OE
SCK0
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE [1, 0] = 01 or
while SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1 while
SMR.C/A = 0, SCR.CKE [1, 0] = 01 or
while SMR.C/A = 1, SCR.CKE 1 = 0
PO0_OE
PO0
NDERL.NDER0 = 1
EDRAK3_OE*
EDRAK3* PFCR8.EDMAS3[A,B]=
00
SYSCR.EXPE=1, EDMDR_3, EDRAKE=1
TIOCB2_OE
TIOCB2
TPU.TIOR_2.IOB3 = 0,
TPU.TIOR_2.IOB[1,0] = 01/10/11
PO15_OE
PO15
NDERH.NDER15 = 1
EDRAK2_OE*
EDRAK2* PFCR8.EDMAS2[A,B]=
00
SYSCR.EXPE=1, EDMDR_2, EDRAKE=1
TIOCA2_OE
TIOCA2
TPU.TIOR_2.IOA3 = 0,
TPU.TIOR_2.IOA[1,0] = 01/10/11
PO14_OE
PO14
NDERH.NDER14 = 1
Signal Selection Register
Settings
Peripheral Module Settings
Rev. 2.00 Jul. 31, 2008 Page 672 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Port
P3
5
4
3
2
1
0
Output
Specification
Signal Name
Output
Signal
Name
EDACK3_OE
EDACK3* PFCR8.EDMAS3[A,B]=
00
SYSCR.EXPE=1, EDACR_3.AMS=1,
EDMDR_3.EDACKE=1
DACK1B_OE
DACK1
DMAC.DACR_1.AMS = 1,
DMDR_1.DACKE = 1
TIOCB1_OE
TIOCB1
TPU.TIOR_1.IOB3 = 0,
TPU.TIOR_1.IOB[1,0] = 01/10/11
PO13_OE
PO13
NDERH.NDER13 = 1
Signal Selection Register
Settings
Peripheral Module Settings
PFCR7.DMAS1[A,B] = 01
ETEND3_OE*
ETEND3* PFCR8.EDMAS3[A,B] = 00 SYSCR.EXPE=1, EDMDR_3.ETEND=1
TEND1B_OE
TEND1
TIOCA1_OE
TIOCA1
TPU.TIOR_1.IOA3 = 0,
TPU.TIOR_1.IOA[1,0] = 01/10/11
PO12_OE
PO12
NDERH.NDER12 = 1
TIOCD0_OE
TIOCD0
TPU.TMDR.BFB = 0,
TPU.TIORL_0.IOD3 = 0,
TPU.TIORL_0.IOD[1,0] = 01/10/11
PO11_OE
PO11
NDERH.NDER11 = 1
EDACK2_OE*
EDACK2* PFCR8.EDMAS2[A,B] = 00 SYSCR.EXPE=1, EDACR_2.AMS=1,
EDMDR_2.EDACKE=1
DACK0B_OE
DACK0
TIOCC0_OE
TIOCC0
TPU.TMDR.BFA = 0,
TPU.TIORL_0.IOC3 = 0,
TPU.TIORL_0.IOD[1,0] = 01/10/11
PO10_OE
PO10
NDERH.NDER10 = 1
ETEND2_OE*
ETEND2* PFCR8.EDMAS2[A,B] = 00 SYSCR.EXPE=1, EDMDR_2.ETENDE=1
TEND0B_OE
TEND0
TIOCB0_OE
TIOCB0
TPU.TIORH_0.IOB3 = 0,
TPU.TIORH_0.IOB[1,0] = 01/10/11
PO9_OE
PO9
NDERH.NDER9 = 1
TIOCA0_OE
TIOCA0
TPU.TIORH_0.IOA3 = 0,
TPU.TIOH_0.IOA[1,0] = 01/10/11
PO8_OE
PO8
NDERH.NDER8 = 1
PFCR7.DMAS1[A,B] = 01
PFCR7.DMAS0[A,B] = 01
PFCR7.DMAS0[A,B] = 01
DMDR_1.TENDE = 1
DMAC.DACR_0.AMS = 1,
DMDR_0.DACKE = 1
DMDR_0.TENDE = 1
Rev. 2.00 Jul. 31, 2008 Page 673 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Output
Specification
Signal Name
Port
P6
Output
Signal
Name
Signal Selection Register
Settings
Peripheral Module Settings
7
EDRAK1B_OE* EDRAK1* PFCR8.EDMAS1[A,B] = 01 SYSCR.EXPE=1, EDMDR_1.EDRAKE=1
6
EDRAK0B_OE* EDRAK0* PFCR8.EDMAS0[A,B] = 01 SYSCR.EXPE=1, EDMDR_0.EDRAKE=1
5
EDACK1B_OE* EDACK1* PFCR8.EDMAS1[A,B] = 00 SYSCR.EXPE=1, EDACR_1.AMS=1,
EDMDR_1.EDACKE=1
DACK3_OE
DACK3
TMO3_OE
TMO3
TMR.TCSR_3.OS[3,2] = 01/10/11 or
TMR.TCSR_3.OS[1,0] = 01/10/11
SCK6_OE
SCK6
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE[1,0] = 01 or
while SMR.GM = 1
When SCMR.SMIF = 0: SCR.TE = 1 or
SCR.RE = 1 while SMR.C/A = 0,
SCR.CKE[1,0] = 01 or while SMR.C/A =
1, SCR.CKE1 = 0
ETEND1B_OE*
ETEND1* PFCR8.EDMAS1[A,B] = 01 SYSCR.EXPE=1, EDMDR_1.ETENDE=1
TEND3_OE
TEND3
3
TxD6_OE
TxD6
2
EDACK0B_OE* EDACK0* PFCR8.EDMAS0[A,B] = 01 SYSCR.EXPE=1, EDACR_0.AMS=1,
EDMDR_0.EDACKE=1
4
1
0
PFCR7.DMAS3[A,B] = 01
PFCR7.DMAS3[A,B] = 01
DMAC.DACR_3.AMS = 1,
DMDR_3.DACKE = 1
DMDR_3.TENDE = 1
SCR.TE = 1
DACK2_OE
DACK2
TMO2_OE
TMO2
TMR.TCSR_2.OS[3,2] = 01/10/11 or
TMR.TCSR_2.OS[1,0] = 01/10/11
SCK4_OE
SCK4
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE [1,0] = 01 or
while SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1 while
SMR.C/A = 0, SCR.CKE [1,0] = 01 or
while SMR.C/A = 1, SCR.CKE 1 = 0
ETEND0B_OE*
ETEND0* PFCR8.EDMAS0[A,B] = 01 SYSCR.EXPE=1, EDMDR_0.ETENDE=1
TEND2_OE
TEND2
TxD4_OE
TxD4
PFCR7.DMAS2[A,B] = 01
PFCR7.DMAS2[A,B] = 01
Rev. 2.00 Jul. 31, 2008 Page 674 of 1438
REJ09B0365-0200
DMAC.DACR_2.AMS = 1,
DMDR_2.DACKE = 1
DMDR_2.TENDE = 1
SCR.TE = 1
Section 13 I/O Ports
Output
Specification
Signal Name
Output
Signal
Name
7
Bφ_OE
Bφ
PADDR.PA7DDR = 1, SCKCR.PSTOP1 =
0
6
AH_OE
AH
SYSCR.EXPE = 1,
MPXCR.MPXEn (n = 7 to 3) = 1
BS-B_OE
BS
AS_OE
AS
SYSCR.EXPE = 1, PFCR2.ASOE = 1
5
RD_OE
RD
SYSCR.EXPE = 1
4
LUB_OE
LUB
SYSCR.EXPE = 1, PFCR6.LHWROE = 1
or SRAMCR.BCSELn = 1
LHWR_OE
LHWR
SYSCR.EXPE = 1, PFCR6.LHWROE = 1
LLB_OE
LLB
SYSCR.EXPE = 1, SRAMCR.BCSELn =
1
LLWR_OE
LLWR
SYSCR.EXPE = 1


Port
PA
3
2
1
0
PB
7
6
5
4
Signal Selection Register
Settings
Peripheral Module Settings
PFCR2.BSS = 0

SYSCR.EXPE = 1, PFCR2.BSE = 1

BACK_OE
BACK
(RD/WR)-A_OE
RD/WR
PFCR2.RDWRS = 0
SYSCR.EXPE = 1, PFCR2.RDWRE = 1
or SRAMCR.BCSELn = 1
BS-A_OE
BS
PFCR2.BSS = 0
SYSCR.EXPE = 1, PFCR2.BSE = 1
BREQO_OE
BREQO
SYSCR.EXPE = 1,BCR1.BRLE = 1
SYSCR.EXPE = 1, BCR1.BRLE = 1,
BCR1.BREQOE = 1
SDφ_OE*
SDφ*
CS7D_OE
CS7
PFCR1.CS7S[A,B] = 11
SYSCR.EXPE = 1, PFCR.CS7E = 1
(RD/WR)-B_OE
RD/WR
PFCR2.RDWRS = 1
SYSCR.EXPE = 1, PFCR2.RDWRE = 1,
or SRAMCR.BCSELn = 1
CS6D_OE
CS6
PFCR1.CS6S[A,B] = 11
SYSCR.EXPE = 1, PFCR0.CS6E = 1
CKE_OE*
CKE*
SYSCR.EXPE = 1, DRAMCR.DRAME=1.
DRAMCR.ETYPE=1, DRAMCR.OEE=1
OE_OE*
OE*
SYSCR.EXPE = 1, DRAMCR.DRAME=1.
DRAMCR.DTYPE=0, DRAMCR.OEE=1
CS5D_OE
CS5
WE_OE*
WE*
CS4B_OE
CS4
MD3 = 1
PFCR1.CS5S[A,B] = 11
SYSCR.EXPE = 1, PFCR0.CS5E = 1
SYSCR.EXPE=1,DRAMCR.DRAME=1
PFCR1.CS4S[A,B] = 01
SYSCR.EXPE = 1, PFCR0.CS4E = 1
Rev. 2.00 Jul. 31, 2008 Page 675 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Port
PB
3
2
1
0
PC
3
Output
Specification
Signal Name
Output
Signal
Name
CAS_OE*
CAS*
CS3A_OE
CS3
PFCR2.CS3S = 0
SYSCR.EXPE = 1, PFCR0.CS3E = 1
CS7A_OE
CS7
PFCR1.CS7S[A,B] = 00
SYSCR.EXPE = 1, PFCR0.CS7E = 1
RAS_OE*
RAS*
CS2A_OE
CS2
PFCR2.CS2S = 0
SYSCR.EXPE = 1, PFCR0.CS2E = 1
CS6A_OE
CS6
PFCR1.CS6S[A,B] = 00
SYSCR.EXPE = 1, PFCR0.CS6E = 1
CS1_OE
CS1
CS2B_OE
CS2
PFCR2.CS2S = 1
SYSCR.EXPE = 1, PFCR0.CS2E = 1
CS5A_OE
CS5
PFCR1.CS5S[A,B] = 00
SYSCR.EXPE = 1, PFCR0.CS5E = 1
CS6B_OE
CS6
PFCR1.CS6S[A,B] = 01
SYSCR.EXPE = 1, PFCR0.CS6E = 1
CS7B_OE
CS7
PFCR1.CS7S[A,B] = 01
SYSCR.EXPE = 1, PFCR0.CS7E = 1
CS0_OE
CS0
CS4A_OE
CS4
PFCR1.CS4S[A,B] = 00
SYSCR.EXPE = 1, PFCR0.CS4E = 1
CS5B_OE
CS5
PFCR1.CS5S[A,B] = 01
SYSCR.EXPE = 1, PFCR0.CS5E = 1
LLCAS_OE*
LLCAS
DQMLL_OE*
DQMLL
SYSCR.EXPE = 1, DRAMCR.DRAME = 1
DRAMCR.DTYPE = 1
LUCAS_OE*
LUCAS
SYSCR.EXPE=1,ABWCR.[ABWH2,
ABWL2]=x0/01,DRAMCR.DRAME=1,
DRAMCR.DTYPE=0
DQMLU_OE*
DQMLU
SYSCR.EXPE=1,ABWCR.[ABWH2,
ABWL2]=x0/01,DRAMCR.DRAME=1,
DRAMCR.DTYPE=1
CS4C_OE
CS4
PFCR1.CS4S[A,B] = 10
SYSCR.EXPE = 1, PFCR0.CS4E = 1
CS5C_OE
CS5
PFCR1.CS5S[A,B] = 10
SYSCR.EXPE = 1, PFCR0.CS5E = 1
CS6C_OE
CS6
PFCR1.CS6S[A,B] = 10
SYSCR.EXPE = 1, PFCR0.CS6E = 1
CS7C_OE
CS7
PFCR1.CS7S[A,B] = 10
SYSCR.EXPE = 1, PFCR0.CS7E = 1
CS3B_OE
CS3
PFCR2.CS3S = 1
SYSCR.EXPE = 1, PFCR0.CS3E = 1
Signal Selection Register
Settings
Peripheral Module Settings
SYSCR.EXPE=1,DRAMCR.DRAME=1,
DRAMCR.DTYPE=1
SYSCR.EXPE = 1, DRAMCR.DRAME = 1
SYSCR.EXPE = 1, PFCR0.CS1E = 1
SYSCR.EXPE = 1, PFCR0.CS0E = 1
SYSCR.EXPE = 1, DRAMCR.DRAME = 1
DRAMCR.DTYPE = 0
2
1
0
Rev. 2.00 Jul. 31, 2008 Page 676 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Output
Specification
Signal Name
Output
Signal
Name
7
A7_OE
A7
SYSCR.EXPE = 1, PDDDR.PD7DDR = 1
6
A6_OE
A6
SYSCR.EXPE = 1, PDDDR.PD6DDR = 1
5
A5_OE
A5
SYSCR.EXPE = 1, PDDDR.PD5DDR = 1
4
A4_OE
A4
SYSCR.EXPE = 1, PDDDR.PD4DDR = 1
3
A3_OE
A3
SYSCR.EXPE = 1, PDDDR.PD3DDR = 1
2
A2_OE
A2
SYSCR.EXPE = 1, PDDDR.PD2DDR = 1
1
A1_OE
A1
SYSCR.EXPE = 1, PDDDR.PD1DDR = 1
0
A0_OE
A0
SYSCR.EXPE = 1, PDDDR.PD0DDR = 1
7
A15_OE
A15
SYSCR.EXPE = 1, PEDDR.PE7DDR = 1
6
A14_OE
A14
SYSCR.EXPE = 1, PEDDR.PE6DDR = 1
5
A13_OE
A13
SYSCR.EXPE = 1, PEDDR.PE5DDR = 1
4
A12_OE
A12
SYSCR.EXPE = 1, PEDDR.PE4DDR = 1
3
A11_OE
A11
SYSCR.EXPE = 1, PEDDR.PE3DDR = 1
2
A10_OE
A10
SYSCR.EXPE = 1, PEDDR.PE2DDR = 1
1
A9_OE
A9
SYSCR.EXPE = 1, PEDDR.PE1DDR = 1
0
A8_OE
A8
SYSCR.EXPE = 1, PEDDR.PE0DDR = 1
7
A23A_OE
A23
SYSCR.EXPE = 1, PFCR4.A23E = 1
SCK5_OE
SCK5
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE[1,0] = 01or while
SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1 while
SMR.C/A = 0, SCR.CKE[1,0] = 01 or
while SMR.C/A = 1, SCR.CKE1 = 0
6
A22A_OE
A22
SYSCR.EXPE = 1, PFCR4.A22E = 1
5
A21A_OE
A21
SYSCR.EXPE = 1, PFCR4.A21E = 1
Port
PD
PE
PF
Signal Selection Register
Settings
Peripheral Module Settings
TxD5_OE
TxD5
SCR.TE = 1
IrTxD_OE
IrTxD
SCR.TE = 1, IrCR.IrE = 1
4
A20_OE
A20
SYSCR.EXPE = 1, PFCR4.A20E = 1
3
A19_OE
A19
SYSCR.EXPE = 1, PFCR4.A19E = 1
2
A18_OE
A18
SYSCR.EXPE = 1, PFCR4.A18E = 1
1
A17_OE
A17
SYSCR.EXPE = 1, PFCR4.A17E = 1
Rev. 2.00 Jul. 31, 2008 Page 677 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Output
Specification
Signal Name
Port
Output
Signal
Name
Signal Selection Register
Settings
Peripheral Module Settings
PF
0
A16_OE
A16
SYSCR.EXPE = 1, PFCR4.A16E = 1
PH
7
D7_E
D7
SYSCR.EXPE = 1
6
D6_E
D6
SYSCR.EXPE = 1
5
D5_E
D5
SYSCR.EXPE = 1
4
D4_E
D4
SYSCR.EXPE = 1
3
D3_E
D3
SYSCR.EXPE = 1
2
D2_E
D2
SYSCR.EXPE = 1
1
D1_E
D1
SYSCR.EXPE = 1
PI
PJ
0
D0_E
D0
SYSCR.EXPE = 1
7
D15_E
D15
SYSCR.EXPE = 1, ABWCR.ABW[H,L]n =
01
6
D14_E
D14
SYSCR.EXPE = 1, ABWCR.ABW[H,L]n =
01
5
D13_E
D13
SYSCR.EXPE = 1, ABWCR.ABW[H,L]n =
01
4
D12_E
D12
SYSCR.EXPE = 1, ABWCR.ABW[H,L]n =
01
3
D11_E
D11
SYSCR.EXPE = 1, ABWCR.ABW[H,L]n =
01
2
D10_E
D10
SYSCR.EXPE = 1, ABWCR.ABW[H,L]n =
01
1
D9_E
D9
SYSCR.EXPE = 1, ABWCR.ABW[H,L]n =
01
0
D8_E
D8
SYSCR.EXPE = 1, ABWCR.ABW[H,L]n =
01
7
TIOCB8_OE
TIOCB8
TPU.TIOR_8.IOB3 = 0,
TPU.TIOR_8.IOB[1,0] = 01/10/11
PO23_OE
PO23
NDERL_1.NDER23 = 1
TIOCA8_OE
TIOCA8
TPU.TIOR_8.IOA3 = 0,
TPU.TIOR_8.IOA[1,0] = 01/10/11
6
5
PO22_OE
PO22
NDERL_1.NDER22 = 1
TIOCB7_OE
TIOCB7
TPU.TIOR_7.IOB3 = 0,
TPU.TIOR_7.IOB[1,0] = 01/10/11
PO21_OE
PO21
NDERL_1.NDER21 = 1
Rev. 2.00 Jul. 31, 2008 Page 678 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Port
PJ
4
3
2
1
0
PK
7
6
5
4
3
Output
Specification
Signal Name
Output
Signal
Name
TIOCA7_OE
TIOCA7
TPU.TIOR_7.IOA3 = 0,
TPU.TIOR_7.IOA[1,0] = 01/10/11
PO20_OE
PO20
NDERL_1.NDER20 = 1
TIOCD6_OE
TIOCD6
TPU.TMDR_6.BFB = 0,
TPU.TIORL_6.IOD3 = 0,
TPU.TIORL_6.IOD[1,0] = 01/10/11
PO19_OE
PO19
NDERL_1.NDER19 = 1
TIOCC6_OE
TIOCC6
TPU.TMDR_6.BFA = 0,
TPU.TIORL_6.IOC3 = 0,
TPU.TIORL_6.IOC[1,0] = 01/10/11
PO18_OE
PO18
NDERL_1.NDER18 = 1
TIOCB6_OE
TIOCB6
TPU.TIORH_6.IOB3 = 0,
TPU.TIORH_6.IOB[1,0] = 01/10/11
PO17_OE
PO17
NDERL_1.NDER17 = 1
TIOCA6_OE
TIOCA6
TPU.TIORH_6.IOA3 = 0,
TPU.TIORH_6.IOA[1,0] = 01/10/11
PO16_OE
PO16
NDERL_1.NDER16 = 1
TIOCB11_OE
TIOCB11
TPU.TIOR_11.IOB3 = 0,
TPU.TIOR_11.IOB[1,0] = 01/10/11
PO31_OE
PO31
NDERH_1.NDER31 = 1
TIOCA11_OE
TIOCA11
TPU.TIOR_11.IOA3 = 0,
TPU.TIOR_11.IOA[1,0] = 01/10/11
PO30_OE
PO30
NDERH_1.NDER30 = 1
TIOCB10_OE
TIOCB10
TPU.TIOR_10.IOB3 = 0,
TPU.TIOR_10.IOB[1,0] = 01/10/11
PO29_OE
PO29
NDERH_1.NDER29 = 1
TIOCA10_OE
TIOCA10
TPU.TIOR_10.IOA3 = 0,
TPU.TIOR_10.IOA[1,0] = 01/10/11
PO28_OE
PO28
NDERH_1.NDER28 = 1
TIOCD9_OE
TIOCD9
TPU.TMDR_9.BFB = 0,
TPU.TIORL_9.IOD3 = 0,
TPU.TIORL_9.IOD[1,0] = 01/10/11
PO27_OE
PO27
NDERH_1.NDER27 = 1
Signal Selection Register
Settings
Peripheral Module Settings
Rev. 2.00 Jul. 31, 2008 Page 679 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Output
Specification
Signal Name
Output
Signal
Name
TIOCC9_OE
TIOCC9
TPU.TMDR_9.BFA = 0,
TPU.TIORL_9.IOC3 = 0,
TPU.TIORL_9.IOC[1,0] = 01/10/11
PO26_OE
PO26
NDERH_1.NDER26 = 1
TIOCB9_OE
TIOCB9
TPU.TIORH_9.IOB3 = 0,
TPU.TIORH_9.IOB[1,0] = 01/10/11
PO25_OE
PO25
NDERH_1.NDER25 = 1
TIOCA9_OE
TIOCA9
TPU.TIORH_9.IOA3 = 0,
TPU.TIORH_9.IOA[1,0] = 01/10/11
PO24_OE
PO24
NDERH_1.NDER24 = 1
3
SCL3_OE
SCL2
ICCRA.ICE = 1
2
SDA3_OE
SDA3
ICCRA.ICE = 1
1
SCL2_OE
SCL2
ICCRA.ICE = 1
SDA2_OE
SDA2
ICCRA.ICE = 1
Port
PK
2
1
0
PN
0
Note:
*
Signal Selection Register
Settings
Peripheral Module Settings
Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 680 of 1438
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Section 13 I/O Ports
13.3
Port Function Controller
The port function controller controls the I/O ports.
The port function controller incorporates the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
Port function control register 0 (PFCR0)
Port function control register 1 (PFCR1)
Port function control register 2 (PFCR2)
Port function control register 4 (PFCR4)
Port function control register 6 (PFCR6)
Port function control register 7 (PFCR7)
Port function control register 8 (PFCR8)*
Port function control register 9 (PFCR9)
Port function control register A (PFCRA)
Port function control register B (PFCRB)
Port function control register C (PFCRC)
Port function control register D (PFCRD)
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 681 of 1438
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Section 13 I/O Ports
13.3.1
Port Function Control Register 0 (PFCR0)
PFCR0 enables/disables the CS output.
Bit
Bit Name
7
6
5
4
3
2
1
0
CS7E
CS6E
CS5E
CS4E
CS3E
CS2E
CS1E
CS0E
0
0
0
0
0
0
0
Undefined*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
R/W
Note: * 1 in external extended mode; 0 in other modes.
Bit
Bit Name
Initial
Value
R/W
Description
7
6
5
4
CS7E
CS6E
CS5E
CS4E
0
0
0
0
R/W
R/W
R/W
R/W
3
2
1
0
CS3E
CS2E
CS1E
CS0E
0
0
0
Undefined*
R/W
R/W
R/W
R/W
CS7 to CS0 Enable
These bits enable/disable the corresponding CSn
output.
0: Pin functions as I/O port
1: Pin functions as CSn output pin
(n = 7 to 0)
Note:
1 in external extended mode, 0 in other modes.
*
13.3.2
Port Function Control Register 1 (PFCR1)
PFCR1 selects the CS output pins.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
CS7SA
CS7SB
CS6SA
CS6SB
CS5SA
CS5SB
CS4SA
CS4SB
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 2.00 Jul. 31, 2008 Page 682 of 1438
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Section 13 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
7
CS7SA*
0
R/W
CS7 Output Pin Select
6
CS7SB*
0
R/W
Selects the output pin for CS7 when CS7 output is
enabled (CS7E = 1)
00: Specifies pin PB3 as CS7-A output
01: Specifies pin PB1 as CS7-B output
10: Specifies pin PC1 as CS7-C output
11: Specifies pin PB7 as CS7-D output
5
CS6SA*
0
R/W
CS6 Output Pin Select
4
CS6SB*
0
R/W
Selects the output pin for CS6 when CS6 output is
enabled (CS6E = 1)
00: Specifies pin PB2 as CS6-A output
01: Specifies pin PB1 as CS6-B output
10: Specifies pin PC1 as CS6-C output
11: Specifies pin PB6 as CS6-D output
3
CS5SA*
0
R/W
CS5 Output Pin Select
2
CS5SB*
0
R/W
Selects the output pin for CS5 when CS5 output is
enabled (CS5E = 1)
00: Specifies pin PB1 as CS5-A output
01: Specifies pin PB0 as CS5-B output
10: Specifies pin PC1 as CS5-C output
11: Specifies pin PB5 as CS5-D output
1
CS4SA*
0
R/W
CS4 Output Pin Select
0
CS4SB*
0
R/W
Selects the output pin for CS4 when CS4 output is
enabled (CS4E = 1)
00: Specifies pin PB0 as CS4-A output
01: Specifies pin PB4 as CS4-B output
10: Specifies pin PC1 as CS4-C output
11: Setting prohibited
Note:
*
If multiple CS outputs are specified to a single pin according to the CSn output pin
select bits (n = 4 to 7), multiple CS signals are output from the pin. For details, see
section 9.5.3, Chip Select Signals.
Rev. 2.00 Jul. 31, 2008 Page 683 of 1438
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Section 13 I/O Ports
13.3.3
Port Function Control Register 2 (PFCR2)
PFCR2 selects the CS output pin, enables/disables bus control I/O, and selects the bus control I/O
pins.
Bit
Bit Name
Initial Value
R/W
Bit
7
7
6
5
4
3
2
1
0
CS3S
CS2S
BSS
BSE
RDWRS
RDWRE
ASOE
WAITS
0
0
0
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
CS3S*
1
Initial
Value
R/W
Description
0
R/W
CS3 Output Pin Select
Selects the output pin for CS3 when CS3 output is
enabled (CS3E = 1)
0: Specifies pin PB3 as CS3-A output pin
1: Specifies pin PB0 as CS3-B output pin
6
CS2S*
1
0
R/W
CS2 Output Pin Select
Selects the output pin for CS2 when CS2 output is
enabled (CS2E = 1)
0: Specifies pin PB2 as CS2-A output pin
1: Specifies pin PB1 as CS2-B output pin
5
BSS
0
R/W
BS Output Pin Select
Selects the BS output pin
0: Specifies pin PA0 as BS-A output pin
1: Specifies pin PA6 as BS-B output pin
4
BSE
0
R/W
BS Output Enable
Enables/disables the BS output
0: Disables the BS output
1: Enables the BS output
3
RDWRS*
2
0
R/W
RD/WR Output Pin Select
Selects the output pin for RD/WR
0: Specifies pin PA1 as RD/WR-A output pin
1: Specifies pin PB6 as RD/WR-B output pin
Rev. 2.00 Jul. 31, 2008 Page 684 of 1438
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Section 13 I/O Ports
Bit
Bit Name
2
2
RDWRE*
Initial
Value
R/W
Description
0
R/W
RD/WR Output Enable
Enables/disables the RD/WR output
0: Disables the RD/WR output
1: Enables the RD/WR output
1
ASOE
1
R/W
AS Output Enable
Enables/disables the AS output
0: Specifies pin PA6 as I/O port
1: Specifies pin PA6 as AS output pin
0
WAITS
0
R/W
WAIT Input Pin Select
Selects the input pin for the wait request signal when
accessing external spaces.
0: Specifies pin PA2 as WAIT-A input pin
1: Specifies pin PC0 as WAIT-B input pin
Notes: 1. If multiple CS outputs are specified to a single pin according to the CSn output pin
select bit (n = 2, 3), multiple CS signals are output from the pin. For details, see section
9.5.3, Chip Select Signals.
2. If an area is specified as a byte control SDRAM space, the pin functions as RD/WR
output regardless of the RDWRE bit value.
13.3.4
Port Function Control Register 4 (PFCR4)
PFCR4 enables or disables the address output.
Bit
Bit Name
7
6
5
4
3
2
1
0
A23E
A22E
A21E
A20E
A19E
A18E
A17E
A16E
0
0
0
0/1*
0/1*
0/1*
0/1*
0/1*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
A23E
0
R/W
Address A23 Enable
Enables/disables the address output (A23)
0: Disables the A23 output
1: Enables the A23 output
Rev. 2.00 Jul. 31, 2008 Page 685 of 1438
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Section 13 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
6
A22E
0
R/W
Address A22 Enable
Enables/disables the address output (A22)
0: Disables the A22 output
1: Enables the A22 output
5
A21E
0
R/W
Address A21 Enable
Enables/disables the address output (A21)
0: Disables the A21 output
1: Enables the A21 output
4
A20E
0/1*
R/W
Address A20 Enable
Enables/disables the address output (A20)
0: Disables the A20 output
1: Enables the A20 output
3
A19E
0/1*
R/W
Address A19 Enable
Enables/disables the address output (A19)
0: Disables the A19 output
1: Enables the A19 output
2
A18E
0/1*
R/W
Address A18 Enable
Enables/disables the address output (A18)
0: Disables the A18 output
1: Enables the A18 output
1
A17E
0/1*
R/W
Address A17 Enable
Enables/disables the address output (A17)
0: Disables the A17 output
1: Enables the A17 output
0
A16E
0/1*
R/W
Address A16 Enable
Enables/disables the address output (A16)
0: Disables the A16 output
1: Enables the A16 output
Notes: *
The initial value changes depending on the operating mode.
The initial value is 1 when the on-chip ROM is disabled, and 0 when the on-chip ROM is
enabled.
Rev. 2.00 Jul. 31, 2008 Page 686 of 1438
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Section 13 I/O Ports
13.3.5
Port Function Control Register 6 (PFCR6)
PFCR6 selects the TPU clock input pin.
Bit
7
6
5
4
3
2
1
0
Bit Name

LHWROE


TCLKS

ADTRG1S
ADTRG0S
Initial Value
R/W
1
1
1
0
0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7

1
R/W
Reserved
This bit is always read as 1. The write value should
always be 1.
6
LHWROE
1
R/W
LHWR Output Enable
Enables/disables LHWR output (valid in external
extended mode).
0: Specifies pin PA4 as I/O port
1: Specifies pin PA4 as LHWR output pin
5

1
R/W
Reserved
This bit is always read as 1. The write value should
always be 1.
4

0
R
Reserved
This is a read-only bit and cannot be modified.
3
TCLKS
0
R/W
TPU External Clock Input Pin Select
Selects the TPU external clock input pins.
0: Specifies pins P32, P33, P35, and P37 as external
clock input pins.
1: Specifies pins P14 to P17 as external clock input
pins.
2

All 0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Jul. 31, 2008 Page 687 of 1438
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Section 13 I/O Ports
Initial
Value
Bit
Bit Name
1
ADTRG1S 0
R/W
Description
R/W
ADTRG1S Input Pin Select
Selects the external trigger input pins of the A/D
converter (unit1).
0: Specifies pin P17 as ADTRG1-A input pin.
1: Specifies pin PC0 as ADTRG1-B input pin.
0
ADTRG0S 0
R/W
ADTRG0S Input Pin Select
Selects the external trigger input pins of the A/D
converter (unit0).
0: Specifies pin P13 as ADTRG0-A input pin.
1: Specifies pin PB6 as ADTRG0-B input pin.
13.3.6
Port Function Control Register 7 (PFCR7)
PFCR7 selects the DMAC I/O pins (DREQ, DACK, and TEND).
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
DMAS3A
DMAS3B
DMAS2A
DMAS2B
DMAS1A
DMAS1B
DMAS0A
DMAS0B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
DMAS3A
0
R/W
DMAC control pin select
6
DMAS3B
0
R/W
Selects the I/O port to control DMAC_3.
00: Setting invalid
01: Specifies pins P63 to P65 as DMAC control pins
10: Setting prohibited
11: Setting prohibited
5
DMAS2A
0
R/W
DMAC control pin select
4
DMAS2B
0
R/W
Selects the I/O port to control DMAC_2.
00: Setting invalid
01: Specifies pins P60 to P62 as DMAC control pins
10: Setting prohibited
11: Setting prohibited
Rev. 2.00 Jul. 31, 2008 Page 688 of 1438
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Section 13 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
3
DMAS1A
0
R/W
DMAC control pin select
2
DMAS1B
0
R/W
Selects the I/O port to control DMAC_1.
00: Specifies pins P14 to P16 as DMAC control pins
01: Specifies pins P33 to P35 as DMAC control pins
10: Setting prohibited
11: Setting prohibited
1
DMAS0A
0
R/W
DMAC control pin select
0
DMAS0B
0
R/W
Selects the I/O port to control DMAC_0.
00: Specifies pins P10 to P12 as DMAC control pins
01: Specifies pins P30 to P32 as DMAC control pins
10: Setting prohibited
11: Setting prohibited
13.3.7
Port Function Control Register 8 (PFCR8)*
Note: * Supported only by the H8SX/1648G Group and H8SX/1648H Group.
PFCR8 selects the EXDMAC I/O pins (EDREQ, EDACK, ETEND, and EDRAK ).
7
6
5
4
3
2
1
0
EDMAS3A
EDMAS3B
EDMAS2A
EDMAS2B
EDMAS1A
EDMAS1B
EDMAS0A
EDMAS0B
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
EDMAS3A 0
R/W
EXDMAC control pin select
6
EDMAS3B 0
R/W
Selects the I/O port to control EXDMAC_3.
Bit
Bit name
Initial vaue:
00: Specifies pins P33 to P35, and P37 as EXDMAC
control pins
01: Setting prohibited
10: Setting prohibited
11: Setting prohibited
Rev. 2.00 Jul. 31, 2008 Page 689 of 1438
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Section 13 I/O Ports
Bit
Bit Name
5
4
Initial
Value
R/W
Description
EDMAS2A 0
R/W
EXDMAC control pin select
EDMAS2B 0
R/W
Selects the I/O port to control EXDMAC_2.
00: Specifies pins P30 to P32, and P36 as EXDMAC
control pins
01: Setting prohibited
10: Setting prohibited
11: Setting prohibited
3
EDMAS1A 0
R/W
EXDMAC control pin select
2
EDMAS1B 0
R/W
Selects the I/O port to control EXDMAC_1.
00: Specifies pins P14 to P17 as EXDMAC control pins
01: Specifies pins P63 to P65, and P67 as EXDMAC
control pins
10: Setting prohibited
11: Setting prohibited
1
EDMAS0A 0
R/W
EXDMAC control pin select
0
EDMAS0B 0
R/W
Selects the I/O port to control EXDMAC_0.
00: Specifies pins P10 to P13 as EXDMAC control pins
01: Specifies pins P60 to P62, and P66 as EXDMAC
control pins
10: Setting prohibited
11: Setting prohibited
13.3.8
Port Function Control Register 9 (PFCR9)
PFCR9 selects the multiple functions for the TPU I/O pins.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
TPUMS5
TPUMS4
TPUMS3A
TPUMS3B
TPUMS2
TPUMS1
TPUMS0A
TPUMS0B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 2.00 Jul. 31, 2008 Page 690 of 1438
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Section 13 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
7
TPUMS5
0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA5 function
0: Specifies pin P26 as output compare output and input
capture
1: Specifies P27 as input capture input and P26 as
output compare
6
TPUMS4
0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA4 function
0: Specifies P25 as output compare output and input
capture
1: Specifies P24 as input capture input and P25 as
output compare
5
TPUMS3A 0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA3 function
0: Specifies P21 as output compare output and input
capture
1: Specifies P20 as input capture input and P21 as
output compare
4
TPUMS3B 0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCC3 function
0: Specifies P22 as output compare output and input
capture
1: Specifies P23 as input capture input and P22 as
output compare
3
TPUMS2
0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA2 function
0: Specifies P36 as output compare output and input
capture
1: Specifies P37 as input capture input and P36 as
output compare
2
TPUMS1
0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA1 function
0: Specifies P34 as output compare output and input
capture
1: Specifies P35 as input capture input and P34 as
output compare
Rev. 2.00 Jul. 31, 2008 Page 691 of 1438
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Section 13 I/O Ports
Initial
Value
Bit
Bit Name
1
TPUMS0A 0
R/W
Description
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA0 function
0: Specifies P30 as output compare output and input
capture
1: Specifies P31 as input capture input and P30 as
output compare
0
TPUMS0B 0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCC0 function
0: Specifies P32 as output compare output and input
capture
1: Specifies P33 as input capture input and P32 as
output compare
13.3.9
Port Function Control Register A (PFCRA)
PFCRA selects the multiple functions for the TPU (unit 1) I/O pins. Do not access this register
because writing to or reading from the bits in this register is not effective when the PCJKE bit in
PFCRD is cleared to 0.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
TPUMS11
TPUMS10
TPUMS9A
TPUMS9B
TPUMS8
TPUMS7
TPUMS6A
TPUMS6B
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
Bit
Bit Name
7
TPUMS11 0
R/W
R/W
Description
TPU I/O Pin Multiplex Function Select
Selects TIOCA11 function
0: Specifies PK6 as output compare output and input
capture
1: Specifies PK7 as input capture input and PK6 as
output compare
Rev. 2.00 Jul. 31, 2008 Page 692 of 1438
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Section 13 I/O Ports
Initial
Value
Bit
Bit Name
6
TPUMS10 0
R/W
R/W
Description
TPU I/O Pin Multiplex Function Select
Selects TIOCA10 function
0: Specifies PK4 as output compare output and input
capture
1: Specifies PK5 as input capture input and PK4 as
output compare
5
TPUMS9A 0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA9 function
0: Specifies PK0 as output compare output and input
capture
1: Specifies PK1 as input capture input and PK0 as
output compare
4
TPUMS9B 0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCC9 function
0: Specifies PK2 as output compare output and input
capture
1: Specifies PK3 as input capture input and PK2 as
output compare
3
TPUMS8
0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA8 function
0: Specifies PJ6 as output compare output and input
capture
1: Specifies PJ7 as input capture input and PJ6 as output
compare
2
TPUMS7
0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA7 function
0: Specifies PJ4 as output compare output and input
capture
1: Specifies PJ5 as input capture input and PJ4 as output
compare
1
TPUMS6A 0
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCA6 function
0: Specifies PJ0 as output compare output and input
capture
1: Specifies PJ1 as input capture input and PJ0 as output
compare
Rev. 2.00 Jul. 31, 2008 Page 693 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Initial
Value
Bit
Bit Name
0
TPUMS6B 0
R/W
Description
R/W
TPU I/O Pin Multiplex Function Select
Selects TIOCC6 function
0: Specifies PJ2 as output compare output and input
capture
1: Specifies PJ3 as input capture input and PJ2 as output
compare
13.3.10 Port Function Control Register B (PFCRB)
• H8SX/1648 Group, H8SX/1648A Group
PFCRB selects the input pins for IRQ15 to IRQ8.
• H8SX/1648L Group
PFCRB selects IRQ14 interrupt / LVD interrupt*1, and the input pins for the IRQ15 and
IRQ13 to IRQ8.
• H8SX/1648G Group
PFCRB selects IRQ15, 32KOVI*2 , and the input pins for IRQ13 to IRQ8.
• H8SX/1648HGroup
PFCRB selects IRQ15, 32KOVI*2 , IRQ14 interrupt / LVD interrupt*1, and the input pins for
IRQ13 to IRQ8.
Bit
Bit Name
Initial Value:
R/W:
7
6
5
4
3
2
1
0
ITS15
ITS14
ITS13
ITS12
ITS11
ITS10
ITS9
ITS8
0
0
0
0
0
0
0
0
R/W
R/W*3
R/W
R/W
R/W
R/W
R/W
R/W
Notes: 1. Supported only by the H8SX/1648L Group and the H8SX/1648H Group.
2. Supported only by the H8SX/1648G Group and the H8SX/1648H Group.
Rev. 2.00 Jul. 31, 2008 Page 694 of 1438
REJ09B0365-0200
Section 13 I/O Ports
• H8SX/1648, and H8SX/1648A Groups
Bit
Bit Name
Initial
Value
R/W
Description
7
ITS15
0
R/W
IRQ15 Pin Select
Selects an input pin for IRQ15.
0: Selects pin P27 as IRQ15-A input
1: Selects pin P67 as IRQ15-B input
6

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
• H8SX/1648L Group
Bit
Bit Name
Initial
Value
R/W
Description
7
ITS15
0
R/W
IRQ15 Pin Select
Selects an input pin for IRQ15.
0: Selects pin P27 as IRQ15-A input
1: Selects pin P67 as IRQ15-B input
6
ITS14
0
R/W
LVD Interrupt / IRQ14 Interrupt Select
Selects whether the LVD interrupt or IRQ14 interrupt is
to be used.
0: Selects pin P26 as IRQ14-A
1: Selects LVD interrupt
• H8SX/1648G Group
Bit
Bit Name
Initial
Value
R/W
Description
7
ITS15
0
R/W
32KOVI / IRQ15 Interrupt Select
Selects whether 32KOVI interrupt or IRQ15 interrupt is
to be used.
0: Selects the 32KOVI interrupt in the TM32K
1: Selects pin P67 as IRQ15-B input
6

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Jul. 31, 2008 Page 695 of 1438
REJ09B0365-0200
Section 13 I/O Ports
• H8SX/1648H Group
Bit
Bit Name
Initial
Value
R/W
Description
7
ITS15
0
R/W
32KOVI / IRQ15 Interrupt Select
Selects whether 32KOVI interrupt or IRQ15 interrupt is
to be used.
0: Selects the 32KOVI interrupt in the TM32K
1: Selects pin P67 as IRQ15-B input
6
ITS14
0
R/W
LVD Interrupt / IRQ14 Interrupt Select
Selects whether the LVD interrupt or IRQ14 interrupt is
to be used.
0: Selects pin P26 as IRQ14-A
1: Selects LVD interrupt
• Each Group in Common
Bit
Bit Name
Initial
Value
R/W
Description
5
ITS13
0
R/W
IRQ13 Pin Select
Selects an input pin for IRQ13.
0: Selects pin P25 as IRQ13-A input
1: Selects pin P65 as IRQ13-B input
4
ITS12
0
R/W
IRQ12 Pin Select
Selects an input pin for IRQ12.
0: Selects pin P24 as IRQ12-A input
1: Selects pin P64 as IRQ12-B input
3
ITS11
0
R/W
IRQ11 Pin Select
Selects an input pin for IRQ11.
0: Selects pin P23 as IRQ11-A input
1: Selects pin P63 as IRQ11-B input
2
ITS10
0
R/W
IRQ10 Pin Select
Selects an input pin for IRQ10.
0: Selects pin P22 as IRQ10-A input
1: Selects pin P62 as IRQ10-B input
Rev. 2.00 Jul. 31, 2008 Page 696 of 1438
REJ09B0365-0200
Section 13 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
1
ITS9
0
R/W
IRQ9 Pin Select
Selects an input pin for IRQ9.
0: Selects pin P21 as IRQ9-A input
1: Selects pin P61 as IRQ9-B input
0
ITS8
0
R/W
IRQ8 Pin Select
Selects an input pin for IRQ8.
0: Selects pin P20 as IRQ8-A input
1: Selects pin P60 as IRQ8-B input
13.3.11 Port Function Control Register C (PFCRC)
PFCRC selects input pins for IRQ7 to IRQ0.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
ITS7
ITS6
ITS5
ITS4
ITS3
ITS2
ITS1
ITS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
ITS7
0
R/W
IRQ7 Pin Select
Selects an input pin for IRQ7.
0: Selects pin P17 as IRQ7-A input
1: Selects pin P57 as IRQ7-B input
6
ITS6
0
R/W
IRQ6 Pin Select
Selects an input pin for IRQ6.
0: Selects pin P16 as IRQ6-A input
1: Selects pin P56 as IRQ6-B input
5
ITS5
0
R/W
IRQ5 Pin Select
Selects an input pin for IRQ5.
0: Selects pin P15 as IRQ5-A input
1: Selects pin P55 as IRQ5-B input
Rev. 2.00 Jul. 31, 2008 Page 697 of 1438
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Section 13 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
4
ITS4
0
R/W
IRQ4 Pin Select
Selects an input pin for IRQ4.
0: Selects pin P14 as IRQ4-A input
1: Selects pin P54 as IRQ4-B input
3
ITS3
0
R/W
IRQ3 Pin Select
Selects an input pin for IRQ3.
0: Selects pin P13 as IRQ3-A input
1: Selects pin P53 as IRQ3-B input
2
ITS2
0
R/W
IRQ2 Pin Select
Selects an input pin for IRQ2.
0: Selects pin P12 as IRQ2-A input
1: Selects pin P52 as IRQ2-B input
1
ITS1
0
R/W
IRQ1 Pin Select
Selects an input pin for IRQ1.
0: Selects pin P11 as IRQ1-A input
1: Selects pin P51 as IRQ1-B input
0
ITS0
0
R/W
IRQ0 Pin Select
Selects an input pin for IRQ0.
0: Selects pin P10 as IRQ0-A input
1: Selects pin P50 as IRQ0-B input
Rev. 2.00 Jul. 31, 2008 Page 698 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.3.12 Port Function Control Register D (PFCRD)
PFCRD enables or disables the port J and port K pin functions.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
PCJKE







0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
PCJKE*
0
R/W
Ports J and K Enable
Enables or disables the port J and K pin functions.
0: Ports J and K are disabled.
1: Port s J and K are enabled (ports D and E are
disabled).

6 to 0
0
R/W
Reserved
These bits are always read as 0 and cannot be
modified. The initial value should not be changed.
Note:
*
This bit is only effective in single-chip mode. In other modes, do not change the initial
value of this bit.
Rev. 2.00 Jul. 31, 2008 Page 699 of 1438
REJ09B0365-0200
Section 13 I/O Ports
13.4
Usage Notes
13.4.1
Notes on Input Buffer Control Register (ICR) Setting
1. When the ICR setting is changed, the LSI may malfunction due to an edge occurred internally
according to the pin state. Before changing the ICR setting, fix the pin state high or disable the
input function corresponding to the pin by the on-chip peripheral module settings.
2. If an input is enabled by setting ICR while multiple input functions are assigned to the pin, the
pin state is reflected in all the inputs. Care must be taken for each module settings for unused
input functions.
3. When a pin is used as an output, data to be output from the pin will be latched as the pin state
if the input function corresponding to the pin is enabled. To use the pin as an output, disable
the input function for the pin by setting ICR.
13.4.2
Notes on Port Function Control Register (PFCR) Settings
1. Port function controller controls the I/O port.
Before enabling a port function, select the input/output destination.
2. When changing input pins, this LSI may malfunction due to the internal edge generated by the
pin level difference before and after the change.
• To change input pins, the following procedure must be performed.
A. Disable the input function by the corresponding on-chip peripheral module settings
B. Select another input pin by PFCR
C. Enable its input function by the corresponding on-chip peripheral module settings
3. If a pin function has both a select bit that modifies the input/output destination and an enable
bit that enables the pin function, first specify the input/output destination by the selection bit
and then enable the pin function by the enable bit.
4. The value of the PCJKE bit must be set during the initial setting immediately after a power-on.
Set the PCJKE bit first and then set other bits in PFCR as required.
5. Do not change the value of the PCJKE bit once it has been set.
Rev. 2.00 Jul. 31, 2008 Page 700 of 1438
REJ09B0365-0200
Section 14 16-Bit Timer Pulse Unit (TPU)
Section 14 16-Bit Timer Pulse Unit (TPU)
This LSI has two on-chip 16-bit timer pulse units (TPU), unit 0 and unit 1, each comprises six
channels. Therefore, this LSI includes twelve channels.
Functions of unit 0 and unit 1 are shown in table 14.1 and table 14.2 respectively. Block diagrams
of unit 0 and unit 1 are shown in figure 14.1 and figure 14.2 respectively.
This section explains unit 0. This explanation is common to unit 1.
14.1
Features
• Maximum 16-pulse input/output
• Selection of eight counter input clocks for each channel
• The following operations can be set for each channel:
 Waveform output at compare match
 Input capture function
 Counter clear operation
 Synchronous operations:
• Multiple timer counters (TCNT) can be written to simultaneously
• Simultaneous clearing by compare match and input capture possible
• Simultaneous input/output for registers possible by counter synchronous operation
• Maximum of 15-phase PWM output possible by combination with synchronous
operation
• Buffer operation settable for channels 0 and 3
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
• Cascaded operation
• Fast access via internal 16-bit bus
• 26 interrupt sources
• Automatic transfer of register data
• Programmable pulse generator (PPG) output trigger can be generated (unit 0 only)
• Conversion start trigger for the A/D converter can be generated (unit 0 only)
• Module stop state can be set
Rev. 2.00 Jul. 31, 2008 Page 701 of 1438
REJ09B0365-0200
Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.1 TPU (Unit 0) Functions
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
Count clock
Pφ/1
Pφ/4
Pφ/16
Pφ/64
TCLKA
TCLKB
TCLKC
TCLKD
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
TCLKA
TCLKB
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/1024
TCLKA
TCLKB
TCLKC
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/4096
TCLKA
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/1024
TCLKA
TCLKC
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
TCLKA
TCLKC
TCLKD
General registers
(TGR)
TGRA_0
TGRB_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TGRA_5
TGRB_5
General registers/
buffer registers
TGRC_0
TGRD_0


TGRC_3
TGRD_3


I/O pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Counter clear function TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
Compare 0 output
match
1 output
output
Toggle
output
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Input capture function O
O
O
O
O
O
Synchronous
operation
O
O
O
O
O
O
PWM mode
O
O
O
O
O
O
Phase counting mode 
O
O

O
O
Buffer operation
O


O


DTC activation
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
Rev. 2.00 Jul. 31, 2008 Page 702 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
DMAC activation
TGRA_0
compare
match or
input
capture
TGRA_1
compare
match or
input
capture
TGRA_2
compare
match or
input
capture
TGRA_3
compare
match or
input
capture
TGRA_4
compare
match or
input
capture
TGRA_5
compare
match or
input
capture
A/D conversion start
trigger
TGRA_0
compare
match or
input
capture
TGRA_1
compare
match or
input
capture
TGRA_2
compare
match or
input
capture
TGRA_3
compare
match or
input
capture
TGRA_4
compare
match or
input
capture
TGRA_5
compare
match or
input
capture
PPG trigger
TGRA_0/
TGRB_0
compare
match or
input
capture
TGRA_1/
TGRB_1
compare
match or
input
capture
TGRA_2/
TGRB_2
compare
match or
input
capture
TGRA_3/
TGRB_3
compare
match or
input
capture


Interrupt sources
5 sources
4 sources
4 sources
5 sources
4 sources
4 sources
Compare
match or
input
capture 0A
Compare
match or
input
capture 1A
Compare
match or
input
capture 2A
Compare
match or
input
capture 3A
Compare
match or
input
capture 4A
Compare
match or
input
capture 5A
Compare
match or
input
capture 0B
Compare
match or
input
capture 1B
Compare
match or
input
capture 2B
Compare
match or
input
capture 3B
Compare
match or
input
capture 4B
Compare
match or
input
capture 5B
Overflow
Compare Overflow
match or
Underflow
input
capture 3C
Compare Overflow
match or
Underflow
input
capture 0C
Underflow
Compare
match or
input
capture 0D
Compare
match or
input
capture 3D
Overflow
Overflow
Overflow
Underflow
[Legend]
O: Possible
: Not possible
Rev. 2.00 Jul. 31, 2008 Page 703 of 1438
REJ09B0365-0200
Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.2 TPU (Unit 1) Functions
Item
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10 Channel 11
Count clock
Pφ/1
Pφ/4
Pφ/16
Pφ/64
TCLKE
TCLKF
TCLKG
TCLKH
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
TCLKE
TCLKF
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/1024
TCLKE
TCLKF
TCLKG
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/4096
TCLKE
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/1024
TCLKE
TCLKG
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
TCLKE
TCLKG
TCLKH
General registers
(TGR)
TGRA_6
TGRB_6
TGRA_7
TGRB_7
TGRA_8
TGRB_8
TGRA_9
TGRB_9
TGRA_10
TGRB_10
TGRA_11
TGRB_11
General registers/
buffer registers
TGRC_6
TGRD_6


TGRC_9
TGRD_9


I/O pins
TIOCA6
TIOCB6
TIOCC6
TIOCD6
TIOCA7
TIOCB7
TIOCA8
TIOCB8
TIOCA9
TIOCB9
TIOCC9
TIOCD9
TIOCA10
TIOCB10
TIOCA11
TIOCB11
Counter clear function TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
Compare 0 output
match
1 output
output
Toggle
output
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Input capture function O
O
O
O
O
O
Synchronous
operation
O
O
O
O
O
O
PWM mode
O
O
O
O
O
O
Phase counting mode 
O
O

O
O
Buffer operation
O


O


DTC activation
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
Rev. 2.00 Jul. 31, 2008 Page 704 of 1438
REJ09B0365-0200
Section 14 16-Bit Timer Pulse Unit (TPU)
Item
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10 Channel 11
DMAC activation
TGRA_6
compare
match or
input
capture
TGRA_7
compare
match or
input
capture
TGRA_8
compare
match or
input
capture
TGRA_9
compare
match or
input
capture
TGRA_10
compare
match or
input
capture
TGRA_11
compare
match or
input
capture
A/D conversion start
trigger






PPG trigger
TGRA_6/
TGRB_6
compare
match
TGRA_7/
TGRB_7
compare
match
TGRA_8/
TGRB_8
compare
match
TGRA_9/
TGRB_9
compare
match


Interrupt sources
5 sources
4 sources
4 sources
5 sources
4 sources
4 sources
Compare
match or
input
capture 6A
Compare
match or
input
capture 7A
Compare
match or
input
capture 8A
Compare
match or
input
capture 9A
Compare
match or
input
capture 6B
Compare
match or
input
capture 7B
Compare
match or
input
capture 8B
Compare
match or
input
capture
10A
Compare
match or
Compare
input
match or
capture 9B input
Compare capture
10B
match or
Compare
match or
input
capture
11A
Compare Overflow
match or
Underflow
input
capture 6C
Overflow
Underflow
Compare
match or
input
capture 6D
input
Overflow
capture 9C Underflow
Compare
match or
input
capture 9D
Overflow
Overflow
Compare
match or
input
capture
11B
Overflow
Underflow
[Legend]
O: Possible
: Not possible
Rev. 2.00 Jul. 31, 2008 Page 705 of 1438
REJ09B0365-0200
TGRD
TGRB
TGRC
TGRB
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4V
TCI4U
Channel 5: TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
A/D conversion start request signal
TGRD
TGRB
TGRB
TGRB
PPG output trigger signal
TGRC
TCNT
TCNT
TGRA
TCNT
TGRA
Bus interface
TGRB
TCNT
TCNT
TGRA
TCNT
TGRA
Module data bus
TGRA
TSR
TSR
TIER
TIER
TSR
TIOR
TIORH TIORL
TIER:
TSR:
TGR (A, B, C, D):
TCNT:
TGRA
TSR
TIER
TSR
TSTR TSYR
TIER
TSR
TIER
TIOR
TIOR
TIOR
TIER
TMDR
TIORH TIORL
TCR
TMDR
Channel 4
TCR
TMDR
Channel 5
TCR
Control logic
TMDR
TCR
TMDR
Channel 1
Channel 0
TCR
Common
Timer start register
Timer synchronous register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
TMDR
Channel 2
[Legend]
TSTR:
TSYR:
TCR:
TMDR:
TIOR (H, L):
Control logic for channels 0 to 2
Input/output pins
TIOCA0
Channel 0:
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Channel 1:
TIOCB1
TIOCA2
Channel 2:
TIOCB2
TCR
Clock input
Internal clock: Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/4096
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Control logic for channels 3 to 5
Input/output pins
TIOCA3
Channel 3:
TIOCB3
TIOCC3
TIOCD3
TIOCA4
Channel 4:
TIOCB4
TIOCA5
Channel 5:
TIOCB5
Channel 3
Section 14 16-Bit Timer Pulse Unit (TPU)
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Timer interrupt enable register
Timer status register
Timer general registers (A, B, C, D)
Timer counter
Figure 14.1 Block Diagram of TPU (Unit 0)
Rev. 2.00 Jul. 31, 2008 Page 706 of 1438
REJ09B0365-0200
TGRD
TGRB
TGRC
TGRB
Interrupt request signals
Channel 9: TGI9A
TGI9B
TGI9C
TGI9D
TCI9V
Channel 10: TGI10A
TGI10B
TCI10V
TCI10U
Channel 11: TGI11A
TGI11B
TCI11V
TCI11U
Internal data bus
TGRD
TGRB
TGRB
TGRB
PPG output trigger signal
TGRC
TCNT
TCNT
TGRA
TCNT
TGRA
Bus interface
TGRB
TCNT
TCNT
TGRA
TCNT
TGRA
Module data bus
TGRA
TSR
TSR
TIER
TIER
TSR
TIOR
TIORH TIORL
TIER:
TSR:
TGR (A, B, C, D):
TCNT:
TGRA
TSR
TIER
TSR
TSTRB TSYRB
TIER
TSR
TIER
TIOR
TIOR
Control logic
TIOR
TIER
TMDR
TIORH TIORL
TCR
TMDR
Channel 10
TCR
TMDR
Channel 11
TCR
TMDR
TCR
TMDR
Channel 7
Channel 6
TCR
Common
Timer start register
Timer synchronous register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
TMDR
Channel 8
[Legend]
TSTRB:
TSYRB:
TCR:
TMDR:
TIOR (H, L):
Control logic for channels 6 to 8
Input/output pins
TIOCA6
Channel 6:
TIOCB6
TIOCC6
TIOCD6
TIOCA7
Channel 7:
TIOCB7
TIOCA8
Channel 8:
TIOCB8
TCR
Clock input
Internal clock: Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/4096
External clock: TCLKE
TCLKF
TCLKG
TCLKH
Control logic for channels 9 to 11
Input/output pins
TIOCA9
Channel 9:
TIOCB9
TIOCC9
TIOCD9
Channel 10: TIOCA10
TIOCB10
Channel 11: TIOCA11
TIOCB11
Channel 9
Section 14 16-Bit Timer Pulse Unit (TPU)
Interrupt request signals
Channel 6: TGI6A
TGI6B
TGI6C
TGI6D
TCI6V
Channel 7: TGI7A
TGI7B
TCI7V
TCI7U
Channel 8: TGI8A
TGI8B
TCI8V
TCI8U
Timer interrupt enable register
Timer status register
Timer general registers (A, B, C, D)
Timer counter
Figure 14.2 Block Diagram of TPU (Unit 1)
Rev. 2.00 Jul. 31, 2008 Page 707 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.2
Input/Output Pins
Table 14.3 shows TPU pin configurations.
Table 14.3 Pin Configuration
Unit
Channel
Symbol
I/O
Function
0
All
TCLKA
Input
External clock A input pin
(Channel 1 and 5 phase counting mode A phase input)
TCLKB
Input
External clock B input pin
(Channel 1 and 5 phase counting mode B phase input)
TCLKC
Input
External clock C input pin
(Channel 2 and 4 phase counting mode A phase input)
TCLKD
Input
External clock D input pin
(Channel 2 and 4 phase counting mode B phase input)
0
1
2
3
4
5
TIOCA0
I/O
TGRA_0 input capture input/output compare output/PWM output pin
TIOCB0
I/O
TGRB_0 input capture input/output compare output/PWM output pin
TIOCC0
I/O
TGRC_0 input capture input/output compare output/PWM output pin
TIOCD0
I/O
TGRD_0 input capture input/output compare output/PWM output pin
TIOCA1
I/O
TGRA_1 input capture input/output compare output/PWM output pin
TIOCB1
I/O
TGRB_1 input capture input/output compare output/PWM output pin
TIOCA2
I/O
TGRA_2 input capture input/output compare output/PWM output pin
TIOCB2
I/O
TGRB_2 input capture input/output compare output/PWM output pin
TIOCA3
I/O
TGRA_3 input capture input/output compare output/PWM output pin
TIOCB3
I/O
TGRB_3 input capture input/output compare output/PWM output pin
TIOCC3
I/O
TGRC_3 input capture input/output compare output/PWM output pin
TIOCD3
I/O
TGRD_3 input capture input/output compare output/PWM output pin
TIOCA4
I/O
TGRA_4 input capture input/output compare output/PWM output pin
TIOCB4
I/O
TGRB_4 input capture input/output compare output/PWM output pin
TIOCA5
I/O
TGRA_5 input capture input/output compare output/PWM output pin
TIOCB5
I/O
TGRB_5 input capture input/output compare output/PWM output pin
Rev. 2.00 Jul. 31, 2008 Page 708 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
Unit
Channel
Symbol
I/O
Function
1
All
TCLKE
Input
External clock E input pin
(Channel 7 and 11 phase counting mode A phase input)
TCLKF
Input
External clock F input pin
(Channel 7 and 11 phase counting mode B phase input)
TCLKG
Input
External clock G input pin
(Channel 8 and 10 phase counting mode A phase input)
TCLKH
Input
External clock H input pin
(Channel 8 and 10 phase counting mode B phase input)
6
7
8
9
10
11
TIOCA6
I/O
TGRA_6 input capture input/output compare output/PWM output pin
TIOCB6
I/O
TGRB_6 input capture input/output compare output/PWM output pin
TIOCC6
I/O
TGRC_6 input capture input/output compare output/PWM output pin
TIOCD6
I/O
TGRD_6 input capture input/output compare output/PWM output pin
TIOCA7
I/O
TGRA_7 input capture input/output compare output/PWM output pin
TIOCB7
I/O
TGRB_7 input capture input/output compare output/PWM output pin
TIOCA8
I/O
TGRA_8 input capture input/output compare output/PWM output pin
TIOCB8
I/O
TGRB_8 input capture input/output compare output/PWM output pin
TIOCA9
I/O
TGRA_9 input capture input/output compare output/PWM output pin
TIOCB9
I/O
TGRB_9 input capture input/output compare output/PWM output pin
TIOCC9
I/O
TGRC_9 input capture input/output compare output/PWM output pin
TIOCD9
I/O
TGRD_9 input capture input/output compare output/PWM output pin
TIOCA10
I/O
TGRA_10 input capture input/output compare output/PWM output pin
TIOCB10
I/O
TGRB_10 input capture input/output compare output/PWM output pin
TIOCA11
I/O
TGRA_11 input capture input/output compare output/PWM output pin
TIOCB11
I/O
TGRB_11 input capture input/output compare output/PWM output pin
Rev. 2.00 Jul. 31, 2008 Page 709 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3
Register Descriptions
The TPU has the following registers in each channel.
Registers in the unit 0 and unit 1 have the same functions except for the bit 7 in TIER, namely, the
TTGE bit in unit 0 and a reserved bit in unit 1. This section gives explanations regarding unit 0.
Unit 0:
• Channel 0:
 Timer control register_0 (TCR_0)
 Timer mode register_0 (TMDR_0)
 Timer I/O control register H_0 (TIORH_0)
 Timer I/O control register L_0 (TIORL_0)
 Timer interrupt enable register_0 (TIER_0)
 Timer status register_0 (TSR_0)
 Timer counter_0 (TCNT_0)
 Timer general register A_0 (TGRA_0)
 Timer general register B_0 (TGRB_0)
 Timer general register C_0 (TGRC_0)
 Timer general register D_0 (TGRD_0)
• Channel 1:
 Timer control register_1 (TCR_1)
 Timer mode register_1 (TMDR_1)
 Timer I/O control register _1 (TIOR_1)
 Timer interrupt enable register_1 (TIER_1)
 Timer status register_1 (TSR_1)
 Timer counter_1 (TCNT_1)
 Timer general register A_1 (TGRA_1)
 Timer general register B_1 (TGRB_1)
Rev. 2.00 Jul. 31, 2008 Page 710 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
• Channel 2:
 Timer control register_2 (TCR_2)
 Timer mode register_2 (TMDR_2)
 Timer I/O control register_2 (TIOR_2)
 Timer interrupt enable register_2 (TIER_2)
 Timer status register_2 (TSR_2)
 Timer counter_2 (TCNT_2)
 Timer general register A_2 (TGRA_2)
 Timer general register B_2 (TGRB_2)
• Channel 3:
 Timer control register_3 (TCR_3)
 Timer mode register_3 (TMDR_3)
 Timer I/O control register H_3 (TIORH_3)
 Timer I/O control register L_3 (TIORL_3)
 Timer interrupt enable register_3 (TIER_3)
 Timer status register_3 (TSR_3)
 Timer counter_3 (TCNT_3)
 Timer general register A_3 (TGRA_3)
 Timer general register B_3 (TGRB_3)
 Timer general register C_3 (TGRC_3)
 Timer general register D_3 (TGRD_3)
• Channel 4:
 Timer control register_4 (TCR_4)
 Timer mode register_4 (TMDR_4)
 Timer I/O control register _4 (TIOR_4)
 Timer interrupt enable register_4 (TIER_4)
 Timer status register_4 (TSR_4)
 Timer counter_4 (TCNT_4)
 Timer general register A_4 (TGRA_4)
 Timer general register B_4 (TGRB_4)
Rev. 2.00 Jul. 31, 2008 Page 711 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
• Channel 5:
 Timer control register_5 (TCR_5)
 Timer mode register_5 (TMDR_5)
 Timer I/O control register_5 (TIOR_5)
 Timer interrupt enable register_5 (TIER_5)
 Timer status register_5 (TSR_5)
 Timer counter_5 (TCNT_5)
 Timer general register A_5 (TGRA_5)
 Timer general register B_5 (TGRB_5)
• Common Registers:
 Timer start register (TSTR)
 Timer synchronous register (TSYR)
Unit 1:
• Channel 6:
 Timer control register_6 (TCR_6)
 Timer mode register_6 (TMDR_6)
 Timer I/O control register H_6 (TIORH_6)
 Timer I/O control register L_6 (TIORL_6)
 Timer interrupt enable register_6 (TIER_6)
 Timer status register_6 (TSR_6)
 Timer counter_6 (TCNT_6)
 Timer general register A_6 (TGRA_6)
 Timer general register B_6 (TGRB_6)
 Timer general register C_6 (TGRC_6)
 Timer general register D_6 (TGRD_6)
Rev. 2.00 Jul. 31, 2008 Page 712 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
• Channel 7:
 Timer control register_7 (TCR_7)
 Timer mode register_7 (TMDR_7)
 Timer I/O control register _7 (TIOR_7)
 Timer interrupt enable register_7 (TIER_7)
 Timer status register_7 (TSR_7)
 Timer counter_7 (TCNT_7)
 Timer general register A_7 (TGRA_7)
 Timer general register B_7 (TGRB_7)
• Channel 8:
 Timer control register_8 (TCR_8)
 Timer mode register_8 (TMDR_8)
 Timer I/O control register_8 (TIOR_8)
 Timer interrupt enable register_8 (TIER_8)
 Timer status register_8 (TSR_8)
 Timer counter_8 (TCNT_8)
 Timer general register A_8 (TGRA_8)
 Timer general register B_8 (TGRB_8)
• Channel 9:
 Timer control register_9 (TCR_9)
 Timer mode register_9 (TMDR_9)
 Timer I/O control register H_9 (TIORH_9)
 Timer I/O control register L_9 (TIORL_9)
 Timer interrupt enable register_9 (TIER_9)
 Timer status register_9 (TSR_9)
 Timer counter_9 (TCNT_9)
 Timer general register A_9 (TGRA_9)
 Timer general register B_9 (TGRB_9)
 Timer general register C_9 (TGRC_9)
 Timer general register D_9 (TGRD_9)
Rev. 2.00 Jul. 31, 2008 Page 713 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
• Channel 10:
 Timer control register_10 (TCR_10)
 Timer mode register_10 (TMDR_10)
 Timer I/O control register _10 (TIOR_10)
 Timer interrupt enable register_10 (TIER_10)
 Timer status register_10 (TSR_10)
 Timer counter_10 (TCNT_10)
 Timer general register A_10 (TGRA_10)
 Timer general register B_10 (TGRB_10)
• Channel 11:
 Timer control register_11 (TCR_11)
 Timer mode register_11 (TMDR_11)
 Timer I/O control register_11 (TIOR_11)
 Timer interrupt enable register_11 (TIER_11)
 Timer status register_11 (TSR_11)
 Timer counter_11 (TCNT_11)
 Timer general register A_11 (TGRA_11)
 Timer general register B_11 (TGRB_11)
• Common Registers:
 Timer start register (TSTRB)
 Timer synchronous register (TSYRB)
Rev. 2.00 Jul. 31, 2008 Page 714 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.1
Timer Control Register (TCR)
TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one
for each channel. TCR register settings should be made only while TCNT operation is stopped.
Bit
Bit Name
Initial Value
R/W
7
6
5
4
3
2
1
0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
CCLR2
0
R/W
Counter Clear 2 to 0
6
CCLR1
0
R/W
5
CCLR0
0
R/W
These bits select the TCNT counter clearing source. See
tables 12.4 and 12.5 for details.
4
CKEG1
0
R/W
Clock Edge 1 and 0
3
CKEG0
0
R/W
These bits select the input clock edge. For details, see
table 14.6. When the input clock is counted using both
edges, the input clock period is halved (e.g. Pφ/4 both
edges = Pφ/2 rising edge). If phase counting mode is
used on channels 1, 2, 4, and 5, this setting is ignored
and the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is Pφ/4
or slower. This setting is ignored if the input clock is Pφ/1,
or when overflow/underflow of another channel is
selected.
2
TPSC2
0
R/W
Timer Prescaler 2 to 0
1
TPSC1
0
R/W
0
TPSC0
0
R/W
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 12.7 to 12.12 for details. To select the external
clock as the clock source, the DDR bit and ICR bit for the
corresponding pin should be set to 0 and 1, respectively.
For details, see section 13, I/O Ports.
Rev. 2.00 Jul. 31, 2008 Page 715 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.4 CCLR2 to CCLR0 (Channels 0 and 3)
Channel
Bit 7
CCLR2
Bit 6
CCLR1
Bit 5
CCLR0
Description
0, 3
0
0
0
TCNT clearing disabled
0
0
1
TCNT cleared by TGRA compare match/input
capture
0
1
0
TCNT cleared by TGRB compare match/input
capture
0
1
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
1
0
0
TCNT clearing disabled
1
0
1
TCNT cleared by TGRC compare match/input
capture*2
1
1
0
TCNT cleared by TGRD compare match/input
capture*2
1
1
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 14.5 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Channel
Bit 7
Bit 6
Reserved*2 CCLR1
Bit 5
CCLR0
Description
1, 2, 4, 5
0
0
0
TCNT clearing disabled
0
0
1
TCNT cleared by TGRA compare match/input
capture
0
1
0
TCNT cleared by TGRB compare match/input
capture
0
1
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Rev. 2.00 Jul. 31, 2008 Page 716 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.6 Input Clock Edge Selection
Clock Edge Selection
Input Clock
CKEG1
CKEG0
Internal Clock
External Clock
0
0
Counted at falling edge
Counted at rising edge
0
1
Counted at rising edge
Counted at falling edge
1
x
Counted at both edges
Counted at both edges
[Legend]
x:
Don't care
Table 14.7 TPSC2 to TPSC0 (Channel 0)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
0
0
0
0
Internal clock: counts on Pφ/1
0
0
1
Internal clock: counts on Pφ/4
0
1
0
Internal clock: counts on Pφ/16
0
1
1
Internal clock: counts on Pφ/64
1
0
0
External clock: counts on TCLKA pin input
1
0
1
External clock: counts on TCLKB pin input
1
1
0
External clock: counts on TCLKC pin input
1
1
1
External clock: counts on TCLKD pin input
Table 14.8 TPSC2 to TPSC0 (Channel 1)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
1
0
0
0
Internal clock: counts on Pφ/1
0
0
1
Internal clock: counts on Pφ/4
0
1
0
Internal clock: counts on Pφ/16
0
1
1
Internal clock: counts on Pφ/64
1
0
0
External clock: counts on TCLKA pin input
1
0
1
External clock: counts on TCLKB pin input
1
1
0
Internal clock: counts on Pφ/256
1
1
1
Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
Rev. 2.00 Jul. 31, 2008 Page 717 of 1438
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.9 TPSC2 to TPSC0 (Channel 2)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
2
0
0
0
Internal clock: counts on Pφ/1
0
0
1
Internal clock: counts on Pφ/4
0
1
0
Internal clock: counts on Pφ/16
0
1
1
Internal clock: counts on Pφ/64
1
0
0