Power AP1280AMP 2a sink/source bus termination regulator Datasheet

Advanced Power
Electronics Corp.
AP1280AMP
2A SINK/SOURCE BUS TERMINATION REGULATOR
FEATURES
DESCRIPTIOON
Ideal for DDR-I, DDR-II and DDR-III VTT Applications
The AP1280AMP is a simple, cost-effective and
high-speed linear regulator designed to generate
termination voltage in double data rate (DDR) memory
system to comply with the JEDEC SSTL_2 and
SSTL_18 or other specific interfaces such as HSTL,
SCSI-2 and SCSI-3 etc. devices requirements. The
regulator is capable of actively sinking or sourcing up to
2A while regulating an output voltage to within 40mV.
The output termination voltage cab be tightly regulated
to track 1/2VDDQ by two external voltage divider resistors
or the desired output voltage can be pro-grammed by
externally forcing the REFEN pin voltage.
The AP1280AMP also incorporates a high-speed
differential amplifier to provide ultra-fast response in
line/load transient. Other features include extremely low
initial offset voltage, excellent load regulation, current
limiting in bi-directions and on-chip thermal shut-down
protection.Built-in
softstart
function
avoids
a
misoperation by inrush current.
The AP1280AMP are available in the ESOP-8
(Exposed Pad) surface mount packages.
Sink and Source up to 2Amp
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL_18,
HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Built-in Soft-start Function
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in ESOP-8 (Exposed Pad) Packages
VIN and VCNTL Under Voltage Protection
RoHS Compliant and Halogen Free
APPLICATION
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
TYPICAL APPLICATION
VIN
VCNTL
VIN
CIN
VCNTL
R1
CCNTL
AP1280AMP
RTT
VOUT
REFEN
Shutdown
R2
CSS
GND
VOUT
COUT
RDUMMY
Enable
R1 = R2 = 100 KΩ , RTT = 50Ω / 33Ω / 25Ω
COUT = 10uF ( + 100 uF under the worst case testing condition )
CSS = 1uF , CIN = 470 uF (Low ESR) , CCNTL = 47uF
Data and specifications subject to change without notice
1
20130617V4.2
Advanced Power
Electronics Corp.
AP1280AMP
ABSOLUTE MAXIMUM RATINGS(Note1)
Input Voltage (VIN) ------------------------------------------ 6V
CNTL Pin Voltage (VCNTL) -------------------------------- 6V
Power Dissipation (PD) ------------------------------------ Internally Limited
Storage Temperature Range (T ST) --------------------- -65 to +150°C
Lead Temperature (Soldering, 10sec.) --------------Thermal Resistance from Junction to Case (R thjc)
260°C
28°C/W
Note1 : Exceeding the absolute maximum rating may damage the device.
OPERATING RATING(Note2)
Input Voltage (VIN) ------------------------------------------ 2.5V to 1.1V +3%
CNTL Pin Voltage (VCNTL) -------------------------------- 5.5V or 3.3V +5%
Junction Temperature Range (T J) ---------------------
-40 to +125°C
Ambient Temperature Range (T A) ---------------------
-40 to +85°C
Note2 : The device is not guaranteed to function outside its operating conditions.
ORDERING / PACKAGE INFORMATION
( Top View )
AP1280 AX
Package Type
VIN
1
8
GND
2
7 NC
REFEN
3
VOUT
4
GND
MP : ESOP-8
NC
6
VCNTL
5
NC
ESOP-8
Rthja = 75oC/W
ELECTRICAL SPECIFICATIONS
(VIN=1.8V, VCNTL=3.3V, VREFEN=0.9V, COUT=10uF(Ceramic), T A =25oC, unless otherwise specified)
Parameter
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Input
VCNTL Operation Current
ICNTL
IOUT = 0A
-
1
2.5
mA
Standby Current
ISTBY
VREFEN= 0V (Shutdown)
-
2
5
uA
IVIN
VREFEN= 0V (Shutdown)
-
-
5
uA
2.4
2.55
2.7
V
-
0.35
-
V
0.8
0.95
1.1
V
-
0.15
-
V
IOUT = 10mA
-20
-
20
VIN Shutdown Current
UVP Function
VCNTL UVP Rising Threshold
VCOP
VCNTL UVP Hysteresis
VCHYS
VIN UVP Rising Threshold
VIOP
VIN UVP Hysteresis
VIHYS
VCNTL Rising
VIOP Rising
Output (DDR / DDRII / DDRIII)
Output Offset Voltage(Note3)
Load Regulation
(Note4)
ΔVOS
ΔVLoad
IOUT = -10mA
-20
-
20
VIN=1.8V, VREFEN=0.9V, IOUT=+10mA ~ +2A
-20
-
20
VIN=1.5V, VREFEN=0.75V, IOUT=+10mA ~ +2A
-20
-
20
VIN=1.2V, VREFEN=0.6V, IOUT=+10mA ~ +2A
-20
-
20
VIN=1.1V, VREFEN=0.55V, IOUT=+10mA ~ +1.8A
-20
-
20
mV
2
Advanced Power
Electronics Corp.
AP1280AMP
ELECTRICAL SPECIFICATIONS (CONTINUED)
Parameter
Protection
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
A
Current Limit
ILIM
2.2
-
-
Thermal Shutdown Temperature
TSD
3.3V < VCNTL < 5V
-
150
-
ΔTSD
3.3V < VCNTL < 5V
-
20
-
0.15
-
0.4
V
-
0.8
-
ms
Thermal Shutdown Hysteresis
o
C
ENABLE and Soft-Start
REFEN Threshold
VEN
Soft-Start Interval
TSS
∆VOUT=1V
Note3. VOS offset is the voltage measurement defined as V OUT subtracted from VREFEN.
Note4. Regulation is measured at constant junction temperature by using a 1ms(on) / 9ms(off) current pulse. Devices are tested for load regulation
in the load range from 10mA to 2A for source and -10mA to -2A for sink capability.
PIN DESCRIPTIONS
PIN SYMBOL
VIN
PIN DESCRIPTION
Power Input Voltage.
GND
Ground Pin
VOUT
Output Voltage
VCNTL
Gate Drive Voltage
REFEN
Reference Voltage Input and Chip Enable
BLOCK DIAGRAM
VCNTL
UVP
Function
VIN
OTP
Function
ENABLE
FUNCTION
REFEN
Soft-Start
Function
OCP
Function
GATE
CONTROL
LOGIC
ERROR
AMPLIFIER
VOUT
GND
3
Advanced Power
Electronics Corp.
AP1280AMP
APPLICATION INFORMATION
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as possible to the AP1280AMP. A low ESR
capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to
minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance and cause undesired oscillation
between AP1280AMP and the preceding powe converter.
Consideration while designs the resistance of voltage divider
Make sure the sinking current capability of pull-down NMOS if the lower resistance was
chosen so that the voltage on VREFEN is below 0.15V. In addition, the capacitor and voltage divider
form the lowpass filter. There are two reasons doing this design; one is for output voltage softstart while another is for noise immunity.
Thermal Consideration
AP1280AMP regulators have internal thermal limiting circuitry designed to protect the device
during overload conditions.For continued operation, do not exceed maximum operation junction
temperature 125oC. The power dissipation definition in device is:
PD = (VIN - VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermal resistance of IC package, PCB
layout, the rate of surroundings airflow and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by following formula:
PD(MAX) = ( TJ(MAX) -TA ) / Rthja
Where TJ(MAX) is the maximum operation junction temperature 125oC, TA is the ambient
temperature and the Rthja is the junction to ambient thermal resistance. The junction to ambient
thermal resistance (Rthja is layout dependent) for ESOP-8 package (Exposed Pad) is 75oC/W on
standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA
= 25oC can be calculated by following formula:
PD(MAX) = (125oC - 25oC) / 75oC/W = 1.33W
The thermal resistance Rthja of ESOP-8 (Exposed Pad) is determined by the package design
and the PCB design. However, the package design has been decided. If possible, it's useful to
increase thermal performance by the PCB design. The thermal resistance can be decreased by
adding copper under the expose pad of ESOP-8 package. We have to consider the copper
couldn't stretch infinitely and avoid the tin overflow
4
Advanced Power
Electronics Corp.
AP1280AMP
MARKING INFORMATION
ESOP-8
Part Number
Package Code
1280AMP
YWWSSS
Date Code (YWWSSS)
Y:Last Digit Of The Year
WW:Week
SSS:Sequence
5
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