TI OPA548T-1G3 High-voltage, high-current operational amplifier Datasheet

OPA548
OPA
548
OPA
548
O PA
548
SBOS070B – OCTOBER 1997 – OCTOBER 2003
High-Voltage, High-Current
OPERATIONAL AMPLIFIER
FEATURES
DESCRIPTION
● WIDE SUPPLY RANGE
Single Supply: +8V to +60V
Dual Supply: ±4V to ±30V
● HIGH OUTPUT CURRENT:
3A Continuous
5A Peak
● WIDE OUTPUT VOLTAGE SWING
● FULLY PROTECTED:
Thermal Shutdown
Adjustable Current Limit
● OUTPUT DISABLE CONTROL
● THERMAL SHUTDOWN INDICATOR
● HIGH SLEW RATE: 10V/µs
● LOW QUIESCENT CURRENT
● PACKAGES:
7-Lead TO-220, Zip and Straight Leads
7-Lead DDPAK Surface-Mount
The OPA548 is a low-cost, high-voltage/high-current operational amplifier ideal for driving a wide variety of loads. A
laser-trimmed monolithic integrated circuit provides excellent
low-level signal accuracy and high output voltage and current.
The OPA548 operates from either single or dual supplies for
design flexibility. In single-supply operation, the input common-mode range extends below ground.
The OPA548 is internally protected against over-temperature
conditions and current overloads. In addition, the OPA548
was designed to provide an accurate, user-selected current
limit. Unlike other designs which use a “power” resistor in
series with the output current path, the OPA548 senses the
load indirectly. This allows the current limit to be adjusted
from 0A to 5A with a resistor/potentiometer or controlled
digitally with a voltage-out or current-out DAC.
The Enable/Status (E/S) pin provides two functions. An input
on the pin not only disables the output stage to effectively
disconnect the load, but also reduces the quiescent current
to conserve power. The E/S pin output can be monitored to
determine if the OPA548 is in thermal shutdown.
APPLICATIONS
●
●
●
●
●
●
VALVE, ACTUATOR DRIVERS
SYNCHRO, SERVO DRIVERS
POWER SUPPLIES
TEST EQUIPMENT
TRANSDUCER EXCITATION
AUDIO AMPLIFIERS
The OPA548 is available in an industry-standard
7-lead staggered and straight lead TO-220 package, and a
7-lead DDPAK surface-mount plastic power package. The
copper tab allows easy mounting to a heat sink or circuit
board for excellent thermal performance. It is specified for
operation over the extended industrial temperature range,
–40°C to +85°C. A SPICE macromodel is available for
design analysis.
V+
–
VIN
OPA548
VO
ILIM
+
VIN
RCL (1/4W Resistor)
RCL sets the current limit
value from 0 to 5A.
E/S
V–
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997-2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Output Current ................................................................. See SOA Curve
Supply Voltage, V+ to V– ................................................................... 60V
Input Voltage .................................................. (V–) – 0.5V to (V+) + 0.5V
Input Shutdown Voltage ........................................................................ V+
Operating Temperature .................................................. –40°C to +125°C
Storage Temperature ..................................................... –55°C to +125°C
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering 10s)(2) .............................................. 300°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
NOTES: (1) Stresses above these ratings may cause permanent damage.
(2) Vapor-phase or IR reflow techniques are recommended for soldering the
OPA547F surface-mount package. Wave soldering is not recommended due to
excessive thermal shock and “shadowing” of nearby devices.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.
PIN CONFIGURATIONS
Top Front View
7-Lead
Stagger-Formed
TO-220 (T)
7-Lead
Straight-Formed
TO-220 (T-1)
1 2 3 4 5 6 7
7-Lead
DDPAK (FA)
Surface-Mount
1 2 3 4 5 6 7
1 2 3 4 5 6 7
VIN+ ILIM V+ E/S
VIN– V– VO
VIN+ ILIM V+ E/S
VIN– V– VO
VIN+ ILIM V+ E/S
VIN– V– VO
NOTE: Tabs are electrically connected to the V– supply.
2
OPA548
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SBOS070B
ELECTRICAL CHARACTERISTICS
At TCASE = +25°C, VS = ±30V and E/S pin open, unless otherwise noted.
OPA548T, F
PARAMETER
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature
vs Power Supply
INPUT BIAS CURRENT(1)
Input Bias Current(2)
vs Temperature
Input Offset Current
CONDITION
MIN
TYP
MAX
UNITS
VCM = 0, IO = 0
TA = –40°C to +85°C
VS = ±4V to ±30V
±2
±30
30
±10
mV
µV/°C
µV/V
VCM = 0V
TA = –40°C to +85°C
VCM = 0V
–100
±0.5
±5
–500
NOISE
Input Voltage Noise Density, f = 1kHz
Current Noise Density, f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range: Positive
Negative
Common-Mode Rejection
Linear Operation
Linear Operation
VCM = (V–) –0.1V to (V+) –3V
(V+) – 3
(V–) – 0.1
80
INPUT IMPEDANCE
Differential
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Full-Power Bandwidth
Settling Time: ±0.1%
Total Harmonic Distortion + Noise, f = 1kHz
OUTPUT
Voltage Output, Positive
Negative
Positive
Negative
Maximum Continuous Current Output: dc
ac
Leakage Current, Output Disabled, dc
Output Current Limit
Current Limit Range
Current Limit Equation
Current Limit Tolerance(1)
VO = ±25V, RL = 1kΩ
VO = ±25V, RL = 8Ω
90
RL = 8Ω
G = 1, 50Vp-p, RL = 8Ω
G = –10, 50V Step
RL = 8Ω, G = +3, Power = 10W
IO = 3A
IO = –3A
IO = 0.6A
IO = –0.6A
(V+) – 4.1
(V–) + 3.7
(V+) – 2.4
(V–) + 1.3
±3
3
POWER SUPPLY
Specified Voltage
Operating Voltage Range
Quiescent Current
Quiescent Current, Shutdown Mode
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance, θJC
7-Lead DDPAK, 7-Lead TO-220
7-Lead DDPAK, 7-Lead TO-220
Thermal Resistance, θJA
7-Lead DDPAK, 7-Lead TO-220
±50
nA
nA/°C
nA
90
200
nV/√Hz
fA/√Hz
(V+) – 2.3
(V–) – 0.2
95
V
V
dB
107 || 6
109 || 4
Ω || pF
Ω || pF
98
90
dB
dB
1
10
See Typical Characteristics
15
0.02(3)
MHz
V/µs
kHz
µs
%
(V+) – 3.7
(V–) + 3.3
(V+) – 2.1
(V–) + 1.0
V
V
V
V
A
Arms
See Typical Characteristics
0 to ±5
ILIM = (15000)(4.75)/(13750Ω + RCL)
±100
±250
RCL = 14.8kΩ (ILIM = ±2.5A),
RL = 8Ω
A
A
mA
See Typical Characteristics(4)
Capacitive Load Drive
OUTPUT ENABLE /STATUS (E/S) PIN
Shutdown Input Mode
VE/S HIGH (output enabled)
VE/S LOW (output disabled)
IE/S HIGH (output enabled)
IE/S LOW (output disabled)
Output Disable Time
Output Enable Time
Thermal Shutdown Status Output
Normal Operation
Thermally Shutdown
Junction Temperature, Shutdown
Reset from Shutdown
100
E/S Pin Open or Forced High
E/S Pin Forced Low
E/S Pin High
E/S Pin Low
(V–) + 2.4
Sourcing 20µA
Sinking 5µA, TJ > 160°C
(V–) + 2.4
(V–) + 0.8
–65
–70
1
3
±4
ILIM Connected to V–, IO = 0
ILIM Connected to V–, IO = 0
(V–) + 3.5
(V–) + 0.35
+160
+140
±30
±17
±6
–40
–40
–55
(V–) + 0.8
V
V
µA
µA
µs
µs
V
V
°C
°C
±30
±20
V
V
mA
mA
+85
+125
+125
°C
°C
°C
f > 50Hz
dc
2
2.5
°C/W
°C/W
No Heat Sink
65
°C/W
NOTES: (1) High-speed test at TJ = +25°C. (2) Positive conventional current flows into the input terminals. (3) See “Total Harmonic Distortion+Noise vs Frequency” in
the Typical Characteristics section for additional power levels. (4) See “Small-Signal Overshoot vs Load Capacitance” in the Typical Characteristics section.
OPA548
SBOS070B
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3
TYPICAL CHARACTERISTICS
At TCASE = +25°C, VS = ±30V and E/S pin open, unless otherwise noted.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
100
RL = 8Ω
60
–45
RL = 8Ω
No
Load
–90
φ
20
–135
0
–180
Input Bias Current (nA)
G
40
–140
0
Phase (°)
80
Gain (dB)
INPUT BIAS CURRENT vs TEMPERATURE
–160
No Load
–100
10
100
1k
10k
100k
1M
VS = ±30V
–80
–60
–40
–75
–20
1
VS = ±5V
–120
10M
–50
–25
0
CURRENT LIMIT vs TEMPERATURE
±5
RCL = 14.7kΩ
±2
RCL = 57.6kΩ
±3
RCL = 57.6kΩ
0
–50
–25
0
25
50
75
100
0
125
±5
±10
±15
±20
–200
Quiescent Current (mA)
–150
–100
–50
VS = ±5V
±14
±12
±10
VS = ±30V
±8
IQ Shutdown
VS = ±5V
±4
–10
0
10
±30
VS = ±30V
IQ
±16
±6
–20
±25
QUIESCENT CURRENT vs TEMPERATURE
±18
Input Bias Current (nA)
±20
Supply Voltage (V)
INPUT BIAS CURRENT
vs COMMON-MODE VOLTAGE
20
–75
30
–50
–25
0
25
50
75
100
125
Temperature (°C)
Common-Mode Voltage (V)
4
125
±2
Temperature (°C)
0
–30
100
RCL = 14.7kΩ
±1
±1
0
–75
75
RCL = 4.02kΩ
±4
Current Limit (A)
Current Limit (A)
±3
50
CURRENT LIMIT vs SUPPLY VOLTAGE
±5
+ILIM
–ILIM
RCL = 4.02kΩ
±4
25
Temperature (°C)
Frequency (Hz)
OPA548
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SBOS070B
TYPICAL CHARACTERISTICS (Cont.)
At TCASE = +25°C, VS = ±30V and E/S pin open, unless otherwise noted.
POWER-SUPPLY REJECTION
vs FREQUENCY
COMMON-MODE REJECTION vs FREQUENCY
100
Power Supply Rejection (dB)
80
60
40
20
80
60
–PSRR
40
20
0
0
10
100
1k
10k
100k
10
1M
1k
10k
100k
1M
Frequency (Hz)
VOLTAGE NOISE DENSITY vs FREQUENCY
OPEN-LOOP GAIN, COMMON-MODE REJECTION,
AND POWER-SUPPLY REJECTION vs TEMPERATURE
100
110
AOL
400
95
AOL, PSRR (dB)
Voltage Noise (nV/√Hz)
100
Frequency (Hz)
500
300
200
105
90
100
PSRR
85
95
100
CMRR
80
–75
0
1
10
100
1k
10k
100k
1M
–50
–25
0
25
50
75
100
Frequency (Hz)
Temperature (°C)
GAIN-BANDWIDTH PRODUCT AND
SLEW RATE vs TEMPERATURE
TOTAL HARMONIC DISTORTION+NOISE
vs FREQUENCY
1.25
13
G = +3
RL = 8Ω
GBW
20W
12
0.75
11
SR+
0.5
10
0.25
10W
0.1
THD+N (%)
1
90
125
1
Slew Rate (V/µs)
Gain-Bandwidth Product (MHz)
+PSRR
CMRR (dB)
Common-Mode Rejection (dB)
100
0.1W
1W
0.01
9
SR–
0
–75
–50
–25
0
25
50
75
100
8
125
0.001
20
Temperature (°C)
1k
10k
20k
Frequency (Hz)
OPA548
SBOS070B
100
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5
TYPICAL CHARACTERISTICS (Cont.)
At TCASE = +25°C, VS = ±30V and E/S pin open, unless otherwise noted.
OUTPUT VOLTAGE SWING vs TEMPERATURE
5
4
4
VSUPPLY – VOUT (V)
VSUPPLY– VOUT (V)
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
5
(V+) –VO
3
(V–) –VO
2
1
IO = +3A
IO = –3A
3
2
IO = +0.6A
1
IO = –0.6A
0
0
0
1
2
3
–75
4
–25
0
25
OUTPUT LEAKAGE CURRENT
vs APPLIED OUTPUT VOLTAGE
125
15
10
RCL = ∞
Leakage Current (mA)
20
RL = 8Ω
5
RCL = 0
0
–5
Output Disabled
VE/S < (V–) + 0.8V
0
1k
10k
100k
–10
–40
1M
–30
–20
–10
0
10
20
Frequency (Hz)
Output Voltage (V)
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
20
14
Typical distribution
of packaged units.
16
14
12
10
8
6
4
30
40
Typical production
distribution of
packaged units.
12
Percent of Amplifiers (%)
Percent of Amplifiers (%)
100
10
Maximum Output
Voltage Without
Slew Rate Induced
Distortion
5
10
8
6
4
2
2
0
0
–10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10
Offset Voltage (mV)
6
75
MAXIMUM OUTPUT VOLTAGE SWING
vs FREQUENCY
25
18
50
Temperature (°C)
30
Output Voltage (Vp)
–50
Output Current (A)
0
10 20 30 40 50 60 70 80 90 100 110 120 130
Offset Voltage Drift (µV/°C)
OPA548
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SBOS070B
TYPICAL CHARACTERISTICS (Cont.)
At TCASE = +25°C, VS = ±30V and E/S pin open, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
G = 3, CL = 1000pF, RL = 8Ω
SMALL-SIGNAL OVERSHOOT
vs LOAD CAPACITANCE
50
G = +1
30
10V/div
Overshoot (%)
40
20
G = –1
10
0
0
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
5µs/div
Load Capacitance (pF)
SMALL-SIGNAL STEP RESPONSE
G = 3, CL = 1000pF
50mV/div
100mV/div
SMALL-SIGNAL STEP RESPONSE
G = 1, CL = 1000pF
2µs/div
2µs/div
OPA548
SBOS070B
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7
APPLICATIONS INFORMATION
Figure 1 shows the OPA548 connected as a basic noninverting
amplifier. The OPA548 can be used in virtually any op amp
configuration.
Power-supply terminals should be bypassed with low series
impedance capacitors. The technique shown in Figure 7,
using a ceramic and tantalum type in parallel is recommended. In addition, we recommend a 0.01µF capacitor
between V+ and V– as close to the OPA548 as possible.
Power-supply wiring should have low series impedance.
V+
10µF
+
G = 1+
0.1µF(2)
R1
R2
R1
2
VIN
OPA548
6
3
1
ILIM(1)
4
(15000)(4.75) – 13750Ω
(1)
ILIM
The low-level control signal (0µA to 330µA) also allows the
current limit to be digitally controlled.
See Figure 3 for a simplified schematic of the internal
circuitry used to set the current limit. Leaving the ILIM pin
open programs the output current to zero, while connecting
ILIM directly to V– programs the maximum output current limit,
typically 5A.
Stress on the output transistors is determined both by the
output current and by the output voltage across the conducting output transistor, VS – VO. The power dissipated by the
output transistor is equal to the product of the output current
and the voltage across the conducting transistor, VS – VO.
The Safe Operating Area (SOA curve, Figure 2) shows the
permissible range of voltage and current.
E/S
7
R CL =
SAFE OPERATING AREA
R2
5
With the OPA548, the simplest method for adjusting the
current limit uses a resistor or potentiometer connected
between the ILIM pin and V– according to the Equation 1:
VO
ZL
0.1µF(2)
0.01µF(2)
10µF
+
SAFE OPERATING AREA
10
Current-Limited
V–
Output Current (A)
NOTES: (1) ILIM connected to V– gives the maximum
current limit, 5A (peak). (2) Connect capacitors directly to
package power-supply pins.
FIGURE 1. Basic Circuit Connections.
POWER SUPPLIES
The OPA548 operates from single (+8V to +60V) or dual
(±4V to ±30V) supplies with excellent performance. Most
behavior remains unchanged throughout the full operating
voltage range. Parameters which vary significantly with operating voltage are shown in the typical characteristic curves.
Some applications do not require equal positive and negative
output voltage swing. Power-supply voltages do not need to
be equal. The OPA548 can operate with as little as 8V
between the supplies and with up to 60V between the
supplies. For example, the positive supply could be set to
55V with the negative supply at –5V, or vice-versa.
ADJUSTABLE CURRENT LIMIT
The OPA548 features an accurate, user-selected current
limit. Current limit is set from 0A to 5A by controlling the input
to the ILIM pin. Unlike other designs which use a power
resistor in series with the output current path, the OPA548
senses the load indirectly. This allows the current limit to be
set with a 0µA to 330µA control signal. In contrast, other
designs require a limiting resistor to handle the full output
current (5A in this case).
8
TC = 25°C
=5
PD
0W
=2
6W
PD
Output current can
be limited to less
than 3A—see text.
1
PD
=1
0W
TC = 85°C
Pulse Operation Only
T = 125°C
(Limit rms current to ≤ 3A) C
0.1
1
2
5
10
20
50
100
VS – VO (V)
FIGURE 2. Safe Operating Area.
The safe output current decreases as VS – VO increases.
Output short-circuits are a very demanding case for SOA. A
short-circuit to ground forces the full power-supply voltage
(V+ or V–) across the conducting transistor. Increasing the
case temperature reduces the safe output current that can be
tolerated without activating the thermal shutdown circuit of
the OPA548. For further insight on SOA, consult Application
Bulletin SBOA022.
AMPLIFIER MOUNTING
Figure 4 provides recommended solder footprints for both the
TO-220 and DDPAK power packages. The tab of both packages is electrically connected to the negative supply, V–. It may
be desirable to isolate the tab of the TO-220 package from its
OPA548
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SBOS070B
RESISTOR METHOD
DAC METHOD (Current or Voltage)
Max IO = ILIM
±ILIM =
13750Ω
4.75V
(4.75) (15000)
Max IO = ILIM
13750Ω + RCL
±ILIM =15000 ISET
3
3
RCL
4
D/A
0.01µF
(optional, for noisy
environments)
4
V–
V–
RCL =
15000 (4.75V)
ILIM
13750Ω
4.75V
ISET
ISET = ILIM /15000
– 13750Ω
VSET = (V–) + 4.75V – (13750Ω) (ILIM)/15000
OPA547 CURRENT LIMIT: 0 to 5A
DESIRED
CURRENT LIMIT
RESISTOR(1)
(RCL)
CURRENT
(ISET)
VOLTAGE
(VSET)
0A
1A
2.5A
3A
4A
5A
ILIM Open
57.6kΩ
14.7kΩ
10kΩ
4.02kΩ
ILIM Connected to V–
0µA
67µA
167µA
200µA
267µA
333µA
(V–) + 4.75V
(V–) + 3.8V
(V–) + 2.5V
(V–) + 2V
(V–) + 1.1V
(V–)
NOTE: (1) Resistors are nearest standard 1% values.
FIGURE 3. Adjustable Current Limit.
DDPAK-7(1)
(Package Designator KTW)
TO220-7
(Package Designator KVT)
0.45
0.04
0.2
0.05
0.085
0.15
0.335
0.51
0.05
0.035
0.105
Mean dimensions in inches. Refer to end of data sheet
or www.ti.com for tolerances and detailed package
drawings.
NOTE: (1) For improved thermal performance increase footprint area.
See Figure 6, “Thermal Resistance vs Circuit Board Copper Area”.
FIGURE 4. TO-220 and DDPAK Solder Footprints.
mounting surface with a mica (or other film) insulator (see
Figure 5). For lowest overall thermal resistance it is best to
isolate the entire heat sink/OPA548 structure from the mounting surface rather than to use an insulator between the
semiconductor and heat sink.
For best thermal performance, the tab of the DDPAK surface-mount version should be soldered directly to a circuit
board copper area. Increasing the copper area improves
heat dissipation. See Figure 6 for typical thermal resistance
from junction-to-ambient as a function of the copper area.
POWER DISSIPATION
Power dissipation depends on power supply, signal, and load
conditions. For dc signals, power dissipation is equal to
the product of output current times the voltage across the
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9
THERMAL RESISTANCE
vs ALUMINUM PLATE AREA
Aluminum Plate Area
Thermal Resistance θJA (°C/W)
18
Vertically Mounted
in Free Air
Flat, Rectangular
Aluminum Plate
16
14
0.030in Al
12
0.050in Al
10
Aluminum
Plate Thickness
0.062in Al
8
0
1
2
3
4
5
6
7
Optional mica or film insulator
for electrical isolation. Adds
OPA548
approximately 1°C/W.
TO220 Package
8
Aluminum Plate Area (inches2)
FIGURE 5. TO-220 Thermal Resistance vs Aluminum Plate Area.
THERMAL RESISTANCE vs
CIRCUIT BOARD COPPER AREA
Thermal Resistance, θJA (°C/W)
50
Circuit Board Copper Area
OPA548F
Surface Mount Package
1oz copper
40
30
20
10
0
0
1
2
3
4
OPA548
Surface-Mount Package
5
Copper Area (inches2)
FIGURE 6. DDPAK Thermal Resistance vs Circuit Board Copper Area.
conducting output transistor. Power dissipation can be minimized by using the lowest possible power-supply voltage
necessary to assure the required output voltage swing.
For resistive loads, the maximum power dissipation occurs at
a dc output voltage of one-half the power-supply voltage.
Dissipation with ac signals is lower. Application Bulletin
SBOA022 explains how to calculate or measure power
dissipation with unusual signals and loads.
THERMAL PROTECTION
Power dissipated in the OPA548 will cause the junction
temperature to rise. The OPA548 has thermal shutdown
circuitry that protects the amplifier from damage. The thermal
protection circuitry disables the output when the junction
temperature reaches approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on load and signal conditions, the thermal protection
10
circuit may cycle on and off. This limits the dissipation of the
amplifier but may have an undesirable effect on the load.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat
sink. For reliable operation, junction temperature should be
limited to 125°C, maximum. To estimate the margin of safety
in a complete design (including heat sink) increase the
ambient temperature until the thermal protection is triggered.
Use worst-case load and signal conditions. For good reliability, thermal protection should trigger more than 35°C above
the maximum expected ambient condition of your application. This produces a junction temperature of 125°C at the
maximum expected ambient condition.
The internal protection circuitry of the OPA548 was designed
to protect against overload conditions. It was not intended to
replace proper heat sinking. Continuously running the OPA548
into thermal shutdown will degrade reliability.
OPA548
www.ti.com
SBOS070B
HEAT SINKING
Combining equations (1) and (2) gives:
Most applications require a heat sink to assure that the
maximum operating junction temperature (125°C) is not
exceeded. In addition, the junction temperature should be
kept as low as possible for increased reliability. Junction
temperature can be determined according to the equation:
TJ = TA + PDθJA
(1)
where, θJA = θJC + θCH + θHA
(2)
TJ = Junction Temperature (°C)
TA = Ambient Temperature (°C)
PD = Power Dissipated (W)
θJC = Junction-to-Case Thermal Resistance (°C/W)
θCH = Case-to-Heat Sink Thermal Resistance (°C/W)
θHA = Heat Sink-to-Ambient Thermal Resistance (°C/W)
θJA = Junction-to-Air Thermal Resistance (°C/W)
Figure 7 shows maximum power dissipation versus ambient
temperature with and without the use of a heat sink. Using a
heat sink significantly increases the maximum power dissipation at a given ambient temperature as shown.
The difficulty in selecting the heat sink required lies in
determining the power dissipated by the OPA548. For dc
output into a purely resistive load, power dissipation is simply
the load current times the voltage developed across the
conducting output transistor, PD = IL(VS–VO). Other loads are
not as simple. Consult Application Bulletin SBOA022 for
further insight on calculating power dissipation. Once power
dissipation for an application is known, the proper heat sink
can be selected.
Power Dissipation (Watts)
TO220 with Thermalloy
6030B Heat Sink
θ JA = 16.7°C/W
8
PD = (TJ (max) – TA) / θ JA
TJ (max) = 150°C
2
DDPAK or TO-220
θJA = 65°C/W (no heat sink)
0
0
25
50
θHA =
TJ – TA
– (θ JC + θ CH )
PD
θHA =
125°C – 40°C
– (2.5°C / W + 1°C / W ) = 13.5°C / W
5W
To maintain junction temperature below 125°C, the heat sink
selected must have a θHA less than 14°C/W. In other words,
the heat sink temperature rise above ambient must be less
than 67.5°C (13.5°C/W • 5W). For example, at 5W Thermalloy
model number 6030B has a heat sink temperature rise of
66°C above ambient (θHA = 66°C/5W = 13.2°C/W), which is
below the 67.5°C required in this example. Figure 7 shows
power dissipation versus ambient temperature for a TO-220
package with a 6030B heat sink.
Another variable to consider is natural convection versus
forced convection air flow. Forced-air cooling by a small fan
can lower θCA (θCH + θHA) dramatically. Heat sink manufactures provide thermal data for both of these cases. For
additional information on determining heat sink requirements,
consult Application Bulletin SBOA021.
The Enable/Status pin provides two functions: forcing this pin
LOW disables the output stage, or E/S can be monitored to
determine if the OPA548 is in thermal shutdown. One or both
of these functions can be utilized on the same device using
single or dual supplies. For normal operation (output enabled), the E/S pin can be left open or pulled HIGH (at least
2.4V above the negative rail). A small value capacitor connected between the E/S pin and V– may be required for noisy
applications.
DDPAK
θ JA = 26°C/W
(3 in2 one oz
copper mounting pad)
4
TJ, TA, and PD are given. θJC is provided in the specification
table, 2.5°C/W (dc). θCH can be obtained from the heat sink
manufacturer. Its value depends on heat sink size, area, and
material used. Semiconductor package type, mounting screw
torque, insulating material used (if any), and thermal
joint compound used (if any) also affect θCH. A typical θCH for
a TO-220 mounted package is 1°C/W. Now we can solve for
θHA:
ENABLE/STATUS (E/S) PIN
With infinite heat sink
( θJA = 2.5°C/W),
max PD = 50W at TA = 25°C.
6
(3)
As mentioned earlier, once a heat sink has been selected,
the complete design should be tested under worst-case load
and signal conditions to ensure proper thermal protection.
MAXIMUM POWER DISSIPATION
vs AMBIENT TEMPERATURE
10
TJ = TA + PD(θJC + θCH + θHA)
75
100
125
Ambient Temperature (°C)
Output Disable
FIGURE 7. Maximum Power Dissipation vs Ambient
Temperature.
Heat Sink Selection Example
A TO-220 package is dissipating 5W. The maximum expected ambient temperature is 40°C. Find the proper heat
sink to keep the junction temperature below 125°C (150°C
minus 25°C safety margin).
A unique feature of the OPA548 is its output disable capability. This function not only conserves power during idle periods (quiescent current drops to approximately 6mA), but also
allows multiplexing in low frequency (f < 20kHz), multichannel applications. Signals greater than 20kHz may cause
leakage current to increase in devices that are shutdown.
Figure 18 shows the two OPA548s in a switched amplifier
configuration. The on/off state of the two amplifiers is controlled by the voltage on the E/S pin.
OPA548
SBOS070B
www.ti.com
11
To disable the output, the E/S pin is pulled LOW, no greater
than 0.8V above the negative rail. Typically the output is
shutdown in 1µs. Figure 8 provides an example of how to
implement this function using a single supply. Figure 9 gives
a circuit for dual-supply applications. To return the output to an
enabled state, the E/S pin should be disconnected (open) or
pulled to at least (V–) + 2.4V. It should be noted that pulling the
E/S pin HIGH (output enabled) does not disable internal
thermal shutdown.
V+
5V
OPA548
2.49kΩ
E/S
TTL
V–
Zetex
ZVN3310
OR
HCT
V+
FIGURE 10. Thermal Shutdown Status with a Single Supply.
OPA548
E/S
5V
V+
V–
CMOS or TTL
1kΩ
OPA548
FIGURE 8. Output Disable with a Single Supply.
2N3906
E/S
22kΩ
470Ω
Zetex
ZVN3310
V+
V–
5V
FIGURE 11. Thermal Shutdown Status with Dual Supplies.
OPA548
E/S
1
(1)
6
Output Disable and Thermal Shutdown Status
5
As mentioned earlier, the OPA548’s output can be disabled
and the disable status can be monitored simultaneously.
Figures 12 and 13 provide examples interfacing to the E/S
pin while using a single supply and dual supplies, respectively.
1
4
HCT or TTL In
4N38
V–
Optocoupler
OUTPUT STAGE COMPENSATION
NOTE: (1) Optional—may be required to limit leakage
current of optocoupler at high temperatures.
FIGURE 9. Output Disable with Dual Supplies.
Thermal Shutdown Status
Internal thermal shutdown circuitry shuts down the output when
the die temperature reaches approximately 160°C, resetting
when the die has cooled to 140°C. The E/S pin can be
monitored to determine if shutdown has occurred. During
normal operation the voltage on the E/S pin is typically 3.5V
above the negative rail. Once shutdown has occurred, this
voltage drops to approximately 350mV above the negative rail.
Figure 10 gives an example of monitoring shutdown in a
single-supply application. Figure 11 provides a circuit for dual
supplies. External logic circuitry or an LED could be used to
indicate if the output has been thermally shutdown, see
Figure 16.
12
The complex load impedances common in power op amp
applications can cause output stage instability. For normal
operation output compensation circuitry is typically not required. However, if the OPA548 is intended to be driven into
current limit, an R/C network may be required. See Figure 14
for an output series R/C compensation (snubber) network
which generally provides excellent stability.
A snubber circuit may also enhance stability when driving
large capacitive loads (> 1000pF) or inductive loads (motors,
loads separated from the amplifier by long cables). Typically
3Ω to 10Ω in series with 0.01µF to 0.1µF is adequate. Some
variations in circuit value may be required with certain loads.
OUTPUT PROTECTION
Reactive and EMF-generating loads can return load current to the amplifier, causing the output voltage to exceed
the power-supply voltage. This damaging condition can be
OPA548
www.ti.com
SBOS070B
V+
V+
R1
5kΩ
R2
20kΩ
R2
= –4
R1
G=–
VIN
OPA548
D1
E/S
OPA548
V–
Open Drain
(Output Disable)
10Ω
(Carbon) Motor
D2
HCT
(Thermal Status
Shutdown)
0.01µF
V–
D1, D2 : Motorola MUR410.
FIGURE 12. Output Disable and Thermal Shutdown Status
with a Single Supply.
FIGURE 14. Motor Drive Circuit.
V+
5V
1
6
5V
OPA548
E/S
5
7.5kΩ
1W
1
6
2
(1)
Zetex
ZVN3310
5
TTL Out
4
4N38
Optocoupler
HCT or TTL In
2
4
4N38
Optocoupler
V–
NOTE: (1) Optional—may be required to limit leakage
current of optocoupler at high temperatures.
FIGURE 13. Output Disable and Thermal Shutdown Status with Dual Supplies.
avoided with clamp diodes from the output terminal to the
power supplies, as shown in Figure 14. Schottky rectifier
diodes with a 5A or greater continuous rating are recommended.
used as a voltage reference, thus eliminating the need for an
external reference. The feedback resistors are selected to
gain VCL to the desired output voltage level.
PROGRAMMABLE POWER SUPPLY
VOLTAGE SOURCE APPLICATION
Figure 15 illustrates how to use the OPA548 to provide an
accurate voltage source with only three external resistors.
First, the current limit resistor, RCL, is chosen according to
the desired output current. The resulting voltage at the ILIM
pin is constant and stable over temperature. This voltage,
VCL, is connected to the noninverting input of the op amp and
A programmable source/sink power supply can easily be
built using the OPA548. Both the output voltage and output
current are user-controlled. See Figure 16 for a circuit using
potentiometers to adjust the output voltage and current while
Figure 17 uses DACs. An LED tied to the E/S pin through a
logic gate indicates if the OPA548 is in thermal shutdown.
OPA548
SBOS070B
www.ti.com
13
R1
R2
V+
VO = VCL (1 + R2/R1)
4.75V
13750Ω
V–
IO =
VCL
15000 (4.75V)
13750Ω + RCL
ILIM
For Example:
RCL
0.01µF
(Optional, for noisy
environments)
If ILIM = 3A, RCL = 10kΩ
VCL =
10kΩ • 4.75V
= 2V
(10kΩ + 13750Ω)
Desired VO = 20V, G =
20
2
Uses voltage developed at ILIM pin
as a moderately accurate reference
voltage.
= 10
R1 = 1kΩ and R2 = 9kΩ
FIGURE 15. Voltage Source.
1kΩ
9kΩ
G=1+
+5V
9kΩ
= 10
1kΩ
+30V
10.5kΩ
5
2
V+
6
Output
Adjust
10kΩ
0.12V to 2.5V
VO = 1.2V to 25V(1)
IO = 0 to 5A
OPA548
1
4
3
7 E/S
74HCT04
ILIM
R ≥ 250Ω
499Ω
V–
+5V
V–
0V to 4.75V
Thermal
Shutdown Status
(LED)
1kΩ
Current
Limit
Adjust
20kΩ
0.01µF(2)
NOTES: (1) For VO ≤ 0V, V– ≤ –1V.
(2) Optional: Improves noise
immunity.
FIGURE 16. Resistor-Controlled Programmable Power Supply.
14
OPA548
www.ti.com
SBOS070B
1kΩ
9kΩ
–5V
OUTPUT ADJUST
VREF
+30V
G = 10
+5V
VREF A
+5V
RFB A
1/2
OPA2336
IOUT A
1/2 DAC7800/1/2(3)
VO = 0.8 to 25V(1)
OPA548
10pF
74HCT04
E/S
DAC A
AGND A
ILIM
IO = 0 to 5A
R ≥ 250Ω
V–
Thermal
Shutdown Status
(LED)
VREF B
RFB B
10pF
1/2
OPA2336
IOUT B
1/2 DAC7800/1/2(3)
DAC B
0.01µF(2)
DGND
AGND B
CURRENT LIMIT ADJUST
NOTES: (1) For VO ≤ 0V, V– ≤ –1V. (2) Optional, improves noise immunity. (3) Chose DAC780X based on
digital interface: DAC7800—12-bit interface, DAC7801—8-bit interface + 4 bits, DAC7802—serial
interface.
FIGURE 17. Digitally-Controlled Programmable Power Supply.
R1
R2
VIN1
OPA548
ILIM
AMP1
E/S
RCL2
RCL1
R3
VE/S
R4
Close for high current
(Could be open drain
output of a logic gate).
VO
VIN2
V–
AMP2
E/S
FIGURE 19. Multiple Current Limit Values.
VE/S > (V–) +2.4V: Amp 1 is on, Amp 2 if off
VO = –VIN1
OPA548
R2
( )
R1
ILIM
VE/S < (V–) +2.4V: Amp 2 is on, Amp 1 if off
VO = –VIN2
R4
( )
VO
As VO increases,
ILIM decreases.
RCL
R3
FIGURE 18. Switched Amplifier.
FIGURE 20. Single Quadrant V • I Limiting.
OPA548
SBOS070B
www.ti.com
15
R2
4kΩ
R1
1kΩ
V+
0.25Ω
800Ω
G= 1 +
4kΩ
1kΩ
= 5(1)
OPA548
ILIM
V–
VO
IO = 10A (peak)(2)
VIN
V+
800Ω
0.25Ω
OPA548
ILIM
V–
R3
1kΩ
R4
4kΩ
NOTES: (1) Works well for G < 10. Input offset causes output current to flow between amplifiers
with G > 10. Gains (resistor ratios) of the two amplifiers should be carefully matched to ensure
equal current sharing. (2) As configured (ILIM connected to V–) output current limit is set to 10A
(peak). Each amplifier is limited to 5A (peak). Other current limit values may be obtained, see
Figure 3, “Adjustable Current Limit”.
FIGURE 21. Parallel Output for Increased Output Current.
16
OPA548
www.ti.com
SBOS070B
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
OPA548F
OBSOLETE
DDPAK/
TO-263
KTW
7
OPA548F/500
ACTIVE
DDPAK/
TO-263
KTW
7
OPA548F/500G3
ACTIVE
DDPAK/
TO-263
KTW
OPA548FKTWT
ACTIVE
DDPAK/
TO-263
OPA548FKTWTG3
ACTIVE
OPA548T
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TBD
Call TI
Call TI
500
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
OPA548F
7
500
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
OPA548F
KTW
7
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
OPA548F
DDPAK/
TO-263
KTW
7
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
OPA548F
ACTIVE
TO-220
KVT
7
50
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 85
OPA548T
OPA548T-1
ACTIVE
TO-220
KC
7
50
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 85
OPA548T
OPA548T-1G3
ACTIVE
TO-220
KC
7
50
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 85
OPA548T
OPA548TG3
ACTIVE
TO-220
KVT
7
50
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 85
OPA548T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
11-Apr-2013
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
OPA548F/500
DDPAK/
TO-263
KTW
7
500
330.0
24.4
OPA548FKTWT
DDPAK/
TO-263
KTW
7
50
330.0
24.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.95
16.5
5.15
16.0
24.0
Q2
10.6
15.6
4.9
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA548F/500
DDPAK/TO-263
KTW
7
500
346.0
346.0
41.0
OPA548FKTWT
DDPAK/TO-263
KTW
7
50
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MPSF015 – AUGUST 2001
KTW (R-PSFM-G7)
PLASTIC FLANGE-MOUNT
0.410 (10,41)
0.385 (9,78)
0.304 (7,72)
–A–
0.006
–B–
0.303 (7,70)
0.297 (7,54)
0.0625 (1,587) H
0.055 (1,40)
0.0585 (1,485)
0.300 (7,62)
0.064 (1,63)
0.045 (1,14)
0.252 (6,40)
0.056 (1,42)
0.187 (4,75)
0.370 (9,40)
0.179 (4,55)
0.330 (8,38)
H
0.296 (7,52)
A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C
0.000 (0,00)
0.019 (0,48)
0.104 (2,64)
0.096 (2,44)
H
0.017 (0,43)
0.050 (1,27)
C
C
F
0.034 (0,86)
0.022 (0,57)
0.010 (0,25) M
B
0.026 (0,66)
0.014 (0,36)
0°~3°
AM C M
0.183 (4,65)
0.170 (4,32)
4201284/A 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSOT010 – OCTOBER 1994
KC (R-PSFM-T7)
PLASTIC FLANGE-MOUNT PACKAGE
0.156 (3,96)
0.146 (3,71)
0.420 (10,67)
0.380 (9,65)
DIA
0.113 (2,87)
0.103 (2,62)
0.185 (4,70)
0.175 (4,46)
0.055 (1,40)
0.045 (1,14)
0.147 (3,73)
0.137 (3,48)
0.335 (8,51)
0.325 (8,25)
1.020 (25,91)
1.000 (25,40)
1
7
0.125 (3,18)
(see Note C)
0.030 (0,76)
0.026 (0,66)
0.010 (0,25) M
0.050 (1,27)
0.300 (7,62)
0.122 (3,10)
0.102 (2,59)
0.025 (0,64)
0.012 (0,30)
4040251 / B 01/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Lead dimensions are not controlled within this area.
All lead dimensions apply before solder dip.
The center lead is in electrical contact with the mounting tab.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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