Cypress CY7C1423AV18-300BZXC 36-mbit ddr-ii sio sram 2-word burst architecture Datasheet

CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
36-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Features
Functional Description
• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
• 300-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configuration
The CY7C1422V18, CY7C1429AV18, CY7C1423V18,
CY7C1424V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II SIO (Double Data Rate Separate I/O)
architecture. The DDR-II SIO consists of two separate ports to
access the memory array. The Read port has dedicated Data
outputs and the Write port has dedicated Data inputs to
completely eliminate the need to “turn around’ the data bus
required with common I/O devices. Access to each port is
accomplished using a common address bus. Addresses for
Read and Write are latched on alternate rising edges of the
input (K) clock. Write data is registered on the rising edges of
both K and K. Read data is driven on the rising edges of C and
C if provided, or on the rising edge of K and K if C/C are not
provided. Each address location is associated with two 8-bit
words in the case of CY7C1422AV18, two 9-bit words in the
case of CY7C1429AV18, two 18-bit words in the case of
CY7C1423AV18, and two 36-bit words in the case of
CY7C1424AV18, that burst sequentially into or out of the
device.
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to
the two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR-II SIO
SRAM in the system design. Output data clocks (C/C) enable
maximum system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K/K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clock. Writes are conducted with on-chip
synchronous self-timed write circuitry.
CY7C1422AV18–4M x 8
CY7C1429AV18–4M x 9
CY7C1423AV18–2M x18
CY7C1424AV18–1M x 36
Selection Guide
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
300
278
250
200
167
MHz
Maximum Operating Current
825
775
700
600
500
mA
Cypress Semiconductor Corporation
Document Number: 38-05617 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 26, 2006
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Logic Block Diagram (CY7C1422AV18)
D[7:0]
8
K
CLK
Gen.
K
DOFF
2M x 8
Memory
Array
Write
Data Reg
Read Add. Decode
21
Write Add. Decode
Address
Register
A(20:0)
Write
Data Reg
2M x 8
Memory
Array
Control
Logic
Read Data Reg.
R/W
VREF
LD
NWS0
16
8
Reg.
Control
Logic
8
Reg. 8
LD
R/W
C
C
CQ
8
Reg.
NWS1
CQ
Q[7:0]
8
Logic Block Diagram (CY7C1429AV18)
D[8:0]
9
K
K
CLK
Gen.
DOFF
R/W
VREF
LD
BWS0
2M x 9
Memory
Array
Write
Data Reg
2M x 9
Memory
Array
Read Add. Decode
21
Write Add. Decode
Address
Register
A(20:0)
Write
Data Reg
Control
Logic
Read Data Reg.
18
Control
Logic
9
Reg.
9
Reg. 9
Reg.
9
Document Number: 38-05617 Rev. *C
LD
R/W
C
C
CQ
CQ
9
Q[8:0]
Page 2 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Logic Block Diagram (CY7C1423AV18)
18
20
K
CLK
Gen.
K
DOFF
R/W
VREF
LD
BWS0
1M x 18
Memory
Array
Write
Data Reg
1M x 18
Memory
Array
Read Add. Decode
Address
Register
A(19:0)
Write
Data Reg
Write Add. Decode
D[17:0]
Control
Logic
Read Data Reg.
36
CQ
CQ
18
Reg.
Control
Logic
LD
R/W
C
C
18
Reg. 18
18
Reg.
BWS1
Q[17:0]
18
Logic Block Diagram (CY7C1424AV18)
36
19
K
K
CLK
Gen.
DOFF
R/W
VREF
LD
BWS[3:0]
Write
Data Reg
512K x 36 152K x 36
Memory
Memory
Array
Array
Read Add. Decode
Address
Register
A(18:0)
Write
Data Reg
Write Add. Decode
D[35:0]
Control
Logic
Read Data Reg.
72
Control
Logic
Reg.
Reg. 36
Reg.
36
Document Number: 38-05617 Rev. *C
CQ
CQ
36
36
LD
R/W
C
C
36
Q[35:0]
Page 3 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Pin Configurations
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1422AV18 (4M x 8)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
CQ
NC
NC/72M
A
NC
NC
NC
NC
NC
D4
NC
NC
NC
4
5
6
7
8
9
10
11
R/W
NWS1
K
NC/144M
LD
A
A
CQ
A
NC/288M
K
NWS0
A
NC
NC
Q3
NC
NC
VSS
VSS
A
A
VSS
A
VSS
VSS
VSS
NC
VSS
NC
NC
NC
D3
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
DOFF
NC
Q5
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
D5
VREF
NC
NC
VREF
Q1
NC
NC
ZQ
D1
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
NC
NC
NC
D7
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
D0
NC
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1429AV18 (4M x 9)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
CQ
NC/72M
A
R/W
NC
K
NC/144M
LD
A
A
CQ
NC
NC
NC
A
NC/288M
K
NC
NC
Q3
NC
D4
NC
NC
VSS
VSS
A
VSS
A
VSS
BWS0
A
VSS
A
NC
NC
VSS
VSS
NC
NC
NC
NC
D3
NC
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
NC
NC
NC
NC
VDDQ
VDD
VSS
DOFF
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
Q5
VDDQ
NC
VDD
VDD
VDD
VDD
VDDQ
D5
VREF
NC
NC
VREF
Q1
NC
NC
ZQ
D1
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
NC
NC
NC
D7
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
D0
NC
NC
NC
Q7
A
A
C
A
A
NC
D8
Q8
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Document Number: 38-05617 Rev. *C
Page 4 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Pin Configurations (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1423AV18 (2M x 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
CQ
NC
NC/144M
A
4
5
6
7
8
9
10
11
BWS1
K
NC/288M
LD
A
NC/72M
CQ
R/W
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
NC
NC
NC
D11
D10
Q10
VSS
VSS
A
A
VSS
A
VSS
VSS
VSS
NC
VSS
NC
Q7
NC
D8
D7
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
NC
NC
Q12
D12
DOFF
NC
D13
VREF
NC
Q13
VDDQ
D14
VDDQ
VDD
VSS
VDD
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
VDDQ
VDDQ
VDDQ
NC
VREF
Q4
Q5
D5
ZQ
D4
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
NC
NC
NC
D17
D16
Q16
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
Q1
NC
D2
D1
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
8
9
10
11
LD
A
A
NC/144M
CQ
D17
Q17
Q8
VSS
VSS
D16
Q16
Q7
D15
D8
D7
CY7C1424AV18 (1M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
2
3
NC/288M NC/72M
5
6
7
R/W
4
BWS2
K
BWS1
A
BWS3
A
VSS
K
A
VSS
BWS0
A
VSS
Q18
D18
Q28
D20
D19
Q19
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
Q30
D30
Q21
D21
VDDQ
VDD
VSS
VDDQ
DOFF
D31
Q22
VDDQ
D23
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
D14
Q13
VDDQ
D12
Q14
D22
VREF
Q31
VDD
VDD
VDD
VDD
D13
VREF
Q4
Q5
D5
ZQ
D4
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
D33
D34
Q34
D26
D25
Q25
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D10
Q10
Q1
D9
D2
D1
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
D27
D28
Document Number: 38-05617 Rev. *C
VSS
VSS
Page 5 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
InputSynchronous
LD
InputSynchronous
Data Input signals, sampled on the rising edge of K and K clocks during valid Write
operations.
CY7C1422AV18 − D[7:0]
CY7C1429AV18 − D[8:0]
CY7C1423AV18 − D[17:0]
CY7C1424AV18 − D[35:0]
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data (one period of bus activity).
NWS[1:0]
InputSynchronous
Nibble Write Select 0, 1 − active LOW (CY7C1422AV18 only). Sampled on the rising edge of
the K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
BWS[3:0]
InputSynchronous
Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K
clocks during Write operations. Used to select which byte is written into the device during the
current portion of the Write operations. Bytes not written remain unaltered.
CY7C1429AV18 − BWS0 controls D[8:0].
CY7C1423AV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1424AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and
BWS3 controls D[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
InputSynchronous
Address Inputs. Sampled on the rising edge of the K clock during active Read and Write
operations. These address inputs are multiplexed for both Read and Write operations. Internally,
the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1422AV18, 4M x 9 (2 arrays
each of 2M x 9) for CY7C1424AV18, 2M x 18 (two arrays each of 1M x 18) for CY7C1429AV18
and 1M x 36 (2 arrays each of 512K x 36) for CY7C1423AV18. Therefore only 21 address inputs
are needed to access the entire memory array of CY7C1422AV18 and CY7C1424AV18, 20
address inputs for CY7C1423AV18, and 19 address inputs for CY7C1424AV18. These inputs
are ignored when the appropriate port is deselected.
Q[x:0]
OutputSynchronous
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K
and K when in single clock mode. When Read access is deselected, Q[x:0] are automatically
tri-stated.
CY7C1422AV18 − Q[7:0]
CY7C1429AV18 − Q[8:0]
CY7C1423AV18 − Q[17:0]
CY7C1424AV18 − Q[35:0]
R/W
InputSynchronous
Synchronous Read/Write Input: When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up
and hold times around edge of K.
C
OutputClock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
C
OutputClock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
K
InputClock
Positive Input Clock for Output Data. The rising edge of K is used to capture synchronous
inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
K
InputClock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
Document Number: 38-05617 Rev. *C
Page 6 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
CQ
Echo Clock
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
VREF
VDD
N/A
InputReference
Power Supply Power supply inputs to the core of the device.
Ground
VSS
VDDQ
Not connected to the die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Outputs as well as AC measurement points.
Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
Functional Overview
The CY7C1422AV18, CY7C1424AV18, CY7C1429AV18,
CY7C1423AV18 are synchronous pipelined Burst SRAMs
equipped with a DDR-II Separate I/O interface.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the rising edge of the output clocks, C/C (or
K/K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of input clocks (K and
K). All synchronous data outputs (Q[x:0]) pass through output
registers controlled by the rising edge of the output clocks, C/C
(or K/K when in single clock mode). All synchronous control
(R/W, LD, BWS[x:0]) inputs pass through input registers
controlled by the rising edge of the input clock (K).
CY7C1423AV18 is described in the following sections. The
same basic descriptions apply to CY7C1422AV18,
CY7C1429AV18, and CY7C1424AV18.
Read Operations
The CY7C1429AV18 is organized internally as two arrays of
1M x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
Document Number: 38-05617 Rev. *C
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the Address inputs is
stored in the Read address register. Following the next K clock
rise the corresponding lowest-order 18-bit word of data is
driven onto the Q[17:0] using C as the output timing reference.
On the subsequent rising edge of C the next 18-bit data word
is driven onto the Q[17:0]. The requested data will be valid
0.45 ns from the rising edge of the output clock (C or C, or K
or K when in single clock mode, for 250-MHz and 200-MHz
devices). Read accesses can be initiated on every K clock
rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output
clocks, C/C (or K/K when in single clock mode).
When Read access is deselected, the CY7C1429AV18 will
first complete the pending Read transactions. Synchronous
internal circuitry will automatically tri-state the outputs
following the next rising edge of the positive output clock (C).
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). On the
following K clock rise the data presented to D[17:0] is latched
and stored into the lower 18-bit Write Data register provided
BWS[1:0] are both asserted active. On the subsequent rising
edge of the negative input clock (K), the information presented
to D[17:0] is also stored into the Write Data register provided
Page 7 of 28
[+] Feedback
CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
BWS[1:0] are both asserted active. Write accesses can be
initiated on every rising edge of input clock (K). Doing so
pipelines the data flow so that 18 bits of data are written into
the device on every rising edge of both input clocks (K and K).
When Write access is deselected, the device will ignore all
data inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1429AV18.
A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each set of 18-bit
data words. Asserting the appropriate Byte Write Select input
during the data portion of a Write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1429AV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation. The
echo clocks are synchronized to input clocks K/K in this mode.
DDR Operation
The CY7C1429AV18 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and double DDR mode of operation. If a Read occurs after a
Write cycle, address and data for the Write are stored in
registers. The write information must be stored because the
SRAM can not perform the last word Write to the array without
conflicting with the Read. The data stays in this register until
the next Write cycle occurs. On the first Write cycle after the
Read(s), the stored data from the earlier Write will be written
into the SRAM array. This is called a Posted Write.
Document Number: 38-05617 Rev. *C
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the Separate I/O DDR. In the single clock mode, CQ is
generated with respect to K and CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC
Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note “DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+”.
Page 8 of 28
[+] Feedback
CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Application Example[1]
SRAM 1
Vt
D
A
R
B
W
B
S
LD
R/W W
LDR/W
## ## ##
SRAM 4
ZQ
Q
CQ
CQ#
C C# K K#
R = 250 Ohms
B
W
LD R/W S
# # #
D
A
DATA IN
DATA OUT
Address
LD#
R/W#
BWS#
R
ZQ
Q
CQ
CQ#
C C# K K#
R = 250 Ohms
Vt
Vt
BUS
MASTER SRAM 1 Input CQ
(CPU SRAM 1 Input CQ#
SRAM 4 Input CQ
or
ASIC) SRAM 4 Input CQ#
Source K
Source K#
Delayed K
Delayed K#
R
R = 50 Ohms
Vt = VREF
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
Write Cycle:
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
L-H
L
L
D(A + 0) at K(t + 1) ↑
D(A + 1) at K(t + 1) ↑
Read Cycle:
Load address; wait one and a half cycle; read data
on consecutive C and C rising edges.
L-H
L
H
Q(A + 0) at C(t + 1) ↑
Q(A + 1) at C(t + 2) ↑
L-H
H
X
High-Z
High-Z
Stopped
X
X
Previous State
Previous State
NOP: No Operation
Standby: Clock Stopped
DQ
DQ
Notes:
1. The above application shows four DDR-II SIO being used.
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document Number: 38-05617 Rev. *C
Page 9 of 28
[+] Feedback
CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Write Cycle Descriptions (CY7C1422AV18 and CY7C1429AV18) [2, 8]
BWS0/NWS0
BWS1/NWS1
K
K
L
L
L-H
-
L
L
-
L
H
L-H
L
H
-
H
L
L-H
H
L
–
H
H
L-H
H
H
–
Comments
During the Data portion of a Write sequence:
CY7C1422AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1423AV18 − both bytes (D[17:0]) are written into the device.
L-H During the Data portion of a Write sequence:
CY7C1422AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1423AV18 − both bytes (D[17:0]) are written into the device.
-
During the Data portion of a Write sequence:
CY7C1422AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]
will remain unaltered,
CY7C1423AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9]
will remain unaltered.
L-H During the Data portion of a Write sequence:
CY7C1422AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]
will remain unaltered,
CY7C1423AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9]
will remain unaltered.
–
During the Data portion of a Write sequence:
CY7C1422AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]
will remain unaltered,
CY7C1423AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0]
will remain unaltered.
L-H During the Data portion of a Write sequence:
CY7C1422AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]
will remain unaltered,
CY7C1423AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0]
will remain unaltered.
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
Note:
8. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1422AV18 and CY7C1429AV18 and also
BWS2, BWS3 in the case of CY7C1423AV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
Document Number: 38-05617 Rev. *C
Page 10 of 28
[+] Feedback
CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Write Cycle Descriptions (CY7C1424AV18)[2, 8]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L-H
–
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L-H
L
H
H
H
–
H
L
H
H
L-H
H
L
H
H
–
H
H
L
H
L-H
H
H
L
H
–
H
H
H
L
L-H
H
H
H
L
–
H
H
H
H
L-H
H
H
H
H
–
L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into
the device.
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
–
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
–
During the Data portion of a Write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] will remain unaltered.
–
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Write Cycle Descriptions (CY7C1429AV18)[2, 8]
BWS0
K
K
Comments
L
L-H
–
During the Data portion of a Write sequence, the single byte (D[8:0]) is written into
the device.
L
–
H
L-H
H
–
Document Number: 38-05617 Rev. *C
L-H During the Data portion of a Write sequence, the single byte (D[8:0]) is written into
the device.
–
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Page 11 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VSS) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document Number: 38-05617 Rev. *C
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Page 12 of 28
[+] Feedback
CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit
#108. When this scan cell, called the “extest output bus
tri-state”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control
the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable
the output buffers to drive the output bus. When LOW, this bit
will place the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Document Number: 38-05617 Rev. *C
Page 13 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
TAP Controller State Diagram[9]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note:
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 38-05617 Rev. *C
Page 14 of 28
[+] Feedback
CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30 29
.
.
2
Identification Register
106 .
.
.
.
2
1
0
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[10, 15, 17]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 µA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
0.65VDD
VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.35VDD
V
IX
Input and OutputLoad Current
–5
5
µA
GND ≤ VI ≤ VDD
TAP AC Switching Characteristics Over the Operating Range[11,12]
Parameter
Description
Min.
Max.
Unit
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
50
ns
20
MHz
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
ns
Notes:
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
12. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05617 Rev. *C
Page 15 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
TAP AC Switching Characteristics Over the Operating Range[11,12] (continued)
Parameter
Description
Min.
Max.
Unit
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions[12]
0.9V
50Ω
ALL INPUT PULSES
TDO
1.8V
Z0 = 50Ω
0.9V
CL = 20 pF
0V
(a)
GND
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
Document Number: 38-05617 Rev. *C
tTDOX
Page 16 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Identification Register Definitions
Value
Instruction Field
CY7C1422AV18
CY7C1424AV18
CY7C1429AV18
CY7C1423AV18
Description
Revision Number
(31:29)
000
000
000
000
Version number.
Cypress Device ID 11010100010000111
(28:12)
Cypress JEDEC
ID (11:1)
11010100010001111 11010100010010111 11010100010100111 Defines the type
of SRAM.
00000110100
00000110100
00000110100
00000110100
Allows unique
identification of
SRAM vendor.
1
1
1
1
Indicate the
presence of an
ID register.
ID Register
Presence (0)
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Document Number: 38-05617 Rev. *C
Page 17 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
11
10N
39
11D
67
1C
95
3M
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
24
9K
52
8A
80
1F
108
Internal
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document Number: 38-05617 Rev. *C
Page 18 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Power-Up Sequence in DDR-II SRAM[13, 14]
DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
• Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
— Apply VDD before VDDQ
— Apply VDDQ before VREF or at the same time as VREF
DLL Constraints
• DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
tKC Var
• The DLL will function at frequencies down to 80 MHz
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
• After the power and clock (K, K, C, C) are stable take DOFF
HIGH
• The additional 1024 cycles of clocks are required for the
DLL to lock
~
~
Power-up Waveforms
K
K
~
~
Unstable Clock
> 1024 Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
Notes:
13. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
14. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Document Number: 38-05617 Rev. *C
Page 19 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015)... > 2001V
(Above which the useful life may be impaired.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied .. –55°C to +125°C
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC Voltage Applied to Outputs
in High-Z State .................................... –0.5V to VDDQ + 0.3V
Range
Com’l
Ind’l
Ambient
Temperature
VDD[16]
VDDQ[16]
0°C to +70°C
1.8 ± 0.1V
1.4V to VDD
–40°C to +85°C
DC Input Voltage[15] ............................ –0.5V to VDDQ + 0.3V
Electrical Characteristics Over the Operating Range[17]
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
Note 18
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 19
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH = −0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage[15]
VREF + 0.1
VDDQ + 0.3
V
VIL
Input LOW Voltage[15]
–0.3
VREF – 0.1
V
IX
Input Load Current
GND ≤ VI ≤ VDDQ
–5
5
µA
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
–5
5
µA
Voltage[20]
VREF
Input Reference
IDD
VDD Operating Supply
ISB1
Automatic
Power-down
Current
0.95
V
VDD = Max.,IOUT = 0 mA, 167 MHz
f = fMAX = 1/tCYC
200 MHz
Typical Value = 0.75V
500
mA
600
mA
250 MHz
700
mA
278 MHz
775
mA
300 MHz
825
mA
167 MHz
220
mA
200 MHz
230
mA
250 MHz
250
mA
278 MHz
260
mA
300 MHz
270
mA
Max.
Unit
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL,
f = fMAX = 1/tCYC,
Inputs Static
0.68
0.75
AC Input Requirements Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
VIH
Input HIGH Voltage
VREF + 0.2
–
–
V
VIL
Input LOW Voltage
–
–
VREF – 0.2
V
Notes:
15. Overshoot: VIH(AC) < VDD+0.85V (Pulse width less than tTCYC/2); Undershoot VIL(AC) > –1.5V (Pulse width less than tTCYC/2).
16. Power-up: Assumes a linear ramp from 0V to VDD(Min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
17. All voltage referenced to ground.
18. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
19. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
20. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54 VDDQ, whichever is smaller.
Document Number: 38-05617 Rev. *C
Page 20 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Capacitance[21]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CO
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
Max.
Unit
5
pF
4
pF
5
pF
Thermal Resistance[21]
Parameter
ΘJA
Description
Test Conditions
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
methods and procedures for measuring
Thermal Resistance (Junction to Case)
thermal impedance, per EIA/JESD51.
ΘJC
165 FBGA Package
Unit
17.2
°C/W
3.2
°C/W
AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
RL = 50Ω
VREF = 0.75V
ZQ
RQ =
250Ω
0.75V
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
5 pF
[22]
0.25V
Slew Rate = 2 V/ns
RQ =
250Ω
(a)
(b)
Notes:
21. Tested initially and after any design or process change that may affect these parameters.
22. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
Document Number: 38-05617 Rev. *C
Page 21 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Switching Characteristics Over the Operating Range[22,23]
Cypress Consortium
Parameter Parameter
300 MHz
Description
VDD(Typical) to the first
Access[24]
tPOWER
278 MHz
250 MHz
200 MHz
167 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1
–
1
tCYC
tKHKH
K Clock and C Clock
Cycle Time
3.30
tKH
tKHKL
Input Clock (K/K and C/C)
HIGH
1.32
–
1.4
tKL
tKLKH
Input Clock (K/K and C/C)
LOW
1.32
–
tKHKH
tKHKH
K Clock Rise to K Clock
Rise and C to C Rise
(rising edge to rising
edge)
1.49
–
tKHCH
tKHCH
K/K Clock Rise to C/C
Clock Rise (rising edge to
rising edge)
0.00
–
5.25 3.60 5.25
1
1
1
Unit
ms
4.0
6.3
5.0
7.9
6.0
8.4
ns
–
1.6
–
2.0
–
2.4
–
ns
1.4
–
1.6
–
2.0
–
2.4
–
ns
1.6
–
1.8
–
2.2
–
2.7
–
ns
0.0
1.8
0.0
2.2
0.0
2.7
ns
1.45 0.00 1.55
Set-up Times
tSA
tAVKH
Address Set-up to K Clock
Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tSC
tIVKH
Control Set-up to K Clock
Rise (LD, R/W)
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tSCDDR
tIVKH
Double Data Rate Control
Set-up to Clock (K, K)
Rise (BWS0, BWS1,
BWS2, BWS3)
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
tSD[25]
tDVKH
D[X:0] Set-up to Clock
(K/K) Rise
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
tHA
tKHAX
Address Hold after K
Clock Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tHC
tKHIX
Control Hold after K Clock
Rise (LD, R/W)
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tHCDDR
tKHIX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
tHD
tKHDX
Double Data Rate Control
Hold after Clock (K, K)
Rise (BWS0, BWS1,
BWS2, BWS3)
D[X:0] Hold after Clock
(K/K) Rise
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Notes:
23. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
24. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
25. For D2 data signal on CY7C1429AV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
Document Number: 38-05617 Rev. *C
Page 22 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Switching Characteristics Over the Operating Range[22,23] (continued)
Cypress Consortium
Parameter Parameter
300 MHz
Description
278 MHz
250 MHz
200 MHz
167 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
tCHCQV
C/C Clock Rise to Echo
Clock Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
tCQOH
tCHCQX
Echo Clock Hold after C/C –0.45
Clock Rise
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
tCQD
tCQHQV
Echo Clock High to Data
Change
–
0.27
–
0.27
–
0.30
–
0.35
–
0.40
ns
tCQDOH
tCQHQX
Echo Clock High to Data
Change
–0.27
–
–0.27
–
–0.30
–
–0.35
–
–0.40
–
ns
tCHZ
tCHQZ
Clock (C/C) Rise to
High-Z
(Active to High-Z)[26, 27]
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
tCLZ
tCHQX1
Clock (C/C) Rise to
Low-Z[26, 27]
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
–
0.20
–
0.20
–
0.20
–
0.20
–
0.20
ns
–
1024
–
1024
–
Cycles
tCO
tCHQV
C/C Clock Rise (or K/K in
single clock mode) to Data
Valid
tDOH
tCHQX
tCCQO
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
tKC lock
tKC lock
DLL Lock Time (K, C)
1024
–
1024
–
1024
tKC Reset
tKC Reset
K Static to DLL Reset
30
–
30
–
30
30
30
ns
Notes:
26. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
27. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document Number: 38-05617 Rev. *C
Page 23 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Switching Waveforms[28, 29, 30]
NOP
READ
(burst of 2)
2
1
READ
(burst of 2)
3
WRITE
(burst of 2)
5
WRITE
(burst of 2)
4
READ
(burst of 2)
6
NOP
7
8
K
tKH
tCYC
tKL
tKHKH
K
LD
t SC
tHC
R/W
A
A0
tSA
A1
A2
A3
A4
tHD
tHD
tHA
tSD
tSD
D
D20
Q00
Q
t KHCH
t
Q01
tCQD
t CLZ
Q10
D21
D31
Q11
Q40
Q41
tDOH
KHCH
tCO
D30
t CHZ
tCQDOH
C
tKH
tKL
tCYC
tKHKH
C#
tCQOH
tCCQO
CQ
tCQOH
tCCQO
CQ#
DON’T CARE
UNDEFINED
Notes:
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.
29. Output are disabled (High-Z) one clock cycle after a NOP.
30. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram
Document Number: 38-05617 Rev. *C
Page 24 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
167
Package
Diagram
Ordering Code
CY7C1422AV18-167BZC
Operating
Range
Package Type
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1429AV18-167BZC
CY7C1423AV18-167BZC
CY7C1424AV18-167BZC
CY7C1422AV18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-167BZXC
CY7C1423AV18-167BZXC
CY7C1424AV18-167BZXC
CY7C1422AV18-167BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1429AV18-167BZI
CY7C1423AV18-167BZI
CY7C1424AV18-167BZI
CY7C1422AV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-167BZXI
CY7C1423AV18-167BZXI
CY7C1424AV18-167BZXI
200
CY7C1422AV18-200BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1429AV18-200BZC
CY7C1423AV18-200BZC
CY7C1424AV18-200BZC
CY7C1422AV18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-200BZXC
CY7C1423AV18-200BZXC
CY7C1424AV18-200BZXC
CY7C1422AV18-200BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1429AV18-200BZI
CY7C1423AV18-200BZI
CY7C1424AV18-200BZI
CY7C1422AV18-200BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-200BZXI
CY7C1423AV18-200BZXI
CY7C1424AV18-200BZXI
250
CY7C1422AV18-250BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1429AV18-250BZC
CY7C1423AV18-250BZC
CY7C1424AV18-250BZC
CY7C1422AV18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-250BZXC
CY7C1423AV18-250BZXC
CY7C1424AV18-250BZXC
Document Number: 38-05617 Rev. *C
Page 25 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
250
Package
Diagram
Ordering Code
CY7C1422AV18-250BZI
Operating
Range
Package Type
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1429AV18-250BZI
CY7C1423AV18-250BZI
CY7C1424AV18-250BZI
CY7C1422AV18-250BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-250BZXI
CY7C1423AV18-250BZXI
CY7C1424AV18-250BZXI
278
CY7C1422AV18-278BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1429AV18-278BZC
CY7C1423AV18-278BZC
CY7C1424AV18-278BZC
CY7C1422AV18-278BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-278BZXC
CY7C1423AV18-278BZXC
CY7C1424AV18-278BZXC
CY7C1422AV18-278BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1429AV18-278BZI
CY7C1423AV18-278BZI
CY7C1424AV18-278BZI
CY7C1422AV18-278BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-278BZXI
CY7C1423AV18-278BZXI
CY7C1424AV18-278BZXI
300
CY7C1422AV18-300BZC
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1429AV18-300BZC
CY7C1423AV18-300BZC
CY7C1424AV18-300BZC
CY7C1422AV18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-300BZXC
CY7C1423AV18-300BZXC
CY7C1424AV18-300BZXC
CY7C1422AV18-300BZI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1429AV18-300BZI
CY7C1423AV18-300BZI
CY7C1424AV18-300BZI
CY7C1422AV18-300BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1429AV18-300BZXI
CY7C1423AV18-300BZXI
CY7C1424AV18-300BZXI
Document Number: 38-05617 Rev. *C
Page 26 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Package Diagram
165-ball FBGA (15 x 17 x 1.40 mm) (51-85195)
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#
51-85195-*A
QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC
and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective
holders.
Document Number: 38-05617 Rev. *C
Page 27 of 28
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CY7C1422AV18
CY7C1429AV18
CY7C1423AV18
CY7C1424AV18
Document History Page
Document Title: CY7C1422AV18/CY7C1429AV18/CY7C1423AV18/CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Document Number: 38-05617
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
247331
See ECN
SYT
New Data Sheet
*A
326519
See ECN
SYT
Removed CY7C1429AV18 from the title
Included 300 MHz Speed grade
Replaced TBDs with their respective values for IDD and ISB1
Added Industrial temperature
Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 17.2°C/W
and ΘJC = 3.2°C/W
Replaced TBDs in the Capacitance Table to their respective values for the
165 FBGA Package
Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS
TRI-STATE on Page 17
Added lead-free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
*B
413953
See ECN
NXR
Converted from preliminary to final
Added CY7C1429AV18 part number to title
Added 278-MHz speed Bin
Changed C, C Description in Feature Section and Pin Description
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Added Power-up sequence and Wave form on page# 18
Added Footnote# 13, 14, 15 on page# 18
Replaced Three-state with Tri-state
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 19
Modified the IDD and ISB values
Modified test condition in Footnote #17 on page# 19 from VDDQ < VDD to
VDDQ < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*C
468029
See ECN
NXR
Modified the ZQ Definition from Alternately, this pin can be connected directly
to VDD to Alternately, this pin can be connected directly to VDDQ
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH,
tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC
Switching Characteristics table
Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Updated the Typo in the AC Switching Characteristics Table
Updated the Ordering Information Table
Document Number: 38-05617 Rev. *C
Page 28 of 28
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