IRLR9343 IRLU9343 IRLU9343-701 D-Pak IRLR9343 Features I-Pak IRLU9343 D Advanced Process Technology l Key Parameters Optimized for Class-D Audio Amplifier Applications l Low RDSON for Improved Efficiency l Low Qg and Qsw for Better THD and Improved Efficiency l Low Qrr for Better THD and Lower EMI l 175°C Operating Junction Temperature for Ruggedness l Repetitive Avalanche Capability for Robustness and Reliability l Multiple Package Options l G S Key Parameters VDS RDS(ON) typ. @ VGS = -10V RDS(ON) typ. @ VGS = -4.5V Qg typ. TJ max -55 93 150 31 175 V m: m: nC °C Absolute Maximum Ratings Max. Units VDS Drain-to-Source Voltage Parameter -55 V VGS Gate-to-Source Voltage Continuous Drain Current, VGS @ -10V -20 ID @ TC = 25°C ID @ TC = 100°C ±20 -14 IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current c PD @TC = 25°C Power Dissipation 79 PD @TC = 100°C Power Dissipation 39 TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range A -60 W 0.53 -40 to + 175 W/°C °C ––– N Clamping Pressure h Thermal Resistance Typ. Max. RθJC Junction-to-Case g Parameter ––– 1.9 RθJA Junction-to-Ambient (PCB Mounted) gj Junction-to-Ambient (free air) g ––– 50 ––– 110 RθJA 2014-8-16 1 Units °C/W www.kersemi.com IRLR/U9343 & IRLU9343-701 Electrical Characteristics @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units BVDSS Drain-to-Source Breakdown Voltage -55 ––– ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– -52 ––– RDS(on) Static Drain-to-Source On-Resistance ––– 93 105 ––– 150 170 VGS(th) Gate Threshold Voltage -1.0 ––– ––– V ∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -3.7 ––– mV/°C IDSS Drain-to-Source Leakage Current µA ––– V Conditions VGS = 0V, ID = -250µA mV/°C Reference to 25°C, ID = -1mA mΩ VGS = -10V, ID = -3.4A e VGS = -4.5V, ID = -2.7A e VDS = VGS, ID = -250µA ––– ––– -2.0 ––– ––– -25 Gate-to-Source Forward Leakage ––– ––– -100 Gate-to-Source Reverse Leakage ––– ––– 100 gfs Forward Transconductance 5.3 ––– ––– Qg Total Gate Charge ––– 31 47 Qgs Gate-to-Source Charge ––– 7.1 ––– VDS = -44V VGS = -10V Qgd Gate-to-Drain Charge ––– 8.5 ––– ID = -14A Qgodr Gate Charge Overdrive ––– 15 ––– See Fig. 6 and 19 td(on) Turn-On Delay Time ––– 9.5 ––– VDD = -28V, VGS = -10Ve tr Rise Time ––– 24 ––– td(off) Turn-Off Delay Time ––– 21 ––– tf Fall Time ––– 9.5 ––– Ciss Input Capacitance ––– 660 ––– Coss Output Capacitance ––– 160 ––– Crss Reverse Transfer Capacitance ––– 72 ––– ƒ = 1.0MHz, Coss Effective Output Capacitance ––– 280 ––– VGS = 0V, VDS = 0V to -44V LD Internal Drain Inductance ––– 4.5 ––– Between lead, LS Internal Source Inductance ––– 7.5 ––– IGSS VDS = -55V, VGS = 0V VDS = -55V, VGS = 0V, TJ = 125°C nA VGS = -20V S VDS = -25V, ID = -14A VGS = 20V ID = -14A ns RG = 2.5Ω VGS = 0V pF nH VDS = -50V See Fig.5 6mm (0.25in.) from package and center of die contact f Avalanche Characteristics Typ. Max. Units EAS Single Pulse Avalanche Energyd Parameter ––– 120 mJ IAR Avalanche Currenti See Fig. 14, 15, 17a, 17b EAR Repetitive Avalanche Energy i A mJ Diode Characteristics Parameter IS @ TC = 25°C Continuous Source Current Min. Typ. Max. Units ––– ––– -20 ISM (Body Diode) Pulsed Source Current ––– ––– -60 VSD (Body Diode)c Diode Forward Voltage ––– ––– -1.2 trr Reverse Recovery Time ––– 57 86 ns Qrr Reverse Recovery Charge ––– 120 180 nC 2014-8-16 A 2 Conditions MOSFET symbol V showing the integral reverse D G S p-n junction diode. TJ = 25°C, IS = -14A, VGS = 0V e TJ = 25°C, IF = -14A di/dt = 100A/µs e www.kersemi.com IRLR/U9343 & IRLU9343-701 100 100 10 BOTTOM TOP -I D, Drain-to-Source Current (A) -I D, Drain-to-Source Current (A) TOP VGS -15V -12V -10V -8.0V -5.5V -4.5V -3.0V -2.5V 1 -2.5V ≤ 60µs PULSE WIDTH Tj = 25°C 10 BOTTOM 1 -2.5V ≤ 60µs PULSE WIDTH Tj = 175°C 0.1 0.1 0.1 1 10 0.1 100 Fig 1. Typical Output Characteristics 10 100 Fig 2. Typical Output Characteristics 100.0 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) -I D, Drain-to-Source Current (Α) 1 -VDS, Drain-to-Source Voltage (V) -VDS, Drain-to-Source Voltage (V) T J = 25°C T J = 175°C 10.0 1.0 VDS = -25V ≤ 60µs PULSE WIDTH 0.1 0.0 5.0 10.0 ID = -14A VGS = -10V 1.5 1.0 0.5 15.0 -60 -40 -20 -V GS, Gate-to-Source Voltage (V) 10000 20 40 60 80 100 120 140 160 180 Fig 4. Normalized On-Resistance vs. Temperature 20 -VGS, Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 1000 Ciss Coss Crss 100 0 T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics C, Capacitance (pF) VGS -15V -12V -10V -8.0V -5.5V -4.5V -3.0V -2.5V ID= -14A 16 VDS= -44V VDS= -28V VDS= -11V 12 8 4 FOR TEST CIRCUIT SEE FIGURE 19 0 10 1 10 0 100 20 30 40 50 QG Total Gate Charge (nC) -V DS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs.Drain-to-Source Voltage 2014-8-16 10 3 Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage www.kersemi.com IRLR/U9343 & IRLU9343-701 1000 -I D, Drain-to-Source Current (A) -I SD, Reverse Drain Current (A) 100.0 T J = 175°C 10.0 T J = 25°C 1.0 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100µsec 10 Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 10msec 1 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1 2.0 10 100 1000 -VDS , Drain-toSource Voltage (V) -V SD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 2.5 -VGS(th) Gate threshold Voltage (V) 20 16 -I D , Drain Current (A) 1msec 12 8 4 2.0 ID = -250µA 1.5 0 1.0 25 50 75 100 125 150 175 -75 -50 -25 T J , Junction Temperature (°C) 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) Fig 10. Threshold Voltage vs. Temperature Fig 9. Maximum Drain Current vs. Case Temperature Thermal Response ( Z thJC ) 10 1 D = 0.50 0.20 0.10 0.05 0.1 τJ 0.02 0.01 R1 R1 τJ τ1 R2 R2 τ2 τ1 τC τ τ2 Ri (°C/W) 1.162 τi (sec) 0.000512 0.7370 0.002157 Ci= τi/Ri Ci i/Ri 0.01 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 2014-8-16 4 www.kersemi.com 500 600 EAS, Single Pulse Avalanche Energy (mJ) RDS(on), Drain-to -Source On Resistance ( mΩ) IRLR/U9343 & IRLU9343-701 ID = -14A 500 400 300 200 T J = 125°C 100 T J = 25°C 0 ID -4.0A -5.5A BOTTOM -14A TOP 400 300 200 100 0 4.0 6.0 8.0 10.0 25 -V GS, Gate-to-Source Voltage (V) 50 75 100 125 150 175 Starting T J, Junction Temperature (°C) Fig 12. On-Resistance Vs. Gate Voltage Fig 13. Maximum Avalanche Energy Vs. Drain Current 1000 Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆ Tj = 25°C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax -Avalanche Current (A) Duty Cycle = Single Pulse 100 0.01 10 0.05 0.10 1 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 tav (sec) Fig 14. Typical Avalanche Current Vs.Pulsewidth 140 TOP Single Pulse BOTTOM 1% Duty Cycle ID = -14A EAR , Avalanche Energy (mJ) 120 100 80 60 40 20 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 15. Maximum Avalanche Energy Vs. Temperature 2014-8-16 5 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 17a, 17b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav www.kersemi.com IRLR/U9343 & IRLU9343-701 D.U.T Driver Gate Drive + - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + D= Period P.W. + Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop InductorInductor Curent - Current ISD Ripple ≤ 5% * Reverse Polarity of D.U.T for P-Channel * VGS = 5V for Logic Level Devices Fig 16. Peak Diode Recovery dv/dt Test Circuit for P-Channel HEXFET® Power MOSFETs L VDS VDS D.U.T RG -V -20V GS VDD A IAS tp VGS DRIVER D.U.T. RG 0.01Ω RD - + VDD -10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 15V Fig 18a. Switching Time Test Circuit Fig 17a. Unclamped Inductive Test Circuit I AS td(on) tr t d(off) tf VGS 10% 90% tp VDS V(BR)DSS Fig 18b. Switching Time Waveforms Fig 17b. Unclamped Inductive Waveforms Id Vds Vgs L DUT VCC 0 Vgs(th) 1K Qgs1 Qgs2 Fig 19a. Gate Charge Test Circuit 2014-8-16 Qgd Qgodr Fig 19b Gate Charge Waveform 6 www.kersemi.com IRLR/U9343 & IRLU9343-701 D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 2.38 (.094) 2.19 (.086) 6.73 (.265) 6.35 (.250) 1.14 (.045) 0.89 (.035) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 0.58 (.023) 0.46 (.018) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 10.42 (.410) 9.40 (.370) LEAD ASSIGNMENTS 3 1 - GATE 0.51 (.020) MIN. -B1.52 (.060) 1.15 (.045) 2 - DRAIN 3 - SOURCE 4 - DRAIN 0.89 (.035) 3X 0.64 (.025) 1.14 (.045) 2X 0.76 (.030) 0.25 (.010) 0.58 (.023) 0.46 (.018) M A M B NOTES: 2.28 (.090) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4.57 (.180) 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). D-Pak (TO-252AA) Part Marking Information Notes : This part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 9U1P INT ERNAT IONAL RECT IFIER LOGO IRFU120 9U 016 1P DAT E CODE YEAR = 0 WEEK = 16 ASS EMBLY LOT CODE Notes : T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN T HE AS S EMBLY LINE "A" INT ERNAT IONAL RECT IFIER LOGO IRFU120 12 ASS EMBLY LOT CODE 2014-8-16 PART NUMBER 7 916A 34 DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A www.kersemi.com IRLR/U9343 & IRLU9343-701 I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) 2.38 (.094) 2.19 (.086) -A- 0.58 (.023) 0.46 (.018) 1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) LEAD ASSIGNMENTS 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.52 (.060) 1.15 (.045) 1 2 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 3 -B- NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 3X 1.14 (.045) 0.76 (.030) 2.28 (.090) 3X 1.14 (.045) 0.89 (.035) 0.89 (.035) 0.64 (.025) 0.25 (.010) M A M B 0.58 (.023) 0.46 (.018) 2X I-Pak (TO-251AA) Part Marking Information Notes : T his part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 9U1P INT ERNAT IONAL RECT IFIER LOGO IRFU120 016 9U 1P DAT E CODE YEAR = 0 WEEK = 16 AS S EMBLY LOT CODE Notes : T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 5678 AS SEMBLED ON WW 19, 1999 IN T HE AS S EMBLY LINE "A" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE 2014-8-16 8 PART NUMBER IRFU120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A www.kersemi.com IRLR/U9343 & IRLU9343-701 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. 2014-8-16 9 www.kersemi.com IRLR/U9343 & IRLU9343-701 I-Pak Leadform Option 701 Package Outline Dimensions are shown in millimeters (inches) Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 1.24mH, RG = 25Ω, IAS = -14A. Pulse width ≤ 400µs; duty cycle ≤ 2%. This only applies for I-Pak, LS of D-Pak is measured between lead and center of die contact Rθ is measured at TJ of approximately 90°C. 2014-8-16 Contact factory for mounting information Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information When D-Pak mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994 Refer to D-Pak package for Part Marking, Tape and Reel information. 10 www.kersemi.com