ICS9DB102 Integrated Circuit Systems, Inc. 2 Output PCI Express* Buffer with CLKREQ# Function Pin Configuration Output Features: • 2 - 0.7V current mode differential output pairs (HSCL) Key Specifications: • Cycle-to-cycle jitter < 35ps • Output-to-output skew < 25 ps Features/Benefits: • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused outputs can be disabled 0852BC—09/12/05 PLL_BW CLK_INT CLK_INC **CLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 ICS9DB102 Recommended Application: • 1-to-2 Zero-delay or fanout buffer for PCI Express 20 19 18 17 16 15 14 13 12 11 VDDA GNDA IREF **CLKREQ1# VDD GND PCIEXT1 PCIEXC1 VDD SMBCLK Note: Pins preceeded by '**' have internal 120K ohm pull down resistors 20-pin SSOP & TSSOP *Other names and brands may be claimed as the property of others. ICS9DB102 Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME PIN TYPE 1 PLL_BW IN 2 3 CLK_INT CLK_INC IN IN 4 **CLKREQ0# IN 5 6 7 8 9 10 11 12 13 14 15 16 VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT SMBCLK VDD PCIEXC1 PCIEXT1 GND VDD PWR PWR OUT OUT PWR I/O IN PWR OUT OUT PWR PWR 17 **CLKREQ1# IN 18 IREF OUT 19 20 GNDA VDDA PWR PWR DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high "True" reference clock input. "Complementary" reference clock input. Output enable for SRC/PCI Express output pair '0' 0 = enabled, 1 = tri-stated Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Output enable for SRC/PCI Express output pair '1' 0 = enabled, 1 = tri-stated This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. Note: Pins preceeded by '**' have internal 120K ohm pull down resistors 0852C—09/12/05 2 ICS9DB102 Integrated Circuit Systems, Inc. General Description The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the ICS9DB102 suitable for Express Card applications. Block Diagram CLKREQ0# CLKREQ1# PCIEX0 CLK_INT C LK_IN C SPREAD COMPATIBLE PLL PCIEX1 PLL_BW SMBDAT CONTROL LOGIC SMBCLK IREF Power Groups Pin Number VDD GND 5,9,12,16 6,15 9 6 20 19 20 19 Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core 0852C—09/12/05 3 ICS9DB102 Integrated Circuit Systems, Inc. Absolute Max Symbol VDDA VDD Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Output Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 2000 Units V V ° C °C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 3.3 V +/-5% 2 Input Low Voltage Input High Current VIL IIH I IL1 Input Low Current I IL2 Operating Supply Current I DD3.3OP Input Frequency 3 Pin Inductance1 Fi Lpin CIN COUT Input Capacitance1 Clk Stabilization1,2 Modulation Frequency Spread Spectrum Modulation Frequency PLL Bandwidth SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time 3.3 V +/-5% VSS - 0.3 VIN = VDD -5 VIN = 0 V; Inputs with no pull-5 up resistors VIN = 0 V; Inputs with pull-up -200 resistors Full Active, CL = Full load; all differential pairs tri-stated VDD = 3.3 V 99 TYP 75 27 100 MAX UNITS NOTES VDD + 0.3 V 1 0.8 5 V uA 1 1 uA 1 uA 1 100 50 101 7 5 4.5 mA mA MHz nH pF pF 1 1 1 1 1 1 1.8 ms 1 Logic Inputs Output pin capacitance From VDD Power-Up to 1st clock Triangular Modulation 30 33 kHz 1 fMOD Lexmark Modulation 25 45 KHz 1 400 KHz 1 BW PLL Bandwidth when PLL_BW=0 PLL Bandwidth when PLL_BW=1 1.2 MHz 1 5.5 0.4 V V mA 1 1 1 TSTAB VDD VOLSMBUS @ I PULLUP IPULLUP SMBus SDATA pin 2.7 4 TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 1 Guaranteed by design and characterization, not 100% tested in production. 0852C—09/12/05 4 ICS9DB102 Integrated Circuit Systems, Inc. Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage SYMBOL CONDITIONS MIN Zo VO = Vx 3000 VHigh VLow Vovs Vuds Statistical measurement on single ended signal using oscilloscope Measurement on single ended signal using absolute value. 660 -150 Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Tabsmin tr tf d-tr d-tf tpd tpdbyp Input to Output Delay Duty Cycle dt3 Output-to-Output Skew tsk3 Jitter, Cycle to cycle tjcyc-cyc tjcyc-cycbyp VT = 50% PLL mode. Measurement from differential wavefrom Additve Jitter in Bypass Mode UNITS NOTES Ω 850 150 1150 mV mV 2 0852C—09/12/05 5 1,3 1,3 1,3 1,3 550 mV 1,3 12 140 mV 1,3 0 10.0030 10.0533 135 3.2 700 700 125 125 185 3.7 ppm ns ns ns ps ps ps ps ps ns 1,2 2 2 1,2 1 1 1 1 1 1 45 55 % 1 25 ps 1 35 ps 1 30 ps 1 9.9970 9.9970 9.8720 175 175 . Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 1 1 350 30 30 PLL Mode. Bypass mode Measurement from differential wavefrom MAX -300 250 Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP ICS9DB102 Integrated Circuit Systems, Inc. SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Byte 0 0 Pin # Name Control Function Type Functions Enables SMBus controlled by Bit 7 SW_EN RW Control SMBus registers RESERVED Bit 6 RW RESERVED Bit 5 RW RESERVED Bit 4 RW RESERVED Bit 3 RW RESERVED Bit 2 RW Selects PLL Bit 1 PLL BW #adjust RW Low BW Bandwidth Bypasses PLL for PLL bypassed Bit 0 PLL Enable RW (fan out mode) board test SMBus Table: Output Enable Register Byte 1 Pin # Name Control Function Type RESERVED Bit 7 RW RESERVED Bit 6 RW RESERVED Bit 5 RW RESERVED Bit 4 RW RESERVED Bit 3 RW RESERVED Bit 2 RW RESERVED Bit 1 RW RESERVED Bit 0 RW SMBus Table: Function Select Register Byte 2 Pin # Name Control Function Type RESERVED Bit 7 RW RESERVED Bit 6 RW RESERVED Bit 5 RW RESERVED Bit 4 RW RESERVED Bit 3 RW RESERVED Bit 2 RW RESERVED Bit 1 RW RESERVED Bit 0 RW 0852C—09/12/05 6 0 1 PWD Functions controlled by device pins 1 X X X X X High BW 1 PLL enabled (ZDB mode) 1 1 PWD X X X X X X X X 1 PWD X X X X X X X X - 0 - ICS9DB102 Integrated Circuit Systems, Inc. SMBus Table: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type Bit 7 RID3 R Bit 6 RID2 R REVISION ID Bit 5 RID1 R Bit 4 RID0 R Bit 3 VID3 R Bit 2 VID2 R VENDOR ID Bit 1 VID1 R Bit 0 VID0 R SMBus Table: DEVICE ID Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Control Function Type R R R Device ID R = 06 Hex R R R R 0 - 0 1 - PWD 0 0 0 0 0 0 0 1 1 PWD 0 0 0 0 0 1 1 0 - SMBus Table: Byte Count Register Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - Name Control Function Type 0 1 PWD BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 0 1 1 0 0852C—09/12/05 7 ICS9DB102 Integrated Circuit Systems, Inc. 20-Lead, 150 mil SSOP (QSOP) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 1.35 1.75 .053 .069 0.10 0.25 .004 .010 -1.50 -.059 0.20 0.30 .008 .012 0.18 0.25 .007 .010 SEE VARIATIONS SEE VARIATIONS 5.80 6.20 .228 .244 3.80 4.00 .150 .157 0.635 BASIC 0.025 BASIC 0.40 1.27 .016 .050 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° SEE VARIATIONS SEE VARIATIONS SYMBOL A A1 A2 b c D E E1 e L N a ZD VARIATIONS D mm. N MIN 8.55 20 MAX 8.75 ZD (Ref) 1.47 D (inch) MIN .337 Reference Doc.: JEDEC Publication 95, MO-137 10-0032 Ordering Information ICS9DB102yFLFT Example: ICS XXXX y F LF T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device 0852C—09/12/05 8 MAX .344 ZD (Ref) .058 ICS9DB102 Integrated Circuit Systems, Inc. c N 20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.65 BASIC 0.0256 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 L E1 INDEX AREA E 1 2 α D A A2 A1 -Ce b VARIATIONS SEATING PLANE N 20 aaa C D mm. MIN 6.40 D (inch) MAX 6.60 MIN .252 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Ordering Information ICS9DB102yGLFT Example: ICS XXXX yG LF T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device 0852C—09/12/05 9 MAX .260 ICS9DB102 Integrated Circuit Systems, Inc. Revision History Rev. C Issue Date Description 1. Changed PLL mode jitter from 40ps to 35ps. 2. Changed Bypass mode addictive jitter from 25ps to 30ps. 3. Updated LF Ordering Information. 9/12/2005 4. Finla Release. 0852C—09/12/05 10 Page # 5, 8-9