AKM AK4490EN Premium 32-bit 2ch dac Datasheet

[AK4490EN]
AK4490EN
Premium 32-Bit 2ch DAC
1. General Description
The AK4490EN is a new generation Premium 32-bit 2ch DAC with new technologies, achieving industry’s
leading level low distortion characteristics and wide dynamic range. The AK4490EN integrates a
newly developed switched capacitor filter “OSR Doubler”, making it capable of supporting wide
range signals and achieving low out-of-band noise while realizing low power consumption. Moreover, the
AK4490EN has five types of 32-bit digital filters, realizing simple and flexible sound tuning in wide range
of applications. The AK4490EN accepts up to 768kHz PCM data and 11.2MHz DSD data, ideal for a
high-resolution audio source playback that are becoming widespread in network audios and USB-DACs.
Application: AV Receivers, CD/SACD player, Network Audios, USB DACs, USB Headphones, Sound
Plates/Bars, Measurement Equipment, Control Systems, Public Audios (PA), Smart Cellular
Phones, IC-Recorders, Bluetooth Headphones, HD Audio/Voice Conference Systems
2. Features
 256x Over sampling
 Sampling Rate: 30kHz  768kHz
 32-bit 8x Digital Filter
- Ripple: 0.005dB, Attenuation: 100dB
- Short Delay Sharp Roll-off, GD=6.25/fs
- Short Delay Slow Roll-off, GD=5.3/fs
- Sharp Roll-off
- Slow Roll-off
- Super Slow Roll-off
 High Tolerance to Clock Jitter
 Low Distortion Differential Output
 2.8MHz, 5.6MHz and 11.2MHz DSD Input Support
- Filter (fc=50kHz, fc=150kHz, 2.8MHz mode)
 Digital De-emphasis for 32, 44.1, 48kHz sampling
 Soft Mute
 Digital Attenuator (255 levels and 0.5dB step + Mute)
 Mono Mode
 External Digital Filter Mode
 THD+N: -112dB
 DR, S/N: 120dB (Mono mode: 123dB)
 I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD
 Master Clock:
30kHz ~ 32kHz: 256fs, 384fs, 512fs, 768fs, 1024fs or 1152fs
30kHz ~ 54kHz: 256fs, 384fs, 512fs or 768fs
30kHz ~ 96kHz: 256fs, 384fs or 512fs
30kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 192kHz: 128fs, 192fs or 256fs
108kHz ~ 216kHz: 128fs or 192fs
384kHz: 32fs, 48fs, 64fs or 96fs
768kHz: 16fs, 32fs, 48fs or 64fs
 Power Supply: DVDD=AVDD=3.0  3.6V, TVDD=1.6V  DVDD,
VDDL/R= VREFHL/VREFHR=4.75  5.25V
 Digital Input Level: CMOS
 Package: 48-pin QFN
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3. Table of Contents
1.
2.
3.
4.
5.
General Description ............................................................................................................................ 1
Features .............................................................................................................................................. 1
Table of Contents ................................................................................................................................ 2
Block Diagram ..................................................................................................................................... 4
Pin Configurations and Functions ....................................................................................................... 5
■ Pin Layout .......................................................................................................................................... 5
■ Pin Functions...................................................................................................................................... 6
■ Handling of Unused Pin ..................................................................................................................... 8
6. Absolute Maximum Ratings ................................................................................................................ 9
7. Recommended Operating Conditions................................................................................................. 9
8. Electrical Characteristics................................................................................................................... 10
■ Analog Characteristics ..................................................................................................................... 10
■ Sharp Roll-Off Filter Characteristics (fs=44.1kHz) .......................................................................... 11
■ Sharp Roll-Off Filter Characteristics (fs=96kHz) ............................................................................. 11
■ Sharp Roll-Off Filter Characteristics (fs=192kHz) ........................................................................... 11
■ Short Delay Sharp Roll-Off Filter Characteristics (fs=44.1kHz) ...................................................... 13
■ Short Delay Sharp Roll-Off Filter Characteristics (fs=96kHz) ......................................................... 13
■ Short Delay Sharp Roll-Off Filter Characteristics (fs=192kHz) ....................................................... 13
■ Slow Roll-Off Filter Characteristics (fs=44.1kHz) ............................................................................ 15
■ Slow Roll-Off Filter Characteristics (fs=96kHz) ............................................................................... 15
■ Slow Roll-Off Filter Characteristics (fs=192kHz) ............................................................................. 15
■ Short Delay Slow Roll-Off Filter Characteristics (fs=44.1kHz) ........................................................ 17
■ Short Delay Slow Roll-Off Filter Characteristics (fs=96kHz) ........................................................... 17
■ Short Delay Slow Roll-Off Filter Characteristics (fs=192kHz) ......................................................... 17
■ DSD Mode Characteristics ............................................................................................................... 19
■ DC Characteristics ........................................................................................................................... 19
■ Switching Characteristics ................................................................................................................. 20
■ Timing Diagram ................................................................................................................................ 22
9. Functional Descriptions ..................................................................................................................... 27
■ D/A Conversion Mode ...................................................................................................................... 27
■ System Clock ................................................................................................................................... 27
■ Audio Interface Format..................................................................................................................... 35
■ D/A Conversion Mode Switching Timing ......................................................................................... 40
■ De-emphasis Filter ........................................................................................................................... 41
■ Output Volume (PCM, DSD) ............................................................................................................ 41
■ Zero Detection (PCM, DSD, EX DF I/F) .......................................................................................... 42
■ Mono Output (PCM, DSD, EX DF I/F) ............................................................................................. 42
■ Sound Quality Control (PCM, DSD, Ex DF I/F) ............................................................................... 42
■ Characteristics (DSD) ...................................................................................................................... 43
■ Soft Mute Operation (PCM, DSD) .................................................................................................... 44
■ System Reset ................................................................................................................................... 44
■ Power ON/OFF timing ...................................................................................................................... 45
■ Reset Function ................................................................................................................................. 46
■ Synchronize Function....................................................................................................................... 48
■ Register Control Interface ................................................................................................................ 50
■ Register Map .................................................................................................................................... 55
■ Register Definitions .......................................................................................................................... 55
10.
Recommended External Circuits................................................................................................... 61
11.
Package ......................................................................................................................................... 66
■ Outline Dimensions .......................................................................................................................... 66
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■ Material & Lead finish....................................................................................................................... 66
■ Marking............................................................................................................................................. 67
12.
Ordering Guide .............................................................................................................................. 67
■ Ordering Guide ................................................................................................................................. 67
13.
Revision History............................................................................................................................. 67
IMPORTANT NOTICE.............................................................................................................................. 68
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4. Block Diagram
TVDD
DVDD
DVSS
PDN
AVDD
AVSS
VSSL
BICK/DCLK/BCK
LRCK/DSDR/DINR
VDDL
Interpolator
PCM
Data
Interface
Normal path
DSDD bit “0”

Modulator
DATT
Soft Mute
AOUTLP
AOUTLN
fs=384kHz, 768kHz
SDATA/DSDL/DINL
DSD
Data
Interface
SCF
Bias
Vref
Volume pass
DSDD bit “1”
External
DF
Interface
SCF
VCML
VREFHL
VREFLL
VREFLR
VREFLL
VCMR
AOUTRP
AOUTRN
WCK
SSLOW
CSN/SMUTE
CCLK/DEM0
Clock
Divider
Control
Register
VDDR
VSSR
CDTI/DEM1
CAD1/ACKS PSN DZFL/DIF0 DZFR/DIF1 CAD0/DIF2
MCLK
Block Diagram
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5. Pin Configurations and Functions
AOUTLP
AOUTLN
VDDL
VDDL
VSSL
VSSL
VSSR
VSSR
VDDR
VDDR
AOUTRN
AOUTRP
36
35
34
33
32
31
30
29
28
27
26
25
■ Pin Layout
VCOML
37
24
VCOMR
VREFLL
38
23
VREFLR
VREFLL
39
22
VREFLR
VREFHL
40
21
VREFHR
VREFHL
41
20
VREFHR
NC
42
19
NC
18
ACKS/CAD1
AK4490EN
Top View
11
12
DIF1/DZFR
DIF2/CAD0
DIF0/DZFL
13
10
48
SLOW/CDTI/SDA
TVDD
9
PSN
SD/CCLK/SCL
14
8
47
SMUTE/CSN
DVDD
7
I2C
SSLOW/WCK
15
6
46
LRCK/DSDR/DINR
DVSS
5
DEM0
SDATA/DSDL/DINL
16
4
45
BICK/DCLK/BCK
MCLK
3
DEM1
PDN
17
2
44
NC
AVSS
1
43
NC
AVDD
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■ Pin Functions
No.
Pin Name
I/O
Function
No internal bonding.
1
NC
Connect to GND.
No internal bonding.
2
NC
Connect to GND.
Power-Down Mode Pin
3
PDN
I
When at “L”, the AK4490EN is in power-down mode and is held in reset.
The AK4490EN must always be reset upon power-up.
BICK
I
Audio Serial Data Clock Pin in PCM Mode
4
DCLK
I
DSD Clock Pin in DSD Mode
BCK
I
Audio Serial Data Clock Pin in External DF Mode
SDATA
I
Audio Serial Data Input Pin in PCM Mode
5
DSDL
I
DSD Lch Data Input Pin in DSD Mode
DINL
I
Lch Audio Serial Data Input Pin in External DF Mode
LRCK
I
L/R Clock Pin in PCM Mode
6
DSDR
I
DSD Rch Data Input Pin in DSD Mode in Serial Control Mode
DINR
I
Rch Audio Serial Data Input Pin in External DF Mode
SSLOW
I
Digital Filter Setting Pin in Parallel Control Mode (PSN=“H”)
7
WCK
I
Word Clock input pin in External DF Mode (PSN=“L”)
Soft Mute Pin in Parallel Control Mode (PSN=“H”)
SMUTE
I
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
8
Chip Select Pin in Serial Control Mode (PSN=“L”, I2C=“L”)
CSN
I
When this pin is PSN=“L”, I2C=“H”, it should be connected to TVDD or
DVSS.
SD
I
Digital Filter Setting Pin in Parallel Control Mode (PSN=“H”)
9
CCLK
I
Control Data Clock Pin in Serial Control Mode (PSN=“L”, I2C=“L”)
SCL
I
Control Data Clock Pin in Serial Control Mode (PSN=“L”, I2C=“H”)
SLOW
I
Digital Filter Setting Pin in Parallel Control Mode (PSN=“H”)
10 CDTI
I
Control Data Input Pin in Serial Control Mode (PSN=“L”, I2C=“L”)
SDA
I/O Control Data Input Pin in Serial Control Mode (PSN=“L”, I2C=“H”)
DIF0
I
Digital Input Format 0 Pin in PCM Mode (PSN=“H”)
11
DZFL
O Lch Zero Input Detect Pin in Serial Control Mode (PSN=“L”)
DIF1
I
Digital Input Format 1 Pin in PCM Mode (PSN=“H”)
12
DZFR
O Rch Zero Input Detect Pin in Serial Control Mode (PSN=“L”)
DIF2
I
Digital Input Format 2 Pin in PCM Mode (PSN=“H”)
13
CAD0
I
Chip Address 0 Pin in Serial Control Mode (PSN=“L”)
Parallel or Serial Select Pin
(Internal pull-up pin)
14 PSN
I
“L”: Serial Control Mode, “H”: Parallel Control Mode
I2C mode select pin in Serial mode
(Internal pull-down pin)
15 I2C
I
“L”: 3 Wire Serial Mode, “H”: I2C-Bus Mode
De-emphasis Enable 0 Pin in Parallel Control Mode (PSN=“H”)
16 DEM0
I
(Internal pull-up pin)
Note 1. All input pins except internal pull-up/down pins must not be left floating.
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De-emphasis Enable 1 Pin in Parallel Control Mode (PSN=“H”)
(Internal pull-down pin)
Master Clock Auto Setting Mode Pin in Parallel Mode (PSN=“H”)
“L”: Manual Setting Mode, “H”: Auto Setting Mode
ACKS
I
(Internal pull-down pin)
18
Chip Address 1 Pin in Serial Control Mode (PSN=“L”)
CAD1
I
(Internal pull-down pin)
No internal bonding.
19 NC
Connect to GND.
20 VREFHR
I
Rch High Level Voltage Reference Input Pin
21 VREFHR
I
Rch High Level Voltage Reference Input Pin
22 VREFLR
I
Rch Low Level Voltage Reference Input Pin
23 VREFLR
I
Rch Low Level Voltage Reference Input Pin
Right channel Common Voltage Pin,
24 VCOMR
Normally connected to VSS with a 10μF electrolytic cap.
25 AOUTRP
O Rch Positive Analog Output Pin
26 AOUTRN
O Rch Negative Analog Output Pin
27 VDDR
Rch Analog Power Supply Pin, 4.75  5.25V
28 VDDR
Rch Analog Power Supply Pin, 4.75  5.25V
29 VSSR
Ground Pin
30 VSSR
Ground Pin
31 VSSL
Ground Pin
32 VSSL
Ground Pin
33 VDDL
Lch Analog Power Supply Pin, 4.75  5.25V
34 VDDL
Lch Analog Power Supply Pin, 4.75  5.25V
35 AOUTLN
O Lch Negative Analog Output Pin
36 AOUTLP
O Lch Positive Analog Output Pin
Left channel Common Voltage Pin,
37 VCOML
Normally connected to VSS with a 10μF electrolytic cap.
38 VREFLL
I
Lch Low Level Voltage Reference Input Pin
39 VREFLL
I
Lch Low Level Voltage Reference Input Pin
40 VREFHL
I
Lch High Level Voltage Reference Input Pin
41 VREFHL
I
Lch High Level Voltage Reference Input Pin
No internal bonding.
42 NC
Connect to GND.
43 AVDD
Analog Power Supply Pin, 3.0  3.6V
44 AVSS
Ground Pin
45 MCLK
I
Master Clock Input Pin
46 DVSS
Ground Pin
47 DVDD
Digital Power Supply Pin, 3.0  3.6V
48 TVDD
I
Input Buffer Power Supply Pin, 1.6V ~ DVDD
The exposed pad on the bottom surface of the package must be connected
Exposed Pad
to the ground.
Note 1. All input pins except internal pull-up/down pins must not be left floating.
17
DEM1
I
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■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
(1) Parallel Mode (PCM Mode only)
Classification Pin Name
AOUTLP, AOUTLN
Analog
AOUTRP, AOUTRN
Digital
I2C
Setting
These pins must be open.
These pins must be open.
This pin must be connected to DVSS or open.
(2) Serial Mode
1. PCM Mode
Classification Pin Name
AOUTLP, AOUTLN
Analog
AOUTRP, AOUTRN
DEM1
DEM0
Digital
SMUTE/CSN
DZFL, DZFR
2. DSD Mode
Classification Pin Name
AOUTLP, AOUTLN
Analog
AOUTRP, AOUTRN
DEM1
DEM0
Digital
SMUTE/CSN
DZFL, DZFR
3. EXDF Mode
Classification Pin Name
AOUTLP, AOUTLN
Analog
AOUTRP, AOUTRN
DEM1
DEM0
Digital
SMUTE/CSN
DZFL, DZFR
pull-up pin List
pull-up pin
14, 16
pull-down pin List
pull-down pin
15, 17, 18
Setting
These pins must be open.
These pins must be open.
This pin must be connected to DVSS or open.
This pin must be connected to TVDD or open.
This pin must be connected to TVDD or DVSS,
when this pin is I2C=“H”.
These pins must be open.
Setting
These pins must be open.
These pins must be open.
This pin must be connected to DVSS or open.
This pin must be connected to TVDD or open.
This pin must be connected to TVDD or DVSS,
when this pin is I2C=“H”.
These pins must be open.
Setting
These pins must be open.
These pins must be open.
This pin must be connected to DVSS or open.
This pin must be connected to TVDD or open.
This pin must be connected to TVDD or DVSS,
when this pin is I2C=“H”.
These pins must be open.
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6. Absolute Maximum Ratings
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 2)
Parameter
Symbol
Min.
Max.
Unit
0.3
4.6
Analog
AVDD
V
Power
0.3
6.0
Analog
VDDL/R
V
Supplies:
Digital
DVDD
V
0.3
4.6
Input Buffer
TVDD
V
0.3
4.6
|AVSS  DVSS| (Note 3)
GND
V
0.3
Input Current, Any Pin Except Supplies
IIN
10
mA
Digital Input Voltage
VIND
0.3
DVDD+0.3
V
Ambient Temperature (Power applied)
Ta
40
85
C
Storage Temperature
Tstg
65
150
C
Note 2. All voltages with respect to ground.
Note 3. AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane.
Note 4. Connect at least 0.1μF or more decoupling capacitors between VDDL/VDDR and VSSL/VSSR to
suppress affections by a static electricity noise or an over voltage (includes over shooting) that
exceeds absolute maximum ratings.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 2)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Analog
AVDD
3.0
3.3
3.6
V
Power Supplies
Analog
VDDL/R
4.75
5.0
5.25
V
(Note 5)
Digital
DVDD
3.0
3.3
3.6
V
Input Buffer
TVDD
1.6
1.8
DVDD
Voltage Reference “H” voltage reference VREFHL/R VDDL/R0.5
VDDL/R
V
(Note 6)
“L” voltage reference VREFLL/R
VSSL/R
V
Note 2. All voltages with respect to ground.
Note 5. Each power-up/down sequence is shown below.
<Power-Up>
1. PDN pin = “L”
2. TVDD (1.8V) power-up
3. AVDD, DVDD (3V) power-up
4. VREFHL/R and VDDL/R (5V) power-up
5. The PDN pin is allowed to be “H” after all power supplies are applied and settled.
otherwise power up the 1.8V power supply, the 3.3V power supplies and the 5V power supplies at
the same time.
<Power-down>
1. PDN pin = “L”
2. VREFHL/R and VDDL/R (5V) power-down
3. AVDD, DVDD (3V) power-down
4. TVDD (1.8V) power-down
Note 6. The analog output voltage scales with the voltage of (VREFH  VREFL).
AOUT (typ.@0dB) = (AOUT+)  (AOUT) = 2.8Vpp  (VREFHL/R  VREFLL/R)/5.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
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8. Electrical Characteristics
■ Analog Characteristics
(Ta=25C; AVDD=DVDD=3.3V; TVDD=1.8V; AVSS=DVSS=VSSL/R=0V; VREFHL/R=VDDL/R=5V,
VREFLL/R= VSSL/R=0V; Input data = 24bit; RL  1k; BICK=64fs; Signal Frequency = 1kHz; Sampling
Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 41; unless
otherwise specified.)
Min.
Typ.
Max.
Parameter
Unit
Resolution
32
Bits
Dynamic Characteristics
(Note 7)
0dBFS
fs=44.1kHz
-112
-105
dB
THD+N
BW=20kHz
-57
-49
dB
60dBFS
0dBFS
fs=96kHz
-109
-100
dB
BW=40kHz
-54
-44
dB
60dBFS
0dBFS
fs=192kHz
-106
-100
dB
BW=40kHz
60dBFS
-54
-44
dB
BW=80kHz
-51
-41
dB
60dBFS
Dynamic Range (60dBFS with A-weighted)
(Note 8)
115
120
dB
S/N (A-weighted)
(Note 9)
115
120
dB
S/N (Mono mode, A-weighted)
118
123
dB
Interchannel Isolation (1kHz)
110
120
dB
DC Accuracy
Interchannel Gain Mismatch
0.15
0.3
dB
Gain Drift
(Note 10)
20
ppm/C
Output Voltage
(Note 11)
2.65
2.8
2.95
Vpp
Load Capacitance
25
pF
Load Resistance
(Note 12)
1
k
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
VDDL/R
22
32
mA
AVDD
0.6
1.2
mA
TVDD
0.5
1
mA
DVDD (fs= 44.1kHz)
10
14
mA
DVDD (fs= 96kHz)
15
20
mA
DVDD (fs = 192kHz)
17
23
mA
Power down (PDN pin = “L”)
(Note 13)
AVDD+VDDL/R+DVDD+TVDD
0
10
A
Note 7. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board
manual.
Note 8. Figure 41 External LPF Circuit Example 2. 101dB for 16-bit data and 118dB for 20-bit data.
Note 9. Figure 41 External LPF Circuit Example 2. S/N does not depend on input data size.
Note 10. The voltage on (VREFH  VREFL) is held +5V externally.
Note 11. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R  VREFLL/R).
AOUT (typ.@0dB) = (AOUT+)  (AOUT) = 2.8Vpp  (VREFHL/R  VREFLL/R)/5.
Note 12. Regarding Load Resistance, AC load is 1k (min) with a DC cut capacitor (Figure 41). DC load
is 1.5k ohm (min) without a DC cut capacitor (Figure 40). The load resistance value is with
respect to ground. Analog characteristics are sensitive to capacitive load that is connected to the
output pin. Therefore the capacitive load must be minimized.
Note 13. In the power down mode. The PSN pin = DVDD, and all other digital input pins including clock
pins (MCLK, BICK and LRCK) are held DVSS.
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■ Sharp Roll-Off Filter Characteristics (fs=44.1kHz)
(Ta=25C; AVDD=DVDD=3.0~3.6V, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Normal
Speed Mode; DEM=OFF; SD bit=“0” or SD pin = “L”, SLOW bit=“0” or SLOW pin = “L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 14) 0.01dB
PB
0
20.0
kHz
6.0dB
22.05
kHz
Stopband
(Note 14)
SB
24.1
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
100
dB
Group Delay
(Note 15)
GD
29.4
1/fs
Digital Filter + SCF
Frequency Response: 0  20.0kHz
+0.1/-0.2
dB
■ Sharp Roll-Off Filter Characteristics (fs=96kHz)
Ta=25C; AVDD=DVDD=3.0~3.6V, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Double
Speed Mode; DEM=OFF; SD bit=“0” or SD pin = “L”, SLOW bit=“0” or SLOW pin = “L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 14) 0.01dB
PB
0
43.5
kHz
6.0dB
48.0
kHz
Stopband
(Note 14)
SB
52.5
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
100
dB
Group Delay
(Note 15)
GD
28.8
1/fs
Digital Filter + SCF
Frequency Response: 0  40.0kHz
+0.1/-0.6
dB
■ Sharp Roll-Off Filter Characteristics (fs=192kHz)
(Ta=25C; AVDD=DVDD=3.0~3.6V, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Quad
Speed Mode; DEM=OFF; SD bit=“0” or SD pin = “L”, SLOW bit=“0” or SLOW pin = “L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 14) 0.01dB
PB
0
87.0
kHz
6.0dB
96.0
kHz
Stopband
(Note 14)
SB
105
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
92
dB
Group Delay
(Note 15)
GD
28.8
1/fs
Digital Filter + SCF
Frequency Response: 0  80.0kHz
+0.1/-0.2
dB
Note 14. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@0.01dB),
SB=0.546×fs.
Note 15. The calculating delay time which occurred by digital filtering. This time is from setting the
16/20/24/32 bit data of both channels to the output of analog signal.
015013666-E-01
2015/12
- 11 -
[AK4490EN]
Figure 1. Sharp Roll-off Filter Frequency Response
Figure 2. Sharp Roll-off Filter Passband Ripple
015013666-E-01
2015/12
- 12 -
[AK4490EN]
■ Short Delay Sharp Roll-Off Filter Characteristics (fs=44.1kHz)
(Ta=25C; AVDD=DVDD=3.0~3.6V, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Normal
Speed Mode; DEM=OFF; SD bit=“1” or SD pin = “H”, SLOW bit=“0” or SLOW pin = “L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 14) 0.01dB
PB
0
20.0
kHz
6.0dB
22.05
kHz
Stopband
(Note 14)
SB
24.1
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
100
dB
Group Delay
(Note 15)
GD
6.25
1/fs
Digital Filter + SCF
Frequency Response : 0  20.0kHz
+0.1/-0.2
dB
■ Short Delay Sharp Roll-Off Filter Characteristics (fs=96kHz)
(Ta=25C; AVDD=DVDD=3.0~3.6V, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Double
Speed Mode; DEM=OFF; SD bit=“1” or SD pin = “H”, SLOW bit=“0” or SLOW pin = “L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 14) 0.01dB
PB
0
43.5
kHz
6.0dB
48.0
kHz
Stopband
(Note 14)
SB
52.5
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
100
dB
Group Delay
(Note 15)
GD
5.63
1/fs
Digital Filter + SCF
Frequency Response : 0  40.0kHz
+0.1/-0.6
dB
■ Short Delay Sharp Roll-Off Filter Characteristics (fs=192kHz)
(Ta=25C; AVDD=DVDD=3.0~3.6V, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Quad
Speed Mode; DEM=OFF; SD bit=“1” or SD pin = “H”, SLOW bit=“0” or SLOW pin = “L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 14) 0.01dB
PB
0
87.0
kHz
6.0dB
96.0
kHz
Stopband
(Note 14)
SB
105
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
92
dB
Group Delay
(Note 15)
GD
5.63
1/fs
Digital Filter + SCF
Frequency Response : 0  80.0kHz
+0.1/-2.0
dB
015013666-E-01
2015/12
- 13 -
[AK4490EN]
Figure 3. Short delay Sharp Roll-off Filter Frequency Response
Figure 4. Short delay Sharp Roll-off Filter Passband Ripple
015013666-E-01
2015/12
- 14 -
[AK4490EN]
■ Slow Roll-Off Filter Characteristics (fs=44.1kHz)
(Ta=25C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Normal
Speed Mode; DEM=OFF; SD bit=“0” or SD pin = “L”, SLOW bit=“1” or SLOW pin = “H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 16) 0.01dB
PB
0
4.4
kHz
6.0dB
18.2
kHz
Stopband
(Note 16)
SB
39.1
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
94
dB
Group Delay
(Note 17)
GD
6.63
1/fs
Digital Filter + SCF
Frequency Response: 0  20.0kHz
+0.1/-4.5
dB
■ Slow Roll-Off Filter Characteristics (fs=96kHz)
(Ta=25C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Double
Speed Mode; DEM=OFF; SD bit=“0” or SD pin = “L”, SLOW bit=“1” or SLOW pin = “H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 16) 0.01dB
PB
0
18.1
kHz
6.0dB
45.6
kHz
Stopband
(Note 16)
SB
85.0
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
100
dB
Group Delay
(Note 17)
GD
6.00
1/fs
Digital Filter + SCF
Frequency Response: 0  40.0kHz
+0.1/-4.0
dB
■ Slow Roll-Off Filter Characteristics (fs=192kHz)
(Ta=25C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Quad
Speed Mode; DEM=OFF; SD bit=“0” or SD pin = “L”, SLOW bit=“1” or SLOW pin = “H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 16) 0.01dB
PB
0
32.9
kHz
6.0dB
90.4
kHz
Stopband
(Note 16)
SB
171
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
97
dB
Group Delay
(Note 17)
GD
6.00
1/fs
Digital Filter + SCF
Frequency Response: 0  80.0kHz
+0.1/-5.5
dB
Note 16. The passband and stopband frequencies scale with fs. For example, PB=0.1836×fs (@0.01dB),
SB=0.8889×fs.
Note 17. The calculating delay time which occurred by digital filtering. This time is from setting the
16/20/24/32 bit data of both channels to the output of analog signal.
015013666-E-01
2015/12
- 15 -
[AK4490EN]
Figure 5. Slow Roll-off Filter Frequency Response
Figure 6. Slow Roll-off Filter Passband Ripple
015013666-E-01
2015/12
- 16 -
[AK4490EN]
■ Short Delay Slow Roll-Off Filter Characteristics (fs=44.1kHz)
(Ta=25C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD , VREFHL/R=VDDL/R=4.75  5.25V; Normal
Speed Mode; DEM=OFF; SD bit=“1” or SD pin = “H”, SLOW bit=“1” or SLOW pin = “H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 18) 0.01dB
PB
0
4.4
kHz
6.0dB
18.2
kHz
Stopband
(Note 18)
SB
39.1
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
94
dB
Group Delay
(Note 19)
GD
5.3
1/fs
Digital Filter + SCF
Frequency Response : 0  20.0kHz
+0.1/-4.5
dB
■ Short Delay Slow Roll-Off Filter Characteristics (fs=96kHz)
(Ta=25C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Double
Speed Mode; DEM=OFF; SD bit=“1” or SD pin = “H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 18) 0.01dB
PB
0
18.1
kHz
6.0dB
45.6
kHz
Stopband
(Note 18)
SB
85.0
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
100
dB
Group Delay
(Note 19)
GD
4.68
1/fs
Digital Filter + SCF
Frequency Response : 0  40.0kHz
+0.1/-0.4
dB
■ Short Delay Slow Roll-Off Filter Characteristics (fs=192kHz)
(Ta=25C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V; Quad
Speed Mode; DEM=OFF; SD bit=“1” or SD pin = “H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
(Note 18) 0.01dB
PB
0
32.9
kHz
6.0dB
96.0
kHz
Stopband
(Note 18)
SB
170
kHz
Passband Ripple
PR
0.005
dB
Stopband Attenuation
SA
97
dB
Group Delay
(Note 19)
GD
4.68
1/fs
Digital Filter + SCF
Frequency Response : 0  80.0kHz
+0.1/-5.5
dB
Note 18. The passband and stopband frequencies scale with fs. For example, PB=0.1836×fs (@0.01dB),
SB=0.8866×fs.
Note 19. The calculating delay time which occurred by digital filtering. This time is from setting the
16/20/24/32 bit data of both channels to the output of analog signal.
015013666-E-01
2015/12
- 17 -
[AK4490EN]
Figure 7. Short Delay Slow Roll-off Filter Frequency Response
Figure 8. Short Delay Slow Roll-off Filter Passband Ripple
015013666-E-01
2015/12
- 18 -
[AK4490EN]
■ DSD Mode Characteristics
(Ta=-40~85C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V;
fs=44.1kHz; DP bit=“1”, DSDF bit=“0”)
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response
20kHz
-0.4
dB
Frequency Response (Note 21)
50kHz
-2.8
dB
100kHz
-15.5
dB
(Ta=-40~85C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V;
fs=44.1kHz; DP bit=“1”, DSDF bit=“1”, DSDD bit=“1”)
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response
20kHz
-0.05
dB
Frequency Response (Note 21)
50kHz
-0.29
dB
100kHz
-1.16
dB
150kHz
-2.8
dB
Note 20. The peak level of DSD signal should be in the range of 25% ~ 75% duty according to the SACD
format book (Scarlet Book).
Note 21. The output level is assumed as 0dB when a 1kHz 25% ~ 75% duty sine wave is input.
■ DC Characteristics
(Ta=25C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
TVDD=1.6  3.0V
High-Level Input Voltage
VIH
80%TVDD
V
Low-Level Input Voltage
VIL
20%TVDD
V
TVDD=3.0  DVDD
High-Level Input Voltage
VIH
70%TVDD
V
Low-Level Input Voltage
VIL
30%TVDD
V
High-Level Output Voltage
VOH
DVDD0.5
V
(DZFL/R pins: Iout=-100µA)
Low-Level Output Voltage
(except SDA pin : Iout= 100µA)
VOL
0.5
V
(SDA pin, 2.0V  TVDD  3.6V: Iout= 3mA)
VOL
0.4
V
(SDA pin, 1.6V  TVDD  2.0V: Iout= 3mA)
VOL
20%DVDD
V
Input Leakage Current
(Note 22)
Iin
10
A
Note 22. The DEM1, I2C and ACKS/CAD1 pins have internal pull-down and DEM0 and PSN pins have
internal pull-up devices, nominally 100k. Therefore the DEM1, I2C, ACKS/CAD1, DEM0 and
PSN pins are not included.
015013666-E-01
2015/12
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[AK4490EN]
■ Switching Characteristics
(Ta=25C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V)
Parameter
Symbol
Min.
Typ.
Max.
Master Clock Timing
Frequency
fCLK
7.7
49.152
Duty Cycle
dCLK
40
60
LRCK Frequency
(Note 23)
1152fs, 512fs or 768fs
fsn
30
54
256fs or 384fs
fsd
54
108
128fs or 192fs
fsq
108
216
64fs
fsoc
384
64fs
fssd
768
Duty Cycle
Duty
45
55
PCM Audio Interface Timing
BICK Period
1152fs, 512fs or 768fs
tBCK
1/128fsn
256fs or 384fs
tBCK
1/64fsd
128fs or 192fs
tBCK
1/64fsq
64fs
tBCK
1/64fso
64fs
tBCK
1/64fsh
BICK Pulse Width Low
tBCKL
9
BICK Pulse Width High
tBCKH
9
BICK “” to LRCK Edge (Note 24)
tBLR
5
LRCK Edge to BICK “” (Note 24)
tLRB
5
SDATA Hold Time
tSDH
5
SDATA Setup Time
tSDS
5
External Digital Filter Mode
BICK Period
tB
27
BCK Pulse Width Low
tBL
10
BCK Pulse Width High
tBH
10
BCK “” to WCK Edge
tBW
5
WCK Edge to BCK “”
tWB
5
WCK Pulse Width Low
tWCK
54
WCK Pulse Width High
tWCH
54
DATA Hold Time
tDH
5
DATA Setup Time
tDS
5
DSD Audio Interface Timing (64 mode,
DSDSEL 1-0 bits = “00”)
tDCK
1/64fs
DCLK Period
tDCKL
160
DCLK Pulse Width Low
tDCKH
160
DCLK Pulse Width High
tDDD
20
20
DCLK Edge to DSDL/R (Note 25)
DSD Audio Interface Timing (128 mode,
DSDSEL 1-0 bits = “01”)
DCLK Period
tDCK
1/128fs
DCLK Pulse Width Low
tDCKL
80
DCLK Pulse Width High
tDCKH
80
DCLK Edge to DSDL/R (Note 25)
tDDD
10
10
015013666-E-01
Unit
MHz
%
kHz
kHz
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2015/12
- 20 -
[AK4490EN]
DSD Audio Interface Timing (256 mode,
DSDSEL 1-0 bit = “10”)
DCLK Period
tDCK
1/256fs
ns
DCLK Pulse Width Low
tDCKL
40
ns
DCLK Pulse Width High
tDCKH
40
ns
DCLK Edge to DSDL/R (Note 25)
tDDD
5
5
ns
Control Interface Timing
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
50
ns
CDTI Hold Time
tCDH
50
ns
CSN High Time
tCSW
150
ns
CSN “” to CCLK “”
tCSS
50
ns
CCLK “” to CSN “”
tCSH
50
ns
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
s
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
s
Clock Low Time
tLOW
1.3
s
Clock High Time
tHIGH
0.6
s
Setup Time for Repeated Start Condition
tSU:STA
0.6
s
SDA Hold Time from SCL Falling
(Note 26)
tHD:DAT
0
s
SDA Setup Time from SCL Rising
tSU:DAT
0.1
s
Rise Time of Both SDA and SCL Lines
tR
0.3
s
Fall Time of Both SDA and SCL Lines
tF
0.3
s
Setup Time for Stop Condition
tSU:STO
0.6
s
Pulse Width of Spike Noise Suppressed by Input
tSP
0
50
ns
Filter
Cb
400
pF
Capacitive load on bus
Reset Timing
PDN Pulse Width
(Note 27)
tPD
150
ns
Note 23. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4490EN
should be reset by the PDN pin or RSTN bit.
Note 24. BICK rising edge must not occur at the same time as LRCK edge.
Note 25. DSD data transmitting device must meet this time.
Note 26. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 27. The AK4490EN can be reset by bringing the PDN pin to “L”.
When the AK8157A is used for MCLK, Minimum Pulse Width is specified as below.
Parameter
Master Clock Timing
Frequency1 (CKSEL= “00”)
Frequency2 (CKSEL= “01”)
Frequency3 (CKSEL= “10” / “11”)
Minimum Pulse Width
Symbol
fCLK
fCLK
fCLK
tCLKH / tCLKL
015013666-E-01
min
typ
16.384
22.5792
24.576
9.155
max
Unit
MHz
MHz
MHz
ns
2015/12
- 21 -
[AK4490EN]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
tWCK
VIH
WCK
VIL
tWCKH
tWCKL
tB
VIH
BCK
VIL
tBH
tBL
Clock Timing
015013666-E-01
2015/12
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[AK4490EN]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDATA
VIL
Audio Interface Timing (PCM Mode)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)
015013666-E-01
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[AK4490EN]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
A4
VIH
VIL
3 Wire Serial Mode WRITE Command Input Timing
015013666-E-01
2015/12
- 24 -
[AK4490EN]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
CDTI
D3
D2
D1
VIH
D0
VIL
3 Wire Serial Mode WRITE Data Input Timing
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
I2C Bus Mode Timing
Stop
015013666-E-01
2015/12
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[AK4490EN]
tPD
PDN
VIL
Power Down & Reset Timing
VIH
WCK
VIL
tBW
tWB
VIH
BCK
VIL
tDS
tDH
VIH
DINL
DINR
VIL
External Digital Filter I/F mode
015013666-E-01
2015/12
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[AK4490EN]
9. Functional Descriptions
■ D/A Conversion Mode
In serial mode, the AK4490EN can perform D/A conversion for either PCM data or DSD data. The DP bit
controls PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins.
When PCM mode, PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode is
changed by DP bit, the AK4490EN should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the
mode. In parallel mode, the AK4490EN performs for only PCM data.
Table 1. PCM/DSD Mode Control
DP bit
Interface
0
PCM
1
DSD
When DP bit= “0”, an internal digital filter or external digital filter can be selected. When using an external
digital filter (EX DF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXDF bit
controls the modes. When switching internal and external digital filters, the AK4490EN must be reset by
RSTN bit. A Digital filter switching takes 2~3k/fs.
Table 2. Digital Filter Control (DP bit = “0”)
EXDF bit
Interface
0
PCM
1
EX DF I/F
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4490EN, are MCLK, BICK and LRCK. MCLK
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital
interpolation filter and the delta-sigma modulator. There are two modes for MCLK frequency setting:
Manual Setting Mode and Auto Setting Mode. In manual setting mode, MCLK frequency is set
automatically (Table 3,Table 9). In auto setting mode, sampling speed and MCLK frequency are detected
automatically (Table 4, Table 10) and then the initial master clock is set to the appropriate frequency
(Table 5, Table 11). When the reset is released (PDN pin = “”), the AK4490EN is in auto setting mode.
The AK4490EN is automatically placed in reset state when MCLK and LRCK are stopped during a normal
operation (PDN pin =“H”), and the analog output becomes Hi-z state. When MCLK and LRCK are input
again, the AK4490EN exits reset state and starts operation. After exiting system reset (PDN pin
=“L”→“H”) at power-up and other situations, the AK4490EN is in power-down mode until MCLK and
LRCK are supplied.
The MCLK frequency corresponding to each sampling speed should be provided externally (Table 3,
Table 4, Table 9, Table 10).
015013666-E-01
2015/12
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[AK4490EN]
(1) Parallel Mode (PSN pin = “H”)
1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided externally (Table 3).
DFS1-0 bit is fixed to “00”. In this mode, only normal speed mode are available.
Table 3. System Clock Example (Manual Setting Mode @Parallel Mode) (N/A: Not available)
LRCK
MCLK (MHz)
BICK
fs
128fs 192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
64fs
32.0kHz
N/A
N/A
8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 2.0480MHz
44.1kHz
N/A
N/A
11.2896 16.9344 22.5792 33.8688
N/A
N/A
2.8224MHz
48.0kHz
N/A
N/A
12.2880 18.4320 24.5760 36.8640
N/A
N/A
3.0720MHz
2. Auto Setting Mode (ACKS pin = “H”)
In auto setting mode, MCLK frequency and sampling frequency are detected automatically (Table 4).
MCLK of corresponded frequency to each sampling speed mode should be input externally. (Table 5)
Table 4. Sampling Speed (Auto Setting Mode @Parallel Mode)
MCLK
Sampling Speed
1152fs
Normal (fs32kHz)
512/256fs
768/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
Table 5. System Clock Example (Auto Setting Mode @Parallel Mode) (N/A: Not available)
LRCK
Fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
32fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
48fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
64fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
N/A
96fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.576
N/A
N/A
MCLK (MHz)
192fs
256fs
N/A
8.192
N/A
11.2896
N/A
12.288
N/A
22.5792
N/A
24.576
33.8688
N/A
36.864
N/A
N/A
N/A
N/A
N/A
384fs
12.288
16.9344
18.432
33.8688
36.864
N/A
N/A
N/A
N/A
512fs
16.384
22.5792
24.576
N/A
N/A
N/A
N/A
N/A
N/A
768fs
24.576
33.8688
36.864
N/A
N/A
N/A
N/A
N/A
N/A
1024fs
32.768
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1152fs
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 32kHz~96kHz. However, the DR
and S/N performances will degrade approximately 3dB as compared to when MCLK= 512fs/768fs when
the sampling rate is 32kHz~48kHz (Table 6).
Table 6. Relationship of MCLK Frequency and DR, S/N Performance (fs = 44.1kHz)
ACKS pin
MCLK
DR,S/N
L
256fs/384fs/512fs/768fs
120dB
H
256fs/384fs
117dB
H
512fs/768fs
120dB
015013666-E-01
2015/12
- 28 -
Sampling
Speed
Normal
Double
Quad
Quad
Oct
Hex
[AK4490EN]
3. Digital filter
The AK4490EN has four kinds of digital filter selected by SSLOW, SD and SLOW pins. Different sound
qualities on playback can be selected by these filters.
SSLOW pin
L
L
L
L
H
Table 7. Digital Filter Setting
SLOW pin
Mode
L
Sharp roll-off filter
H
Slow roll-off filter
L
Short delay Sharp roll-off filter
H
Short delay Slow roll-off filter
Super Slow roll-off filter
SD pin
L
L
H
H
-
(default)
The AK4490EN can be operated on a slower sampling frequency. This mode is available when the
SSLOW pin = “H”.
(2) Serial Mode (PSN pin = “L”)
1. Manual Setting Mode (ACKS bit = “0”)
MCLK frequency is detected automatically and the sampling speed is set by DFS2-0 bits (Table 8). The
MCLK frequency corresponding to each sampling speed should be provided externally (Table 9). The
AK4490EN is set to Manual Setting Mode at power-up (PDN pin = “L” →“H”). When DFS2-0 bits are
changed, the AK4490EN should be reset by RSTN bit.
DFS2
0
0
0
0
1
1
1
1
Table 8. Sampling Speed (Manual Setting Mode @Serial Mode)
DFS1 DFS0
Sampling Rate (fs)
(default)
0
0
Normal Speed Mode
30kHz  54kHz
0
1
Double Speed Mode
54kHz  108kHz
1
1
0
0
1
1
0
1
0
1
0
1
Quad Speed Mode
Reserved
Oct Speed Mode
Hex Speed Mode
Reserved
Reserved
015013666-E-01
120kHz  216kHz
384kHz
768kHz
-
2015/12
- 29 -
[AK4490EN]
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
Table 9. System Clock Example (Manual Setting Mode @Serial Mode)
MCLK (MHz)
16fs
32fs
48fs
64fs
96fs
128fs
192fs
256fs
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288
24.576
384fs
512fs
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
N/A
N/A
N/A
16.3840
22.5792
24.5760
45.1584
49.152
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
18.432
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
49.152
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
MCLK (MHz)
768fs 1024fs
1152fs
Sampling
Speed
24.5760
33.8688
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
32.7680
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
33.8688
36.8640
N/A
N/A
8.1920
11.2896
12.2880
22.5792
24.5760
45.1584
49.152
N/A
N/A
Sampling
Speed
Normal
Double
Quad
Quad
Oct
Hex
Normal
Double
Quad
Quad
Oct
Hex
2. Auto Setting Mode (ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 10) and DFS1-0 bits are
ignored. The MCLK frequency corresponding to each sampling speed should be provided externally
(Table 11).
Table 10. Sampling Speed (Auto Setting Mode @Serial Mode)
MCLK
Sampling Speed
1152fs
Normal (fs32kHz)
512/256fs
768/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 11. System Clock Example (Auto Setting Mode @Serial Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
32fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
48fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
64fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
N/A
96fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
128fs
N/A
N/A
N/A
N/A
N/A
22.5792
24.576
N/A
N/A
MCLK(MHz)
192fs
256fs
N/A
8.192
N/A
11.2896
N/A
12.288
N/A
22.5792
N/A
24.576
33.8688
N/A
36.864
N/A
N/A
N/A
N/A
N/A
015013666-E-01
384fs
12.288
16.9344
18.432
33.8688
36.864
N/A
N/A
N/A
N/A
512fs
16.384
22.5792
24.576
N/A
N/A
N/A
N/A
N/A
N/A
768fs
24.576
33.8688
36.864
N/A
N/A
N/A
N/A
N/A
N/A
1024fs
32.7680
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1152fs
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
Speed
Normal
Double
Quad
Quad
Oct
Hex
2015/12
- 30 -
[AK4490EN]
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 32kHz~96kHz. However, the DR
and S/N performances will degrade approximately 3dB as compared to when MCLK= 512fs/768fs when
the sampling rate is 32kHz~48kHz (Table 12).
Table 12. Relationship of MCLK Frequency and DR, S/N Performance (fs = 44.1kHz)
ACKS bit
MCLK
DR,S/N
0
256fs/384fs/512fs/768fs
120dB
1
256fs/384fs
117dB
1
512fs/768fs
120dB
3. Digital filter
The AK4490EN has four kinds of digital filter selected by SSLOW, SD and SLOW bits. Different sound
qualities on playback can be selected by these filters.
SSLOW bit
0
0
0
0
1
SD bit
0
0
1
1
-
Table 13. Digital Filter Setting
SLOW bit
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Short delay Sharp roll-off filter
1
Short delay Slow roll-off filter
Super Slow roll-off filter
(default)
The AK4490EN can be operated on a slower sampling frequency. This mode is available when the
SSLOW bit = “1” (05H D0).
015013666-E-01
2015/12
- 31 -
[AK4490EN]
[2] DSD Mode
The AK4490EN has a DSD playback function. The external clocks, which are required in DSD mode, are
MCLK and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency
of MCLK is set by DCKS bit.
The AK4490EN is automatically placed in reset state when MCLK is stopped during a normal operation
(PDN pin =“H”), and the analog output becomes Hi-z state. However, the external clock (DCLK) should
not be stopped. When DCLK is not supplied, the AK4490EN may not be able to operate properly because
of an over current since it has a dynamic logic circuit internally. The PDN pin should be set to “L” when
stopping the DCLK. When the reset is released (PDN pin = “L” → “H”), the AK4490EN is in power-down
state until MCLK and DCLK are input.
DCKS bit
0
1
Table 14. System Clock (DSD Mode)
MCLK Frequency
DCLK Frequency
512fs
64fs/128fs/256fs
768fs
64fs/128fs/256fs
(default)
The AK4490EN supports DSD data stream of 2.8224MHz (64fs), 5.6448MHz (128fs) and 11.2896MHz
(256fs). The data sampling speed is selected by DSDSEL1-0 bits.
Table 15. DSD Sampling Speed Control
DSDSEL1 DSDSEL0 DSD data stream
0
0
2.8224MHz
(default)
0
1
5.6448MHz
1
0
11.2896MHz
1
1
Reserved
The AK4490EN has a Volume bypass function for play backing DSD signal. Two modes are selectable by
DSDD bit. When setting DSDD bit = “1”, the output volume control function is not available.
Table 16. DSD Play Back Mode Control
DSDD
Mode
0
Normal Path
1
Volume Bypass
(default)
When DSDD bit = “1”, filter characteristic can be switched between 50kHz and 100kHz by DSDF bit.
DSDD bit
Table 17. DSD Filter Select
DSDF bit
Cut Off Filter
0
0
50kHz
0
1
Reserved
1
0
50kHz
1
1
150kHz
015013666-E-01
(default)
2015/12
- 32 -
[AK4490EN]
Full Scale (FS) DSD Signal Detection Function
The AK4490EN has a full scale (FS) detection function at each channel in DSD Mode. When DSDL or
DSDR input data is continuously “0” (-FS) or “1” (+FS) for 2048 cycles, the AK4490EN detects full scale
and enters full scale detection status and DML or DMR bit becomes “1”. The output will be muted by full
scale detection if DDM bit = “1”. When DSDD bit is “0”, the output is attenuated in soft transition. When
DSDD bit is “1”, the soft transition is disabled.
Recovery method to normal operation mode from full scale detection status is controlled by DMC bit when
DDM bit = “1”. When DMC bit = “0”, the AK4490EN returns to normal operation automatically by a normal
signal input. When DMC bit = “1”, the AK4490EN returns normal operation by writing DMRE bit = “1”.
Table 18. DSD Mode and the Device Status after Detection (DDM bit= “1”)
DSDD
Mode
Status After Detection
0
Normal Path
Soft Mute Enable
1
Volume Bypass
Soft Mute Disable
(default)
Table 19. Recovery Method to Normal Operation Mode from Full Scale Detection Status
DDM
DMC
DMRE
Status After Detection
0
*
*
When full scale is detected, Mute function is Disable.
(default)
When full scale is detected, Mute function is Enable.
1
0
*
The AK4490EN returns normal operation automatically
by a normal signal input.
When full scale is detected, Mute function is Enable.
1
1
0
The AK4490EN keeps mute mode, even if a normal
signal is input.
When full scale is detected, Mute function is Enable.
1
1
1
The AK4490EN returns normal operation, when a
(Note 28)
normal signal is input and DMRE bit is set “1”.
Note 28. After the AK4490EN returns normal operation, DMRE bit is returned to “0” automatically.
DSD Error
(DDR or DDLbit)
DSD Data
2048fs
DSD Data
DSD Data(FS or -FS )
DSD Data
AOUT
Mode
Figure 9. Analog Output Waveform on DSD FS Detection (DSDD bit= “1”)
2048fs
DSD Error
(DDR or DDLbit)
DSD Data
DSD Data
DSD Data(FS or -FS )
DSD Data
AOUT
Mode
Figure 10. Analog Output Waveform on DSD FS Detection (DSDD bit= “0”)
015013666-E-01
2015/12
- 33 -
[AK4490EN]
[3] External Digital Filter Mode (EX DF I/F Mode)
The AK4490EN has the External Digital Filter playback function. The external clocks, which are required
in EX DF I/F mode, are MCLK, BCK and WCK. BCK should be same frequency with MCLK. The
frequency of WCK is set by ECS bit.
Table 20. EX DF Sampling Speed
ECS
WCK [kHz]
0
768kHz
1
384kHz
015013666-E-01
(default)
2015/12
- 34 -
[AK4490EN]
■ Audio Interface Format
[1] PCM Mode
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and
selected by the DIF2-0 pins (Parallel control mode) or DIF2-0 bits (Serial control mode) as shown in Table
21. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising edge of
BICK. Mode 2 can be used for 20-bit and 16-bit MSB justified formats by zeroing the unused lower bit.
Mode
0
1
2
3
4
5
6
7
DIF2
0
0
0
0
1
1
1
1
Table 21. Audio Interface Format
DIF0
Input Format
BICK
0
16-bit LSB justified
 32fs
1
20-bit LSB justified
 48fs
0
24-bit MSB justified
 48fs
1
24-bit I2S compatible
 48fs
0
24-bit LSB justified
 48fs
1
32-bit LSB justified
 64fs
0
32-bit MSB justified
64fs
2
1
32-bit I S compatible
 64fs
DIF1
0
0
1
1
0
0
1
1
Figure
Figure 11
Figure 12
Figure 13
Figure 14
Figure 12
Figure 15
Figure 16
Figure 17
(default)
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA
Mode 0
15
0
14
1
6
5
14
4
15
3
16
2
17
1
0
31
15
0
14
1
6
5
14
4
15
3
16
2
17
1
0
31
15
0
14
1
BICK
(64fs)
SDATA
Mode 0
Don’t care
15
14
0
Don’t care
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 11. Mode 0 Timing
015013666-E-01
2015/12
- 35 -
[AK4490EN]
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
BICK
(64fs)
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA
Mode 4
23
Don’t care
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 12. Mode 1/4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDATA
23
22
1
0
Don’t care
23
22
0
1
Don’t care
23
22
0
1
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 13. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
BICK
(64fs)
SDATA
23
22
1
0
Don’t care
23
22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 14. Mode 3 Timing
015013666-E-01
2015/12
- 36 -
[AK4490EN]
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31
0
1
2
12
13
14
23
1
24
0
31
31
0
1
2
12
13
14
23
1
24
0
31
0
1
BICK(64fs)
SDATA
31 30
20 19 18
8
9
0
1
31 30
20
19 18
Lch Data
8
9
0
1
31
Rch Data
31: MSB, 0:LSB
Figure 15. Mode 5 Timing
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31 30
0
1
12 11 10
2
12
13
0
14
31 30
23
24
31
0
1
12
11 10
2
12
0
13
14
31
23
24
31
0
1
BICK(64fs)
SDATA
31 30
20 19 18
8
9
0
1
31 30
20
19 18
Lch Data
8
9
0
1
31
Rch Data
31: MSB, 0:LSB
Figure 16. Mode 6 Timing
LRCK
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
24
25
31
0
1
BICK(128fs)
SDATA
31
0
1
13 12 11
2
12
13
0
14
31
24
25
31
0
1
13
2
12 11
12
0
13
14
0
1
BICK(64fs)
SDATA
0
31
21 20 19
9
8
2
1
0
31
Lch Data
21
20 19
9
8
2
1
0
Rch Data
31: MSB, 0:LSB
Figure 17. Mode 7 Timing
015013666-E-01
2015/12
- 37 -
[AK4490EN]
[2] DSD Mode
In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is selected
between 64fs, 128fs and 256fs. DCKB bit can invert the polarity of DCLK. Phase modulation function is
not available in 256fs mode.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D2
D3
Figure 18. DSD Mode Timing
015013666-E-01
2015/12
- 38 -
[AK4490EN]
[3] External Digital Filter Mode (EX DF I/F Mode)
DW indicates the number of BCK in one WCK cycle. The audio data is input by MCLK, BCK and WCK
from the DINL and DINR pins. Three formats are available (Table 23) by DIF2-0 bits setting. The data is
latched on the rising edge of BCK. The BCK and MCLK clocks must be the same frequency and must not
burst. BCK and MCLK frequencies for each sampling speed are shown in Table 22.
Table 22. System Clock Example (EX DF I/F mode) (N/A: Not available)
Sampling
Speed[kHz]
44.1(30~48)
44.1(30~48)
96(54~96)
96(54~96)
192(108~192)
192(108~192)
MCLK&BCK [MHz]
128fs
N/A
N/A
N/A
N/A
N/A
N/A
12.288
32
24.576
32
N/A
N/A
192fs
N/A
N/A
N/A
N/A
N/A
N/A
18.432
48
36.864
48
36.864
96
256fs
N/A
N/A
11.2896
32
24.576
32
N/A
N/A
N/A
N/A
N/A
N/A
384fs
N/A
N/A
16.9344
48
36.864
48
36.864
96
N/A
N/A
N/A
N/A
WCK
512fs
22.5792
32
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
768fs
33.8688
48
33.8688
96
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
16fs
DW
8fs
DW
8fs
DW
4fs
DW
4fs
DW
2fs
DW
ECS
0
(default)
1
0
1
0
1
Table 23. Audio Interface Format (EX DF I/F mode) (N/A: Not available)
Mode
DIF2
DIF1
DIF0
Input Format
0
0
0
0
16-bit LSB justified
1
0
0
1
N/A
2
0
1
0
N/A
3
0
1
1
N/A
4
1
0
0
24-bit LSB justified
5
1
0
1
32-bit LSB justified (default)
6
1
1
0
N/A
7
1
1
1
N/A
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[AK4490EN]
1/(16fs) or 1/(8fs) or 1/(4fs) or 1/(2fs)
WCK
0
1
8
9
10
11
16
17
26
27
28
29
30
31
0
1
BCK
(32WCK)
DINL or
DINR
BCK
(48WCK)
DINL or
DINR
31
0
30
24 23
1
13
Don’t care
0
22
14
21
15
20
16
Don’t care
1
5
6
7
17
16
23
15
24
14
6
5
4
3
44
25
31
8
2
45
48
65
49
92
46
2
3
47
1
93
0
47
1
94
0
0
95
1
Don’t care
0
1
BCK
(96WCK)
DINL or
DINR
Don’t care
Don’t care
Don’t care
31
3
2
1
0 Don’t care
31: MSB, 0:LSB
Figure 19. EX DF I/F Mode Timing
■ D/A Conversion Mode Switching Timing
RSTN bit
4/fs
D/A Mode
PCM Mode
DSD Mode
0
D/A Data
PCM Data
DSD Data
Figure 20. D/A Mode Switching Timing (PCM to DSD)
RSTN bit
D/A Mode
DSD Mode
PCM Mode
4/fs
D/A Data
DSD Data
PCM Data
Figure 21. D/A Mode Switching Timing (DSD to PCM)
Note 29. The signal range is identified as 25% ~ 75% duty ratios in DSD mode. DSD signal must not go
beyond this duty range at the SACD format book (Scarlet Book).
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[AK4490EN]
■ De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is
enabled or disabled with DEM1-0 pins or DEM1-0 bits. In case of 256fs/384fs and 128fs/192fs, the digital
de-emphasis filter is always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held
even if PCM mode and DSD mode are switched.
Table 24. De-emphasis Control
DEM1
DEM0
Mode
0
0
44.1kHz
0
1
OFF
(default)
1
0
48kHz
1
1
32kHz
■ Output Volume (PCM, DSD)
The AK4490EN includes channel independent digital output volumes (ATT) with 256 levels at 0.5dB step
including MUTE. This volume control is in front of the DAC and it can attenuate the input data from 0dB to
–127dB or mute. When changing output levels, it is executed in soft transition thus no switching noise
occurs during these transitions. It takes 7395/fs from FFH (0dB) to 00H (MUTE). The attenuation level is
initialized to FFH by setting to PDN pin = “L”. Register setting values will be kept even switching the PCM
and DSD modes.
Table 25. ATT Transition Time
Transition Time
Sampling Speed
0dB to MUTE
fs=44.1kHz
168.3ms
fs=96kHz
77.3ms
fs=192kHz
38.6ms
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[AK4490EN]
■ Zero Detection (PCM, DSD, EX DF I/F)
The AK4490EN has a channel-independent zeros detect function. When the input data at each channel is
continuously zeros for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each
channel immediately returns to “L” if the input data of each channel is not zero after going to “H”. If the
RSTN bit is “0”, the DZF pins of both L and R channels go to “H”. The DZF pin of each channel returns to
“L” in 4 ~ 5/fs after the input data of each channel becomes “1” when RSTN bit is set to “1”. If DZFM bit is
set to “1”, the DZF pins of both L and R channels go to “H” only when the input data for both channels are
continuously zeros for 8192 LRCK cycles. The zero detect function can be disabled by setting the DZFE
bit. In this case, DZF pins of both channels are always “L”. The DZFB bit can invert the polarity of the DZF
pin.
Table 26. Zero Detect Function and DZF Pin Output
DZFE
DZFB
Data
DZF-pin
0
0
-
L
1
-
H
not zero
L
Zero detect
H
not zero
H
Zero detect
L
0
1
1
■ Mono Output (PCM, DSD, EX DF I/F)
The AK4490EN can select input/output for both output channels by setting the MONO bit and SELLR bit.
This function is available for any audio format.
Table 27 MONO Mode Output Select
MONO bit
SELLR bit
Lch Out
Rch Out
0
0
1
1
0
1
0
1
Lch In
Rch In
Lch In
Rch In
Rch In
Lch In
Lch In
Rch In
■ Sound Quality Control (PCM, DSD, Ex DF I/F)
Sound quality of the AK4490EN can be selected by SC1-0 bits.
SC1
Table 28. SC1-0 bits Control
SC0
Mode
0
0
Sound Setting 1
0
1
Sound Setting 2
1
0
Sound Setting 3
1
1
Reserved
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[AK4490EN]
■ Characteristics (DSD)
(Ta=25C; AVDD=DVDD=3.3V; AVSS=DVSS=VSSL/R=0V; VREFHL/R=VDDL/R=5V, VREFLL/R=
VSSL/R=0V; Input data = 24bit; RL  1k; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;
Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 41; unless otherwise specified.)
Dynamic Characteristics
DSD data stream
0dBFS
-110
dB
2.8224MHz
THD+N
DSD data stream
0dBFS
-110
dB
5.6448MHz
DSD data stream
0dBFS
-110
dB
11.2896MHz
S/N (A-weighted, Normal path)
Digital “0”
120
dB
DC Accuracy
Output Voltage (Normal path )
2.8
Vpp
Output Voltage (Volume pass )
1.87
Vpp
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[AK4490EN]
■ Soft Mute Operation (PCM, DSD)
The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE
bit set to “1”, the output signal is attenuated by  during ATT_DATA  ATT transition time from the
current ATT level. When the SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is
cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA  ATT
transition time. If the soft mute is cancelled before attenuating  after starting the operation, the
attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE pin or
SMUTE bit
(1)
(1)
ATT_Level
(3)
Attenuation
-
GD
(2)
GD
(2)
AOUT
DZF pin
(4)
8192/fs
Note 30.
(1) ATT_DATA  ATT transition time. For example, this time is 7395LRCK cycles at ATT_DATA=255 in
Normal Speed Mode.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating  after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles, the DZF pin for
each channel goes to “H”. The DZF pin immediately returns to “L” if input data are not zero.
Figure 22. Soft Mute Function
■ System Reset
The AK4490EN should be reset once by bringing the PDN pin = “L” upon power-up. It initializes register
settings of the device. The analog block of the AK4490EN exits power-down mode by MCLK input, and
the digital block exits power-down mode after the internal counter counts MCLK for 4/fs.
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[AK4490EN]
■ Power ON/OFF timing
The AK4490EN is placed in the power-down mode by bringing the PDN pin “L” and the registers are
initialized. The analog outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin
signal, the analog output should be muted externally if the click noise influences system application.
The DAC can be reset by setting RSTN bit to “0”. In this case, registers are not initialized and the
corresponding analog outputs go to VCML/R. As some click noise occurs at the edge of RSTN signal, the
analog output should be muted externally if click noise aversely affect system performance.
Power
PDN pin
(1)
Internal
State
Normal Operation
DAC In
(Digital)
“0”data
“0”data
GD
DAC Out
(Analog)
(3)
Reset
(2)
(4)
GD
(4)
(3)
(5)
Clock In
MCLK,LRCK,BICK
(8)
(8)
(7)
DZFL/DZFR
External
Mute
(6)
Mute ON
Mute ON
Note 31.
(1) Digital and analog power supply should be powered up at the same time, otherwise power up the
1.8V base power supplies (TVDD) at first, the 3.3V base power supplies secondarily (DVDD,
AVDD) and 5V base power supplies finally (VDDL/R, VREFHL/R). After TVDD, AVDD and DVDD
reach to 90%VDD, the PDN pin should be “L” for 150ns or more.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are floating (Hi-Z) in power-down mode.
(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(6) Mute the analog output externally if click noise (4) adversely affect system performance
The timing example is shown in this figure.
(7) DZFL/R pins are “L” in the power-down mode (PDN pin = “L”).
(8) Clocks should be input after power supplies are powered up.
Figure 23. Power-down/up Sequence Example
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[AK4490EN]
■ Reset Function
(1) RESET by RSTN bit = “0”
When the RSTN bit = “0”, the AK4490EN’s digital block is powered down, but the internal register values
are not initialized. In this time, the analog outputs go to VCML/R voltage and DZFL/DZFR pins are “H”.
Figure 24 shows an example of reset by RSTN bit.
RSTN bit
3~4/fs (5)
2~3/fs (5)
Internal
RSTN bit
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
“0” data
(1)
D/A Out
(Analog)
Normal Operation
Digital Block
GD
GD
(3)
(2)
(3)
(1)
2/fs(4)
DZF
(6)
Note 32.
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs settle to VCOM voltage.
(3) Small pop noise occurs at the edges(“ ”) of the internal timing of RSTN bit. This noise is output
even if “0” data is input.
(4) The DZF pins change to “H” when the RSTN bit becomes “0”, and return to “L” at 2/fs after RSTN bit
becomes “1”.
(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1”
to the internal RSTN bit “1”.
(6) Mute the analog output externally if click noise (3) and Hi-Z (2) adversely affect system performance
Figure 24. Reset Sequence Example 1
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[AK4490EN]
(2) RESET by MCLK or LRCK/WCK Stop
The AK4490EN is automatically placed in reset state when MCLK or LRCK is stopped during PDM mode
(PDN pin = “H”), and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the
AK4490EN exits reset state and starts the operation. Zero detect function is disable when MCLK or LRCK
is stopped. In DSD mode the AK4490EN is in reset state when MCLK is stopped, and it is in reset state
when MCLK or WCK are stopped in external digital filter mode.
AVDD pin
DVDD pin
PDN pin
(1)
Internal
State
Power-down
D/A In
(Digital)
Power-down
Normal Operation
Normal Operation
(3)
GD
D/A Out
(Analog)
Digital Circuit Power-down
(2)
GD
(5)
Hi-Z
(5)
(2)
(5)
(4)
(5)
Clock In
MCLK, BICK, LRCK, WCK
External
MUTE
MCLK, BICK, LRCK, WCK Stop
(7)
(6)
(6)
(6)
Note 33.
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data can be stopped. Click noise after MCLK and LRCK are input again can be reduced
by inputting “0” data during this period.
(4) Click noise occurs within 3 ~ 4LRCK cycles from the riding edge (“↑”) of the PDN pin or MCLK
inputs. This noise occurs even when “0” data is input.
(5) Clocks (MCLK, BICK, LRCK/WCK) can be stopped in the reset state (MCLK or LRCK/WCK is
stopped).
(6) Mute the analog output externally if click noise (4) and (5) influences system applications. The
timing example is shown in this figure.
(7) Clocks should be input after power supplies are powered up.
Figure 25. Reset Sequence Example 2
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[AK4490EN]
■ Synchronize Function
The AK4490EN has a function that resets the internal counter to synchronize with the external clock edge
(LRCK) in a range of 3/256fs. Clock synchronize function becomes valid if SYNCE bit is set to “1” during
operation in PCM mode or EXDF mode and input data of both L and R channels are “0” for 8129 times
continuously or RSTN bit is “1”. In PCM mode, the internal counter is synchronized with a falling edged of
LRCK (rising edge of LRCK in I2C mode), and it is synchronized with a falling edge of WCK in EXDF
mode. In this case, the analog output has the same voltage as VCML/R. Figure 26 shows a synchronizing
sequence when the input data is “0” for 8192 times continuously. Figure 27 shows a synchronizing
sequence by RSTN bit.
(1) Synchronization by continuous “0” data input for 8192 times
If the input data is “0” for 8192 times continuously, or if the data becomes “0” for 8192 times continuously
by attenuation, the DZFL/DZFR pin goes to “H” and the synchronize function becomes valid. The
synchronize function is enabled only when both L and R channels data are “0” for 8192 times
continuously. Figure 26 shows a synchronizing sequence when the input data is “0” for 8192 times
continuously.
D/A In
(Digital)
SMUTE
(1)
(1)
ATT_Level
Attenuation
-
GD
GD
(4)
AOUT
DZF pin
(2)
8192/fs
(2)
8192/fs
SYNC
Operation (2)
Internal Counter
Reset
Internal
Data Reset
GD
SYNC
Operation (2)
(5)
4~5/fs (3)
Note 34.
(1) ATT_DATA  ATT transition time. For example, this time is 7395LRCK cycles (1020/fs) at
ATT_DATA=255 in Normal Speed Mode.
(2) When both L and R channels data are “0” for 8192 times continuously, DZFL/R pins become “H” and
the synchronize function is valid.
(3) Internal data is fixed to “0” forcibly for 4 to 5/fs when internal counter is reset.
(4) A click noise may occur when the internal counter is reset. This noise is output even if a “0” data is
input. Mute the analog output externally if this click noise affects the system performance.
(5) When the internal clock and external clock are in synchronization, the internal counter is not reset
even if the synchronize function is valid.
Figure 26. Synchronizing Sequence by Continuous “0” Data Input for 8192 Times
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[AK4490EN]
(2) Synchronization by RSTN bit
If RSTN bit is set to “0”, the output signal of the DZFL/DZFR pin becomes “H”. Then, the DAC is reset 3 to
4/fs after the DZFL/DZFR pin = “H” and the analog output becomes the same voltage as VCML/R. The
synchronize function becomes valid when both of the DZFL and DZFR pins output “H”. Figure 27 shows a
synchronizing sequence by RSTN bit.
RSTN bit
3~4/fs (4)
2~3/fs (4)
Internal
RSTN bit
Internal
State
Normal Operation
D/A In
(Digital)
force”0” (2)
(3)
D/A Out
(Analog)
Normal Operation
Digital Block Power-down
GD
GD (3)
(5)
(5)
2/fs(4)
DZF
SYNC Operation (1)
Internal Counter
Reset
Internal
Data Reset
4~5/fs (2)
Note 35.
(1) DZFL/R pin becomes “H” by a rising edge of RSTN bit, and becomes “L” 2/fs after a falling edge of
internal signal of RSTN bit. The synchronize function is valid During the DZFL/R pin = “H”.
(2) Internal data is fixed to “0” forcibly for 4 to 5/fs when the internal counter is reset.
(3) Since the analog output corresponding to digital input has group delay (GD), it is recommended to
have a no-input period longer than the group delay before writing “0” to RSTN bit.
(4) It takes 3 to 4/fs when falling to change the internal RSTN signal of the LSI after writing to RSTN
bit. It also takes 3 to 4/fs when rising to change the internal RSTN signal of the LSI. The
synchronize function becomes valid immediately when “0” is written to RSTN bit. Therefore, there
is a case that the internal counter is reset before internal RSTN signal of the LSI is changed.
(5) A click noise occurs on the rising or falling edge of the internal RSTN signal and when the internal
counter is reset. This noise is output even if a “0” data is input. Mute the analog output externally if
this click noise affects the system performance.
Figure 27. Synchronizing Sequence by RSTN bit
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[AK4490EN]
■ Register Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Pins (parallel control mode) or registers (serial control mode) can control the functions of the AK4490EN.
In parallel control mode, the register setting is ignored, and in serial control mode the pin settings are
ignored. When the state of the PSN pin is changed, the AK4490EN should be reset by the PDN pin. The
serial control interface is enabled by the PSN pin = “L”. Internal registers may be written to through3-wire
µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits,
C1/0), Read/Write (1-bit; fixed to “1”), Register address (MSB first, 5-bits) and Control data (MSB first,
8-bits). The data is output on a falling edge of CCLK and the data is received on a rising edge of CCLK.
The writing of data is valid when CSN “”. The clock speed of CCLK is 5MHz (max).
Table 29. Function List1 (Y: Available, -: Not available)
Parallel Control
Serial Control
Function
Mode
Mode
Audio Format
Y
Y
Auto Setting Mode
Y
Y
De-emphasis
Y
Y
SMUTE
Y
Y
DSD Mode
Y
EX DF I/F
Y
Zero Detection
Y
Sharp Roll off filter
Y
Y
Slow Roll off filter
Y
Y
Minimum delay Filter
Y
Y
Digital Attenuator
Y
Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal
timing circuit is reset by the RSTN bit, but the registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 28. Control I/F Timing
* The AK4490EN does not support read commands in 3-wire serial control mode.
* When the AK4490EN is in power down mode (PDN pin = “L”), writing into control registers is prohibited.
* The control data cannot be written when the CCLK rising edge is 15 times or less or 17 times or more
during CSN is “L”.
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[AK4490EN]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4490EN supports the fast-mode I2C-bus (max: 400kHz, Ver 1.0).
(2)-1. WRITE Operations
Figure 29 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 35). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bits). This bit identifies
the specific device on the bus. The hard-wired input pin (CAD1pins, CAD0 pin) sets these device address
bits (Figure 30). If the slave address matches that of the AK4490EN, the AK4490EN generates an
acknowledge and the operation is executed. The master must generate the acknowledge-related clock
pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 36). A R/W bit value
of “1” indicates that the read operation is to be executed, and “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4490EN and the format is MSB first.
(Figure 31). The data after the second byte contains control data. The format is MSB first, 8bits (Figure
32). The AK4490EN generates an acknowledge after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line
while SCL is HIGH defines a STOP condition (Figure 35).
The AK4490EN can perform more than one byte write operation per sequence. After receipt of the third
byte the AK4490EN generates an acknowledge and awaits the next data. The master can transmit more
than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving
each data packet the internal address counter is incremented by one, and the next data is automatically
taken into the next address. If the address exceeds “09H” prior to generating a stop condition, the address
counter will “roll over” to “00H” and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 37) except for the
START and STOP conditions.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 29. Data Transfer Sequence at I2C Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(CAD0 is set by the pin)
Figure 30. The First Byte
0
0
0
A4
A3
A2
A1
A0
D1
D0
Figure 31. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 32. The Third Byte and After The Third Byte
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[AK4490EN]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4490EN. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds “09H” prior to generating stop condition, the address counter will “roll over” to “00H” and the data
of “00H” will be read out.
The AK4490EN supports two basic read operations: Current Address Read and Random Address Read.
(2)-2-1. Current Address Read
The AK4490EN has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address
with R/W bit “1”, the AK4490EN generates an acknowledge, transmits 1-byte of data to the address set by
the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK4490EN ceases the
transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 33. Current Address Read
(2)-2-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit “1”. The AK4490EN then generates an acknowledge, 1 byte of data and
increments the internal address counter by 1. If the master does not generate an acknowledge but
generates a stop condition instead, the AK4490EN ceases the transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 34. Random Address Read
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[AK4490EN]
SDA
SCL
S
P
start condition
stop condition
Figure 35. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 36. Acknowledge (I2C Bus)
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 37. Bit Transfer (I2C Bus)
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Function List
Table 30. Function List (Y: Available, -: Not available)
Default
Address Bit
PCM
0dB
03H
ATT7-0
Y
04H
External Digital Filter I/F Mode Disable
00H
EXDF
Y
EX DF I/F mode clock setting
16fs(fs=44.1kHz)
00H
ESC
Audio Data Interface Modes
24bit MSB justified 00H
DIF2-0
Y
Data Zero Detect Enable
Disable
01H
DZFE
Y
Data Zero Detect Mode
Separated
01H
DZFM
Y
Minimum delay Filter Enable
Sharp roll-off filter
01H
SD
Y
De-emphasis Response
OFF
01H
DEM1-0
Y
Soft Mute Enable
Normal Operation
01H
SMUTE
Y
DSD/PCM Mode Select
PCM mode
02H
DP
Y
Master Clock Frequency Select 512fs
02H
DCKS
at DSD mode
MONO mode Stereo mode
Stereo
02H
MONO
Y
select
Inverting Enable of DZF
“H” active
02H
DZFB
Y
The data selection of L channel R channel
02H
SELLR
Y
and R channel
Function
Attenuation Level
015013666-E-01
DSD
EX DF I/F
Y
-
Y
Y
Y
Y
Y
Y
Y
-
Y
-
Y
Y
Y
-
Y
Y
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[AK4490EN]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register
Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
Control4
Control5
Control6
Control7
Control8
D7
D6
D5
D4
D3
D2
D1
D0
ACKS
DZFE
DP
ATT7
ATT7
INVL
DDM
0
0
0
EXDF
DZFM
0
ATT6
ATT6
INVR
DML
0
0
0
ECS
SD
DCKS
ATT5
ATT5
0
DMR
0
0
0
0
DFS1
DCKB
ATT4
ATT4
0
DMC
0
0
0
DIF2
DFS0
MONO
ATT3
ATT3
0
DMRE
0
0
0
DIF1
DEM1
DZFB
ATT2
ATT2
0
0
0
0
0
DIF0
DEM0
SELLR
ATT1
ATT1
DFS2
DSDD
0
SC1
DSDF
RSTN
SMUTE
SLOW
ATT0
ATT0
SSLOW
DSDSEL0
SYNCE
SC0
DSDSEL1
Note 36.
In 3-wire serial control mode, the AK4490EN does not support read commands.
The AK4490EN supports read command in I2C-bus control mode.
Data must not be written into addresses from 0AH to 1FH.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their
default values.
When the state of the PSN pin is changed, the AK4490EN should be reset by the PDN pin.
■ Register Definitions
Addr Register Name
00H Control 1
R(I2C)/W
Default
D7
ACKS
R/W
0
D6
EXDF
R/W
0
D5
ECS
R/W
0
D4
0
R
0
D3
DIF2
R/W
0
D2
DIF1
R/W
1
D1
DIF0
R/W
0
D0
RSTN
R/W
0
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized. (default)
1: Normal Operation
Writing “0” to this bit resets the internal timing circuit but register values are not initialized.
When the PSN pin = “H”, the AK4490EN operates regardless of this register setting.
DIF2-0: Audio Data Interface Modes (Table 21)
Initial value is “010” (Mode 2: 24-bit MSB justified).
ECS: EX DF I/F mode clock setting (Table 22)
0: WCK=768kHz mode (default)
1: WCK=384kHz mode
EXDF: External Digital Filter I/F Mode (Serial mode only)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
0: Disable: Manual Setting Mode (default)
1: Enable: Auto Setting Mode
When ACKS bit = “1”, MCLK frequency and the sampling frequency are detected
automatically.
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Addr Register Name
01H Control 2
R(I2C)/W
Default
D7
DZFE
R/W
0
D6
DZFM
R/W
0
D5
SD
R/W
1
D4
DFS1
R/W
0
D3
DFS0
R/W
0
D2
DEM1
R/W
0
D1
DEM0
R/W
1
D0
SMUTE
R/W
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM1-0: De-emphasis Response
Initial value is “01” (OFF).
DFS2-0: Sampling Speed Control (Table 31)
Initial value is “000” (Normal Speed). Click noise occurs when DFS2-0 bits are changed.
(05H, D1: DFS2 bit )
DFS2
0
0
0
0
1
1
1
1
SD:
Table 31. Sampling Speed (Manual Setting Mode @Serial Mode)
DFS1 DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
(default)
30kHz  54kHz
0
1
Double Speed Mode
54kHz  108kHz
1
0
Quad Speed Mode
120kHz  216kHz
1
1
Reserved
0
0
Oct Speed Mode
384kHz
0
1
Hex Speed Mode
768kHz
1
0
Reserved
1
1
Reserved
-
Minimum delay Filter Enable
0: Traditional filter
1: Short delay filter (default)
SSLOW bit
0
0
0
0
1
SD bit
0
0
1
1
-
Table 32. Digital Filter Setting
SLOW bit
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Short delay Sharp roll-off filter
1
Short delay Slow roll-off filter
Super Slow roll-off filter
(default)
DZFM:
Data Zero Detect Mode
0: Channel Separated Mode (default)
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both L and R channels go to “H” only when the
input data at both channels are continuously zeros for 8192 LRCK cycles.
DZFE:
Data Zero Detect Enable
0: Disable (default)
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both
channels are always “L”.
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Addr Register Name
02H Control 3
R(I2C)/W
Default
SLOW:
D7
DP
R/W
0
D6
0
R
0
D5
DCKS
R/W
0
D4
DCKB
R/W
0
D3
MONO
R/W
0
D2
DZFB
R/W
0
D1
SELLR
R/W
0
D0
SLOW
R/W
0
Slow Roll-off Filter Enable
0: Sharp roll-off filter (default)
1: Slow roll-off filter
SSLOW bit
0
0
0
0
1
SD bit
0
0
1
1
-
Table 33. Digital Filter Setting
SLOW bit
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Short delay Sharp roll-off filter
1
Short delay Slow roll-off filter
Super Slow roll-off filter
(default)
SELLR: The data selection of L channel and R channel
MONO bit
0
0
1
1
Table 34 MONO Mode Output Select
SELLR bit
Lch Out
Rch Out
0
Lch In
Rch In
1
Rch In
Lch In
0
Lch In
Lch In
1
Rch In
Rch In
(default)
DZFB: Inverting Enable of DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
Table 35. Zero Detect Function and DZF Pin Output
DZFE
DZFB
Data
DZF-pin
0
L
0
1
H
not zero
L
0
Zero detect
H
1
not zero
H
1
Zero detect
L
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
When MONO bit is “1”, MONO mode is enabled.
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP:
DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When DP bit is changed, the AK4490EN should be reset by RSTN bit.
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Addr Register Name
03H Lch ATT
04H Rch ATT
R(I2C)/W
Default
D7
ATT7
ATT7
R/W
1
D6
ATT6
ATT6
R/W
1
D5
ATT5
ATT5
R/W
1
D4
ATT4
ATT4
R/W
1
D3
ATT3
ATT3
R/W
1
D2
ATT2
ATT2
R/W
1
D1
ATT1
ATT1
R/W
1
D0
ATT0
ATT0
R/W
1
ATT7-0: Attenuation Level
255 levels, 0.5dB step + MUTE
Data
FFH
FEH
FDH
:
02H
01H
00H
Attenuation
0dB
-0.5dB
-1.0dB
:
-126.5dB
-127.0dB
MUTE (-)
The transition between set values is soft transition of 7396 levels. It takes 7395/fs
(168ms@fs=44.1kHz) from FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are
initialized to FFH. The ATTs are FFH when RSTN bit= “0”. When RSTN return to “1”, the ATTs
fade to their current value. This digital attenuator is independent of soft mute function.
Addr Register Name
05H Control 4
R(I2C)/W
Default
D7
INVL
R/W
0
D6
INVR
R/W
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
DFS2
R/W
0
D0
SSLOW
R/W
0
SSLOW: Super Slow Roll-off Filter Enable
0: Disable (default)
1: Enable
DFS2-0: Sampling Speed Control (Table 36)
Initial value is “000” (Normal Speed). Click noise occurs when DFS2-0 bits are changed.
(01H, D4, D3: DFS1-0 bits)
DFS2
0
0
0
0
1
1
1
1
Table 36. Sampling Speed (Manual Setting Mode @Serial Mode)
DFS1
DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
30kHz  54kHz
0
1
Double Speed Mode
54kHz  108kHz
1
0
Quad Speed Mode
120kHz  216kHz
1
1
Reserved
0
0
Oct Speed Mode
384kHz
0
1
Hex Speed Mode
768kHz
1
0
Reserved
1
1
Reserved
-
INVR:
AOUTR Output Phase Inverting
0: Disable (default)
1: Enable
INVL:
AOUTL Output Phase Inverting
0: Disable (default)
1: Enable
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[AK4490EN]
Addr Register Name
06H Control 5
R(I2C)/W
Default
D7
DDM
R/W
0
D6
DML
R/W
0
D5
DMR
R/W
0
D4
DMC
R/W
0
D3
DMRE
R/W
0
D2
0
R
0
D1
D0
DSDD
DSDSEL0
R/W
R/W
0
0
DSDSEL1-0: DSD Sampling Speed Control (See also Control 7 register.)
Table 15. DSD Sampling Speed Control
DSDSEL1 bit
DSDSEL0 bit DSD data stream
0
0
2.8224MHz
0
1
5.6448MHz
1
0
11.2896MHz
1
1
Reserved
(default)
DSDD: DSD Play Back Path Control
Table 16. DSD Play Back Mode Control
DSDD
Mode
0
Normal Path
(default)
1
Volume Bypass
DMRE:DSD Mute Release
0: Hold (default)
1: Release Mute
This register is only valid when DDM bit = “1” and DMC bit = “1”. When the AK4490EN
mutes DSD data by DDM and DMC bits settings, the mute is released by setting DMRE bit
to “1”.
Table 19. Recovery Method to Normal Operation Mode from Full Scale Detection Status
DDM
DMC
DMRE
Status After Detection
0
*
*
When full scale is detected, Mute function is Disable.
(default)
When full scale is detected, Mute function is Enable.
1
0
*
The AK4490EN returns normal operation automatically
by a normal signal input.
When full scale is detected, Mute function is Enable.
1
1
0
The AK4490EN keeps mute mode, even if a normal
signal is input.
When full scale is detected, Mute function is Enable.
1
1
1
The AK4490EN returns normal operation, when a
(Note 28)
normal signal is input and DMRE bit is set “1”.
Note 28. After the AK4490EN returns normal operation, DMRE bit is returned to “0” automatically.
DMC: DSD Mute Control
0: Auto Return (default)
1: Mute Hold (manual return)
This register is only valid when DDM bit = “1”. It selects the mute releasing mode of when the
DSD data level becomes under full-scale after the AK4490EN mutes DSD data by DDM bit
setting.
DMR/DML
This register outputs detection flag when a full scale signal is detected at DSDR/L channel.
DDM: DSD Data Mute
0: Disable (default)
1: Enable
The AK4490EN has an internal mute function that mutes the output when DSD audio data
becomes all “1” or all “0” for 2048 Samples (1/fs). DDM bit controls this function.
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[AK4490EN]
Addr Register Name
07H Control 6
R(I2C)/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
SYNCE
R/W
0
SYNCE: Synchronization control
0: Disable (default)
1: Enable
This register enables the function that synchronizes multiple AK4490ENs when using more
than one AK4490ENs in a system.
Addr Register Name
08H Control 7
R(I2C)/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
SC1
R/W
0
D0
SC0
R/W
0
D2
D1
D0
SC1-0: Sound control bit
SC1
0
0
1
1
Addr Register Name
09H Control 8
R(I2C)/W
Default
Table 37. SC1-0 bits Control
SC0
Sound Mode
0
Sound Setting 1
1
Sound Setting 2
0
Sound Setting 3
1
Reserved
D7
D6
D5
D4
(default)
D3
0
0
0
0
0
0
DSDF
DSDSEL
1
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
DSDSEL1-0: DSD Sampling Speed Control (See also Control 4 register.)
Table 15. DSD Sampling Speed Control
DSDSEL1 DSDSEL0 DSD data stream
0
0
2.8224MHz
(default)
0
1
5.6448MHz
1
0
11.2896MHz
1
1
Reserved
DSDF: DSD Filter
When DSDD bit= “1”, the filter characteristics can be switched between 50kHz and 150kHz by
DSDF bit.
Table 17. DSD Filter Select
DSDD bit DSDF bit
Cut Off Filter
0
0
50kHz
(default)
0
1
Reserved
1
0
50kHz
1
1
150kHz
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10. Recommended External Circuits
Figure 38 shows the system connection diagram. Figure 40, Figure 41 and Figure 42 show the analog
output circuit examples. The evaluation board (AKD4490) demonstrates the optimum layout, power supply
arrangements and measurement results.
Digital Digital
1.8V 3.3V
VCML 37
VREFLL 38
VREFLL 39
VREFHL 40
NC 42
10u
AOUTLP 36
AOUTLN 35
VDDL 34
4 BICK
VDDL 33
AK4490EN
3 PDN
SDATA
6 LRCK
7 WCK
8 CSN
Lch
LPF
Lch
Mute
Lch Out
Rch
LPF
Rch
Mute
Rch Out
0.1u 10u
VSSL 32
VSSL 31
VSSR 30
N
9 CCLK
0.1u 10u
VSSR 29
VDDR 28
24 VCMR
23 VREFLR
22 VREFLR
21 VREFHR
20 VREFHR
19 NC
18 CAD1
AOUTRP 25
17 DEM1
12 DZFR
16 DEM0
AOUTRN 26
15 I2C
VDDR 27
11 DZFL
14 PSN
10 CDTI
13 CAD0
Controller
VREFHL 41
AVSS 44
2 NC
5
Micro-
AVDD 43
DVSS 46
10u
0.1u
MCLK 45
10u
0.1u
TVDD 48
10u 10u
0.1u 0.1u
DVDD 47
1 NC
DSP
Analog 5.0V
Analog 3.3V
0.1u
10u
Digital
Ground
Analog
Ground
10u
Ceramic Capacitor
Figure 38. Typical Connection Diagram (AVDD=3.3V, VDDL/R=5V, DVDD=3.3V, Serial control mode)
(TVDD=1.8V, DVDD=3.3V, AVDD=3.3V, VDDL/R=5.0V and VREFHL/R=5.0V, Serial control mode)
Note 37.
(1) Chip Address = “00”. BICK = 64fs, LRCK = fs
(2) Power lines of AVDD and DVDD should be distributed separately from the point with low impedance
of regulator etc.
(3) AVSS, DVSS, VSSL, VSSR, VREFLL and VREFLR must be connected to the same analog ground
plane.
(4) When AOUT drives a capacitive load, some resistance should be connected in series between
AOUT and the capacitive load.
(5) All input pins except pull-down/pull-up pins should not be allowed to float.
(6) The exposed pad on the bottom surface of the package must be connected to the ground.
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[AK4490EN]
Connection with AK8157A
The AK8157A is recommended to use with a premium DAC, the AK4490EN. Circuits for a high quality
premium audio solution are shown as below.
In this circuit, a 9.6MHz external clock is input to the AK8157A. MCLK, BCLK and LRCK are generated by
the AK8157A. SDATA for the AK4490EN is output from the external DSP in synchronization with BCLK
and LRCK.
Digital
1.8V
VDD1.8V ground
6 LRCK
VCML 37
VREFLL 38
SMUTE
9
SCL
VDDR 28
10 SDA
VDDR 27
11 DIF0
AOUTRN 26
12 DIF1
AOUTRP 25
VSSR 30
0.1u 10u
VSSR 29
+
Rch
LPF
24 VCMR
N
23 VREFLR
13 CAD0
8
Controller
0.1u 10u
+
VSSL 31
WCK
22 VREFLR
0.1u
Micro-
Lch
LPF
VSSL 32
7
17 DEM1
4
VREFLL 39
SDATA
19 NC
BCLK
VDDL 33
5
18 CAD1
VSS2
0.1u
VDDL 34
BICK
16 DEM0
VDD3
VDD4
PDN
4
15 I2C
CAD1
3
RSTN
AOUTLP 36
3
14 PSN
SDA
10u
AOUTLN 35
AK4490EN
VDD2
AK8157A
2
VREFHL 40
1 NC
2 NC
21 VREFHR
VSS3
NC 42
LRCK
VREFHL 41
SCL
0.1u
20 VREFHR
VSS1
1
AVSS 44
MCLK
AVDD 43
A
VDD1
DVSS 46
B
CAD0
10u
0.1u
MCLK 45
C
CLKIN
10u
0.1u
TVDD 48
D
10u 10u
0.1u 0.1u
DVDD 47
9.6MHz
0.1u
Analog 5.0V
Analog 3.3V
0.1u
DSP
Digital
3.3V
0.1u
10u
Digital
1.8V
Digital
ground
Digital
1.8V
Digital
Ground
10u
Analog ground
Analog
Ground
+
Electrolytic Capacitor
Ceramic Capacitor
Figure 39. High Quality Premium Audio Solution of the AK4490EN with the AK8157A
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1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to TVDD, DVDD, AVDD
and VDDL/R respectively. VDDL/R and VREFHL/R are supplied from analog supply in system, and TVDD,
DVDD and AVDD are supplied from digital supply in system. Power lines of TVDD, DVDD, AVDD and
VDDL/R and VREFHL/R should be distributed separately from the point with low impedance of regulator
etc. Digital and analog power supply should be powered up at the same time, otherwise power up the 1.8V
base power supplies (TVDD) at first, the 3.3V base power supplies secondarily (DVDD, AVDD) and 5V
base power supplies finally (VDDL/R, VREFHL/R). DVSS, AVSS, VSSL/R and VREFLL/R must be
connected to the same analog ground plane. Decoupling capacitors for high frequency should be
placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R
pin is normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R
and VREFLL/R should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to
eliminate the effects of high frequency noise. No load current may be drawn from VCML/R pin. All signals,
especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid
unwanted noise coupling into the AK4490EN.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R  VREFLL/R = 5V) centered
around VDDR/2 and VDDL/2 voltages. The differential outputs are summed externally, VAOUT = (AOUT+) 
(AOUT) between AOUT+ and AOUT. If the summing gain is 1, the output range is 5.6Vpp (typ,
VREFHL/R  VREFLL/R = 5V). The bias voltage of the external summing circuit is supplied externally. The
input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFFFH
(@32bit) and a negative full scale for 80000000H (@32bit). The ideal VAOUT is 0V for 00000000H(@32bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond
the audio passband. Figure 40 shows an example of external LPF circuit summing the differential outputs
by an op-amp.
Figure 41 shows an example of differential outputs and LPF circuit example by three op-amps.
AK4490EN
AOUT-
1.5k
1.5k
390
1n
+Vop
AOUT+
2.2n
1.5k
1.5k
Analog
Out
390
1n
-Vop
Figure 40. External LPF Circuit Example 1 for PCM (fc = 99.2kHz, Q=0.704)
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Table 38. Frequency Response of External LPF Circuit Example 1 for PCM
Frequency
Gain
Response
20kHz
0.011dB
40kHz
0.127dB
80kHz
1.571dB
+15
3.3n
+
180
7
3
2 +
* 4
AOUTL- +
3.9n
10k
330
-15
10µ
0.1µ
6
NJM5534D
+
10µ
0.1µ
620
620
3.3n
+
100µ
180
7
3
+
2 4
AOUTL+ +
3.9n
10k
330
1.2k
2
- 4
3 + 7
100
6
1.0n NJM5534D
Lch
g
10µ
0.1µ
6
NJM5534D
680
+10µ
1.0n
1.2k
680
0.1µ
560
560
100µ
0.1µ
+
+
10µ
10µ
0.1µ
Figure 41. External LPF Circuit Example 2 for PCM
Table 39. Frequency Response of External LPF Circuit Example 2 for PCM
1st Stage
2nd Stage
Total
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz -0.025dB
-0.021dB
-0.046dB
Frequency
40kHz -0.106dB
-0.085dB
-0.191dB
Response
80kHz -0.517dB
-0.331dB
-0.848dB
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It is recommended for SACD format book (Scarlet Book) that the filter response at SACD playback is an
analog low pass filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The
AK4490EN can achieve this filter response by combination of the internal filter (Table 40) and an external
filter (Figure 42).
Table 40. Internal Filter Response at DSD Mode
Frequency
Gain
20kHz
0.4dB
50kHz
2.8dB
100kHz
15.5dB
2.0k
1.8k
4.3k
AOUT1.0k
270p
2.8Vpp
2200p
+Vop
3300p
2.0k
1.8k
1.0k
+
AOUT+
+
-
2.8Vpp
4.3k
270p
Analog
Out
6.34Vpp
-Vop
Figure 42. External 3rd Order LPF Circuit Example for DSD
Table 41. 3rd Order LPF (Figure 42) Response
Frequency
Gain
20kHz
0.05dB
50kHz
0.51dB
100kHz
16.8dB
DC gain = 1.07dB
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11. Package
■ Outline Dimensions
48-pin QFN (Unit mm)
0.85 0.05
37
B
48
1
0.10
36
C0.35
0.10
24
A
0.10
0 ~ 0.05
13
0.40
0.20 0.05
0.07 M C A B
(0.20)
6.00
0.40 0.10
(0.55)
4.10
6.00
0.10
4.10
0.08 C
C
Note 38. The exposed pad on the bottom surface of the package must be connected to the ground.
■ Material & Lead finish
Package molding compound:
Lead frame material:
Pin surface treatment:
Epoxy, Halogen (bromine and chlorine) free
Cu
Solder (Pb free) plate
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■ Marking
AKM
AK4490EN
XXXXXXX
1) AKM Logo
2) Pin #1 indication
3) Date Code: XXXXXXX(7 digits)
4) Marking Code: AK4490EN
12. Ordering Guide
■ Ordering Guide
AK4490EN
AKD4490EN
40  +85C
48-pin QFN (0.4mm pitch)
Evaluation Board for AK4490EN
13. Revision History
Date (Y/M/D)
15/10/15
15/12/08
Revision
00
01
Reason
Page
First Edition
Description 7, 61, 66
Addition
Contents
The descriptions regarding the Exposed Pad
were added.
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IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
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application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants
any license to any intellectual property rights or any other rights of AKM or any third party with
respect to the information in this document. You are fully responsible for use of such information
contained in this document in your product design or applications. AKM ASSUMES NO
LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE
USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
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safeguards for your hardware, software and systems which minimize risk and avoid situations in
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4. Do not use or otherwise make available the Product or related technology or any information
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RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
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6. Resale of the Product with provisions different from the statement and/or technical features set
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written consent of AKM.
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