ATA6870N
Li-Ion, NiMH Battery Measuring, Charge Balancing and
Power-supply Circuit
DATASHEET
Features
● 12-bit battery-cell voltage measurement
● Simultaneous battery cells measurement in parallel
● Cell temperature measurement
● Charge Balancing Capability
● Parallel balancing of cells possible
● Integrated power supply for MCU
● Undervoltage detection
● Less than 10µA standby current
● Low cell imbalance current (< 10µA)
● Hot plug-in capable
● Interrupt timer for cycling MCU wake-ups
● Cost-efficient solution due to cost-optimized 30V CMOS technology
● Reliable communication between stacked ICs due to level shifters with current
sources and checksum monitoring of data
● Daisy-chainable
● Each IC monitors up to 6 battery cells
● 16 ICs (96 cells) per string
● No limit on number of strings
● Package QFN48 7mm ×7mm
Applications
● Battery measurement, supply and monitoring IC for Li-ion and NiMH battery
systems in Electric (EV) and Hybrid Electrical (HEV) Vehicles
● Electrical and hybrid electrical vehicles
● Li-Ion batteries as 12V lead-acid battery replacement
● Ebike, scooters
● Uninterruptible power supply (UPS)
● Smart grid
Benefits
● Cost reduction due to integrated measurement circuit and high voltage
power-supply
9317B-AUTO-06/14
1.
Description
The Atmel® ATA6870N is a measurement and monitoring circuit designed for Li-ion and NiMH multicell battery stacks in
hybrid electrical vehicles.
The Atmel ATA6870N monitors the battery-cell voltage and the battery-cell temperature with a 12-bit ADC.
The circuit also provides charge-balancing capability for each battery-cell.
In addition, a linear regulator is integrated to supply a microcontroller or other external components. Reliable communication
between stacked ICs is achieved by level-shifters with current sources. The Atmel ATA6870N can be connected to three,
four, five or six battery-cells. Up to 16 circuits (96 cells) can be cascaded in one string. The number of strings is not limited.
2.
Block Diagram
Figure 2-1. Block Diagram
To ATA6870
above
VDDHV
MBAT7
PD_N
DISCH6
Digital
Level Shifter
Cell 6:
Reference
ADC
Cell Balancing
Standby Control
PD_N_OUT
VDDHVP
3.3V
Voltage Regulator
MBAT6
POW_ENA
VDDHVM
AVDD
3.3V Internal
Voltage Regulator
DISCH1
Logic
Cell 1:
Reference
ADC
Cell Balancing
Digital
Level Shifter
MBAT2
BIASRES
Internal Biasing
MBAT1
NTC
NTC
Interchip
and
Microcontroller
Communication
Interface
Test
Cell
Temperature
Measuring
TEMP1
Digital
Level Shifter
TEMPREF
TEMP2
TEMPVSS
GND AVSS DVSS SCANMODE
PWTST
DTST
CS_FUSE
DVDD
VDDFUSE
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
CLK_OUT
IRQ_IN
CS_N
SCK
MOSI
MISO
IRQ
CLK
MCU
MFIRST
ATST
To ATA6870
below
2
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Pin Configuration
Table 3-1.
MBAT6
DISCH6
MBAT7
VDDHV
IRQ_IN
CLK_OUT
CS_N_OUT
SCK_OUT
MOSI_OUT
MISO_IN
PD_N
VDDHVP
Figure 3-1. Pinning QFN48, 7 mm ×7 mm
48
47
46
45
44
43
42
41
40
39
38
37
DISCH5
1
36
VDDHVM
MBAT5
2
35
PD_N_OUT
DISCH4
3
34
POW_ENA
MBAT4
4
33
PWTST
DISCH3
5
32
BIASRES
MBAT3
6
31
TEMPREF
DISCH2
7
30
TEMP2
MBAT2
8
29
TEMP1
DISCH1
9
28
TEMPVSS
MBAT1
10
27
AVSS
IRQ
11
26
AVDD
CLK
12
25
ATST
15
16
17
18
19
20
21
22
23
24
MISO
MFIRST
DTST
SCANMODE
CS_FUSE
VDDFUSE
DVSS
DVDD
GND
14
MOSI
13
SCK
Atmel
ATA6870N
CS_N
3.
Pin Description
Pad Number
Pad Name
Exposed Pad
Function
Remark
Heatslug
1
DISCH5
Output to drive external cell-balancing
transistor
2
MBAT5
Battery cell sensing line
3
DISCH4
Output to drive external cell-balancing
transistor
4
MBAT4
Battery cell sensing line
5
DISCH3
Output to drive external cell-balancing
transistor
6
MBAT3
Battery cell sensing line
7
DISCH2
Output to drive external cell-balancing
transistor
8
MBAT2
Battery cell sensing line
9
DISCH1
Output to drive external cell-balancing
transistor
10
MBAT1
Battery cell sensing line
11
IRQ
Interrupt output for MCU/ATA6870N below
12
CLK
System clock
13
CS_N
14
SCK
SPI clock input from MCU/ATA6870N below
15
MOSI
Master Out Slave In input from MCU
Chip select input from MCU/ATA6870N below
SPI data input
ATA6870N [DATASHEET]
9317B–AUTO–06/14
3
Table 3-1.
4
Pin Description (Continued)
Pad Number
Pad Name
Function
Remark
16
MISO
Master In Slave Out output for MCU
SPI data output
17
MFIRST
18
DTST
Test-mode pin
Keep pin open (output)
19
SCANMODE
Test-mode pin
Connected to VSSA
20
CS_FUSE
Test-mode pin
Connected to VSSA
21
VDDFUSE
Test-mode pin
Connected to VSSA
22
DVSS
Digital negative supply
23
DVDD
Digital positive supply input (3.3V)
24
GND
Ground
25
ATST
Test-mode pin
26
AVDD
3.3V Regulator output
27
AVSS
Analog negative supply
28
TEMPVSS
29
TEMP1
Temperature measuring input 1
30
TEMP2
Temperature measuring input 2
31
TEMPREF
Reference voltage for temperature measuring
32
BIASRES
Internal supply current adjustment
Select Master/Slave
PWTST
34
POW_ENA
Power regulator enable/disable
35
PD_N_OUT
Power down output
36
VDDHVM
Power regulator output to supply e.g. an
external microcontroller
37
VDDHVP
Power regulator supply voltage
38
PD_N
39
MISO_IN
Master In Slave Out input from ATA6870N
above
40
MOSI_OUT
Master Out Slave In output for ATA6870N
above
41
SCK_OUT
SPI clock output for input of ATA6870N above
42
CS_N_OUT
43
CLK_OUT
Test - mode pin
Power down input
Chip select output for input of ATA6870N
above
System clock output for input of ATA6870N
above
44
IRQ_IN
Interrupt input from ATA6870N above
45
VDDHV
Supply voltage
46
MBAT7
Battery cell sensing line
47
DISCH6
Output to drive external cell-balancing
transistor
48
MBAT6
Battery cell sensing line
9317B–AUTO–06/14
Keep pin open (output)
Ground for temperature measuring
33
ATA6870N [DATASHEET]
Connected to AVDD
Keep pin open (output)
4.
ATA6870N System Overview
The Atmel® ATA6870N can be stacked up to 16 times in one string. The communication with MCU is carried out on the
lowest level through an SPI bus. The data on the SPI bus is transmitted to the 15 other Atmel ATA6870Ns using the
communication interface implemented inside Atmel ATA6870N.
Figure 4-1. Battery Management Architecture with One Battery String
Atmel
ATA6870N
Atmel
ATA6870N
Atmel
ATA6870N
Atmel
ATA6870N
MCU
ATA6870N [DATASHEET]
9317B–AUTO–06/14
5
Figure 4-2. Battery Management Architecture with Several Battery Strings
Atmel
ATA6870N
Atmel
ATA6870N
MCU
OPTO
Atmel
ATA6870N
Atmel
ATA6870N
MCU
6
ATA6870N [DATASHEET]
9317B–AUTO–06/14
To Battery
Master Controller
5.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Unless otherwise specified all voltages to pin VSSA.
Parameters
Pin
Symbol
Min.
Max.
Unit
TA
–40
+85
°C
Junction temperature
TJ
–40
+125
°C
Storage temperature
TS
–55
+150
°C
VMBAT(i+1) VMBAT(i)
–0.3
+5.5
V
Ambient temperature
Battery cell voltage
MBAT(i+1),
MBAT(i)
VVDDHV - VVMBAT7max
VVDDHV - VVMBAT7
–5.5
+0.3
V
MBAT1
VMBAT1
–0.3
+0.3
V
VDDHVP
VVDDHVP
–0.3
+33.6
V
VDDHV
VVDDHV
–0.3
+30
V
Supply voltage DVDD (regulator is off)
DVDD
VDVDD
–0.3
+5.5
V
Supply voltage AVDD (regulator is off)
AVDD
VAVDD
–0.3
+5.5
V
Test-input
VDDFUSE
VVDDFUSE
–0.3
+5.5
V
Reference voltage for temperature
measuring (regulator is Off)
TEMPREF
VTEMPREF
–0.3
VDD+0.3
V
Supply voltage VDDHVM (regulator is Off)
VDDHVM
V VDDHVM
–0.3
+5.5
V
Digital ground
DVSS
VAVSS - VGND
–0.3
+0.3
V
Analog ground
AVSS
VAVSS - VGND
–0.3
+0.3
V
AVSS, DVSS
VAVSS - VDVSS
–0.3
+0.3
V
TEMPVSS
VTEMPVSS
–0.3
+0.3
V
CLK, CS_N,
SCK, MOSI,
DTST, ATST,
SCANMODE,
MFIRST,
POW_ENA,
CS_FUSE,
PWTST
VCLK, VCS_N,
VSCK, VMOSI,
VDTST, VATST,
VSCANMODE,
VMFIRST,
VPOW_ENA,
VCS_FUSE,
VPWTST
–0.3
VDD + 0.3
V
IRQ, MISO
VIRQ, VMISO
–0.3
+5.5
V
Input voltage for analog I/O pins
TEMP1,
TEMP2,
BIASRES
VTEMP1, VTEMP2,
VBIASRES
–0.3
VDD + 0.3
V
Input voltage for digital high voltage input
pins
MISO_IN,
IRQ_IN
VMISO_IN, VIRQ_IN
VDDHV – 0.3
VDDHV + 0.3
V
Voltage at digital high voltage output pins
MOSI_OUT,
SCK_OUT,
CS_N_OUT,
CLK_OUT
VMOSI_OUT,
VSCK_OUT,
VCS_N_OUT,
VCLK_OUT
VDDHV – 0.3
VDDHV + 0.3
V
VMBAT1
Supply voltage power regulator
Operating supply voltage
Digital/analog ground
Ground voltage for temperature measuring
Input voltage for logic I/O pins
Input: PD_N
Output: PD_N_OUT
Voltage at cell balancing outputs
PD_N
V PD_N
VDDHV – 5.5
VDDHV + 0.3
V
PD_N_OUT
V PD_N_OUT
–5.5
+0.3
V
DISCH(i)
VDISCH(i)
VMBAT(i) – 0.3
VMBAT(i+1) + 0.3
V
ATA6870N [DATASHEET]
9317B–AUTO–06/14
7
5.
Absolute Maximum Ratings (Continued)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Unless otherwise specified all voltages to pin VSSA.
Parameters
Pin
Symbol
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
CDM ESD STM 5.3.1
Max.
Unit
±2
kV
500
V
750
V
±100
mA
ESD
1, 12, 13, 24,
25, 36, 37, 48
Latch-up acc. to AECQ100-004, JESD78A
6.
Min.
LATCH-UP
Thermal Resistance
Parameters
Symbol
Value
Unit
Rthjamax
20
K/W
Package. QFN48 7×7
Max. thermal resistance junction-ambient(1)
Max. thermal resistance junction-case
RthjCmax
TBD
Note:
1. Package mounted on 4 large PCB (per JESD51-7) under natural convention as defined in JESD51-2.
7.
K/W
Circuit Description and Electrical Characteristics
Unless otherwise specified all parameters in this section are valid for a supply voltage range of 6.9V < VDDHV < 30V and a
battery cell voltage of VMBAT(i+1) – VMBAT(i) = 0V to 5V, –40°C < TA < 85°C. All values refer to pin VSSA, unless otherwise
specified.
7.1
Operating Modes
The Atmel® ATA6870N has two operation modes.
1. Power-down mode (PDmode)
2.
7.1.1
Normal mode (NORM mode)
Power-down Mode
In power-down mode all blocks of the IC are switched off.
The circuit can be switched from Power-down to ON mode or back via the PD_N input. If the pin is connected to VDDHV via
an external optocoupler, for example, the circuit is in ON mode. If several Atmel ATA6870N are stacked, the power-down
signal must be only provided for the IC on the top level of the stack. The next lower IC receives this information from the
PD_N_OUT output of its upper IC. The PD_N_OUT pin must be connected to either the PD_N pin of the next lower Atmel
ATA6870N or to VSSA.
8
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Figure 7-1. Power-down
VDDHV
MBAT7
PD_N
Digital
Level Shifter
Cell 6:
Reference
ADC
Cell Balancing
DISCH6
Standby Control
PD_N_OUT
VDDHVP
3.3V
Voltage Regulator
POW_ENA
VDDHVM
MBAT6
AVDD
ATA6870
3.3V Internal
Voltage Regulator
Cell 1:
Reference
ADC
Cell Balancing
DISCH1
Internal Biasing
MBAT1
NTC
Interchip
and
Microcontroller
Communication
Interface
Test
Cell
Temperature
Measuring
TEMP1
NTC
Digital
Level Shifter
TEMPREF
TEMP2
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
CLK_OUT
IRQ_IN
CS_N
SCK
MOSI
MISO
IRQ
CLK
MFIRST
VDDFUSE
ATST
DTST
CS_FUSE
PWTST
SCANMODE
DVSS
GND
TEMPVSS
AVSS
DVDD
BIASRES
Logic
Digital
Level Shifter
MBAT2
VDDHV
MBAT7
PD_N
Digital
Level Shifter
Cell 6:
Reference
ADC
Cell Balancing
DISCH6
Standby Control
PD_N_OUT
VDDHVP
3.3V
Voltage Regulator
POW_ENA
VDDHVM
MBAT6
AVDD
ATA6870
3.3V Internal
Voltage Regulator
Cell 1:
Reference
ADC
Cell Balancing
DISCH1
Logic
Digital
Level Shifter
MBAT2
BIASRES
Internal Biasing
MBAT1
TEMPREF
NTC
MCU
MFIRST
VDDFUSE
ATST
DTST
CS_FUSE
PWTST
SCANMODE
DVSS
GND
TEMPVSS
AVSS
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
CLK_OUT
IRQ_IN
CS_N
SCK
MOSI
MISO
IRQ
CLK
Test
Cell
Temperature
Measuring
TEMP1
NTC
Interchip
and
Microcontroller
Communication
Interface
Digital
Level Shifter
TEMP2
DVDD
ATA6870N [DATASHEET]
9317B–AUTO–06/14
9
Table 7-1.
Electrical Characteristics
No. Parameters
Pin
Symbol
1.1
Maximum allowed input
current in power-down
mode (e.g., leakage
current of an optocoupler)
Test Conditions
PD_N
IPD_N
1.2
Input current in ON mode
PD_N
IPD_N
1.3
Maximum voltage
(pin PD_N left open)
Max.
Unit
Type*
50
µA
A
5
mA
A
PD_N
VVDDHV VPD_N
5
V
A
1.4
Propagation delay time
from power-down mode
to NORM mode
DVDD
tVDDON
3
ms
A
1.5
Propagation delay time
from NORM mode to
power-down mode
DVDD
tVDDOFF
10
ms
A
IPD_N = 0 to 50µA
Min.
Typ.
2.5
min slope
1 mA
I PD_N = ------------msec
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
7.1.2
Normal Operating Mode (NORM Mode)
The Atmel® ATA6870N turns on when the PD_N signal is switched from low to high. The power supplies AVDD and DVDD
as well as VDDHVM (if the input signal POW_ENA = high) are turned on. The configuration registers are set to their default
values. In NORM mode the Atmel ATA6870N can acquire analog data (voltage or temperature channels) upon request from
the host microcontroller. When the host microcontroller orders an acquisition through the SPI bus, the IC starts digitizing all
voltage and one temperature channel in parallel. The on-chip digital signal processor filters, in real time, the channel
samples. When conversion and filtering are done, the data-ready interrupt to the host processor indicates the data
availability. The MCU can now read the ADC result registers. The MCU reads the Atmel ATA6870N’s status registers to
check each IC and to acknowledge the interrupt. When Atmel ATA6870N is in NORM mode, the MCU can be active or in idle
mode. In order to wake-up the MCU by an interrupt, the Low Frequency Timer (LFT) can be activated in Atmel ATA6870N.
Interrupt is signaled with a high level on IRQ pin. The LFT is re-programmable on the fly and can be reset through SPI, but is
not stoppable.
Figure 7-2. Atmel ATA6870N in NORM Mode
ASICs in NOMode
Idle
IRQ
SPI
MCU
10
ACQ Cmd
Background Send SPI Background
task
Command
task/Idle
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Acquisition
Asserted
Read status register
Interrupt
Handling
Idle
Read data burst mode
Background
task
Processing
Table 7-2.
Electrical Characteristics
No. Parameters
Pin
Symbol
Min.
2.1
Supply voltage
Test Conditions
VDDHV
VVDDHV
6.9
2.2
Current consumption
IVDDHV (normal mode)
VDDHV
IVDDHV
2.3
Current consumption in
power-down mode
(PDmode) IVDDHV +
IMBAT(i)max(1)
VMBAT(i+1) –
VMBAT(i) = 3.7V
VDDHV
2.4
Imbalance from battery
cell to battery cell in
power-down mode
(PDN Mode)
VMBAT(i+1) –
VMBAT(i) = 3.7V
MBAT(i+1)
Typ.
IMBAT(i+1)
Max.
Unit
Type*
30
V
A
15
mA
A
10
µA
A
10
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
7.2
1.
Largest input current of the cell inputs MBAT(i)
Interface to Battery Cells
Each input line MBAT(i) and the supply lines VDDHV, AVSS can be protected by additional resistors and a filter capacitor as
shown below.
Figure 7-3. External Components between Atmel ATA6870N and the Battery Cells
R_VDDHV
R_IN
VDDHV
MBAT(i+1)
Discharge
Resistor
Battery
cell(i)
Cell(i)
DISCH(i)
R_IN
R_VSS
Battery cell
Board
MBAT(i)
AVSS
ATA6870
MBAT(i) are high impedance input (~2MΩ). Thus, external components can be added to protect ATA6870N chip against
current spikes and overvoltage at battery cell level.
ATA6870N [DATASHEET]
9317B–AUTO–06/14
11
Table 7-3.
Electrical Characteristics
No.
Parameters
Max.
Unit
Type*
3.1
R_IN
Test Conditions
MBAT(i)
Pin
Symbol
Min.
Typ.
1
kΩ
D
3.2
R_VDDHV
VDDHV
50
Ω
D
3.3
R_VSS
AVSS
50
Ω
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
7.3
Reduced Number of Battery Cells Configuration
It is possible for Atmel® ATA6870N to operate with a reduced number of cells: 3, 4, 5, and 6 cell operation are possible. In
these cases, the cell-chip inputs corresponding to the missing cells should be connected to the upper cell potential of the
module.
VDDHV
Figure 7-4. Connection with 4 Cells only
MBAT7
PD_N
PD_N_OUT
DISCH6
VDDHVP
POW_ENA
MBAT6
VDDHVM
DISCH5
AVDD
DVDD
MBAT5
BIASRES
DISCH4
Atmel
ATA6870N
MBAT4
DISCH3
MISO_IN
MOSI_OUT
SCK_OUT
MBAT3
CS_N_OUT
CLK_OUT
DISCH2
IRQ_IN
MBAT2
CS_N
DISCH1
SCK
MFIRST
VDDFUSE
ATST
DTST
CS_FUSE
SCANMODE
AVSS
MISO
DVSS
MOSI
TEMPREF
TEMP2
TEMP1
TEMPVSS
GND
MBAT1
IRQ
CLK
Battery cell 1 (MBAT1, MBAT2) and battery cell 6 (MBAT6, MBAT7) must always be used for the lowest/highest cell.
12
ATA6870N [DATASHEET]
9317B–AUTO–06/14
7.4
ATA6870N External MCU Supply
The Atmel® ATA6870N provides a 3.3V power-supply for external components such as the microcontroller unit (MCU). The
input pin for this supply is pin VDDHVP, and the output pin is VDDHVM. This regulator is able to supply the MCU directly
from the topmost battery cell of a string. The power regulators of all stacked Atmel ATA6870N are therefore put in serial
configuration to avoid imbalance.The regulator can be disabled with the digital input pin POW_ENA.
Table 7-4.
Truth Table
Pin
Symbol
POW_ENA
VPOW_ENA
Value
Function
Low
Voltage regulator disabled
High
Voltage regulator enabled
Logic levels: Low = VDVSS, High = VDVDD
ATA6870N [DATASHEET]
9317B–AUTO–06/14
13
Figure 7-5. MCU Supply with the Internal Power Supply
VDDHV
MBAT7
PD_N
Digital
Level Shifter
Standby Control
Cell 6:
Reference
ADC
Cell Balancing
DISCH6
PD_N_OUT
VDDHVP
3.3V
Voltage Regulator
POW_ENA
VDDHVM
MBAT6
AVDD
ATA6870
3.3V Internal
Voltage Regulator
Cell 1:
Reference
ADC
Cell Balancing
DISCH1
Logic
Digital
Level Shifter
MBAT2
BIASRES
Internal Biasing
MBAT1
Cell
Temperature
Measuring
TEMP1
Interchip
and
Microcontroller
Communication
Interface
Test
Digital
Level Shifter
TEMPREF
TEMP2
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
CLK_OUT
IRQ_IN
CS_N
SCK
MOSI
MISO
IRQ
CLK
MFIRST
VDDFUSE
ATST
DTST
CS_FUSE
PWTST
SCANMODE
DVSS
GND
TEMPVSS
AVSS
DVDD
+
VDDHV
MBAT7
PD_N
Standby Control
Digital
Level Shifter
Cell 6:
Reference
ADC
Cell Balancing
DISCH6
PD_N_OUT
VDDHVP
3.3V
Voltage Regulator
POW_ENA
VDDHVM
MBAT6
AVDD
ATA6870
3.3V Internal
Voltage Regulator
Cell 1:
Reference
ADC
Cell Balancing
DISCH2
Logic
Digital
Level Shifter
MBAT2
BIASRES
TEMPREF
Interchip
and
Microcontroller
Communication
Interface
Digital
Level Shifter
Test
Cell
Temperature
Measuring
TEMP1
9317B–AUTO–06/14
MFIRST
VDDFUSE
ATST
DTST
CS_FUSE
PWTST
SCANMODE
DVSS
GND
ATA6870N [DATASHEET]
AVSS
TEMPVSS
14
+
Internal Biasing
MBAT1
TEMP2
DVDD
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
CLK_OUT
IRQ_IN
CS_N
SCK
MOSI
MISO
IRQ
CLK
MCU
Table 7-5.
Electrical Characteristics
No.
Parameters
Pin
Symbol
Min.
4.1
Supply voltage
Test Conditions
VDDHVP
VVDDHVP
6.9
4.2
Output voltage
VDDHVM
VVDDHVM
3.1
4.3
DC output current
VDDHVM
IVDDHVM
IVDDHVM
(1)
Typ.
Max.
Unit
Type*
33.3
V
A
3.5
V
A
20
mA
A
50
3.3
4.4
Peak output current
VDDHVM
mA
A
4.5
Capacitor load(2)
VDDHVM
30
33
µF
D
4.6
Capacitor load(2)
VDDHVM
200
220
nF
D
4.7
High level input voltage
POW_ENA
VPOW_ENA
V
A
4.8
Low level input voltage
POW_ENA
VPOW_ENA
V
A
4.9
Hysteresis
POW_ENA
VPOW_ENA
0.05 ×
VDVDD
V
C
4.10
Input current
POW_ENA
IPOW_ENA
–1
µA
A
VPOW_ENA = 0V to
VDVDD
0.7 ×
VDVDD
0.3 ×
VDVDD
+1
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
Maximum current the power regulator can provide, time limited by thermal consideration only
2.
These capacitors are mandatory
ATA6870N [DATASHEET]
9317B–AUTO–06/14
15
Figure 7-6. MCU Supply with an External Power Supply
VDDHV
MBAT7
PD_N
Digital
Level Shifter
Standby Control
Cell 6:
Reference
ADC
Cell Balancing
DISCH6
PD_N_OUT
VDDHVP
3.3V
Voltage Regulator
POW_ENA
VDDHVM
MBAT6
AVDD
ATA6870
3.3V Internal
Voltage Regulator
Cell 1:
Reference
ADC
Cell Balancing
DISCH2
Logic
Digital
Level Shifter
MBAT2
BIASRES
Internal Biasing
MBAT1
Cell
Temperature
Measuring
TEMP1
Interchip
and
Microcontroller
Communication
Interface
Test
Digital
Level Shifter
TEMPREF
TEMP2
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
CLK_OUT
IRQ_IN
CS_N
SCK
MOSI
MISO
IRQ
CLK
MFIRST
VDDFUSE
ATST
DTST
CS_FUSE
PWTST
SCANMODE
DVSS
GND
TEMPVSS
AVSS
DVDD
VDDHV
MBAT7
PD_N
Standby Control
Digital
Level Shifter
Cell 6:
Reference
ADC
Cell Balancing
DISCH6
PD_N_OUT
VDDHVP
3.3V
Voltage Regulator
MBAT6
VDDHVM
AVDD
ATA6870
3.3V Internal
Voltage Regulator
Cell 1:
Reference
ADC
Cell Balancing
DISCH2
Logic
Digital
Level Shifter
MBAT2
BIASRES
Cell
Temperature
Measuring
TEMP1
Interchip
and
Microcontroller
Communication
Interface
Test
Digital
Level Shifter
TEMPREF
TEMP2
MFIRST
VDDFUSE
ATST
DTST
CS_FUSE
PWTST
SCANMODE
DVSS
GND
9317B–AUTO–06/14
AVSS
TEMPVSS
ATA6870N [DATASHEET]
DVDD
Internal Biasing
MBAT1
16
POW_ENA
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
CLK_OUT
IRQ_IN
CS_N
SCK
MOSI
MISO
IRQ
CLK
MCU
7.5
Analog Blocks
7.5.1
Battery Voltage Measuring
Figure 7-7. Block Diagram Battery Voltage Measurement
External
ATA6870N
1.666V
Reference
DVDD
MBAT(i+1)
Cell i
MBAT(i)
12 bits
incremental
ADC
High
voltage
level shifter
(digital)
DISCH(i)
Bitstream
CLK
MUX
Disch(i)
DVSS
The battery voltage measurement block contains
● a 2-input multiplexer
●
●
●
a voltage reference,
a 12-bit ADC
the upper part of digital voltage level shifters
7.5.1.1 Input Multiplexer
The multiplexer has 3 inputs. Each of the functions are described in the table below:
Table 7-6.
Inputs of the Multiplexer
Input
Function
V(MBAT(i+1), MBAT(i))
Input voltage measurement
V(MBAT(i), MBAT(i))
Offset error acquisition of ADC
The multiplexer inputs are controlled by SPI.
ATA6870N [DATASHEET]
9317B–AUTO–06/14
17
7.5.1.2 12 Bits Incremental ADC
The purpose of this cell is to convert an analog input into a 12-bit digital word.
Table 7-7.
Electrical Characteristics
No. Parameters
5.1
Accuracy of voltage
channel(1)
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Maximum input noise
0.5mVrms
2.2V < VMBAT(i+1) – VMBAT(i)
< 4.5V
MBAT(i+1),
MBAT(i)
–10
+10
mV
A
Maximum input noise
0.5mVrms
0V < VMBAT(i+1) – VMBAT(i)
< 5V
MBAT(i+1),
MBAT(i)
–20
+20
mV
A
Maximum input noise
0.5mVrms
VMBAT(i+1) – VMBAT(i) = 3.7V
TJ = –20°C to +65°C
MBAT(i+1),
MBAT(i)
–7
+7
mV
A
Maximum input noise
0.5mVrms Aging(3)
MBAT(i+1),
MBAT(i)
–11
+11
mV
C
Maximum input noise
0.5mVrms Aging(4)
MBAT(i+1),
MBAT(i)
–17
+17
mV
C
0
5
V
A
MBAT(i+1),
MBAT(i)
5.2 Input voltage range
VMBAT(i+1),
VMBAT(i)
5.3 Input resolution (1 LSB)
VLSB
1.5
mV
D
5.4 Reference voltage
VRef
1.667
V
D
5.5 Offset voltage
MBAT(i+1),
MBAT(i)
VMBAT(i+1),
VMBAT(i)
410
LSB
A
5.6 Gain voltage
MBAT(i+1),
MBAT(i)
VMBAT(i+1),
VMBAT(i)
655
LSB/V
A
5.7 System clock
CLK
fCLK
kHz
D
5.8 SPI interface clock
SCK
fSCK
5.9 Conversion rate(2)
tconv = (212 + 1) / fCLK
5.10 Input bandwidth
MBAT(i+1),
MBAT(i)
450
500
550
0.5 ×
fCLK
D
tconv
8.194
ms
D
fBW
50
Hz
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
18
1.
The accuracy of the voltage channels is guaranteed with no external resistor in the MBAT(i), MBAT(i+1) lines.
2.
Conversion rate without readout times of SPI
3.
Aging temperature TJ = 125°C, drift measured at 25°C and 85°C
4.
Aging temperature TJ = 125°C, drift measured at –40°C
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Converting ADC Results to Voltage
The silicon is factory adjusted by measuring offset voltage (VOffset) with both ADC inputs connected to MBATi and
calibration of the adc(MBATi+1) value to 3031 at MBATi+1 = 4.0V (see Figure 7-8).
Figure 7-8. Characteristics of AD-converter
ADC output
3686D = 0.9D x 212
3031
Slope = (3031 - 410D)/4V = 655DLSB/V
410D = 0.1 x 212
Input Voltage
(MBATi+1, MBATi)
0
0
4
5
adc(VOffset): ADC result with both ADC inputs connected to MBATi (0V input voltage)
adc(VMBATi+1-VMBATi): Uncorrected ADC result of the ADC input voltage
Standard Procedure with Frequent Offset Adjustment
To use the frequent offset adjustment of the ADC the following parameters need to be measured:
adc(VOffset) ADC result with both ADC inputs connected to MBATi (0V input voltage)
adc(VMBATi+1-VMBATi) Uncorrected ADC result of the ADC input voltage
Calculation of the battery cell voltage:
VIn = 4V × (adc(VMBATi+1-VMBATi) – adc(VOffset)) / (3031 – adc(VOffset))
with VIn = V(MBATi+1)-V(MBATi)
It’s not necessary to measure VOffset during every measuring cycle.
Regular updates are sufficient.
Standard Procedure without Offset Adjustment
With increasing input voltages the failure caused by the ADC can be ignored. In this case the battery cell voltage can be
calculated by the following equation:
VIn = 4V × (adc(VMBATi+1-VMBATi) – 0.1 × 212) / (3031 – 0.1 × 212)
The following simplification can be done with less than 1mV rounding error:
VIn = 1.52656 × 10-3 × (adc(VMBATi+1-VMBATi) – 410)
ATA6870N [DATASHEET]
9317B–AUTO–06/14
19
7.5.1.3 Acquisition Time and Clocking
The acquisition time depends on the number of Atmel® ATA6870Ns to be addressed.
Table 7-8.
Electrical Characteristics
Number of ATA6870N
SCK Frequency (kHz)
CLK Frequency
(kHz)
Conversion
Time (ms)
Total Acquisition
Duration (ms)(1)
1
250
500
8.2
9.5
2
250
500
8.2
10.2
3
250
500
8.2
10.8
4
250
500
8.2
11.5
5
250
500
8.2
12.2
6
125
500
8.2
17.0
7
125
500
8.2
18.4
8
125
500
8.2
19.7
9
125
500
8.2
21.1
10
62.5
500
8.2
36.1
Notes:
11
62.5
500
8.2
38.8
12
62.5
500
8.2
41.5
13
62.5
500
8.2
44.2
14
62.5
500
8.2
46.8
15
62.5
500
8.2
49.5
16
62.5
500
8.2
52.2
1. The total acquisition time takes the following into account:
- ADC conversion
- Reading of voltage values in burst mode for all ATA6870N devices,
- Reading of temperature values for all ATA6870N devices (only one temperature input is read).
SPI clock (pin SCK) must a maximum of half the frequency of the system clock CLK.
20
ATA6870N [DATASHEET]
9317B–AUTO–06/14
7.5.2
Battery Cell Discharge
Each battery cell can be discharged with an external resistor and an NMOS transistor.
Figure 7-9. External Circuit for Cell Balancing
R_VDDHV
VDDHV
R_IN
MBAT(i+1)
Discharge
Resistor
Battery
cell(i)
Cell(i)
DISCH(i)
R_IN
MBAT(i)
R_VSS
Battery cell
AVSS
Board
ATA6870
The pin DISCH(i) (Discharge for battery cell i) is intended to switch on the external discharge resistor in parallel to the battery
cell to bypass charge current for cell balancing reasons.
The pin DISCH(i) is a digital output:
No discharge: VDISCH(i) = VMBAT(i)
Discharge: VDISCH(i) = VMBAT(i+1)
Table 7-9.
Electrical Characteristics
No. Parameters
Test Conditions
6.1 Operating voltage range
Pin
Symbol
Min.
MBAT(i)
MBAT(i+1) –
MBAT(i)
1.5
Typ.
Max.
Unit
Type*
5
V
A
6.2 High-level output voltage
IDISCH(i) = –10µA,
MBAT(i+1) – MBAT(i) =
1.5V to 5V
DISCH(i)
VDISCH(i) –
VMBAT(i)
VMBAT(i+1) –
50 mV
V
A
6.3 High-level output voltage
IDISCH(i) = –1mA
MBAT(i+1) – MBAT(i) =
3V to 5V
DISCH(i)
VDISCH(i) –
VMBAT(i)
VMBAT(i+1) –
0.6V
V
A
kΩ
A
6.4 Pull-down resistor(1)
DISCH(i)MBAT(i)
60
140
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1.
Integrated pull-down resistor between pins DISCH(i) and MBAT(i)
ATA6870N [DATASHEET]
9317B–AUTO–06/14
21
7.5.3
Temperature Channel
The temperature sensors are based on a resistor divider using a standard resistor and an NTC resistor. This resistor divider
is connected to the reference of the ADC for temperature measuring. As the ADC is sharing same reference value, the
output of temperature measurement with ADC is ratio metric.
Figure 7-10. Battery Cell Temperature Measurement
AVDD
TEMPREF
RES_REF2
1.2V
Reference
RES_REF1
TEMP1
TEMP2
RES_NTC2
12 bits
Incremental ADC
OUT
RES_NTC1
Operation Register
TEMPVSS
During one measuring cycle only one temperature input can be measured by the ADC. The channel can be selected in the
Operation Register (0x02) by the TempMode bit (bit 3).
The ADC output is equal to:
RES_NTC(1)
8
8
out = 2048 × 1 + --------------------------------------------------------------------------- × ------ – ------
(RES_NTC(1) + RES_REF(1)) 15 10
Table 7-10. Electrical Characteristics
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1.1
1.2
1.3
V
A
2
mA
A
VTEMPR
V
A
V
A
µA
A
7.1
Reference voltage
TEMPREF
VTEMPREF –
VTEMPVSS
7.2
Reference voltage output
current
TEMPREF
ITEMPREF
7.3
Input voltage range
TEMP1
VTEMP1
0
VTEMP2
0
7.4
Input voltage range
TEMP2
TEMPx
EF
VTEMPR
EF
7.5
Input current
VTEMPx = 1.2V
ITEMPx
1
7.6
Code output for
value(RES_NTCx) =
value (RES_REFx)
V(TEMPi,
TEMPVSS) = 0.5 ×
V(TEMPREF,
TEMPVSS)
931D
956D
981D
A
7.7
Code output for
value(RES_NTC) = 0
V(TEMPi,
TEMPVSS) = 0
385D
410D
435D
A
7.8
Code output for
value(RES_NTC) =
infinite
V(TEMPi,
TEMPVSS) =
V(TEMPREF)
1477D
1502D
1527D
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA6870N [DATASHEET]
9317B–AUTO–06/14
7.5.4
Internal Voltage Regulator
The regulator output is pin AVDD. The pins AVDD and DVDD have to be connected together. An external filtering capacitor
(10nF recommended) is used to filter and stabilize the function. The regulator output can be used to supply outside functions
at the price of power supply imbalance between battery cells.
Table 7-11. Electrical Characteristics
No. Parameters
Test Conditions
Pin
Symbol
Min.
8.1
Supply voltage range
VDDHV
VVDDHV
6.9
8.2
Regulated output voltage
AVDD
VAVDD
3.1
8.3
Output current
AVDD
IAVDD
0
8.4
Cload (load capacitor)
Cload
9
Typ.
Max.
Unit
Type*
30
V
A
3.3
3.5
V
A
5
mA
A
nF
D
10
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
7.5.5
Central Biasing
This block generates a precise bias current to supply internal blocks of the IC. Connection of any external loads to this pin is
not allowed.
Table 7-12. Electrical Characteristics
No. Parameters
9.1
Biasing voltage
9.2
External resistor
9.3
Tolerance
9.4
Maximum external
parasitic capacitor
Test Conditions
Pin
Symbol
BIASRES
VBIASRES
1.2
V
A
RRefbias
121
kΩ
D
+1
%
D
50
pF
D
ΔRRefbias
BIASRES
Min.
Typ.
Max.
–1
CExternal
Unit
Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 7-11. Internal Bias Current Generation
IBIAS
Bandgap 1.2V
BIASRES
RREFBIAS
121kΩ
ATA6870N [DATASHEET]
9317B–AUTO–06/14
23
7.5.6
RC Oscillator
Table 7-13. Internal RC Oscillator Frequency
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
fOsc
45
50
55
kHz
A
10.1 Oscillator frequency
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
7.5.7
Power On Reset
The power on reset is used to initialize the digital part at power-up.
The power on reset circuit is functional when the voltage at pin DVDD is larger than VPOROP.
There are two reset sources:
System “hard reset”
System hard reset occurs when the voltage at pin DVVD goes below the power on reset threshold.
ATA6870N registers are set to their initial values.
After t = tRESET, the MCU can access the Atmel® ATA6870N.
Figure 7-12. Power On Reset
VPOROFF
VPORON
VPOROP
VDVDD
VPOR
Table 7-14. Electrical Characteristics
No. Parameters
Test Conditions
Pin
Symbol
11.1 Power on reset functional
DVDD
VPOROP
11.2 Power on reset off
DVDD
VPOROFF
1.5
11.3 Power on reset hysteresis
DVDD
VPOROFF –
VPORON
0.03
11.4 Power on reset time
tRESET
Min.
Typ.
Max.
Unit
Type*
0.8
V
A
2.5
V
A
V
C
µs
A
800
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
24
ATA6870N [DATASHEET]
9317B–AUTO–06/14
7.6
Digital Part
7.6.1
General Features
The digital parts of the ATA6870N includes the following blocks:
● 4-wire-SPI full duplex communication with external host MCU
●
●
●
●
7.6.2
SPI system protocol management (frames decoding) and configuration registers bank
Interrupt to MCU management
Operations decoding (voltage and/or temperature acquisition) and analog part control
Low frequency timer (50kHz) for wake-up management
Host Interface
Figure 7-13. Host Interface
VDDMicrocontroller Unit
CS_N
VDVDD
SCK
SPI
Master
SPI
MOSI
MFIRST
MISO
MCU
IRQ
SPI Slave
ATA6870N (1)
The communication between Atmel® ATA6870N (1) and its host MCU, as well as ATA6870N (n) and ATA6870N(n-1) is
based on a 4 wire serial/parallel SPI interface (CS_N, SCK, MISO, MOSI) and an interrupt line (IRQ). The SPI interface
allows register read and write operations. The interrupt line indicates events that require host intervention.
Atmel ATA6870N(n)’s 4 wire-SPI bus inputs (CS_N, SCK, MOSI) are up-shifted through level shifters. They are internally
connected to the outputs CS_N_OUT, SCK_OUT, MOSI_OUT and connected to ATA6870N(n+1) (CS_N, SCK, MOSI).
Atmel ATA6870N(n)’s 4 wire-SPI bus output (MISO) and ATA6870N(n)’s interrupt (IRQ) are down-shifted through level
shifters and connected to ATA6870N(n-1) (MOSI_IN, IRQ_IN) or host MCU (n = 1).
ATA6870N [DATASHEET]
9317B–AUTO–06/14
25
7.6.3
Interrupt
In NORM mode (normal mode), the reasons for an interrupt request are:
● The availability of measured data (data ready)
When a voltage measurement is completed, the dataRdy flag is set in the status register.
The ATA6870N cannot decode any new incoming operation until the dataRdy flag is released.
●
The low frequency timer (LFT) elapses (wakeup)
The wakeup flag is set in the status register when the LFT elapses. The LFT is controlled via the SPI interface.
●
●
A transmission error is flagged during the last SPI transaction (the commError bit is set in the status register).
If an undervoltage condition occurs. The undervoltage function is controllable via SPI interface.
A mask bit in the irqMask register corresponds to each interrupt source. The MCU must read the ATA6870N status register
before the interrupt is cleared. With each SPI access a 16-bit IRQ state is sent via MISO to the MCU with the interrupt state
of all stacked ATA6870N (see Section 7.6.4.1 “SPI Transaction Fields” on page 26).
In PDmode (power down), if the digital control part and MCU are not supplied, neither SPI command nor interrupt are
transmitted over the interface.
7.6.4
SPI Interface
The full duplex SPI interface block allows communication with the host MCU using four wires (MISO, MOSI, SCK and
CS_N). SPI transactions are based on a byte-access MSB first protocol.
7.6.4.1 SPI Transaction Fields
Most of the time, the SPI frame is defined by 4 distinct fields:
IDENTIFICATION (2 bytes): 16-bit chip identification (MOSI), in parallel 16-bit IRQ state (MISO)
CONTROL (1 byte): 7-bit register address + 1-bit read/write information (MOSI)
DATA (k byte): k*8 bits data (MOSI or MISO depending on the access direction)
CHKSUM (1 byte): 8 bits if the Chksum_ena bit is set in the Ctrl register (register 0x01, bit 4)
Figure 7-14. SPI Transaction Fields Organization
byte1
byte2
byte3
byte4
byte5 to n-1
MOSI
ChipID1
ChipID0
CONTROL
DATA
....
MISO
IRQID1
IRQID0
byte n
CS_N
CHKSUM
(1)
CHKSUM
(1)
SPI write access
CS_N
MOSI
ChipID1
ChipID0
MISO
IRQID1
IRQID0
CONTROL
DATA
SPI read access
Note:
26
1.
Only send if chksum_ena bit set to 1 in the Ctrl register
ATA6870N [DATASHEET]
9317B–AUTO–06/14
....
7.6.4.2 Identification Field
Atmel ATA6870N Chip Identification
The two chip identification bytes are sent over MOSI to the Atmel® ATA6870N(n) in the chain. The ATA6870N(n) checks the
LSB. When LSB=1, the information is for this device. The SPI address will be decoded and the information processed.
Independent from this the identification bytes are shifted by one bit to the right and transferred to the next ATA6870N(n) in
the chain. The 2 identification bytes allows the identification of up to 16 ATA6870Ns.
Figure 7-15. Identification Field: Chip-ID Reception
IDENTIFICATION FIELD
CS_N
ATA6870N (1)
MOSI_IN
0x00
0x08
CONTROL
DATA
ATA6870N (2)
MOSI_IN
0x00
0x04
CONTROL
DATA
ATA6870N (3)
MOSI_IN
0x00
0x02
CONTROL
DATA
ATA6870N (4)
MOSI_IN
0x00
0x01
CONTROL
DATA
ATA6870N (n>4)
MOSI_IN
0x00
0x00
CONTROL
DATA
ATA6870N (1->3) identification
field has lsb = 0 => device is not
affected.
ATA6870N (4) identification
Shift it ”on the fly” once
field has lsb = 1 => decode
to the right
SPI access.
Shift it ”on the fly” once
to the right
ATA6870N (>4) identification
field has lsb = 0 => device is not
affected.
Shift it ”on the fly” once
to the right
ATA6870N [DATASHEET]
9317B–AUTO–06/14
27
7.6.4.3 ATA6870N IRQ Identification
Figure 7-16. IRQ Propagation Scheme
IRQ_IN
IRQ
≥1
irq_int
ATA6870N (n)
IRQ_IN
IRQ
≥1
irq_int
ATA6870N (n-1)
IRQ_IN
MCU
IRQ
≥1
irq_int
ATA6870N (1)
ATA6870N(n) IRQ output is connected to ATA6870N(n-1) IRQ_IN input.
ATA6870N(n-1) IRQ output is a logic OR between IRQ_IN and its internal irq_int signal.
ATA6870N(1) IRQ output is connected to MCU.
Figure 7-17. Identification Field: Interrupt State Emission
CS_N
ATA6870N (1)
MISO
0x20
0x00
ATA6870N (2)
MISO
0x40
0x00
ATA6870N (3)
MISO
0x80
0x00
ATA6870N (16)
MISO
0x00
0x00
ATA6870N (3) IRQ is set. =>
ATA6870N (3) sets the MSB of the
first byte to be shifted out. Others
bits are those coming from upper
ATA6870, shifted once to the right.
28
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Master SPI receives
identification word = 0x2000 = 213 = 2m.
This means ATA6870N number
(16-m = 16-13) = 3 has IRQ pending.
Others ATA6870Ns assert the MSB
of the first byte to 0. Others bits are
those coming from upper ATA6870N,
shifted once to the right.
Note:
n = IC number
m = bit number
m = n -1
1 < = n < = 16
0 < = m < = 15
With each SPI access, a 16- bit IRQ state is send via MISO synchronous to the identification field to the MCU with the
interrupt state of all stacked Atmel ATA6870N. The MCU, interrupted by an ATA6870N, has to send the identification field to
check the IRQ levels (in that case the checksum is not considered). It is also possible to continue the transaction with
CONTROL and DATA field. The MCU decodes the identification field shifted in MISO input. When bit m is set,
ATA6870N(16-m) is requesting interrupt.
Figure 7-18. Identification Field
CS_N
SCK
MOSI
M(16) M(15) M(14) M(13) M(12) M(11) M(10) M(9)
MISO
I(1)
I(2)
I(3)
I(4)
I(5)
I(6)
I(7)
M(8) M(7) M(6) M(5) M(4) M(3) M(2) M(1)
I(8)
I(9)
I(10) I(11) I(12) I(13) I(14) I(15) I(16)
7.6.4.4 CONTROL Field
The CONTROL field defines the register to access and the direction (read/write). The size of the data (8, 16, or 112 bits) is
defined by the address value in the CONTROL field.
Table 7-15. Control Field
CONTROL Field
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
A6
A5
A4
A3
A2
A1
A0
W/Rd
7.6.4.5 DATA Field
The DATA field can be composed of 1, 2, or 14 bytes depending on the accessed register. Irrespective of the data direction,
a byte is always transmitted with MSB first; a multi-byte word is transmitted with MSByte first.
Figure 7-19. CONTROL and DATA Fields - 8-bits Register Write
CS_N
SCK
MOSI
A(6)
A(5)
A(4)
MISO
A(3)
A(2)
A(1)
A(0)
1
D(7)
D(6)
Data not relevant
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
D(1)
D(0)
Data not relevant
Figure 7-20. CONTROL and DATA Fields - 8-bits Register Read
CS_N
SCK
MOSI
MISO
A(6)
A(5)
A(4)
A(3)
A(2)
A(1)
Data not relevant
A(0)
0
Data not relevant
D(7)
D(6)
D(5)
D(4)
D(3)
D(2)
ATA6870N [DATASHEET]
9317B–AUTO–06/14
29
Figure 7-21. CONTROL and DATA Fields - 16-bits Register Write
CS_N
SCK
MOSI
A(6) A(5) A(4) A(3) A(2) A(1) A(0)
MISO
1
Data not relevant
D(15) D(14) D(13) D(12) D(11) D(10) D(9) D(8)
Data not relevant
D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Data not relevant
Figure 7-22. CONTROL and DATA Fields - 16-bits Register Read
CS_N
SCK
MOSI
A(6) A(5) A(4) A(3) A(2) A(1) A(0)
MISO
Data not relevant
0
D(15) D(14) D(13) D(12) D(11) D(10) D(9) D(8)
D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
In order to retrieve results from all channels in one Atmel® ATA6870N without having to request for each channel, an SPI
112-bit read-only "burst access" (dataRd16Burst register; address = 0x7F) is implemented. When requested, the ATA6870N
outputs its 6 voltage channels V6 to V1 and one of the two temperature channels T2 and T1 in sequence on the SPI bus.
The diagrams below show the CONTROL and DATA fields of such an access.
30
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Figure 7-23. CONTROL and DATA Fields - 112-bits Register Read
CS_N
SCK
MOSI
1
1
1
MISO
1
1
1
1
0
0
Data not relevant
0
0
0
D(11) D(10) D(9) D(8)
D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Channel V6
CS_N
SCK
MOSI
MISO
0
0
0
0
D(11) D(10) D(9) D(8)
D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Channel V1
CS_N
SCK
MOSI
MISO
0
0
0
0
D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Channel temperature T1 or T2
One Atmel® ATA6870N frame corresponds to the set of results obtained in one Atmel ATA6870N. An Atmel ATA6870N
frame is formatted as follows:
Figure 7-24. SPI Access to dataRd16burst Register 0x7F
Voltage channels
Temp channel
16 bit
16 bit
16 bit
16 bit
16 bit
16 bit
16 bit
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADCT
Padding: 0x00
msb
12-bit ADC data
lsb
When reading data of chained ATA6870N, data is transferred as follow:
ATA6870N [DATASHEET]
9317B–AUTO–06/14
31
Figure 7-25. Example with two Atmel ATA6870N in a Chain
CS_N
SCK
MOSI
SPI Clock
SPI Clock
Rd Reg command chip1
Rd Reg command chip2
MISO
ATA6870 #1 Frame
ATA6870 #2 Frame
7.6.4.6 Communication Error
Correct communication can be verified using various functions of the Atmel ATA6870N.
For internal synchronization, it is mandatory to keep CLK running during any SPI access; CLK must be set on 4 clock cycles
(at least) before SPI access starts, and must be kept on 4 clock cycles (at least) after SPI access ends up. Keeping at least
4 CLK clock cycles between two consecutive SPI accesses is mandatory. If this is not the case, the Atmel ATA6870Ns will
detect an error in communication. The CommError bit will be set in the status register 0x06).
Figure 7-26. SPI Access and CLK Activity
CLK OFF
CLK ON
4 clk_ticks
CLK_OFF
4 clk_ticks
4 clk ticks
SPI ACCESS
SPI ACCESS
The Atmel ATA6870N verifies that complete bytes (8bits long) are always transmitted. A transition starts when CS_N goes to
low and it ends when CS_N goes to high. The number of clock cycles (signal SCK) is monitored during the transition. This
number of clock cycles has to be modulo 8. If the CS_N length is not modulo 8 clock cycles, the bit CommError is set in the
status register. This will cause an interrupt to the MCU if the CommError is not masked by the commErrorMsk bit in the
IrqMask register.
7.6.4.7 CHKSUM Field
The Atmel® ATA6870N provides the possibility of verifying the transmitted data using a checksum. Setting chksum_ena bit
to 1 in the Ctrl register (default = 0) activates the checksum feature.
The chksum field is an 8-bit checksum computed from the proceeding data (control and data fields, byte 3 to byte n-1). It is
based on the polynomial x8+x2+x1+1. The way it is computed is depicted below:
Figure 7-27. LFSR-based Checksum Computation
F0i
serial bitstream
MSB first
F1i
z-1
F2i
z-1
F3i
z-1
F4i
z-1
F5i
z-1
F6i
z-1
F6o
z-1
The checksum is calculated from the CONTROL field and DATA field by a polynomial division. The DATA field can consist of
1 byte up to 14 bytes (112-bit read-only “burst access”). The IDENTIFICATION field (2 bytes) is not used to generate the
checksum. The checksum is always sent by the microcontroller, independent of read write mode.
The checksum is in the LFSR (linear feedback shift register) when the complete bitstream (the whole fields of the
transaction) followed by 0x00 have been shifted in the LFSR.
The checksum verification on the complete data transmission was OK when the complete bitstream followed by the
checksum have been shifted in the LFSR, and the content of the LFSR is 0x00. If this is not the case, the receiving
ATA6870N will set the chkError bit in the status register. This will cause an interrupt to the MCU if the chkError is not masked
by the chkErrorMsk bit in the IrqMask register. See the example below. The checksum is serially computed from the 8-bit
value 0x57. So the bitstream 0x5700 is shifted in the LFSR. The resulting checksum is [f6o, f6i, f5i … f0i] at the last shift in
cycle:
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ATA6870N [DATASHEET]
9317B–AUTO–06/14
Table 7-16. checksum = [f6o, f6i, ... f0i] = 0xA2
5D
7D
0D
Input
f01
f1i
f2i
f3i
f4i
f5i
f6i
f6o
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1
0
1
0
0
1
1
1
1
0
1
0
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
1
1
0
1
0
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
1
0x2
0xA
During an SPI write access, the checksum is computed by the MCU and sent MSB first in the CHKSUM field. For an SPI
read access, the checksum is computed by the Atmel® ATA6870N and is checked by the MCU. During CHKSUM, MCU has
to send 0x00 on MOSI, and must check that its own LFSR equals 0x00 at the end of CHKSUM field.
7.6.4.8 Device Position
For the Atmel ATA6870N (1), this is the device on the lowest level, the SPI has to work as a standard logic CMOS interface
to the MCU. The SPI’s between stacked ATA6870N have to work as level-shifters based on current sources. These different
physical interfaces can be selected by the Pin MFIRST.
Table 7-17. Device Position
MFIRST
Configuration
0
ATA6870N (2) to ATA6870N (n)
1
ATA6870N (1)
Table 7-18. Electrical Characteristics
No. Parameters
Pin
Symbol
Min.
12.1 High level input voltage
MFIRST
MFIRST
0.7 ×
DVDD
12.2 Low level input voltage
MFIRST
MFIRST
12.3 Hysteresis
MFIRST
MFIRST
0.05 ×
DVDD
MFIRST
MFIRST
–1
12.4 Input current
Test Conditions
VMFIRST = 0V to VDVDD
Typ.
Max.
Unit
Type*
V
A
V
A
V
C
µA
A
0.3 ×
DVDD
+1
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6870N [DATASHEET]
9317B–AUTO–06/14
33
7.6.5
Digital Inputs and Outputs
7.6.5.1 Digital Output Characteristics
Digital Output Characteristics (MISO, IRQ)
If the Atmel® ATA6870N is configured as first IC (master) in a string (MFIRST = 1), these pins are configured as an open
drain output. If the ATA6870N is configured to be a stacked IC (MFIRST = 0), the output signals MISO and IRQ coming from
the upper IC need to be transferred to the MISO and IRQ outputs of the master in the string via the MISO_IN and IRQ_IN
inputs. In this case the MISO and IRQ outputs act as level shifters based on current sources.
Table 7-19. Electrical Characteristics
No. Parameters
Test Conditions
Pin
Symbol
13.1 Low level output voltage
IOUT = +5mA
MFIRST = 1
MISO, IRQ
VMISO, VIRQ
13.2 Low level output current
±0.3V, MFIRST = 0
MISO, IRQ
IMISO, IIRQ
13.3 High level output current
±0.3V, MFIRST = 0
MISO, IRQ
IMISO, IIRQ
Min.
Typ.
Max.
Unit
Type*
0.2 ×
VDD
V
A
–13
–8
µA
A
–65
–40
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Digital Output Characteristics (MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT)
These outputs act as level shifters based on current sources. They transfer the input signals MOSI_OUT, SCK_OUT,
CS_N_OUT, CLK_OUT to the next IC above. If the ATA6870N is the IC on the top level of a string, these outputs must be
connected to VDDHV.
Table 7-20. Electrical Characteristics
No. Parameters
Test Conditions
Pin
Symbol
Min.
14.1 Low level output current
VDDHV + 1V to
VDDHV + 2V
(1)
V(1)
14.2 High level output current
VDDHV + 1V to
VDDHV + 2V
(1)
V(1)
Typ.
Max.
Unit
Type*
25
55
µA
A
–1
+1
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1.
MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT
7.6.5.2 Digital Input Characteristics
Digital Input Characteristics (MISO_IN, IRQ_IN)
Table 7-21. Electrical Characteristics
No. Parameters
Test Conditions
Pin
Symbol
Min.
15.1 Low level input current
(VDDHV + 1.4V)
±0.3V
MISO_IN,
IRQ_IN
IMISO_IN
IIRQ_IN
13
15.2 High level input current
(VDDHV + 1.4V)
±0.3V
MISO_IN,
IRQ_IN
IMISO_IN
IIRQ_IN
Typ.
Max.
40
Unit
Type*
µA
A
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
34
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Digital Input Characteristics (CS_N, SCK, MOSI, CLK)
Table 7-22. Electrical Characteristics
No. Parameters
Test Conditions
Pin
Symbol
Min.
0.7 ×
DVDD
Typ.
Max.
Unit
Type*
DVDD
V
A
0.3 ×
DVDD
V
A
16.1 High level input voltage
MFIRST = 1
(1)
V(1)
16.2 Low level input voltage
MFIRST = 1
(1)
V(1)
16.3 High level input current
MFIRST = 1
I(1)
50
100
µA
A
16.4 Low level input current
MFIRST = 1
(1)
–130
–70
µA
A
16.5 Low level input current
MFIRST = 0,
V(1) = 1V to 2V
(1)
I(1)
–55
–35
µA
A
16.6 High level input current
MFIRST = 0
V(1) = 1V to 2V
(1)
I(1)
–1
+1
µA
A
I
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1.
CS_N, SCK, MOSI, CLK
7.6.5.3 Test-mode Pins
The test-mode pins DTST, ATST, PWTST (outputs) have to be kept open in the application. The test-mode pins
SCANMODE and CS_FUSE (inputs) have to be connected to VSSA. These inputs have an internal pull-down resistor. The
test-mode pin VDDFUSE is a supply pin. It must also be connected to VSSA.
Table 7-23. Input Characteristics Pins SCANMODE, CS_FUSE, VDDFUSE
No. Parameters
18.1 Pull-down resistor
Test Conditions
Pin
Symbol
SCANMODE, RSCANMODE,
CS_FUSE
RCS_FUSE
Min.
50
Typ.
Max.
Unit
Type*
200
kΩ
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6870N [DATASHEET]
9317B–AUTO–06/14
35
7.7
Operations
7.7.1
Voltage and Temperature Measurement
At startup, the Atmel® ATA6870N is supplied and is waiting for any operation request.
The available operations are:
● 6 channels voltage acquisition with a temperature acquisition
●
with voltage = V(MBATi+1, MBATi) (standard operation)
and with voltage = V(TEMP1 or TEMP2, TEMPVSS) (standard operation)
●
with voltage = V(MBATi, MBATi) (offset calibration: CalOffset operation)
and with voltage = V(TEMPVSS, TEMPVSS) (offset calibration: CalOffset operation)
Operation completion is flagged to the host MCU via the IRQ output in conjunction with dataRdy bit set in the status register.
In order to retrieve the full results in a single access, the user has to access the dataRd16burst register (112bits). Getting the
results of a single channel (voltage or temperature) is also possible. For this, first select the channel to read through the
ChannelReadSel register, then retrieve the channel value through the DataRd16 register. It is not possible to order a new
operation until the previous operation has been acknowledged. The host MCU acknowledges the interrupt by reading the
status register. This resets the dataRdy bit as well as the IRQ output, and enables the ATA6870N to start the next operation.
Writing NoOp in the Operation register during an operation running aborts the current operation. In this case, the dataRdy bit
is not set and interrupt is not requested to the host MCU. The Opstatus register flags whether operation is running, aborted,
ended, or no operation is running.
7.7.2
Discharge Function
Each channel is independently dischargeable. Discharge is activated or deactivated by the register ChannelDischSel.
7.7.3
Low Frequency Timer Function
A low frequency timer (LFT), synchronous to internal 50 kHz oscillator provides the host MCU with a low power timer, which
useful to either synchronize operations in the host MCU or monitor the Atmel ATA6870N’s activity.
The LFT elapsing asserts an interrupt to the host MCU if the corresponding mask bit in the IrqMask register is not set.
Default is LFT not enabled. To enable the LFT, set the LFTimer_ena bit to 1 in the Ctrl register.
LFT counting time is fully programmable in the register LFTimer.
Changing the LFTimer register restarts the LFT if the new counting time is smaller than the current value of the LFT.
Otherwise, LFT runs until it reaches the new end value.
Asserting LFTRst bit in the Rstr register resets and restarts the LFT if the LFT is enabled. Otherwise, LFT is reset but not
started.
Each ATA6870N will assert its own interrupt when the timer elapses. Depending on how the timer is used, the host MCU
may mask LFTdone interrupts in the whole ATA6870Ns chain, except the first one. As internal RC oscillators are not
synchronized, this prevents the MCU from being interrupted each time one of the LFT elapses.
7.7.4
Undervoltage Detection
A programmable undervoltage detection function is embedded in the ATA6870N. After being digitalized, each of the 6
voltages is compared to a programmable threshold defined in the UdvThresh register. If one of the six channels is out of the
range defined by the threshold, an interrupt is requested to the host MCU if the corresponding udv mask bit is not set in the
IrqMask register.
The default threshold is 1.5V.
As soon as MCU has acknowledged, undervoltage information is no more available to MCU, because status register is
cleared when MCU reads it out. As a consequence, the next undervoltage interrupt cannot occur until the Atmel ATA6870N
leaves its current undervoltage state.
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ATA6870N [DATASHEET]
9317B–AUTO–06/14
7.8
Registers
Registers are read and written through the SPI interface.
Table 7-24. Register Mapping
Register
Address
Control Field Control Field
Read Mode
Write Mode
Register Name
Access
Type
Function
0x00
0x00
-
RevID
R
8 bits
Revision ID/value Mfirst, pow_on
0x01
0x02
0x03
Ctrl
RW
8 bits
Control register
0x02
0x04
0x05
Operation
RW
8 bits
Operation request
0x03
0x06
-
OpStatus
R
8 bits
Operation status
0x04
-
0x09
Rstr
W
8 bits
Software reset
0x05
0x0A
0x0B
IrqMask
RW
8 bits
Mask interrupt sources
0x06
0x0C
-
Status
R
8 bits
Status interrupt sources
0x08
0x10
-
ChannelUdvStatus
R
8 bits
Channels undervoltage status
0x09
0x12
0x13
ChannelDischSel
RW
8 bits
Select channel to discharge
0x0A
0x14
0x15
ChannelReadSel
RW
8 bits
Select channel to read
0x0B
0x16
0x17
LFTimer
RW
8 bits
Low frequency timer control
0x0C
0x18
-
CalibStatus
R
8 bits
Reserved
0x0D
0x1A
0x1B
FuseCtrl
RW
8 bits
Reserved
0x10
0x20
0x21
UdvThresh
RW
16 bits
Undervoltage detection threshold
0x11
0x22
-
DataRd16
R
16 bits
Single access to selected channel
value
0x12
0x24
0x25
ATA6870NTest
RW
16 bits
Reserved
0x7F
0xFE
-
DataRd16Burst
R
112 bits
Burst Access to the whole channels
(6 voltage and 1 temperature)
7.8.1
Registers Content
7.8.1.1 RevID Register
Table 7-25. RevId Register Overview
Register
RevID
Address
0x00
Reset Value
7 (msb)
6
5
4
3
x
x
x
pow_en
Mfirst
2
0x02
1
0 (lsb)
RevID
Table 7-26. RevId Register Content
Bit Field
Description
RevID
ATA6870N revision number, revision B: 0x02
Mfirst
Status input pin MFIRST
pow_en
Status input pin POW_EN
ATA6870N [DATASHEET]
9317B–AUTO–06/14
37
7.8.1.2 Ctrl Register
Table 7-27. Ctrl Register Overview
Register
Ctrl
Address
0x01
Reset Value
0x00
7 (msb)
6
5
4
3
2
1
0 (lsb)
x
x
x
Chksum_ena
LFTimer_ena
TFMODE_ena
x
x
Table 7-28. Ctrl Register Content
Bit Field
Description
TFMode_ena
0: Prevent ATA6870N to switch to test mode
1: Not allowed for customer use
LFTimer_ena
0: Disable internal low frequency timer
1: Enable internal low frequency timer
Chksum_ena
0: Disable SPI transaction checksum computation/check
1: Enable SPI transaction checksum computation/check
7.8.1.3 Operation Register
Table 7-29. Operation Register Overview
Register
Operation
Address
0x02
7 (msb)
6
x
x
5
4
OpMode
Reset Value
3
TempMode
2
0x02
1
VoltMode
0 (lsb)
OpRqst
Table 7-30. Operation Register Content
Bit Field
Description
OpRqst
0: NoOp: No Operation, or abort current operation
1: AcqRqst: Start the analog to digital conversion
An interrupt is generated when data is available in DataRd16/DataRd16Burst.
00: Caloffset: select V(MBAT(i), MBAT(i)) as input of voltage channels. (offset calibration)
VoltMode
TempMode
OpMode
01: AcqV: select V(MBAT(i+1), MBAT(i)) as input of voltage channels (default)
10: Not allowed
0: Select TEMP1 input pin as input of temperature channel
1: Select TEMP2 input pin as input of temperature channel
00: 6 voltage channels and temperature acquisition
01: 6 voltage channels acquisition only
1X: Temperature acquisition only
When a conversion operation is finished and the interrupt has been acknowledged by the MCU the operation register is
automatically reset to “NoOp”. Writing “NoOp” in the register when conversion operation is running, aborts the current
operation. Other changes are not accepted during any operation.
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ATA6870N [DATASHEET]
9317B–AUTO–06/14
Figure 7-28. Typical Data Acquisition Flow
ASIC3 (MFIRST = 0)
ASIC2 (MFIRST = 0)
ASIC1 (MFIRST = 1)
Init State
Opstatus = NoOP
Status Cleared
Init State
Opstatus = NoOP
Status Cleared
Init State
Opstatus = NoOP
Status Cleared
Runs Conversion
Opstatus = Running
Runs Conversion
Opstatus = Running
Runs Conversion
Opstatus = Running
Conversion Finished
Opstatus = Result Available
Status = Data Ready
IRQ DATA RDY
Conversion Finished
Opstatus = Result Available
Status = Data Ready
IRQ DATA RDY
Conversion Finished
Opstatus = Result Available
Status = Data Ready
IRQ DATA RDY
MCU
...
Set Operation = ACQ*/CAL*
Background Tasks/Idle
ASIC3
Read/Check Opstatus
Read/Check Status
Opstatus = NoOP
Status Cleared
ASIC2
Read/Check Opstatus
Read/Check Status
Opstatus = NoOP
Status Cleared
Opstatus = NoOP
IRQ Acknowledged
Status Cleared
ASIC1
Read/Check Opstatus
Read/Check Status
ASIC3 Burst Read Data
ASIC2 Burst Read Data
ASIC1 Burst Read Data
...
7.8.1.4 OpStatus Register
Table 7-31. OpStatus Register Overview
Register
OpStatus
Address
0x03
Reset Value
7 (msb)
6
5
4
3
2
x
x
x
x
x
x
0x00
1
0 (lsb)
OpStatus
Table 7-32. OpStatus Register Content
Bit Field
Description
OpStatus
00: No Operation
01: Operation is ongoing
10: Operation is finished, result is available
11: Operation is cancelled, result is not available
ATA6870N [DATASHEET]
9317B–AUTO–06/14
39
Figure 7-29. Operation Status Register Management
User reads Operation Status Register,
Reset
NO OP
Users programs conversions operation
Operation Running
Users programs NoOp
End of conversion
Operation Aborted,
Result not Available
Operation Finished,
Result Available
User programs conversion operation or
reads operation status register
Status reg has been read and:
User programs conversion operation or
reads operation status register
The OPStatus register is reset when read after a completed or aborted operation. Reading the register before starting an
operation is not mandatory. Reading data conversion results or reading the OpStatus register during an operation does not
affect the OpStatus register.
7.8.1.5 Rstr Register
Table 7-33. Rstr Register Overview
Register
Rstr
Address
0x04
Reset Value
0x00
7 (msb)
6
5
4
3
2
1
0 (lsb)
x
x
x
x
x
x
LFTRst
0
Table 7-34. Rstr Register Content
Bit Field
Description
0: No reset
1: Low Frequency Timer software reset
LFTRst
LFTRst resets and restarts the low frequency timer if not disabled (LFTimer_ena = 0).
7.8.1.6 IrqMask Register
Table 7-35. IrqMask Register Overview
Register
IrqMask
Address
40
0x05
Reset Value
0x00
7 (msb)
6
5
4
3
2
1
0 (lsb)
x
x
x
chkErrorMask
udvmask
commErrorMask
LFTdoneMask
dataDryMask
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Table 7-36. IrqMask Register Content
Bit Field
Description
dataRdyMask
Mask data ready interrupt when set to 1
WakeupMask
Mask LFTdone interrupt when set to 1
commErrorMask
udvMask
Mask commError interrupt when set to 1
Mask undervoltage detection interrupt when set to 1
chkErrorMask
Mask checksum error interrupt when set to 1
7.8.1.7 Status Register
Table 7-37. Status Register Overview
Register
Status
Address
0x06
Reset Value
0x20
7 (msb)
6
5
4
3
2
1
0 (lsb)
x
TFMdeOn
por
chkError
udv
commError
LFTdone
dataRdy
Table 7-38. Status Register Content
Bit Field
Description
dataRdy
Conversion finished
LFTdone
Low frequency timer elapsed
commError
udv
Bad SPI command detected (wrong length)
Undervoltage detected
chkError
Error on checksum check
Por
Power on reset detected
TFMdeOn
Test mode on
Any bit among {dataRdy, LFTdone, commError, udv, chkError} set in the status register requests an interrupt to the external
MCU if the corresponding mask bit in the IrqMask register is 0. Reading the status register acknowledges the interrupt and
resets its content. Por and TFMdeOn cause no interrupt.
7.8.1.8 ChannelUdvStatus Register
Table 7-39. ChannelUdvStatus Register Overview
Register
ChannelUdvStatus
Address
0x08
Reset Value
0x00
7 (msb)
6
5
4
3
2
1
0 (lsb)
x
x
chUdv6_stat
chUdv5_stat
chUdv4_stat
chUdv3_stat
chUdv2_stat
chUdv1_stat
ATA6870N [DATASHEET]
9317B–AUTO–06/14
41
Table 7-40. ChannelUdvStatus Register Content
Bit Field
Description
chUdv1_stat
1: Undervoltage detected on channel 1
0: No undervoltage detected on channel 1
chUdv2_stat
1: Undervoltage detected on channel 2
0: No undervoltage detected on channel 2
chUdv3_stat
1: Undervoltage detected on channel 3
0: No undervoltage detected on channel 3
chUdv4_stat
1: Undervoltage detected on channel 4
0: No undervoltage detected on channel 4
chUdv5_stat
1: Undervoltage detected on channel 5
0: No undervoltage detected on channel 5
chUdv6_stat
1: Undervoltage detected on channel 6
0: No undervoltage detected on channel 6
Undervoltage is detected when voltage decreases under the threshold value defined in udvThresh register.
When undervoltage is detected on a channel, the Atmel® ATA6870N requests an interrupt if the UDVmask bit in the
IRQMask register is 0.
7.8.1.9 ChannelDischSel Register
Table 7-41. ChannelDischSel Register Overview
Register
ChannelDischSel
Address
0x09
Reset Value
7 (msb)
6
5
4
3
2
1
0 (lsb)
x
x
chV6_disch
chV5_disch
chV4_disch
chV3_disch
chV2_disch
chV1_disch
Table 7-42. ChannelDischSel Register Content
Bit Field
Description
chV1_disch
1: Enable voltage channel 1 discharge
0: Disable voltage channel 1 discharge
chV2_disch
1: Enable voltage channel 2 discharge
0: Disable voltage channel 2 discharge
chV3_disch
1: Enable voltage channel 3 discharge
0: Disable voltage channel 3 discharge
chV4_disch
1: Enable voltage channel 4 discharge
0: Disable voltage channel 4 discharge
chV5_disch
1: Enable voltage channel 5 discharge
0: Disable voltage channel 5 discharge
chV6_disch
1: Enable voltage channel 6 discharge
0: Disable voltage channel 6 discharge
The channels are dischargeable simultaneously.
42
0x00
ATA6870N [DATASHEET]
9317B–AUTO–06/14
7.8.1.10 ChannelReadSel Register
Table 7-43. ChannelReadSel Register Overview
Register
ChannelReadSel
Address
7 (msb)
0x0A
6
5
4
Reset Value
3
2
0x00
1
0 (lsb)
ChannelReadSel
Table 7-44. ChannelReadSel Register Content
Bit Field
Description
111: Value of the LFT is returned in DataRd16 register
110: Temperature channel available in DataRd16 register
101: Voltage channel6, value available in DataRd16 register
100: Voltage channel5, value available in DataRd16 register
011: Voltage channel4, value available in DataRd16 register
010: Voltage channel3, value available in DataRd16 register
001: Voltage channel2, value available in DataRd16 register
000: Voltage channel1, value available in DataRd16 register
ChannelReadSel
This register can be used to quickly read a single channel without using a full burst access. The value of the selected
channel will be available in the DataRd16 register. The value will always be updated by writing a channel address to the
ChannelReadSel register. Data in this register is not valid during ongoing data conversion.
7.8.1.11 LFTimer Register
Table 7-45. LFTimer Register Overview
Register
LFTimer
Address
7 (msb)
0x0B
6
5
4
LFTPrescaler
Reset Value
3
2
0xF9
1
0 (lsb)
LFTDelay
Table 7-46. LFTimer Register Content
Bit Field
Description
LFTDelay
Contains the present low frequency timer delay value
LFTPrescaler
0: PrescalerValue = 1
1: PrescalerValue = 6
The default timer value is 59.965s (0xF9) for fOSC = 50kHz.
ATA6870N [DATASHEET]
9317B–AUTO–06/14
43
Figure 7-30. Block Diagram LFTimer
LFTprescaler
50kHz
/4096
LFTdelay
Comp
7-bit
counter
/6
Delay Time elapsed
clear
Formula for Delay Time calculation:
LFTprescaler D
1
Delay Time = ------------------------ × 4096 × ( 6
) × ( LFTdelay D + 1 )
T OSC [Hz]
The LFT can be programmed to the following values (fOSC = 50kHz):
LFTprescaler = 0:
LFTprescaler = 1:
0.082s <= duration <= 10.486s, Increment = 82ms
492 ms <= duration <= 62.915s, Increment = 492ms
When LFT elapsed, an interrupt is requested unless LFTdoneMask bit is set in the IRQMask register.
For details on the tolerances for the oscillator, see Section 7.5.6 “RC Oscillator” on page 24.
Keeping at list 100 µs between two successive LFTimer register write accesses prevents internal metastability issues, which
might result in bad LFTdelay decoding.
7.8.1.12 Test-Mode Register
Table 7-47. Test-Mode Register 1 Overview
Register
TESTmode1
Address
0x0C
Reset Value
0x03
7 (msb)
6
5
4
3
2
1
0 (lsb)
0
0
0
0
0
0
1
1
Table 7-48. Test-Mode Register 2 Overview
Register
TESTmode2
Address
0x0D
Reset Value
0x07
7 (msb)
6
5
4
3
2
1
0 (lsb)
0
0
0
0
0
1
1
1
Table 7-49. Test-Mode Register 3 Overview
Register
UdvThresh
Address
0x12
Reset value
0x0E00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
Test-mode registers 1, 2, and 3 are reserved for the factory calibration process. They are not allowed for customer use.
44
ATA6870N [DATASHEET]
9317B–AUTO–06/14
7.8.1.13 UdvThresh Register
Table 7-50. UdvThresh Register Overview
Register
UdvThresh
Address
0x10
15
14
13
12
x
x
x
x
11
10
9
Reset value
8
7
6
5
4
0x0570
3
2
3
2
1
0
udvThresh
Table 7-51. UdvThresh Register Content
Bit Field
Format
Description
udvThresh
12 bits
Threshold for undervoltage detection
Default value is 1.5V (0x0570, 1392D)
1.5V = VREF × (1392 – 410) / (1502 – 410)
See also Section 7.5.1.2 “12 Bits Incremental ADC” on page 18.
7.8.1.14 DataRd16 Register
Table 7-52. DataRd16 Register Overview
Register
DataRd16
Address
0x11
15
14
13
12
x
x
x
x
11
10
9
Reset value
8
7
6
5
4
0x0000
1
0
DataRd16
Table 7-53. DataRd16 Register Content
Bit Field
Format
Description
DataRd16
12 bits
Return selected channel value (see Section 7.8.1.10 “ChannelReadSel
Register” on page 43)
ATA6870N [DATASHEET]
9317B–AUTO–06/14
45
7.8.1.15 DataRd16burst Register
Table 7-54. DataRd16burst Register Overview
Register
DataRd16Burst
Address
0x7F
111
110
109
108
X
X
X
x
95
94
93
92
x
x
x
x
79
78
77
76
x
x
x
x
63
62
61
60
x
x
x
x
47
46
45
44
x
x
x
x
31
30
29
28
x
x
x
x
15
14
13
12
x
x
x
x
107
106
105
Reset value
104
103
102
101
0x0000
100
99
98
97
96
84
83
82
81
80
68
67
66
65
64
52
51
50
49
48
36
35
34
33
32
20
19
18
17
16
4
3
2
1
0
Channel6 data
91
90
89
88
87
75
74
73
72
71
86
85
Channel5 data
70
69
Channel4 data
59
58
57
56
55
43
42
41
40
39
54
53
Channel3 data
38
37
Channel2 data
27
26
25
24
23
11
10
9
8
7
22
21
Channel1 data
6
5
Temperature data
Table 7-55. DataRd16burst Register Content
46
Bit Field
Format
Description
DataRd16burst
112bits
Returns the values of all channels from one ATA6870N, including temperature
measurement
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Figure 7-31. Application
10Ω
1kΩ
1.5kΩ
PD_N
VDDHVP
MISO_IN
MOSI_OUT
SCK_OUT
CS_N_OUT
IRQ_IN
100nF
CLK_OUT
MBAT7
VDDHV
MBAT6
1kΩ
DISCH6
100nF
VDDHVM
+
33μF
DISCH5
PD_N_OUT
MBAT5
POW_ENA
220nF
1kΩ
100nF
PWTST
DISCH4
ATST
MBAT4
BIASRES
1kΩ
121kΩ
100nF
ATA6870N
DISCH3
TEMPVREF
MBAT3
TEMP2
1kΩ
100nF
DISCH2
+
TEMP1
MBAT2
TEMPVSS
NTC
1kΩ
10μF
NTC
100nF
DVDD
GND
DVSS
VDDFUSE
AVSS
CS_FUSE
DTST
MISO
MOSI
SCK
CLK
IRQ
CS_N
MBAT1
MFIRST
DISCH1
1kΩ
SCANMODE
100nF
AVDD
10nF
10Ω
10Ω
1kΩ
PD_N
VDDHVP
MISO_IN
MOSI_OUT
SCK_OUT
CLK_OUT
100nF
CS_N_OUT
IRQ_IN
VDDHV
MBAT7
MBAT6
1kΩ
DISCH6
100nF
VDDHVM
+
33μF
DISCH5
PD_N_OUT
MBAT5
POW_ENA
220nF
+
1kΩ
10μF
100nF
100nF
PWTST
DISCH4
ATST
MBAT4
BIASRES
1kΩ
121kΩ
100nF
ATA6870N
DISCH3
TEMPVREF
MBAT3
TEMP2
1kΩ
100nF
DISCH2
TEMP1
MBAT2
TEMPVSS
NTC
1kΩ
NTC
DVDD
GND
DVSS
VDDFUSE
AVSS
CS_FUSE
DTST
MISO
MOSI
SCK
IRQ
CLK
1kΩ
CS_N
MBAT1
MFIRST
DISCH1
SCANMODE
100nF
AVDD
10nF
10Ω
MISO
MOSI
SCK
CSN
CLK
IRQ
VDD
OUT
Microcontroller
GND
Figure 7-31 shows an application with 2 stacked Atmel® ATA6870Ns.
ATA6870N [DATASHEET]
9317B–AUTO–06/14
47
8.
Ordering Information
Extended Type Number
Package
MOQ
ATA6870N-PLPW
QFN48, 7 × 7
1,000 pieces
ATA6870N-PLQW
QFN48, 7 × 7
4,000 pieces
9.
Package Information
Top View
D
48
1
E
PIN 1 ID
technical drawings
according to DIN
specifications
12
Dimensions in mm
A
Side View
A3
A1
Standard Singulation process
Bottom View
D2
24
25
13
12
COMMON DIMENSIONS
E2
(Unit of Measure = mm)
1
A
36
48
37
e
MIN
NOM
MAX
A
0.8
0.9
1
A1
A3
0.0
0.15
0.02
0.2
0.05
0.25
D
6.9
7
7.1
D2
5.45
5.6
5.75
E
6.9
7
7.1
E2
5.45
5.6
5.75
L
0.3
0.4
0.5
b
e
0.16
0.23
0.5 BSC
0.3
NOTE
L
A (10:1)
Symbol
b
09/07/11
TITLE
Package Drawing Contact:
[email protected]
48
ATA6870N [DATASHEET]
9317B–AUTO–06/14
Package: VQFN_7x7_48L
Exposed pad 5.6x5.6
GPC
DRAWING NO.
REV.
6.543-5130.01-4
3
9.1
Markings
As a minimum, the devices will be marked with the following:
● Date code (year and week number)
●
10.
Atmel® part number (ATA6870N)
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
9317B-AUTO-06/14
• Put datasheet in the latest template
ATA6870N [DATASHEET]
9317B–AUTO–06/14
49
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