HY57V641620HG-I Series 4 Banks x 1M x 16Bit Synchronous DRAM DESCRIPTION The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications r which require low power consumption and extended temperature range. HY57V641620HG is organized as 4banks of 1,048,576x16. HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • Single 3.3±0.3V power supply Note) • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms • JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch • Programmable Burst Length and Burst Type • All inputs and outputs referenced to positive edge of system clock • Data mask function by UDQM or LDQM • Internal four banks operation - 1, 2, 4, 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. Clock Frequency HY57V641620HGT-5I/55I/6I/7I 200/183/166/143MHz HY57V641620HGT-KI 133MHz HY57V641620HGT-HI 133MHz HY57V641620HGT-8I 125MHz HY57V641620HGT-PI 100MHz HY57V641620HGT-SI 100MHz HY57V641620HGLT-5I/55I/6I/7I 200/183/166/143MHz HY57V641620HGLT-KI 133MHz HY57V641620HGLT-HI 133MHz HY57V641620HGLT-8I 125MHz HY57V641620HGLT-PI 100MHz HY57V641620HGLT-SI 100MHz Power Organization Interface Package 4Banks x 1Mbits x16 LVTTL 400mil 54pin TSOP II Normal Low power Note : VDD(Min) of HY57V641620HG(L)T-5I/55I/6I is 3.135V This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0/Jan. 02 1 HY57V641620HG PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 54pin TSOP II 400mil x 875mil 0.8mm pin pitch VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION PIN PIN NAME DESCRIPTION CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select Enables or disables all inputs except CLK, CKE and DQM BA0,BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 1.0/Jan. 02 2 HY57V641620HG FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 16 I/O Synchronous DRAM Self refresh logic & timer Internal Row counter 1Mx16 Bank 3 CLK Row active Row Pre Decoders 1Mx16 Bank 2 CS Column Pre Decoders UDQM Y decoders LDQM Bank Select A0 A1 Rev. 1.0/Jan. 02 DQ1 DQ14 DQ15 Column Add Counter Address Registers Address buffers A11 BA0 BA1 DQ0 I/O Buffer & Logic Column Active Memory Cell Array Sense AMP & I/O Gate WE X decoders refresh 1Mx16 Bank 0 X decoders CAS State Machine RAS 1Mx16 Bank 1 X decoders X decoders CKE Burst Counter Mode Registers CAS Latency Data Out Control Pipe Line Control 3 HY57V641620HG ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA -40 ~ 85 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA= -40 to 85°C) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1,2 Input High Voltage VIH 2.0 3.0 VDDQ + 2.0 V 1,3 Input Low Voltage VIL VSSQ - 2.0 0 0.8 V 1,4 Note : 1.All voltages are referenced to VSS = 0V 2.VDD(min) of HY57V641620HG(L)T-5I/55I/6I is 3.135V 3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration 4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration AC OPERATING CONDITION (TA= -40 to 85°C, VDD=3.3 ± 0.3VNote2, VSS=0V) Parameter Symbol Value Unit AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V Vtrip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voutref 1.4 V CL 50 pF Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Note 1 Note : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit 2.VDD(min) of HY57V641620HG(L)T-5I/55I/6I is 3.135V Rev. 1.0/Jan. 02 4 HY57V641620HG CAPACITANCE (TA=25°C, f=1MHz) Parameter Pin Input capacitance Data input / output capacitance Symbol Min Max Unit CLK CI1 2 4 pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM CI2 2.5 5 pF DQ0 ~ DQ15 CI/O 2 6.5 pF OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (TA= -40 to 85°C, VDD=3.3±0.3VNote3) Parameter Symbol Min. Max Unit Note Input Leakage Current ILI -1 1 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -4mA Output Low Voltage VOL - 0.4 V IOL = +4mA Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6 Rev. 1.0/Jan. 02 5 HY57V641620HG DC CHARACTERISTICS II (TA= -40 to 85°C, VDD=3.3±0.3VNote5, VSS=0V) Speed Parameter Symbol Test Condition Unit Note -5I -55I -6I -7I -KI -HI -8I -PI -SI 100 95 90 85 85 85 80 80 80 Operating Current IDD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA Precharge Standby Current in Power Down Mode IDD2P CKE ≤ VIL(max), tCK = min 2 mA IDD2PS CKE ≤ VIL(max), tCK = ∞ 2 mA IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD0.2V or ≤ 0.2V 15 mA IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 12 mA IDD3P CKE ≤ VIL(max), tCK = min 6 mA IDD3PS CKE ≤ VIL(max), tCK = ∞ 5 mA IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins ≥ VDD0.2V or ≤ 0.2V 30 mA IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 20 mA Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode CL=3 170 160 150 150 CL=2 NA NA NA NA 150 150 120 120 120 120 mA mA 1 1 mA 160 mA 2 1 mA 3 400 uA 4 Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V641620HGT-5I/55I/6I/7I/KI/HI/PI/SI 4.HY57V641620HGLT-5I/55I/6I/7I/KI/HI/PI/SI Rev. 1.0/Jan. 02 6 HY57V641620HG AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -5I Parameter -6I -7I -KI -HI -8I -PI -SI Unit Min System clock cycle time -55I Symbol CAS Latency = tCK3 3 Max 5 Min 5.5 1000 CAS Latency = tCK2 2 Max 10 Min Max Max 7 6 100 0 1000 10 Min 10 Min Max 7.5 1000 10 Min Max 7.5 1000 7.5 Min Max 8 1000 10 Min Max 10 1000 10 Min 10 1000 10 Note Max ns 1000 12 ns Clock high pulse width tCHW 1.75 - 2 - 2 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 Clock low pulse width tCLW 1.75 - 2 - 2 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 CAS Latency = tAC3 3 - 4.5 - 5 - 5.4 - 5.4 - 5.4 5.4 - 6 6 - 6 ns CAS Latency = tAC2 2 - 6 - 6 - 6 - 6 - 5.4 6 - 6 - 6 - 8 ns Access time from clock 2 Data-out hold time tOH 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - 2.0 - ns Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Data-Input hold time tDH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Address setup time tAS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Address hold time tAH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CKE setup time tCKS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 CKE hold time tCKH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Command setup time tCS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Command hold time tCH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 1 - 1 - 1 - 1.5 - 1.5 - 1.5 - 1 - 1 - 2 - ns 3 6 CLK to data output in low Z-time tOLZ CLK to data output in high Z-time CAS Latency = tOHZ3 3 5.4 5.4 5.4 CAS Latency = tOHZ2 2 5.4 5.4 5.4 ns 6 3 6 6 ns Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate Rev. 1.0/Jan. 02 7 HY57V641620HG AC CHARACTERISTICS II Parameter Symbo l -5I -55I -6I -7I -KI -HI -8I -PI -SI Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Operation tRC 55 - 55 - 60 - 62 - 65 - 65 - 68 - 70 - 70 - ns Auto Refresh tRRC 60 - 60 - 60 - 62 - 65 - 65 - 68 - 70 - 70 - ns RAS to CAS Delay tRCD 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns RAS Active Time tRAS 42 100 K 42 120K 45 120K 45 120K 48 100 K 50 120K 50 120K ns RAS Precharge Time tRP 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns RAS to RAS Bank Active Delay tRRD 10 - 11 - 12 - 14 - 15 - 15 - 16 - 20 - 20 - ns CAS to CAS Delay tCCD 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK Data-In to Precharge Command tDPL 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK Data-In to Active Command tDAL 5 - 5 - 5 - 4 - 4 - 4 - 5 - 3 - 3 - CLK DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - 1 - 1 - 1 - 2 - 1 - 1 - CLK CAS Latency =3 tPROZ 3 3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - CLK CAS Latency =2 tPROZ 2 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK Power Down Exit Time tPDE 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms RAS Cycle Time Precharge to Data Output Hi-Z 38.5 100K 38.5 100K Note 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 1.0/Jan. 02 8 HY57V641620HG DEVICE OPERATING OPTION TABLE HY57V641620HG(L)T-5I CAS Latency tRCD tRAS tRC tRP tAC tOH 200MHz(5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 4.5ns 2.0ns 183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.0ns 2.0ns 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.0ns HY57V641620HG(L)T-55I CAS Latency tRCD tRAS tRC tRP tAC tOH 183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.0ns 2.0ns 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.0ns 143MHz(7ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.0ns HY57V641620HG(L)T-6I CAS Latency tRCD tRAS tRC tRP tAC tOH 166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.0ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.0ns 133MHz(7.5ns) 2CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.0ns CAS Latency tRCD tRAS tRC tRP tAC tOH HY57V641620HG(L)T-7I 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.0ns 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.0ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.0ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.0ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns HY57V641620HG(L)T-KI HY57V641620HG(L)T-HI CAS Latency tRCD tRAS tRC tRP tAC tOH 133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.0ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.0ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns Rev. 1.0/Jan. 02 9 HY57V641620HG-I Series 4 Banks x 1M x 16Bit Synchronous DRAM HY57V641620HG(L)T-8I CAS Latency tRCD tRAS tRC tRP tAC tOH 125MHz(8ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 6ns 2.0ns 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 3CLKs 6ns 2.0ns 83MHz(12ns) 3CLKs 3CLKs 6CLKs 9CLKs 2CLKs 6ns 2.0ns CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.0ns HY57V641620HG(L)T-PI HY57V641620HG(L)T-SI CAS Latency tRCD tRAS tRC tRP tAC tOH 100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.0ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.0ns This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0/Jan. 02 10 HY57V641620HG COMMAND TRUTH TABLE Command A10/ AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X ADDR RA Read L V H Write L H X L H L L X CA Write with Autoprecharge H X L L H L X Burst Stop H DQM H Auto Refresh H H L L L Burst-READ-SingleWRITE H X L L Entry H L L H Exit L H H X L H H L X L V X X V X H X X L L X A9 Pin High (Other Pins OP code) L L H X X X X X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge power down H X Precharge selected Bank Entry V H Precharge All Banks X X Exit Clock Suspend Note V CA Read with Autoprecharge Self Refresh1 BA Entry Exit L H L H X L H X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation Rev. 1.0/Jan. 02 11 HY57V641620HG PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 0.80(0.0315)BSC Rev. 1.0/Jan. 02 0.400(0.016) 0.300(0.012) 1.194(0.0470) 0.991(0.0390) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 12