TI MC3487J Quadruple differential line driver Datasheet

SLLS098C − MAY 1980 − REVISED FEBRUARY 2004
D Meets or Exceeds Requirements of ANSI
D
D
D
D
D
D, N, OR NS PACKAGE
(TOP VIEW)
TIA/EIA-422-B and ITU
Recommendation V.11
3-State, TTL-Compatible Outputs
Fast Transition Times
High-Impedance Inputs
Single 5-V Supply
Power-Up and Power-Down Protection
1A
1Y
1Z
1, 2EN
2Z
2Y
2A
GND
description/ordering information
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4A
4Y
4Z
3, 4EN
3Z
3Y
3A
The MC3487 offers four independent differential line drivers designed to meet the specifications of ANSI
TIA/EIA-422-B and ITU Recommendation V.11. Each driver has a TTL-compatible input buffered to reduce
current and minimize loading.
The driver outputs utilize 3-state circuitry to provide high-impedance states at any pair of differential outputs
when the appropriate output enable is at a low logic level. Internal circuitry is provided to ensure the
high-impedance state at the differential outputs during power-up and power-down transition times, provided the
output enable is low.
The MC3487 is designed for optimum performance when used with the MC3486 quadruple line receiver. It is
supplied in a 16-pin dual-in-line package and operates from a single 5-V supply.
ORDERING INFORMATION
PDIP − N
0°C to 70°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC − D
Tube
MC3487N
Tube
MC3487D
Tape and reel
MC3487DR
TOP-SIDE
MARKING
MC3487N
MC3487
SOP − NS
Tape and reel
MC3487NSR
MC3487
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each driver)
OUTPUTS
INPUT
OUTPUT
ENABLE
H
H
H
L
L
H
L
H
X
L
Z
Z
Y
Z
H = TTL high level, L = TTL low level,
X = irrelevant, Z = High impedance
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
! "#$ %!&
% "! "! '! ! !( !
%% )*& % "!+ %! !!$* $%!
!+ $$ "!!&
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1
SLLS098C − MAY 1980 − REVISED FEBRUARY 2004
logic diagram (positive logic)
1, 2EN
1A
2A
3, 4EN
3A
4A
4
1
7
2
3
6
5
1Y
1Z
2Y
2Z
12
9
15
10
11
14
13
3Y
3Z
4Y
4Z
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
TYPICAL OF ALL OUTPUTS
VCC
Input
9 Ω NOM
Output
2
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• DALLAS, TEXAS 75265
SLLS098C − MAY 1980 − REVISED FEBRUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, θJA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential output voltage, VOD, are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
VCC
VIH
Supply voltage
VIL
TA
Low-level input voltage
High-level input voltage
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Operating free-air temperature
0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
0.8
V
70
°C
3
SLLS098C − MAY 1980 − REVISED FEBRUARY 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
Input clamp voltage
VOL
|VOD|
Low-level output voltage
Differential output voltage
VIL = 0.8 V,
RL = 100 Ω,
∆|VOD|
Change in magnitude of
differential output voltage†
RL = 100 Ω,
VOC
Common-mode output voltage‡
∆|VOC|
High-level output voltage
II = −18 mA
VIL = 0.8 V,
MIN
MAX
−1.5
VIH = 2 V,
VIH = 2 V,
IOH = −20 mA
IOL = 48 mA
2.5
UNIT
V
V
0.5
V
See Figure 1
±0.4
V
RL = 100 Ω,
See Figure 1
3
V
Change in magnitude of
common-mode output voltage†
RL = 100 Ω,
See Figure 1
±0.4
V
IO
Output current with power off
VCC = 0
VO = 6 V
VO = −0.25 V
−100
IOZ
High-impedance-state output current
Output enables at 0.8 V
VO = 2.7 V
VO = 0.5 V
II
Input current at maximum input
voltage
VI = 5.5 V
100
µA
VI = 2.7 V
VI = 0.5 V
50
µA
IIH
IIL
High-level input current
IOS
Short-circuit output current §
ICC
Supply current (all drivers)
Low-level input current
See Figure 1
2
100
100
−100
VI = 2 V
Outputs disabled
−40
No load
µA
A
−400
µA
−140
mA
105
Outputs enabled,
A
µA
85
mA
† ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
‡ In ANSI Standard TIA/EIA-422-B, VOC, which is the average of the two output voltages with respect to ground, is called output offset voltage,
VOS.
§ Only one output at a time should be shorted, and duration of the short circuit should not exceed one second.
switching characteristics over recommended operating free-air temperature range, VCC = 5 V
PARAMETER
TEST CONDITIONS
MIN
MAX
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
CL = 15 pF,
See Figure 2
tsk
tt(OD)
Skew time
CL = 15 pF,
See Figure 2
6
ns
Differential-output transition time
CL = 15 pF,
See Figure 3
20
ns
tPZH
tPZL
Output enable time to high level
tPHZ
tPLZ
Output disable time from high level
4
Output enable time to low level
Output disable time from low level
CL = 50 pF,
See Figure 4
CL = 50 pF,
See Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
20
UNIT
tPLH
tPHL
20
30
30
25
30
ns
ns
ns
SLLS098C − MAY 1980 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
50 Ω
VOD
50 Ω
VOC
Figure 1. Differential and Common-Mode Output Voltages
3V
Input
5V
SW1
Generator
(see Note A)
200 Ω
1.5 V
1.5 V
tPHL
tPLH
VOH
1.5 V
Y Output
1.5 V
Skew
50 Ω
tPHL
CL = 15 pF
(see Note B)
3V
See Note C
0V
Skew
tPLH
1.5 V
Z Output
ÏÏÏ
ÏÏÏ
VOL
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 5 ns, tf ≤ 5 ns, PRR ≤ 1 MHz, duty cycle = 50%,
ZO = 50 Ω.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or 1N3064.
Figure 2. Test Circuit and Voltage Waveforms
CL
Generator
(see Note A)
50 Ω
RL = 100 Ω
Output
3V
Input
0V
tt(OD)
tt(OD)
3V
CL = 15 pF
(see Note B)
90%
Output
10%
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 5 ns, tf ≤ 5 ns, PRR ≤ 1 MHz, duty cycle = 50%,
ZO = 50 Ω.
B. CL includes probe and stray capacitance.
Figure 3. Test Circuit and Voltage Waveforms
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5
SLLS098C − MAY 1980 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
5V
Output
SW3
200 Ω
SW1
0 V or 3 V
Generator
(see Note A)
CL = 15 pF
(see Note B)
1 kΩ
See Note C
50 Ω
SW2
TEST CIRCUIT
Output
Enable Input
Output
Enable Input
3V
1.5 V
tPHZ
0V
tPZL
0V
VOH
SW1 Closed
SW2 Closed
≈1.5 V
≈1.5 V
SW1 Closed
0.5 V SW2 Closed
VOL
3V
1.5 V
0.5 V
Output
tPLZ
Output
1.5 V
Output
VOL
tPZH
Output
SW1 Closed
SW2 Open
1.5 V
VOH
SW1 Open
SW2 Closed
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 5 ns, tf ≤ 5 ns, PRR ≤ 1 MHz, duty cycle = 50%,
ZO = 50 Ω.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or 1N3064.
Figure 4. Driver Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
MC3487D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MC3487
MC3487DE4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MC3487
MC3487DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MC3487
MC3487DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MC3487
MC3487DRE4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MC3487
MC3487DRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MC3487
MC3487J
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
-55 to 125
MC3487N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
MC3487N
MC3487NE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
MC3487N
MC3487NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MC3487
MC3487NSRE4
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MC3487
MC3487NSRG4
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MC3487
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MC3487DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
MC3487DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MC3487DR
SOIC
D
16
2500
333.2
345.9
28.6
MC3487DR
SOIC
D
16
2500
367.0
367.0
38.0
Pack Materials-Page 2
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