LINER LTC1650 Low glitch 16-bit voltage output dac Datasheet

LTC1650
Low Glitch 16-Bit
Voltage Output DAC
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FEATURES
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DESCRIPTIO
The LTC®1650 is a deglitched rail-to-rail voltage output
16-bit digital-to-analog converter (DAC) available in a
16-pin narrow SO package. It has 16-bit monotonicity
over temperature and includes a rail-to-rail output buffer
amplifier and an easy to use three-wire cascadable serial
interface. The LTC1650 operates with dual ±5V supplies.
16-Bit Monotonic Over Temperature
Low Glitch Impulse: 2nV-s
Low Noise: 30nV/√Hz
Buffered Rail-to-Rail Voltage Output
Low Power: 50mW from ±5V Supplies
Unipolar or Bipolar Output (0V to VREF or ±VREF)
4-Quadrant Multiplying Capability
Asynchronous Clear to User-Defined Voltage
Power-On Reset
Three-Wire SPI and MICROWIRETM Compatible
Serial Interface
Schmitt Trigger On CLK Input Allows Direct
Optocoupler Interface
16-Pin Narrow SO Package
With REFLO = 0V and REFHI = VREF, the output will swing
from 0V to VREF in unipolar mode or ±VREF in bipolar
mode.
The LTC1650 has excellent accuracy over its full operating
temperature range along with very low power dissipation
of 50mW with dual ±5V supplies. This, along with the
small outline package, makes it the most flexible high
resolution digital-to-analog converter available today.
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APPLICATIO S
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The LTC1650 has a fast settling time of 4µs to 16 bits and
a low midscale glitch of under 2nV-s. This makes the
LTC1650 ideal for waveform generation or other applications where output dynamic performance is important.
Industrial Process Control
Precision Industrial Equipment
Waveform Generation
Automatic Test Equipment
High Resolution Offset and Gain Adjustment
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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TYPICAL APPLICATIO
5V
5V
3
CS/LD
8
CLK
7
RSTOUT
4.096V
DVDD
11
REFHI
15
10
AVDD
Differential Nonlinearity
vs Input Code
1.0
DOUT
16-BIT
DAC
9
CLR
2
VRST
+
1
VOUT
–
0.8
0.6
DNL ERROR (LSB)
16-BIT DAC REGISTER
5
16-BIT SHIFT REGISTER
DIN
POWER-ON RESET
SUPPLY SENSE
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
6
16
4
DGND
12,13
REFLO
14
AVSS
1650 TA01
UNI/BIP
– 1.0
0
16384
32768
CODE
49152
65535
1650 TA02
– 5V
1
LTC1650
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AXI U
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
AVDD, DVDD to DGND .............................. – 0.5V to 7.5V
TTL Input Voltage .................................... – 0.5V to 7.5V
VOUT, VRST ................................ – 0.5V to (AVDD + 0.5V)
AVSS .........................................................0.5V to – 7.5V
Operating Temperature Range
LTC1650C .............................................. 0°C to 70°C
LTC1650I ............................................ – 40°C to 85°C
Maximum Junction Temperature ......................... 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
VOUT 1
16 UNI/BIP
VRST 2
15 AVDD
DVDD 3
14 AVSS
DGND 4
13 REFLO S
DIN 5
12 REFLO F
DOUT 6
ORDER PART
NUMBER
LTC1650ACN
LTC1650AIN
LTC1650ACS
LTC1650AIS
LTC1650CN
LTC1650IN
LTC1650CS
LTC1650IS
11 REFHI
CLK 7
10 RSTOUT
CS/LD 8
9
N PACKAGE
16-LEAD PDIP
CLR
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 85°C/ W (N)
TJMAX = 125°C, θJA = 130°C/ W (S)
Consult LTC Marketing for parts specified with wider operating temperature
ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AVDD = 4.75V to 5.25V, AVSS = – 4.75V to – 5.25V, DVDD = 4.75V to
5.25V, REFLO = 0V, REFHI = 4.096V, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
LTC1650CS/CN
LTC1650IS/IN
MIN
TYP
MAX
CONDITIONS
LTC1650ACS/ACN
LTC1650AIS/AIN
MIN
TYP
MAX
UNITS
DAC Characteristics, Unipolar/Bipolar Output Unless Otherwise Noted
Resolution
Monotonicity
●
16
●
16
16
Bits
16
Bits
DNL
Differential Nonlinearity
Guaranteed Monotonic (Note 2)
●
±0.15
±0.9
±0.15
±0.5
LSB
INL
Integral Nonlinearity
Integral Nonlinearity (Note 2)
●
±4
±16
±4
±8
LSB
Bipolar Zero Error
Bipolar Zero Error
TA = 25°C
TA = TMIN to TMAX
±5
±12
±18
±5
●
±12
±18
LSB
LSB
VOS
Unipolar Offset Error
TA = TMIN to TMAX
●
±0.5
±12
±0.5
±12
LSB
VOSTC
Offset Error Temperature
Coefficient
Gain Error
±0.5
TA = TMIN to TMAX
●
±18
±0.5
Gain Error Temperature
Coefficient
2
±4
±0.5
Bipolar Negative
Full-Scale Error
TA = TMIN to TMAX
See Definitions Section
Bipolar Negative
Full-Scale Error Tempco
See Definitions Section
●
±1
±0.75
±4
µV/°C
±12
±0.5
±16
±1
±0.75
LSB
ppm/°C
±12
LSB
ppm/°C
LTC1650
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AVDD = 4.75V to 5.25V, AVSS = – 4.75V to – 5.25V, DVDD = 4.75V to
5.25V, REFLO = 0V, REFHI = 4.096V, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Characteristics
AVDD
Positive Supply Voltage
●
4.75
5.0
5.25
V
DVDD
Positive Supply Voltage
●
4.75
5.0
5.25
V
AVSS
Negative Supply Voltage
●
– 4.75
– 5.0
– 5.25
V
IAVDD
AVDD Supply Current
4.75V ≤ AVDD ≤ 5.25V (Note 5)
●
5
7.5
IAVSS
AVSS Supply Current
– 5.25V ≤ AVSS ≤ – 4.75V (Note 5)
●
– 7.5
–5
IDVDD
DVDD Supply Current
4.75V ≤ DVDD ≤ 5.25V (Note 5)
●
0.1
0.25
mA
AVDD, DVDD Supply Rejection
4.75V ≤ AVDD, DVDD ≤ 5.25V
●
0.5
1.5
LSB/V
AVSS Supply Rejection
– 5.25V ≤ AVSS ≤ – 4.75V
●
0.5
1.5
LSB/V
PSRR
mA
mA
Reference Input
RIN
Reference Input Resistance
●
2.5
5
7.5
kΩ
REFHI Range
●
– 4.0
4.0
4.5
V
REFLO Range
●
– 1.0
0
1.0
V
Op Amp DC Performance
Short-Circuit Current Low
VOUT Shorted to GND
●
25
50
mA
Short-Circuit Current High
VOUT Shorted to VCC
●
25
50
mA
Output Impedance
Measured at Midscale
DAC Output Range
Unipolar Mode (Note 9)
Bipolar Mode (Note 9)
0.15
Ω
0V to VREF
±VREF
V
V
AC Performance
Voltage Output Slew Rate
Voltage Output Settling Time
SINAD
●
Unloaded (Note 4)
0.8
2.0
4
V/µs
µs
Midscale Glitch Impulse
1.8
nV-s
Digital Feedthrough
0.05
nV-s
Output Noise Voltage Density
1kHz to 100kHz (Note 6)
30
nV/√Hz
Signal-to-Noise + Distortion Ratio
REFHI = 1kHz 4VP-P
96
dB
3
LTC1650
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AVDD = 4.75V to 5.25V, AVSS = – 4.75V to – 5.25V, DVDD = 4.75V to
5.25V, REFLO = 0V, REFHI = 4.096V, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
V
Digital I/O Characteristics
VIH
Digital Input High Voltage
●
VIL
Digital Input Low Voltage
●
VOH
Digital Output High Voltage
VOL
ILK
CIN
2.4
V
IOUT = –1mA, DOUT Only
●
VCC – 1.0
V
Digital Output Low Voltage
IOUT = 1mA, DOUT Only
●
0.4
V
Digital Input Leakage
VIN = GND to VCC
●
±10
µA
Digital Input Capacitance
(Note 3)
10
pF
200
500
Ω
2.5
2.5
3.2
3.2
V
V
Reset Characteristics
RON
VOUT and VRST Switch Resistance
Threshold Voltage for Reset
VRST = 0.5V (Note 7)
●
AVDD or DVDD (Note 8)
●
●
1.5
1.5
●
40
AVSS(Note 8)
Switching Characteristics
t1
DIN Valid to CLK Setup
t2
DIN Valid to CLK Hold
●
0
ns
t3
CLK High Time
(Note 3)
●
40
ns
t4
CLK Low Time
(Note 3)
●
40
ns
t5
CS/LD Pulse Width
(Note 3)
●
50
ns
t6
LSB CLK to CS/LD
(Note 3)
●
40
ns
t7
CS/LD Low to CLK
(Note 3)
●
20
ns
t8
DOUT Output Delay
CLOAD = 100pF
●
5
t9
CLK Low to CS/LD Low
(Note 3)
●
20
ns
t10
CLR Pulse Width
●
50
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity is defined from code 0 to code 65535 (full scale)
(end point INL, see Definitions section).
Note 3: Guaranteed by design. Not subject to test.
Note 4: To ±1LSB. Unipolar mode. DAC switched between all 1s and all 0s.
4
ns
45
150
ns
Note 5: Digital Inputs at 0V or DVDD.
Note 6: Measured at VOUT. REFHI = REFLO = 0V, unipolar mode.
Note 7: When part powers up or when it is reset, the output is connected
to VRST through this switch.
Note 8: Reset is active when any supply goes below this threshold.
Note 9: REFLO = 0V, REFHI = VREF. For REFLO ≠ 0V see Operation section.
LTC1650
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TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity (DNL) vs
Input Code
5
1.0
4
0.8
3
0.6
2
0.4
DNL ERROR (LSB)
INL ERROR (LSB)
Integral Nonlinearity (INL) vs
Input Code
1
0
–1
–2
CS/LD
5V/DIV
4.096V
0.2
VOUT
1V/DIV
0
–0.2
–0.4
–3
–0.6
–4
–0.8
–5
Large Signal Settling Time
0V
–1.0
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
1650 G01
65535
1µs/DIV
1650 G02
Large Signal Settling Time
Mid-Scale Glitch
CS/LD
5V/DIV
1650 G03
Broadband Noise
CS/LD
5V/DIV
4.096V
50µV/DIV
REFERRED
TO DAC
OUTPUT
VOUT
10mV/DIV
VOUT
1V/DIV
0V
BW = 100kHz
500ns/DIV
1650 G04
Minimum Supply Headroom for
Full Output Swing vs Load Current
1.0
0.8
100
5.5
5.4
90
ATTENUATION (dB)
0.7
VCC – VOUT
AVDD Supply Current vs
Temperature
Reference Feedthrough
∆ VOUT < 1LSB
VOUT = 4.096V
CODE: ALL 1’s
0.9
1650 G06
1650 G05
0.6
0.5
0.4
0.3
0.2
5.3
SUPPLY CURRENT (mA)
1µs/DIV
200µs/DIV
80
70
60
5.2
5.1
5.0
4.9
4.8
4.7
50
0.1
4.6
0
40
0
5.0
10.0
LOAD CURRENT (mA)
15.0
1650 G07
1
100
10k
1M
FREQUENCY (Hz)
100M
1650 G08
4.5
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1650 G09
5
LTC1650
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TYPICAL PERFOR A CE CHARACTERISTICS
AVSS Supply Current vs
Temperature
DVDD Supply Current vs
Temperature
–4.5
Offset Error vs Temperature
0
25
–4.6
–4.8
–4.9
–5.0
–5.1
–5.2
OFFSET ERROR (LSB)
20
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
–4.7
15
10
–0.5
–1.0
–1.5
–5.3
5
–5.4
–5.5
–55 –35 –15
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
1650 G10
–25
5
35
65
TEMPERATURE (°C)
95
125
1650 G12
1650 G11
Supply Current vs Logic Input
Voltage
Gain Error vs Temperature
0
2
ALL LOGIC INPUTS
TIED TOGETHER
DVDD SUPPLY CURRENT (mA)
–1
–2
–3
GAIN ERROR (LSB)
–2.0
–55
–4
–5
–6
–7
–8
1
–9
–10
–55
0
–25
5
35
65
TEMPERATURE (°C)
95
125
0
1
2
3
4
LOGIC INPUT VOLTAGE (V)
1650 G13
5
1650 G14
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PI FU CTIO S
VOUT (Pin 1): The DAC Output. The output will swing from
REFLO to REFHI in unipolar mode and from (2 • REFLO
– REFHI) to REFHI in bipolar mode.
VRST (Pin 2): The user-defined voltage to which the output
gets reset when CLR is active, when any of the supplies
drop below 2.5V or when the part powers-up. The output
will stay at this voltage until a new code is loaded into the
DAC register.
DVDD (Pin 3): The Digital Positive Supply Input. 4.75V ≤
DVDD ≤ 5.25V.
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DGND (Pin 4): Digital Ground.
DIN (Pin 5): The TTL Level Input for the Serial Interface
Data. Data on the DIN pin is latched into the shift register
on the rising edge of the serial clock. Data is loaded as one
16-bit word, MSB first.
DOUT (Pin 6): The output of the shift register that becomes valid on the rising edge of the serial clock.
CLK (Pin 7): The TTL Level Input for the Serial Interface
Clock.
LTC1650
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PI FU CTIO S
CS/LD (Pin 8): The TTL Level Input for the Serial Interface
Enable and Load Control. When CS/LD is low, the CLK
signal is enabled so the data can be clocked in. When
CS/LD is pulled high, data is loaded from the shift register
into the DAC register, updating the DAC output.
REFLO F/REFLO S (Pins 12, 13): The Force and Sense Pin
for the Lower Reference Input. This should nominally be
tied to ground. This pin can swing from – 1V to 1V.
CLR (Pin 9): The DAC is cleared to VRST when this pin is
pulled low. It should be logic high for normal operation.
AVDD (Pin 15): The Analog Positive Supply Input. 4.75V
≤ AVDD ≤ 5.25V. Requires a bypass capacitor to ground.
RSTOUT (Pin 10): The logic output pin that goes active
when any of the supplies drop below 2.5V. This pin is
active low.
UNI/BIP (Pin 16): The Unipolar/Bipolar Selection Pin. For
unipolar operation, tie this pin to VOUT and for bipolar
operation, tie this pin the REFHI.
AVSS (Pin 14): The Analog Negative Supply Input. – 5.25V
≤ AVSS ≤ – 4.75V. Requires a bypass capacitor to ground.
REFHI (Pin 11): The Reference Input Pin. The DAC is
capable of 4-quadrant multiplying; this pin can swing
from 4.5V to – 4V.
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TI I G DIAGRA
t6
t2
t1
t4
t3
t7
CLK
B15
MSB
DIN
B14
B13
B0
LSB
B1
t9
t5
CS/LD
t8
DOUT
B15
(PREVIOUS
WORD)
B14
B13
B1
B0
1650 TD
7
LTC1650
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DEFINITIONS
Resolution (n)
Differential Nonlinearity (DNL)
Resolution is defined as the number of digital input bits,
n. It defines the number of DAC output states (2n) that
divide the full-scale range. The resolution does not imply
linearity.
DNL is the difference between the measured change and
the ideal 1LSB change between any two adjacent codes.
The DNL error between any two codes is calculated as
follows:
Full-Scale Voltage (VFS)
This is the output of the DAC when all bits are set to 1. The
output will swing from REFLO to REFHI in unipolar mode
and from (2 • REFLO – REFHI) to REFHI when in bipolar
mode.
Voltage Offset Error (VOS)
This is the voltage at the output when the DAC is loaded
with all zeros.
Least Significant Bit (LSB)
One LSB is the ideal voltage difference between two
successive codes.
LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/65535
DNL = (∆VOUT – LSB)/LSB
∆VOUT = The measured voltage difference between two
adjacent codes.
Gain Error (GE)
Gain error is the difference between the full-scale output of
a DAC from its ideal full-scale value after offset error has
been adjusted for.
Bipolar Zero Error
When configured for bipolar output and with REFLO tied
to 0V, the LTC1650 output should be 0V with (100…00)
loaded in. Any deviation from 0V at this code is called
bipolar zero error.
Bipolar Negative Full-Scale Error
Integral Nonlinearity (INL)
Endpoint INL is the maximum deviation from a straight
line passing through the endpoints of the DAC transfer
curve. It is measured after adjusting out gain and offset
error for the DAC.
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This is the offset error of the LTC1650 in bipolar mode.
LTC1650
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OPERATIO
Serial Interface
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one
16-bit word, MSB first. The DAC register loads the data
from the shift register when CS/LD is pulled high. The
clock is disabled internally when CS/LD is high. Note: CLK
must be low before CS/LD is pulled low to avoid an extra
internal clock pulse.
The buffered output of the 16-bit shift register is available
on the DOUT pin which swings from DGND to DVDD.
Multiple LTC1650s may be daisy-chained together by
connecting the DOUT pin to the DIN pin of the next chip
while the clock and CS/LD signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
the chips, then the CS/LD signal is pulled high to update all
of them simultaneously.
When CLR is pulled low or when the part powers up, the
output connects through an internal pass gate to VRST and
will go to whatever voltage is on VRST. When any of three
supplies (DVDD, AVDD, |AVSS|) goes below 2.5V, the
RSTOUT pin goes low and stays low as long as the supply
is below 2.5V. The power-on reset is also activated when
one of the supplies drops below 2.5V and the output is
then connected to VRST. The output connects to VRST
when any of three conditions occur: CLR goes low, the part
powers up or one of the supplies drops below 2.5V. This
condition exists as long as CS/LD is low. As soon as CS/LD
goes high, the DAC register is loaded with the data in the
shift register and the output will settle to its new value.
Voltage Output
The LTC1650 rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range. The
output is specified to swing up to ±4.5V on ±4.75V
supplies with VOUT unloaded. (For typical output swing at
various load currents, refer to the typical curve “Minimum
Supply Headroom for Full Output Swing vs Load Current.”) The buffer amplifier can drive 1000pF without
going into oscillation. The LTC1650 has a deglitched
voltage output. The midscale glitch is less than 2nV-s. The
digital feedthrough is about 0.05nV-s.
Output Ranges
The LTC1650 is capable of unipolar or bipolar output
swing. When the UNI/BIP pin is connected to VOUT the part
is configured for unipolar operation and the output will
swing from REFLO to REFHI. When UNI/BIP is connected
to REFHI the part is configured in bipolar mode and the
output will swing from (2 • REFLO – REFHI) to REFHI and
will be at REFLO at midscale. With REFLO = 0V the output
swing is ±REFHI in bipolar mode and 0V to REFHI in
unipolar mode.
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LTC1650
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TYPICAL APPLICATIO
16-Bit Industrial Process Controller
6V TO 30V
5V
IN
LT1019-4.5
0.1µF
5V
0.1µF
4.5V
REFHI
AVDD
DVDD UNI/BIP
CLK
DIN
CS/LD
µP
LTC1650
VOUT
CLR
CONTROL VOLTAGE
0V TO 4.5V
(69µV/LSB)
RSTOUT
DOUT
REFLO F/S
DGND
AVSS
VRST
–5V
0.1µF
1650 TA03
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LTC1650
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PACKAGE DESCRIPTION
N Package
16-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.255 ± 0.015*
(6.477 ± 0.381)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.020
(0.508)
MIN
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
0.045 – 0.065
(1.143 – 1.651)
)
0.065
(1.651)
TYP
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N16 1098
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
2
3
4
5
6
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
0.014 – 0.019
(0.355 – 0.483)
TYP
8
0.004 – 0.010
(0.101 – 0.254)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
7
0.050
(1.270)
BSC
S16 1098
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1650
U
TYPICAL APPLICATIO
A ±10V Bipolar Output 16-Bit DAC
5V
0.1µF
5V
0.1µF
BIPOLAR
OUT
IN
UNIPOLAR
IN
DVDD
AVDD
UNI/BIP
REFHI
15V
LT1019-4.5
CLK
DIN
15V
CS/LD
µP
VOUT
LTC1650
CLR
RSTOUT
+
LT1468
–
REFLO
DGND
AVSS
VRST
–15V
110k
–5V
0.1µF
0V TO 10V
(UNIPOLAR MODE)
–10V TO 10V
(BIPOLAR MODE)
90k
10pF
1650 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1257
Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V,
Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V
5V to 15V Single Supply, Complete VOUT DAC in
SO-8 Package
LTC1446/LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V
Output Swings from GND to REF. REF Input
Can Be Tied to VCC
LTC1450/LTC1450L
Single 12-Bit VOUT DACs with Parallel Interface
LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1451/LTC1452/
LTC1453
Single 12-Bit VOUT DACs with Serial Interface
LTC1451: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1452: VCC = 2.7V to 5.5V, VOUT = 0V to 2 • VREF
LTC1453: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1456
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,
Full Scale: 4.095V, VCC: 4.5V to 5.5V
Low Power, Complete VOUT DAC in SO-8
Package with Clear Pin
LTC1458/LTC1458L
Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1595/LTC1596
16-Bit Serial I/O Multiplying IOUT DACs
±1LSB Max INL/DNL, Low Glitch,
SO-8 Package (LTC1595), Clear Pin (LTC1596)
LTC1659
Single Rail-to-Rail 12-Bit VOUT DAC in MSOP-8 Package,
VCC: 2.7V TO 5.5V
Low Power Multiplying VOUT DAC in MSOP-8 Package.
Output Swings from GND to REF. REF Input Can be Tied
to VCC
DACs
References
LT1019
Precision Voltage Reference
Ultralow Drift 5ppm/°C, Initial Accuracy: 0.05%
LT1634
Micropower Precision Reference
Low Drift 10ppm/°C, Initial Accuracy: 0.05%
12
Linear Technology Corporation
1650fa LT/TP 1001 1.5K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 1998