Renesas HD74ALVCH162827 20-bit buffers / drivers with 3-state output Datasheet

HD74ALVCH162827
20-bit Buffers / Drivers with 3-state Outputs
REJ03D0042-0400Z
(Previous ADE-205-188B (Z) )
Rev.4.00
Oct.02.2003
Description
The HD74ALVCH162827 is composed of two 10-bit sections with separate output enable signals. For
either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 22OE2) inputs must both
be low for the corresponding Y outputs to be active. If either output enable input is high, the outputs of that
10-bit buffer section aree in the high impedance state. Active bus hold circuitry is provided to hold unused
or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include
26 Ω resistors to reduce overshoot and undershoot.
Features
•
•
•
•
•
•
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±12 mA (@VCC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
external resistors are required.
All outputs have equivalent 26 Ω series resistors, so no ex
Rev.4.00, Oct.02.2003, page 1 of 9
HD74ALVCH162827
Function Table
Inputs
Output Y
OE1
OE2
A
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
H : High level
L : Low level
X : Immaterial
Z : High impedance
Rev.4.00, Oct.02.2003, page 2 of 9
HD74ALVCH162827
Pin Arrangement
56 1OE2
1OE1 1
1Y1 2
55 1A1
1Y2 3
54 1A2
GND 4
53 GND
1Y3 5
52 1A3
1Y4 6
VCC 7
51 1A4
1Y5 8
49 1A5
1Y6 9
48 1A6
1Y7 10
47 1A7
GND 11
46 GND
1Y8 12
45 1A8
1Y9 13
44 1A9
1Y10 14
43 1A10
2Y1 15
42 2A1
2Y2 16
41 2A2
2Y3 17
40 2A3
GND 18
39 GND
2Y4 19
38 2A4
2Y5 20
37 2A5
2Y6 21
36 2A6
VCC 22
35 VCC
2Y7 23
34 2A7
2Y8 24
33 2A8
GND 25
32 GND
2Y9 26
31 2A9
2Y10 27
30 2A10
2OE1 28
29 2OE2
50 VCC
(Top view)
Rev.4.00, Oct.02.2003, page 3 of 9
HD74ALVCH162827
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
VCC
–0.5 to 4.6
V
Input voltage *1
VI
–0.5 to 4.6
V
VO
–0.5 to VCC +0.5
V
Input clamp current
IIK
–50
mA
VI < 0
Output clamp current
IOK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
VCC, GND current / pin
ICC or IGND
±100
mA
Maximum power dissipation
*3
at Ta = 55°C (in still air)
PT
1
W
Storage temperature
Tstg
–65 to 150
°C
Output voltage
*1, 2
Conditions
TSSOP
Notes: Stresses beyond those listed under “absolute
e maximum ratings” may cause permanent damage to
the device. These are stress ratings only, and functional
unctional operation of the device at these or any
other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Supply voltage
VCC
2.3
3.6
V
Input voltage
VI
0
VCC
V
Output voltage
VO
0
VCC
V
High level output current
IOH
—
–6
mA
—
–8
VCC = 2.7 V
—
–12
VCC = 3.0 V
—
6
—
8
VCC = 2.7 V
—
12
VCC = 3.0 V
Low level output current
IOL
Max
Unit
mA
Input transition rise or fall rate
∆t / ∆v
0
10
ns / V
Operating temperature
Ta
–40
85
°C
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.4.00, Oct.02.2003, page 4 of 9
Conditions
VCC = 2.3 V
VCC = 2.3 V
HD74ALVCH162827
Logic Diagram
1OE1 1
1OE2 56
1A1
55
2
1Y1
To nine other channels
2OE1 28
2OE2 29
2A1
42
15
2Y1
To nine other channels
Rev.4.00, Oct.02.2003, page 5 of 9
HD74ALVCH162827
Electrical Characteristics
(Ta = –40 to 85°C)
Item
Symbol VCC (V) *1
Min
Max
Unit
Input voltage
VIH
2.3 to 2.7
1.7
—
V
2.7 to 3.6
2.0
—
2.3 to 2.7
—
0.7
2.7 to 3.6
—
0.8
VIL
Output voltage
VOH
IOH = –100 µA
Min to Max VCC–0.2
—
2.3
1.9
—
IOH = –4 mA, VIH = 1.7 V
2.3
1.7
—
IOH = –6 mA, VIH = 1.7 V
3.0
2.4
—
IOH = –6 mA, VIH = 2.0 V
2.7
2.0
—
IOH = –8 mA, VIH = 2.0 V
3.0
2.0
—
IOH = –12 mA, VIH = 2.0 V
Min to Max —
0.2
IOL = 100 µA
µ
2.3
—
0.4
IOL = 4 mA, VIL = 0.7 V
2.3
—
0.55
IOL = 6 mA, VIL = 0.7 V
3.0
—
0.55
IOL = 6 mA, VIL = 0.8 V
2.7
—
0.6
IOL = 8 mA, VIL = 0.8 V
3.0
—
0.8
IOL = 12 mA, VIL = 0.8 V
IIN
3.6
—
±5
IIN (hold)
2.3
45
—
VIN = 0.7 V
2.3
–45
—
VIN = 1.7 V
3.0
75
—
VIN = 0.8 V
3.0
–75
—
VIN = 2.0 V
3.6
—
±500
VIN = 0 to 3.6 V
VOL
Input current
V
Test Conditions
µA
VIN = VCC or GND
IOZ
3.6
—
±10
µA
VOUT = VCC or GND
Quiescent supply current ICC
3.6
—
40
µA
VIN = VCC or GND
3.0 to 3.6
—
750
µA
VIN = one input at (VCC–0.6) V,
other inputs at VCC or GND
Off state output current
*2
∆ICC
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2. For I/O ports, the parameter IOZ includes the input leakage current.
Rev.4.00, Oct.02.2003, page 6 of 9
HD74ALVCH162827
Switching Characteristics
(Ta = –40 to 85°C)
Item
Symbol
Propagation delay time
Output enable time
Output disable time
Input capacitance
Output capacitance
VCC (V)
Min
Typ
Max
tPLH
2.5±0.2
1.0
―
4.4
tPHL
2.7
―
―
4.4
3.3±0.3
1.0
―
3.8
tZH
2.5±0.2
1.2
―
6.3
tZL
2.7
―
―
6.2
3.3±0.3
1.0
―
5.1
tHZ
2.5±0.2
1.9
―
5.9
tLZ
2.7
―
―
5.2
3.3±0.3
1.3
―
4.7
3.3
―
3.5
―
3.3
―
6.0
―
3.3
―
7.0
―
CIN
CO
Unit
FROM (input) TO (output)
ns
A
Y
ns
OE
Y
ns
OE
Y
pF
Control inputs
Data inputs
pF
outputs
Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
C L = 50 pF
500 Ω
Load Circuit for Outputs
Note:
1.
Symbol
t PLH / t PHL
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
OPEN
OPEN
t ZH/ t HZ
t ZL / t LZ
GND
GND
4.6 V
6.0 V
CL includes probe and jig capacitance.
Rev.4.00, Oct.02.2003, page 7 of 9
HD74ALVCH162827
Waveforms-1
tr
tf
Input
VIH
90 %
Vref
90 %
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Output
Vref
Vref
VOL
Waveforms-2
tf
tr
90 %
Vref
Output
Control
VIH
90 %
Vref
10 %
t ZL
10 %
GND
t LZ
≈VOH1
Vref
Waveform - A
t ZH
Waveform - B
VOL + 0.3 V
t HZ
VOH – 0.3 V
Vref
VOL
VOH
≈VOL1
TEST
VIH
Vref
VOH1
VOL1
Notes:
1.
2.
3.
4.
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
2.3 V
2.7 V
1.2 V
2.3 V
1.5 V
3.0 V
GND
GND
All Notes: 1. ll input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V)
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V)
Waveform – A is for an output with internal conditions such that the output is low except
when disabled by the output control.
Waveform – B is for an output with internal conditions such that the output is high except
when disabled by the output control.
The output are measured one at a time with one transition per measurement.
Rev.4.00, Oct.02.2003, page 8 of 9
HD74ALVCH162827
Package Dimensions
As of January, 2003
14.0
14.2 Max
56
Unit: mm
6.10
29
*0.19 ± 0.05
0.50
28
0.08 M
1.0
8.10 ± 0.20
0.10
*Ni/Pd/Au plating
Rev.4.00, Oct.02.2003, page 9 of 9
0˚ – 8˚
*0.15 ± 0.05
1.20 Max
0.65 Max
0.10 ± 0.05
1
0.50 ± 0.1
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-56DAV
—
—
0.23 g
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is alwa
always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem
placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
distrib
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor
for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
a
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and
algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances
in which human life
ci
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace,
nuclear, or undersea repeater
aerosp
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials
materials.
7. If these products or technologies are subject
ect to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the countr
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein
therein.
http://www.renesas.com
RENESAS SALES OFFICES
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 1.0