ON MC100EP14 3.3v / 5v 1:5 differential ecl/pecl/hstl clock driver Datasheet

MC100EP14
3.3V / 5V1:5 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100EP14 is a low skew 1−to−5 differential driver, designed with
clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single−ended (if the VBB output is used). HSTL inputs can be used when
the LVEP14 is operating under PECL conditions.
The EP14 specifically guarantees low output−to−output skew. Optimal
design, layout, and processing minimize skew within a device and from
device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The MC100EP14, as with most other ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the EP14 to be
used for high performance clock distribution in 5.0 V systems.
Designers can take advantage of the EP14’s performance to distribute
low skew clocks across the backplane or the board.
Features
•
•
•
•
•
•
•
•
•
400 ps Typical Propagation Delay
100 ps Device−to−Device Skew
25 ps Within Device Skew
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode:
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode:
VCC = 0 V with VEE = −3.0 V to −5.5 V
Open Input Default State
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 5
http://onsemi.com
TSSOP−20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
20
100
EP14
ALYWG
G
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
1
Publication Order Number:
MC100EP14/D
MC100EP14
VCC
EN
VCC
CLK1
CLK1
VBB
CLK0
CLK0
CLK_SEL
VEE
20
19
18
17
16
15
14
13
12
11
1
0
D
Q
1
2
3
4
5
6
7
8
9
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
WARNING: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. TSSOP−20 (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Table 2. FUNCTION TABLE
Function
CLK0*, CLK0**
ECL/PECL/HSTL CLK Input
CLK1*, CLK1**
ECL/PECL/HSTL CLK Input
Q0:4, Q0:4
ECL/PECL Outputs
CLK_SEL*
ECL/PECL Active Clock Select Input
EN*
ECL Sync Enable
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
CLK0
CLK1
CLK_SEL
EN
Q
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*
* On next negative transition of CLK0 or CLK1
* Pins will default low when left open.
** Pins will default to VCC/2 when left open.
http://onsemi.com
2
MC100EP14
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP−8
Flammability Rating
Oxygen Index: 28 to 34
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
357 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−20
TSSOP−20
140
100
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−20
23 to 41
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VI VCC
VI VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
http://onsemi.com
3
MC100EP14
Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
55
65
48
58
68
52
62
72
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 3)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 3)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single−Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
1875
1.2
1875
150
D
D
0.5
−150
1875
150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
3. All loading with 50 W to VCC − 2.0 V.
4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 6. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
55
65
48
58
68
52
62
72
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 6)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single−Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
5.0
1.2
5.0
1.2
5.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
3575
1.2
150
D
D
0.5
−150
3575
150
0.5
−150
0.5
−150
3575
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
6. All loading with 50 W to VCC − 2.0 V.
7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
http://onsemi.com
4
MC100EP14
Table 7. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 8)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
45
55
65
48
58
68
52
62
72
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 9)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 9)
−1945
−1820
−1695
−1945
−1820
−1695
−1945
−1820
−1695
mV
VIH
Input HIGH Voltage (Single−Ended)
−1225
−880
−1225
−880
−1225
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1945
−1625
−1945
−1625
−1945
−1625
mV
VBB
Output Reference Voltage
−1525
−1325
−1525
−1325
−1525
−1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current CLK
CLK
−1425
VEE+1.2
0.0
−1425
VEE+1.2
150
0.5
−150
0.0
−1425
VEE+1.2
150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with VCC.
9. All loading with 50 W to VCC − 2.0 V.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 11)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
VOPP
Output Voltage Amplitude @ 2 GHz
(Figure 2)
440
540
tPLH
tPHL
Propagation Delay to
Output Differential
275
330
400
tskew
Within−Device Skew
Device−to−Device Skew
(Note 12)
25
100
35
125
ts
th
Setup Time to CLK EN to CLK
Hold Time
EN to CLK
tJITTER
Cycle−to−Cycle Jitter (Figure 2)
VPP
Minimum Input Swing
tr/tf
Output Rise/Fall Time (20%−80%)
100
200
50
140
Min
Typ
420
520
275
375
450
30
150
45
175
100
200
0.2
<1
150
800
1200
105
155
205
85°C
Max
50
140
Min
Typ
380
480
280
380
480
ps
40
175
50
200
ps
100
200
0.2
<1
150
800
1200
145
200
270
Max
Unit
GHz
50
140
ps
0.2
<1
ps
150
800
1200
mV
150
225
300
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
12. Skew is measured between outputs under identical transitions.
http://onsemi.com
5
MC100EP14
9
900
5.0 V
VOUTpp (mV)
800
8
3.3 V
7
750
6
700
5
650
4
600
550
3
500
2
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉ
(JITTER)
450
400
0.0
0.5
1.0
1.5
1
2.0
JITTER OUT ps (RMS)
850
ÉÉ
ÉÉ
2.5
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC100EP14DT
TSSOP−20*
75 Units / Rail
MC100EP14DTG
TSSOP−20*
75 Units / Rail
MC100EP14DTR2
TSSOP−20*
2500 / Tape & Rail
MC100EP14DTR2G
TSSOP−20*
2500 / Tape & Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
6
MC100EP14
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
http://onsemi.com
7
MC100EP14
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC100EP14
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC10EP14/D
Similar pages