ON CS2082 Dual airbag deployment asic Datasheet

CS2082
Dual Airbag
Deployment ASIC
The CS2082 controls and monitors two airbag firing loops. The
independent firing loops are low– and high–side controlled. Device
communication is through a Serial Peripheral Interface (SPI) port, and
includes frame error detection circuitry for data reliability.
Diagnostics include squib resistance measurement and continuous
monitoring for shorts to ground, shorts to battery, and for open loops.
The high– and low–side drivers can be individually activated to
guarantee function and to identify shorts between firing loops.
Additional features include power on reset, overtemperature
protection, a charge pump, high–side safing sensor closure detection,
an analog multiplexer, a monitor to ensure battery potential, and a
programmable monitor to ensure firing potential.
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SO–20L
DW SUFFIX
CASE 751D
PIN CONNECTIONS AND
MARKING DIAGRAM
Features
• Serial Input Bus
• Two Squib Outputs
• Low– and High–Side Control
• Monitors
– Squib Resistance
– Short to Ground or Battery
– Battery Potential
– Firing Potential
• Safing Sensor Detection
• 60 V Peak Transient Voltage
1
A
WL, L
YY, Y
WW, W
CS2082
AWLYYWW
VBAT
CHRG
VRES
VR1
SH1
SL1
FG1
DOUT
CLK
MR
20
GND
VCC
DIN
VR2
SH2
SL2
FG2
AIN
AOUT
CS
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2001
July, 2001 – Rev. 7
1
Package
Shipping
CS2082EDW20
SO–20L
37 Units/Rail
CS2082EDWR20
SO–20L
1000 Tape & Reel
Publication Order Number:
CS2082/D
CS2082
CHRG
VCC
VRES
VBAT
Battery
Monitor
VRES
Monitor
Charge Pump
Monitor
Charge
Pump
Sensor
Monitor
CHRG
VR1
1.5 Ω
Gate
Drive
VBAT
1
VBAT
Current
Limit
2
10 k
R
SH1
+
–
VRES
2R
+
–
SPI
1.5 Ω
Gate
Drive
SL1
10 k
Current
Limit
R
Diagnostic
FG1
Overtemperature
GND
Reset
VCC
CHRG
VR2
1.5 Ω
Gate
Drive
VBAT
1
VBAT
Current Limit
2
+ 50 mV
Current
Limit
10 k
SH2
–
+
Analog
MUX
VRES
VCC
Gate
Drive
Resistive
Measurement
1.5 Ω
SL2
10 k
Current
Limit
FG2
CS CLK DIN DOUT AIN AOUT MR
Figure 1. Block Diagram
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2
CS2082
MAXIMUM RATINGS*
Rating
Value
Unit
Storage Temperature
–40 to 150
°C
VBAT
–0.3 to 24
V
VRES
–0.3 to 30
V
VCC
–0.3 to 6.0
V
ESD Susceptibility (Human Body Model)
500
V
Power Dissipation (Non–Firing)
0.15
W
Power Dissipation (Both Firing Loops With Squibs Shorted)
140
W
Power Dissipation (Squib Resistance Measurement)
1.6
W
Peak Transient Voltage (46 V Load Dump @ 14 V VBAT)
60
V
230 peak
°C
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (4.75 V < VCC < 5.25 V, 8.0 V < VRES < 30 V, 9.0 V < VBAT < 18 V,
–40°C < TA < +85°C; unless otherwise stated.)
Test Conditions
Parameter
Min
Typ
Max
Unit
Supply Requirements
VCC Quiescent Current
VCC = 5.25 V
–
2.0
4.0
mA
VBAT Quiescent Current
VBAT = 18 V
–
2.5
5.0
mA
VBAT Measurement Current
VBAT = 18 V, RSQUIB = 1.0 Ω
–
–
80
mA
VRES Quiescent Current
VRES = 30 V
–
–
1.0
mA
VRES Firing Current
VRES = 30 V
–
–
3.0
mA
Power on Reset
VBAT = 9.0 V, VRES = 10 V
Power Reset Active Voltage
VCC Falling
3.50
4.00
4.25
V
Power Reset Off Voltage
VCC Rising
3.65
4.20
4.50
V
50
–
–
mV
–
–
1.8
V
1.2
1.6
2.0
A
Hysteresis
Low Side Driver
–
VRES = 8.0 V = VRX, VCC = 5.0 V, VBAT = 8.0 V
Saturation Voltage
I = 1.2 A
Current Limit (ILIMIT)
VSLX – VFGX = 5.0 V
Turn–on Delay Time
From CS falling Edge, ID = 0.9 × ILIMIT(MIN)
–
–
75
µs
Turn–off Delay Time
From CS falling Edge, ID = 0.1 × ILIMIT(MIN)
–
–
25
µs
–
–
1.8
V
High Side Driver
VRES = 8.0 V = VRX, VCC = 5.0 V, VBAT = 8.0 V
Saturation Voltage
I = 1.2 A
Current Limit (ILIMIT)
VRX – VSHX = 5.0 V
1.2
2.0
2.5
A
VR1 Quiescent Current Drivers off
VRX = VRES = 30 V
–
–
1.0
mA
VR2 Quiescent Current Drivers off
VRX = VRES = 30 V
–
–
100
µA
Turn–on Delay Time
From CS falling Edge, ID = 0.9 × ILIMIT(MIN)
–
–
100
µs
Turn–off Delay Time
From CS falling Edge, ID = 0.1 × ILIMIT(MIN)
–
–
25
µs
Thermal Shut Down
Thermal Shutdown Temp
Guaranteed by Design
150
180
210
°C
Thermal Hysteresis
Guaranteed by Design
30
40
60
°C
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CS2082
ELECTRICAL CHARACTERISTICS (continued) (4.75 V < VCC < 5.25 V, 8.0 V < VRES < 30 V, 9.0 V < VBAT < 18 V,
–40°C < TA < +85°C; unless otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
7.0
–
–
ms
46
53
60
mV
–1.0
–
1.0
%
Thermal Shut Down
Time to Thermal Shutdown
Squib Resistive Measurements
RSQUIB = 0, VRX = 30 V, T = 85°C,
Guaranteed by Design
VCC = 5.0 V, RMR = 49.9 , VRES = 30 V
Squib Differential Voltage
VDIFF = SHx – SLx, RSQUIB = 1.0 Ω to 10 Ω
Difference Between SHx & MR
current – SHx reference
ISQUIB = 50 mA
SHx Current Limit
RSQUIB = 0
67
100
133
mA
SLx Current Limit
RMR = 0
77
115
153
mA
MR Voltage Clamp
–
VCC – 0.3
–
VCC + 0.3
V
Turn On Delay Time excluding
external Capacitors
–
–
–
100
µs
Turn off Delay Time
–
–
–
50
µs
4.0
4.0
10
10
17
17
kΩ
kΩ
Short Measurements
SHx pull–up resistance to VBAT
SLx pull–down resistance
VCC = 5.0 V, VRES VBAT, VRX VBAT
VBAT = 18 V
Pull–up resistor matching
–
–5.0
–
5.0
%
Pull–down resistor matching
–
–5.0
–
5.0
%
Short to VBAT Trip
SHx short to Battery
SLx bit set to 1
0.73 × VBAT
0.75 × VBAT
0.77 × VBAT
V
Short to GND Trip
SHx short to GND
SGx bit set to 1
0.23 × VBAT
0.25 × VBAT
0.27 × VBAT
V
VBAT Monitoring
VCC = 5.0 V, External VBAT Diode not included, VRES = 30 V
VBAT Low Trip
BL bit set to 1 when below trip
7.5
8.5
9.5
V
VBAT High Trip
BL bit set to 0 when above trip
8.0
9.0
10
V
VRES Monitoring
VCC = 5.0 V, VBAT = 18 V
VRES Low Trip
$6d AUX register b0 = 0
15.7
17.5
19.3
V
VRES High Trip
$6d AUX register b0 = 0
16.5
18.5
20.5
V
VRES Low Trip
$6d AUX register b0 = 1
21.5
24.0
26.5
V
VRES High Trip
$6d AUX register b0 = 1
22.5
25
27.5
V
30
400
600
Ω
200
–
800
kHz
Safing Sensor Monitor
External Resistance Trip Range
Charge Pump and Monitor
SSC bit set when resistance is less
VCC = 5.0 V, VBAT = 10 V
Oscillator Frequency
VRES = 10 V
Charge Pump charge time
CCHG = 0.1 µF, VRES = 8.0 V,
Chrg from 8.0 V to 14 V
–
–
20
ms
Charge Pump Low Voltage
CL bit set to 1 when below trip
14.5
16.0
17.5
V
Charge Pump High Voltage
CL bit set to 0 when above trip
15.0
17.5
18.0
V
Analog MUX
VCC = 5.0 V
AOUT Output Range
–
0.1
–
VCC – 0.1
V
AIN Input Range
–
0
–
VCC
V
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CS2082
ELECTRICAL CHARACTERISTICS (continued) (4.75 V < VCC < 5.25 V, 8.0 V < VRES < 30 V, 9.0 V < VBAT < 18 V,
–40°C < TA < +85°C; unless otherwise stated.)
Parameter
Analog MUX
Test Conditions
Min
Typ
Max
Unit
–
–
100
mV
VCC = 5.0 V
MUX internal voltage drop
IOUT = 100 µA
Proportion of VBAT
on AOUT with VBAT selected
–
23
25
27
%
AOUT Impedance with VBAT
selected
–
6.0
15.0
35
kΩ
Proportion of VRES
on AOUT with VRES selected
–
15
17
19
%
AOUT Impedance with VRES
selected
–
6.0
12.5
25.5
kΩ
Digital Inputs – DIN, CLK, CS
VCC = 5.25 V, VBAT = 18 V, VRES = 30 V
Input Low Voltage (VIL)
–
0
–
0.3 × VCC
V
Input High Voltage (VIH)
–
0.7 × VCC
–
VCC
V
Input Voltage Hysteresis
–
100
–
–
mV
Input Pull Down Current (IIH)
–
50
100
200
µA
–
–
0.4
V
Digital Outputs – DOUT
VCC = 4.75 V, VBAT = 18 V, VRES = 30 V
Output Low Voltage (VOL)
ISINK = 1.0 mA
Output High Voltage (VOH)
ISOURCE = 1.0 mA
VCC – 0.75
–
–
V
Tri–State Pull–up Current
CS = 0, DOUT = 0
50
100
200
µA
Rise | Fall Time
CLOAD = 200 pF
–
–
50
ns
PACKAGE PIN DESCRIPTION
Package Lead Number
SO–20L
Pin Symbol
1
VBAT
Battery Supply Voltage.
2
CHRG
Charge pump Storage.
3
VRES
Reserve Supply Voltage.
4
VR1
Loop 1 Supply.
5
SH1
Squib 1 High Side.
6
SL1
Squib 1 Low Side.
7
FG1
Loop 1 Return.
8
DOUT
Serial Port output.
9
CLK
Serial Port Clock.
10
MR
Squib Resistance Output Current.
11
CS
Serial Port Chip Select.
12
AOUT
13
AIN
Analog MUX Input.
14
FG2
Loop 2 Return.
15
SL2
Squib 2 Low Side.
16
SH2
Squib 2 High Side.
17
VR2
Loop 2 Supply.
Function
Analog MUX Output.
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CS2082
PACKAGE PIN DESCRIPTION (continued)
Package Lead Number
SO–20L
Pin Symbol
18
DIN
Serial Port Input.
19
VCC
5.0 V Regulated Supply.
20
GND
Signal Ground.
Function
FUNCTIONAL DESCRIPTION
the VRES and VR1 pins, the state of the internal charge
pump, and the state of external VBAT and VRES power
supplies. The status register is an 8–bit active–high register
with bit definition as shown in Table 2.
The CS2082 is an automotive air bag deployment and
diagnostic system for up to two independent firing loops.
Communication with the ASIC is through a synchronous
serial port using Serial Peripheral Interface (SPI) protocol,
at CLK rates up to 2.0 MHz.
Data is simultaneously sent from the DOUT pin and
received at the DIN pin under the control of the CS and CLK
pins. Error detection logic is included in the SPI to guard
against glitches on either the CS or CLK logic signal inputs.
A valid CS frame must contain exactly 8 CLK cycles for
each CS low–high–low transition. Detection of a frame error
will cause input data for that frame to be ignored and an error
code ($FE) to be sent during the next valid CS frame.
The data at DOUT is sent MSB first and is guaranteed valid
before the rising edge of CLK. The 8 bits sent from DOUT
after CS goes high will be the previous data received, data
from either the status register or the fault register, or the CS
frame error code ($FE).
The data at DIN is received MSB first and must be valid
before the rising edge of CLK. The 8 bits received at DIN
before CS goes low will be the current command. Table 1
defines the legal 8–bit SPI commands, where d = four data
bits and x = don’t care. All other inputs will be ignored.
Table 2. Status Register Bit Definition
$1x
$2x
VALUE
DESCRIPTION
D7
0
Always Logic zero
D6
0
Always Logic zero
D5
F1
SH1 and SL1 switches active
D4
F2
SH2 and SL2 switches active
D3
SSC
D2
RL
VRES voltage is below trip
D1
BL
VBAT voltage is below trip
D0
CL
CHRG voltage is below trip
Safing Sensor is closed
Read Fault Register – $2x
The $2x command causes the data contained in the fault
register to be sent from DOUT during the next valid CS
frame. The register reports fire path faults by continuously
comparing each path to a portion of the voltage at the VBAT
pin. The fault register is an 8–bit active–high register with
bit definition as shown in Table 3.
Table 1. Valid CS2082 SPI Commands
COMMAND
BIT
FUNCTION
Table 3. Fault Register Bit Definition
Read Staus Register
Read Fault Register
$3d
Squib Resistance Measurements
$4d
Analog MUX Select
$5d
Low Side Switch Control
$6d
Auxiliary Control Register
$Ad
High Side Switch Control
Read Status Register – $1x
The $1x command causes the data contained in the status
register to be sent from DOUT during the next valid CS
frame. The status register reports the condition of the firing
paths, closure detection of an external safing switch between
BIT
VALUE
D7
0
Always Logic zero
D6
0
Always Logic zero
D5
0
Always Logic zero
D4
0
Always Logic zero
D3
SB2
High Side of Sqib 2 above
75% VBAT trip threshold
D2
SB1
High Side of Sqib 1 above
75% VBAT trip threshold
D1
SG2
Low Side of Sqib 2 below
25% VBAT trip threshold
D0
SG1
Low Side of Sqib 1 below
25% VBAT trip threshold
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DESCRIPTION
CS2082
4.5
Each SHx pin is pulled up to VBAT while each SLx pin is
pulled down to GND through separate nominal 10 kΩ
resistors, thus biasing each normal fire path to about 1/2
VBAT. An open fire path has been detected if both the SBx
and SGx bits are set for that path. To detect faults between
fire paths and to test driver function, each driver should be
activated individually. The activated driver should cause its
respective fault bit to be set. If an activated driver does not
set its respective fault bit, a driver fault has been detected. If
an activated driver causes the fault bit of an inactivated
driver to be set, a fault between fire paths has been detected.
Table 4 defines the implied ranges over which the various
types of faults can be detected.
4.0
3.5
VMR
3.0
2.5
2.0
1.5
1.0
0.5
0
0.6
1.4
2.2
3.0
3.8
RSQUIB
4.6
5.4
Figure 2. Typical MR Voltage Response
Table 4. Implied Resistive Fault Detection Ranges
Fault
Min
Nom
Max
Unit
Short to Ground
1
5
10
kΩ
Short to Battery
1
5
10
kΩ
Open
5
20
40
kΩ
Driver Open
1
5
10
kΩ
Driver Shorted
1
5
10
kΩ
Squib to Squib
1
5
10
kΩ
Measurement accuracy of the CS2082 with combined
tolerances and with and external 1% load resistor at the MR
pin can be defined by the equation:
RSQ(E) where VDIFF(IDEAL) and RMR(IDEAL) are the assumed
values for the squib resistance solution algorithm, RSQ(A) is
the actual squib resistance, and RSQ(E) is the result of the
solution algorithm. An additional error may be added if the
MR voltage is measured through the analog multiplexer.
In operation, current is sourced from VBAT to the SHx pin,
through the squib to the SLx pin, and returned to ground
through the MR load resistor. Current clamps are provided
for both the SHx and SLx pins and a voltage clamp is
provided for the MR pin. These clamps along with the
resolution of the ADC are the constraining factors for the
minimum and maximum measurable squib resistance
values.
The minimum measurable squib resistance can be defined
as:
The $3d command activates squib resistance
measurement for the selected firing path. The respective
active–high bit definitions are shown in Table 5. At
power–up, the default path is ‘None.’
Table 5. Squib Resistance Path Select
D2
D1
D0
x
x
0
0
NONE
x
x
0
1
SQUIB 1
x
x
1
0
SQUIB 2
x
x
1
1
NONE
Path
VDIFF(MIN)
VDIFF(MIN) RMR(MIN)
RSQUIB(MIN) ILIM(MAX)
VCLAMP(MAX)
Squib resistance is measured by forcing 50 mV nominal
(proportional to VCC) across the squib. The resulting squib
current is passed to an external load resistor at the MR pin,
converting the current back into a voltage. This voltage may
be read directly at the MR pin, or passed through the analog
multiplexer to be read at the AOUT pin. The known values of
the squib differential voltage (VDIFF) and the MR resistance
(RMR), and the measured MR voltage (VMR) indicate squib
resistance such that:
RSQUIB 1% RMR 1%
RSQ(A)12.5%15.94%
Squib Resistance Measurement – $3d
D3
VDIFF(IDEAL) RMR(IDEAL)
12%
VDIFF
RSQ(A)
The maximum measurable squib resistance can be
defined as:
RSQUIB(MAX) VDIFF(MAX) RMR(MAX) (2n 1)
VCC(MIN)
In the above equations, VDIFF is the SHx–SLx forced
differential voltage, ILIM is the SHx resistive measure
current limit, VCLAMP is the MR clamp voltage, RMR is the
toleranced MR load resistor value and n is the number of bits
of resolution of the ADC.
It should be noted that during resistive measurements,
faults to GND or BAT (dependent on VBAT voltage and
RMR VDIFF
VMR
Typical MR voltage response for RMR = 50 Ω over a squib
resistance range of 0.6 Ω to 6.0 Ω is illustrated in Figure 2.
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CS2082
Table 7. Low Side Switch Select
squib resistance) may be reported by the fault register and
should be ignored.
Power Dissipation during resistive measurement can be
calculated as:
P ISQUIB(VBAT VDIFF) (ISQUIB RMR)
where VBAT is the voltage at the CS2082 VBAT pin and
ISQUIB is the measurement current through the squib. A
typical value for P is 300 mW when VBAT = 13.5,
VDIFF = 50 mV, RSQUIB = 2.0 Ω and RMR = 49.9 Ω.
The resultant increase in power dissipation will cause a
corresponding increase in die temperature which will cause
a corresponding decrease in time to thermal shutdown of the
CS2082. To minimize the impact of squib resistive
measurements on time to thermal shutdown a 5% duty cycle
is recommended.
D3
D2
D1
D0
x
x
0
0
BOTH
Active
x
x
0
1
SL2
x
x
1
0
SL1
x
x
1
1
NONE
Auxiliary Control Register – $6d
The $6d command selects the VRES Monitoring trip
threshold. The threshold determines when the $1x Status
Register reports VRES = 1. Bit assignment is shown in Table
8. At power–up, default trip is 17 V.
Table 8. VRES Monitor Trip Select
D3
D2
D1
D0
Trip
Analog MUX – $4d
x
x
x
0
17 V
The $4d command selects one of five states at the AOUT
pin. The states are: High–Z; MR voltage; AIN voltage;
proportion of VBAT; proportion of VRES. The active–high
Analog Mux select register bit definitions are shown in
Table 6. All other states will be interpreted as High–Z. At
power–up, the default state is ‘High–Z.’
x
x
x
1
23 V
High Side Switch Control – $Ad
The $Ad command activates the high side switches. When
a data bit is high, that switch is turned on. More than one
switch can be activated at a time. Bit assignment is shown in
Table 9. Note that the $5d and $Ad commands are binary
complements, i.e., by sending 1010xx11, both high side
switches are activated, and by sending the complement
0101xx00, both low side switches are activated. At
power–up, no switches are active.
Table 6. Analog MUX Output Select
D3
D2
D1
D0
State
0
0
0
0
High–Z
0
0
0
1
MR
0
0
1
0
AIN
0
1
0
0
BAT
D3
D2
D1
D0
1
0
0
0
RES
x
x
0
0
NONE
x
x
0
1
SH1
x
x
1
0
SH2
x
x
1
1
BOTH
Table 9. High Side Switch Select
Low Side Switch Control – $5d
The $5d command activates the low side switches. When
a data bit is low that switch is turned on. More than one
switch can be activated at a time. Bit assignment is shown in
Table 7. At power–up, no switches are active.
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Active
CS2082
VIGN
VCC
VBOOST
VBAT
GND
CHRG
+
CDM
CCM
VRES
DIN
VR1
VR2
SH1
SL1
CS2082
CRES
CCM
VCC
SH2
CCM
SL2
CCM
FG1
FG2
DOUT
AIN
CLK
AOUT
CS
MR
CMR
MCU
Figure 3. Application Diagram
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CDM
Analog
Input
+
CRES
CS2082
PACKAGE DIMENSIONS
SO–20L
DW SUFFIX
CASE 751D–05
ISSUE F
A
20
X 45 h
1
10
20X
B
0.25
DIM
A
A1
B
C
D
E
e
H
h
L
B
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
T
C
PACKAGE THERMAL DATA
Parameter
SO–20L
Unit
RΘJC
Typical
17
°C/W
RΘJA
Typical
90
°C/W
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MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
CS2082
Notes
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CS2082
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
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For additional information, please contact your local
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