AD AD8028ARM-REEL7 Low distortion, high speed rail-to-rail input/output amplifier Datasheet

Low Distortion, High Speed
Rail-to-Rail Input/Output Amplifiers
AD8027/AD8028
FEATURES
High speed
190 MHz, –3 dB bandwidth (G = +1)
100 V/µs slew rate
Low distortion
120 dBc @ 1 MHz SFDR
80 dBc @ 5 MHz SFDR
Selectable input crossover threshold
Low noise
4.3 nV/√Hz
1.6 pA/√Hz
Low offset voltage: 900 µV max
Low power: 6.5 mA/amplifier supply current
Power-down mode
No phase reversal: VIN > |VS| + 200 mV
Wide supply range: 2.7 V to 12 V
Small packaging: SOIC-8, SOT-23-6, MSOP-10
APPLICATIONS
Filters
ADC drivers
Level shifting
Buffering
Professional video
Low voltage instrumentation
CONNECTION DIAGRAMS
SOT-23-6
(RT)
SOIC-8
(R)
NC 1
8
DISABLE/SELECT
–IN 2
7
+VS
+IN 3
6
VOUT
–VS 4
5
NC
VOUT 1
–VS 2
+
+IN 3
NC = NO CONNECT
SOIC-8
(R)
–
+IN A 3
+
–VS 4
+VS
5
DISABLE/SELECT
4
–IN
MSOP-10
(RM)
VOUTA 1
–IN A 2
–
6
VOUTA 1
8
+VS
7
VOUTB
–IN A 2
–
10 +VS
+
6
–IN B
+IN A 3
+
–
5
+IN B
–VS 4
9
VOUTB
–
8
–IN B
+
7
+IN B
6
DISABLE/SELECT B
DISABLE/SELECT A 5
03327-B-001
Figure 1. Connection Diagrams (Top View)
With its wide supply voltage range (2.7 V to 12 V) and wide
bandwidth (190 MHz), the AD8027/AD8028 amplifier is
designed to work in a variety of applications where speed and
performance are needed on low supply voltages. The high performance of the AD8027/AD8028 is achieved with a quiescent
current of only 6.5 mA/amplifier typical. The AD8027/AD8028
has a shut down mode that is controlled via the SELECT pin.
The AD8027/AD8028 is available in SOIC-8, MSOP-10, and
SOT-23-6 packages. They are rated to work over the industrial
temperature range of –40°C to +125°C.
–20
GENERAL DESCRIPTION
The AD8027/AD80281 is a high speed amplifier with rail-torail input and output that operates on low supply voltages and
is optimized for high performance and wide dynamic signal
range. The AD8027/AD8028 has low noise (4.3 nV/√Hz,
1.6 pA/√Hz) and low distortion (120 dBc @ 1 MHz). In applications that use a fraction of or the entire input dynamic range
and require low distortion, the AD8027/AD8028 is an ideal
choice.
G = +1
FREQUENCY = 100kHz
RL = 1kΩ
–40
–60
VS = +5V
SFDR (dB)
VS = +3V
VS = ±5V
–80
–100
–120
Many rail-to-rail input amplifiers have an input stage that
switches from one differential pair to another as the input signal crosses a threshold voltage, which causes distortion. The
AD8027/AD8028 has a unique feature that allows the user to
select the input crossover threshold voltage through the
SELECT pin. This feature controls the voltage at which the
complementary transistor input pairs switch. The AD8027/
AD8028 also has intrinsically low crossover distortion.
–140
0
1
2
3
4
5
6
7
OUTPUT VOLTAGE (V p-p)
8
9
10
03327-A-063
Figure 2. SFDR vs. Output Amplitude
1
Protected by U.S. patent numbers 6,486,737B1; 6,518,842B1
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2003 Analog Devices, Inc. All rights reserved.
AD8027/AD8028
TABLE OF CONTENTS
Specifications..................................................................................... 3
Wideband Operation ..................................................................... 18
Absolute Maximum Ratings............................................................ 6
Circuit Considerations .............................................................. 19
Maximum Power Dissipation ..................................................... 6
Applications..................................................................................... 20
Typical Performance Characteristics ............................................. 7
Using the AD8027/AD8028 SELECT Pin ............................... 20
Theory of Operation ...................................................................... 16
Driving a 16-Bit ADC ................................................................ 20
Input Stage................................................................................... 16
Band-Pass Filter.......................................................................... 21
Crossover Selection .................................................................... 16
Design Tools and Technical Support ....................................... 21
Output Stage................................................................................ 17
Outline Dimensions ....................................................................... 22
DC Errors .................................................................................... 17
Ordering Guide .......................................................................... 23
REVISION HISTORY
Revision B:
10/03—Data Sheet changed from Rev. A to Rev. B
Changes to Figure 1...........................................................................1
Revision A:
8/03—Data Sheet changed from Rev. 0 to Rev. A
Addition of AD8028........................................................... Universal
Changes to GENERAL DESCRIPTION.........................................1
Changes to Figures 1, 3, 4, 8, 13, 15, 17............................ 1, 6, 7, 8, 9
Changes to Figures 58, 60 .........................................................18, 20
Changes to SPECIFICATIONS........................................................3
Updated OUTLINE DIMENSIONS .............................................22
Updated ORDERING GUIDE.......................................................23
Revision 0: Initial Version
Rev. B | Page 2 of 24
AD8027/AD8028
SPECIFICATIONS
Table 1. VS = ±5 V (@ TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Crosstalk, Output to Output
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current1
Input Bias Current1
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Impedance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
SELECT PIN
Crossover Low—Selection Input Voltage
Crossover High—Selection Input Voltage
Disable Input Voltage
Disable Switching Speed
Enable Switching Speed
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
Short Circuit Output
Off Isolation
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1
Conditions
Min
Typ
G = +1, VO= 0.2 V p-p
G = +1, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, VO = 2 V Step/G = –1, VO = 2 V Step
G = +2, VO = 2 V Step
138
20
190
32
16
90/100
35
MHz
MHz
MHz
V/µs
ns
fC = 1 MHz, VO = 2 V p-p, RF = 24.9 Ω
fC = 5 MHz, VO = 2 V p-p, RF = 24.9 Ω
f = 100 kHz
f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
G = +1, RL =100 Ω, VOUT = 2 V p-p,
VS = ±5 V @ 1 MHz
120
80
4.3
1.6
0.1
0.2
–93
dBc
dBc
nV/√Hz
pA/√Hz
%
Degree
dB
SELECT = Tri-State or Open, PNP Active
SELECT = High NPN Active
TMIN to TMAX
VCM = 0 V, NPN Active
TMIN to TMAX
VCM = 0 V, PNP Active
TMIN to TMAX
100
200
240
1.50
4
4
–8
–8
±0.1
110
90
6
2
–5.2 to +5.2
110
MΩ
pF
V
dB
–3.3 to +5
–3.9 to –3.3
–5 to –3.9
980
45
V
V
V
ns
ns
40/45
ns
VO = ±2.5 V
VCM = ±2.5 V
Tri-State < ±20 µA
50% of Input to <10% of Final VO
VI = +6 V to –6 V, G = –1
–VS + 0.10
Sinking and Sourcing
VIN = 0.2 V p-p, f = 1 MHz, SELECT = Low
30% Overshoot
+VS – 0.06,
–VS + 0.06
120
–49
20
2.7
SELECT = Low
VS ± 1 V
90
No sign or a plus indicates current into pin, minus indicates current out of pin.
Rev. B | Page 3 of 24
6.5
370
110
Max
800
900
6
–11
±0.9
+VS – 0.10
Unit
µV
µV
µV/°C
µA
µA
µA
µA
µA
dB
V
mA
dB
pF
12
8.5
500
V
mA
µA
dB
AD8027/AD8028
SPECIFICATIONS
Table 2. VS = +5 V (@ TA = 25°C, RL = 1 kΩ to midsupply, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Crosstalk, Output to Output
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current1
Input Bias Current1
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Impedance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
SELECT PIN
Crossover Low—Selection Input Voltage
Crossover High—Selection Input Voltage
Disable Input Voltage
DISABLE Switching Speed
Enable Switching Speed
OUTPUT CHARACTERISTICS
Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
Off Isolation
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1
Conditions
Min
Typ
G = +1, VO = 0.2 V p-p
G = +1, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, VO = 2 V Step/G = –1, VO = 2 V Step
G = +2, VO = 2 V Step
131
18
185
28
12
85/100
40
MHz
MHz
MHz
V/µs
ns
fC = 1 MHz, VO = 2 V p-p, RF = 24.9 Ω
fC = 5 MHz, VO = 2 V p-p, RF = 24.9 Ω
f = 100 kHz
f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
G = 1, RL = 100 Ω, VOUT = 2 V p-p,
VS = ±5 V @ 1 MHz
90
64
4.3
1.6
0.1
0.2
–92
dBc
dBc
nV/√Hz
pA/√Hz
%
Degree
dB
SELECT = Tri-State or Open, PNP Active
SELECT = High NPN Active
TMIN to TMAX
VCM = 2.5 V, NPN Active
TMIN to TMAX
VCM = 2.5 V, PNP Active
TMIN to TMAX
96
200
240
2
4
4
–8
–8
±0.1
105
90
6
2
–0.2 to +5.2
105
MΩ
pF
V
dB
1.7 to 5
1.1 to 1.7
0 to 1.1
1100
50
V
V
V
ns
ns
50/50
ns
VO = 1 V to 4 V
VCM = 0 V to 2.5 V
Tri-State < ±20 µA
50% of Input to <10% of Final VO
VI = –1 V to +6 V, G = –1
RL = 1 kΩ
–VS + 0.08
VIN = 0.2 V p-p, f = 1 MHz, SELECT = Low
Sinking and Sourcing
30% Overshoot
+VS – 0.04,
–VS + 0.04
–49
105
20
2.7
SELECT = Low
VS ± 1 V
No sign or a plus indicates current into pin, minus indicates current out of pin.
Rev. B | Page 4 of 24
90
6
320
105
Max
800
900
6
–11
±0.9
+VS – 0.08
Unit
µV
µV
µV/°C
µA
µA
µA
µA
µA
dB
V
dB
mA
pF
12
8.5
450
V
mA
µA
dB
AD8027/AD8028
SPECIFICATIONS
Table 3. VS = +3 V (@ TA = 25°C, RL = 1 kΩ to midsupply, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Crosstalk, Output to Output
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current1
Input Bias Current1
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Impedance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
SELECT PIN
Crossover Low—Selection Input Voltage
Crossover High—Selection Input Voltage
Disable Input Voltage
DISABLE Switching Speed
Enable Switching Speed
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
Short Circuit Current
Off Isolation
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1
Conditions
Min
Typ
G = +1, VO = 0.2 V p-p
G = +1, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, VO = 2 V Step/G = –1, VO = 2 V Step
G = +2, VO = 2 V Step
125
19
180
29
10
73/100
48
MHz
MHz
MHz
V/µs
ns
fC = 1 MHz, VO = 2 V p-p, RF = 24.9 Ω
85
dBc
fC = 5 MHz, VO = 2 V p-p, RF = 24.9 Ω
f = 100 kHz
f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
G = 1, RL = 100 Ω, VOUT = 2 V p-p,
VS = 3 V @ 1 MHz
64
dBc
4.3
1.6
0.15
0.20
–89
nV/√Hz
pA/√Hz
%
Degree
dB
SELECT = Tri-State or Open, PNP Active
SELECT = High NPN Active
TMIN to TMAX
VCM = 1.5 V, NPN Active
TMIN to TMAX
VCM = 1.5 V, PNP Active
TMIN to TMAX
VO = 1 V to 2 V
RL = 1 kΩ
VCM = 0 V to 1.5 V
90
88
6
2
–0.2 to +3.2
100
MΩ
pF
V
dB
1.7 to 3
1.1 to 1.7
0 to 1.1
1150
50
V
V
V
ns
ns
55/55
ns
50% of Input to <10% of Final VO
VI = –1 V to +4 V, G = –1
–VS + 0.07
Sinking and Sourcing
VIN = 0.2 V p-p, f = 1 MHz, SELECT = Low
30% Overshoot
+VS – 0.03,
–VS + 0.03
72
–49
20
2.7
SELECT = Low
VS ± 1 V
88
No sign or a plus indicates current into pin, minus indicates current out of pin.
Rev. B | Page 5 of 24
6.0
300
100
800
900
Unit
200
240
2
4
4
–8
–8
±0.1
100
Tri-State < ±20 µA
RL = 1 kΩ
Max
6
–11
±0.9
+VS – 0.07
µV
µV
µV/°C
µA
µA
µA
µA
µA
dB
V
mA
dB
pF
12
8.0
420
V
mA
µA
dB
AD8027/AD8028
ABSOLUTE MAXIMUM RATINGS
PD = Quiescent Power + (Total Drive Power – Load Power )
Table 4.
Rating
12.6 V
See Figure 3
±VS ± 0.5 V
±1.8 V
–65°C to +125°C
–40°C to +125°C
300°C
V V
PD = (VS × I S )+  S × OUT
RL
 2
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Maximum Power Dissipation
The maximum safe power dissipation in the AD8027/AD8028
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die will locally
reach the junction temperature. At approximately 150°C, which
is the glass transition temperature, the plastic will change its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
AD8027/AD8028. Exceeding a junction temperature of 175°C
for an extended period of time can result in changes in the
silicon devices, potentially causing failure.
PD = (VS × I S ) +
(
(VS /4 )2
RL
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS/2.
Airflow will increase heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θJA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in
the board layout section.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8
(125°C/W), SOT-23-6 (170°C/W), and MSOP-10 (130°C/W)
packages on a JEDEC standard 4-layer board.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current
from the AD8027/AD8028 will likely cause catastrophic failure.
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
TJ = TA + PD × θ JA
 VOUT 2
–

RL

RMS output voltages should be considered. If RL is referenced
to VS–, as in single-supply operation, then the total drive power
is VS × IOUT.
)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, then the total drive power is VS/2 × IOUT, some of
which is dissipated in the package and some in the load (VOUT ×
IOUT). The difference between the total drive power and the load
power is the drive power dissipated in the package.
Rev. B | Page 6 of 24
2.0
MAXIMUM POWER DISSIPATION (W)
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
1.5
SOIC-8
1.0
MSOP-10
SOT-23-6
0.5
0
–55
–35
–15
5
25
45
65
85
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation
105
125
03327-A-002
AD8027/AD8028
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions VS = +5 V (TA = +25°C, RL = 1 kΩ, unless otherwise noted.)
2
8
AD8027
G = +1
VOUT = 200mV p-p
G = +2
7 VOUT = 200mV p-p
0
6
–1
5
CLOSED-LOOP GAIN (dB)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
–2
–3
G = +2
–4
AD8028
G = +1
–5
G = +10
–6
–7
G = –1
1
10
FREQUENCY (MHz)
100
–1
–4
0.1
1000
CLOSED-LOOP GAIN (dB)
0
–1
VS = ±5V
–4
–5
–6
–7
–10
0.1
10
FREQUENCY (MHz)
100
–2
–3
–4
–5
–6
–7
VS = +5V
–9
–10
0.1
1000
VS = ±5V
1
03327-A-004
Figure 5. AD8027 Small Signal Frequency Response for Various Supplies
10
FREQUENCY (MHz)
100
1000
03327-A-007
Figure 8. AD8028 Small Signal Frequency Response for Various Supplies
2
8
G = +2
7 VOUT = 2V p-p
G = +1
1 VOUT = 2V p-p
0
6
CLOSED-LOOP GAIN (dB)
VS = ±5V
–1
–2
–3
VS = +3V
–4
–5
–6
–7
–8
1
10
FREQUENCY (MHz)
5
VS = ±5V
4
3
VS = +5V
2
1
0
VS = +3V
–1
–2
VS = +5V
–9
–10
0.1
VS = +3V
–8
VS = +5V
1
1000
03327-A-006
G = +1
1 VOUT = 200mV p-p
0
–3
100
2
VS = +3V
–2
10
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Supplies
–1
–9
1
03327-A-003
G = +1
VS = +3V RF = 24.9Ω
1 VOUT = 200mV p-p
–8
VS = ±5V
0
–3
2
CLOSED- LOOP GAIN (dB)
2
–2
Figure 4. Small Signal Frequency Response for Various Gains
CLOSED-LOOP GAIN (dB)
3
–9
1
VS = +5V
4
–8
–10
0.1
VS = +3V
–3
100
–4
0.1
1000
03327-A-005
Figure 6. Large Signal Frequency Response for Various Supplies
1
10
FREQUENCY (MHz)
100
1000
03327-A-008
Figure 9. Large Signal Frequency Response for Various Supplies
Rev. B | Page 7 of 24
AD8027/AD8028
4
3
G = +1
3 VOUT = 200mV p-p
2
CLOSED-LOOP GAIN (dB)
CL = 5pF
0
–1
–2
–3
CL = 0pF
–4
–5
–6
1
10
FREQUENCY (MHz)
–3
CL = 0pF
–4
–5
–6
–7
100
1000
5
CLOSED-LOOP GAIN (dB)
6
5
4
3
VOUT = 2V p-p
0
–1
–2
–4
0.1
1
3
VOUT = 2.0V p-p
RL = 150Ω
2
1
0
–1
10
FREQUENCY (MHz)
100
–4
0.1
1000
VOUT = 2.0V p-p
RL = 1kΩ
0
CLOSED-LOOP GAIN (dB)
1
0
–1
–2
–40°C
+125°C
–4
–5
+25°C
G = +1
VOUT = 200mV p-p
10
FREQUENCY (MHz)
100
10
FREQUENCY (MHz)
100
1000
03327-A-013
Figure 14. Small Signal Frequency Response for Various RLOAD Values
1
–6
1
03327-A-010
2
1
VOUT = 0.2V p-p
RL = 1kΩ
4
2
–8
0.1
1000
03327-A-012
VOUT = 0.2V p-p
RL = 150Ω
–3
Figure 11. Frequency Response for Various Output Amplitudes
–3
100
–2
VOUT = 4V p-p
–3
G = +2
7
6
1
10
FREQUENCY (MHz)
Figure 13. AD8028 Small Signal Frequency Response for Various CLOAD
VOUT = 200mV p-p
2
1
03327-A-009
8
G = +2
7
CLOSED-LOOP GAIN (dB)
–2
–10
0.1
Figure 10. AD8027 Small Signal Frequency Response for Various CLOAD
CLOSED-LOOP GAIN (dB)
–1
–9
–8
0.1
–7
CL = 5pF
–8
–7
8
CL = 20pF
0
1
CLOSED-LOOP GAIN (dB)
G = +1
2 VOUT = 200mV p-p
1
CL = 20pF
–1
–2
–3
–5
1000
Figure 12. AD8027 Small Signal Frequency Response vs. Temperature
–40°C
–6
–7 G = +1
VOUT = 200mV p-p
–8
0.1
1
03327-A-011
+125°C
–4
+25°C
10
FREQUENCY (MHz)
100
1000
03327-A-014
Figure 15. AD8028 Small Signal Frequency Response vs. Temperature
Rev. B | Page 8 of 24
AD8027/AD8028
2
110
VICM = VS+ – 0.3V
SELECT = HIGH
100
OPEN-LOOP GAIN (dB)
VICM = VS– + 0.2V
SELECT = TRI
–2
–3
–4
VICM = 0V
SELECT = HIGH OR TRI
–5
–6
95
70
PHASE
75
60
50
55
40
35
30
20
15
10
–7
–5
0
–8
0.1
1
10
FREQUENCY (MHz)
100
–10
10
1000
R1
50Ω
VI
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
–25
1G
03327-A-017
Figure 18. Open-Loop Gain and Phase vs. Frequency
100
+
R2
50Ω
U1
+
1/2
AD8028
1/2
AD8028
R3
1kΩ
–
VOUT
–
CROSSTALK = 20log (VOUT/VIN)
–10
100
U2
VOLTAGE NOISE (nV/ Hz)
V1
100
03327-A-015
Figure 16. Small Signal Frequency Response vs.
Input Common-Mode Voltages
–20
–30
–40
–50
10
10
VOLTAGE
CURRENT
–60
–70
–80
B TO A
–90
1
10
A TO B
100
1k
10k
–110
1M
10M
100M
–130
0.01
0.1
1
10
100
FREQUENCY (MHz)
1
1G
03327-A-018
Figure 19. Voltage and Current Noise vs. Frequency
G = +1
VS = 5V
RL = 1kΩ
–120
–140
0.001
100k
FREQUENCY (Hz)
–100
6.9
G = +2
6.8 RL = 150Ω
1000
6.7
03327-A-016
CLOSED-LOOP GAIN (dB)
CROSSTALK (dB)
115
80
0
–1
135
GAIN
90
VICM = VS+ – 0.2V
SELECT = HIGH
1
CLOSED-LOOP GAI (dB)
VICM = VS– + 0.3V
SELECT = TRI
PHASE (Degrees)
G = +1
3 VOUT = 200mV p-p
CURRENT NOISE (pA/ Hz)
4
Figure 17. AD8028 Crosstalk Output to Output
VOUT = 200mV p-p
6.6
6.5
6.4
6.3
6.2
VOUT = 2V p-p
6.1
6.0
5.9
0.1
1
10
FREQUENCY (MHz)
100
Figure 20. 0.1 dB Flatness Frequency Response
Rev. B | Page 9 of 24
1000
03327-A-019
AD8027/AD8028
–20
–20
G = +1 (RF = 24.9Ω)
VOUT = 2.0V p-p
SECOND HARMONIC: SOLID LINE
–40 THIRD HARMONIC: DASHED LINE
–60
DISTORTION (dB)
DISTORTION (dB)
G = +1
VOUT = 2V p-p
RL = 1kΩ
–40
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
VS = +3V
–80
VS = +5V
–100
VS = ±5V
–120
–140
0.1
1
FREQUENCY (MHz)
10
–80
RL = 150Ω
–100
–140
0.1
20
1
FREQUENCY (MHz)
03327-A-020
10
20
03327-A-023
Figure 24. Harmonic Distortion vs. Frequency and Load
–45
G = +1 (RF = 24.9Ω)
FREQUENCY = 100kHz
RL = 1kΩ
–40
–60
–120
Figure 21. Harmonic Distortion vs. Frequency and Supply Voltage
–20
RL = 1kΩ
–55
G = +1 (RF = 24.9Ω)
VOUT = 1.0V p-p @ 2MHz
SELECT = TRI
–60
SELECT = HIGH
VS = +5V
VS = +3V
DISTORTION (dB)
DISTORTION (dB)
–65
VS = ±5V
–80
–100
–75
–85
–95
–105
–120
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
–140
0
1
2
3
4
5
6
7
OUTPUT VOLTAGE (V p-p)
8
9
–115
–60
1.0
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
4.0
4.5
03327-A-024
Figure 25. Harmonic Distortion vs. Input Common-Mode Voltage, VS = +5 V
–50
G = +1 (RF = 24.9Ω)
VOUT = 1.0V p-p @ 100kHz
RL = 1kΩ
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
03327-A-021
Figure 22. Harmonic Distortion vs. Output Amplitude
–50
–125
0.5
10
SELECT = HIGH
SELECT = TRI
–60
G = +1 (RF = 24.9Ω)
VOUT = 1.0V p-p @ 100kHz
VS = +3V
VS = +5V
VS = +5V
–70
–70
DISTORTION (dB)
DISTORTION (dB)
VS = +3V
–80
–90
–100
–110
–140
0.5
–90
–100
–110
–120
–120
–130
–80
–130
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
1.0
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
4.0
–140
0.5
4.5
03327-A-022
Figure 23. Harmonic Distortion vs. Input Common-Mode Voltage,
SELECT = High
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
1.0
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
4.0
4.5
03327-A-025
Figure 26. Harmonic Distortion vs. Input Common-Mode Voltage,
SELECT = Tri-State or Open
Rev. B | Page 10 of 24
AD8027/AD8028
–20
DISTORTION (dB)
VS = +5
VOUT = 2.0V p-p
SECOND HARMONIC: SOLID LINE
–40 THIRD HARMONIC: DASHED LINE
2.5
G = +2
G = +2
2.0 VS = ±2.5V
1.5
VOUT = 4V p-p
VOUT = 2V p-p
1.0
–60
G = +10
0.5
G = +1
–80
0
–0.5
–100
–1.0
–1.5
–120
–2.0
–140
0.1
1
FREQUENCY (MHz)
10
50mV/DIV
20ns/DIV
–2.5
20
03327-A-026
03327-A-029
Figure 30. Large Signal Transient Response, G = +2
Figure 27. Harmonic Distortion vs. Frequency and Gain
0.20
0.15
0.20
G = +1
VS = ± 2.5V
0.15
0.10
0.10
0.05
0.05
0
0
–0.05
–0.05
–0.10
–0.10
CL = 20pF
CL = 5pF
–0.15
–0.15
50mV/DIV
50mV/DIV
20ns/DIV
–0.20
–0.20
03327-A-027
Figure 28. Small Signal Transient Response
2.0
G = +1
VS = ±2.5V
G = +1
VS = ±2.5V
03327-A-030
Figure 31. Small Signal Transient Response with Capacitive Load
4.0
G = –1
3.5
RL = 1kΩ
3.0 V = ±2.5V
S
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
500mV/DIV
–4.0
VOUT = 4V p-p
VOUT = 2V p-p
1.0
0
–1.0
–2.0
500mV/DIV
20ns/DIV
100ns/DIV
03327-A-028
50ns/DIV
03327-A-031
Figure 29. Large Signal Transient Response, G = +1
Figure 32. Output Overdrive Recovery
Rev. B | Page 11 of 24
AD8027/AD8028
–6.5
–7.0
4.0
SELECT = HIGH
3.5 VS = ±5V
3.0
–7.5
VS = +5V
–8.0
SELECT = TRI
2.5
–40
03327-A-032
VS = +3V
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
Figure 33. Input Overdrive Recovery
80
95
–8.5
125
110
03327-A-035
Figure 36. Input Bias Current vs. Temperature
–10
G = +2
–8
VIN (200mV/DIV)
SELECT = TRI
INPUT BIAS CURRENT (µA)
–6
+0.1%
VOUT – 2VIN (2mV/DIV)
–0.1%
–4
–2
VS = +5V
0
VS = ±5V
2
4
VS = +3V
6
SELECT = HIGH
8
5µs/DIV
10
03327-A-033
0
1
Figure 34. Long-Term Settling Time
2
3
4
5
6
7
8
INPUT COMMON-MODE VOLTAGE (V)
9
10
03327-A-036
Figure 37. Input Bias Current vs. Input Common-Mode Voltage
250
VIN (200mV/DIV)
200
VOUT (400mV/DIV)
COUNT = 1780
SELECT HIGH TRI
MEAN
49µV
55µV
STD. DEV 193µV 150µV
SELECT = TRI
VOUT – 2VIN (0.1%/DIV)
FREQUENCY
+0.1%
–0.1%
150
SELECT = HIGH
100
50
20ns/DIV
0
–800
03327-A-034
–600
–400
–200
0
200
400
INPUT OFFSET VOLTAGE (µV)
Figure 35. 0.1% Short-Term Settling Time
Figure 38. Input Offset Voltage Distribution
Rev. B | Page 12 of 24
600
800
03327-A-037
INPUT BIAS CURRENT (SELECT = TRI) (µA)
50ns/DIV
INPUT BIAS CURRENT (SELECT = HIGH) (µA)
4.5
4.0
G = +1
3.5
RL = 1kΩ
3.0 V = ±2.5V
S
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
500mV/DIV
–4.0
AD8027/AD8028
360
270
VS = +3V
340
320
250
280
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
300
SELECT = TRI
260
VS = ±5V
240
VS = +3V
220
SELECT = HIGH
200
180
VS = +5V
160
140
120
100
SELECT = HIGH
230
210
SELECT = TRI
190
170
80
60
–40
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
150
125
0
03327-A-038
0.50
1.00
1.50
2.00
2.50
INPUT COMMON-MODE VOLTAGE (V)
3.00
03327-A-041
Figure 42. Input Offset Voltage vs. Input Common-Mode Voltage, VS = +3
Figure 39. Input Offset Voltage vs. Temperature
120
290
VS = ±5V
100
SELECT = HIGH
250
80
230
CMRR (dB)
INPUT OFFSET VOLTAGE (µV)
270
210
SELECT = TRI
60
40
190
20
170
150
–5
–4
–3
–2
–1
0
1
2
3
INPUT COMMON-MODE VOLTAGE (V)
4
0
1k
5
10k
100k
1M
FREQUENCY (Hz)
03327-A-039
10M
100M
03327-A-042
Figure 43. CMRR vs. Frequency
Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage, VS = ±5
290
0
VS = +5V
–10
270
250
–30
SELECT = HIGH
–40
230
PSSR (dB)
INPUT OFFSET VOLTAGE (µV)
–20
210
SELECT = TRI
190
–PSRR
–50
+PSRR
–60
–70
–80
–90
170
–100
150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
INPUT COMMON-MODE VOLTAGE (V)
4.5
–110
100
5.0
03327-A-040
Figure 41. Input Offset Voltage vs. Input Common-Mode Voltage, VS = +5
Rev. B | Page 13 of 24
1k
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 44. PSRR vs. Frequency
100M
1G
03327-A-043
AD8027/AD8028
–20
45
OUTPUT SATURATION VOLTAGE (mV)
VIN = 0.2V p-p
G = +1
–30 SELECT = LOW
OFF ISOLATION (dB)
–40
–50
–60
–70
–80
–90
–100
10k
100k
1M
10M
FREQUENCY (Hz)
100M
VS+ – VOH
30
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
100
VOL – VS–
VS = +3V
0
VS = +5V VS = ±5V
–50
95
110
125
03327-A-047
130
120
50
80
Figure 48. Output Saturation Voltage vs. Temperature
OPEN-LOOP GAIN (dB)
OUTPUT SATURATION VOLTAGE (mV)
VOL – VS–
35
03327-A-044
LOAD RESISTANCE TIED
TO MIDSUPPLY
150
40
25
–40
1G
Figure 45. Off Isolation vs. Frequency
200
VS = +5V
RL = 1kΩ TIED TO MIDSUPPLY
VOH – VS+
–100
±5V
110
+5V
100
+3V
90
80
70
–150
–200
100
1000
LOAD RESISTANCE (Ω)
60
10000
0
10
20
03327-A-045
Figure 46. Output Saturation Voltage vs. Output Load
30
ILOAD (mA)
40
50
60
03327-A-048
Figure 49. Open-Loop Gain vs. Load Current
100
1M
SELECT = LOW
100k
1
OUTPUT IMPEDANCE (Ω)
OUTPUT IMPEDANCE (Ω)
10
G = +5
0.1
G = +2
G = +1
0.01
0.001
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
10k
1k
100
10
100k
1G
03327-A-046
Figure 47. Output Enabled— Impedance vs. Frequency
1M
10M
FREQUENCY (Hz)
100M
1G
03327-A-049
Figure 50. Output Disabled—Impedance vs. Frequency
Rev. B | Page 14 of 24
AD8027/AD8028
80
SELECT PIN (–2.0V TO –0.5V)
60
VS = +10V
@ +25°C
40
1.0
+25°C
20
OUTPUT VOLTAGE (V)
SELECT CURRENT (µA)
1.5
+125°C
VS = +5V
–40°C
0
–20
–40
–80
0.5
0
0.5
1.0
1.5
2.0
SELECT VOLTAGE (V)
2.5
RL = 100Ω
0
RL = 1kΩ
–0.5
RL = 10kΩ
–1.0
–60
OUTPUT
G = –1
VS = ±2.5V
VIN = –1.0V
–1.5
0.5 1
3.0
4
5
6
7
8
9
10
03327-A-052
Figure 53. Disable Turn-Off Timing
9.0
1.5
SELECT PIN (–2.0V TO –0.5V)
8.5
1.0
8.0
SUPPLY CURRENT (mA)
OUTPUT
OUTPUT VOLTAGE (V)
3
TIME (µs)
Figure 51. SELECT Pin Current vs.
SELECT Pin Voltage and Temperature
0.5
RL = 100Ω
0
RL = 1kΩ
–0.5
RL = 10kΩ
7.5
VS = ±5V
7.0
VS = +5V
6.5
VS = +3V
6.0
5.5
5.0
–1.0
–1.5
2
03327-A-050
G = –1
VS = ±2.5V
VIN = –1.0V
0
50
100
150
TIME (ns)
Figure 52. Enable Turn-On Timing
200
4.5
4.0
–40
250
03327-A-051
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
125
03327-A-053
Figure 54. Quiescent Supply Current vs. Supply Voltage and Temperature
Rev. B | Page 15 of 24
AD8027/AD8028
THEORY OF OPERATION
the positive rail. Both input pairs are protected from differential
input signals above 1.4 V by four diodes across the input (see
Figure 55). In the event of differential input signals that exceed
1.4 V, the diodes will conduct and excessive current will flow
through them. A series input resistor should be included to limit
the input current to 10 mA.
The AD8027/AD8028 is a rail-to-rail input and output amplifier
designed in Analog Devices XFCB process. The XFCB process
enables the AD8027/AD8028 to run on 2.7 V to 12 V supplies
with 190 MHz of bandwidth and over 100 V/µs of slew rate. The
AD8027/AD8028 has 4.3 nV/√Hz of wideband noise with
17 nV/√Hz noise at 10 Hz. This noise performance, with an
offset and drift performance of less than 900 µV maximum and
1.5 µV/°C typical, respectively, makes the AD8027/AD8028
ideal for high speed precision applications. Additionally, the
input stage operates 200 mV beyond the supply rails and shows
no phase reversal. The amplifier features overvoltage protection
on the input stage. Once the inputs exceed the supply rails by
0.7 V, ESD protection diodes will turn on, drawing excessive
current through the differential input pins. A series input resistor should be included to limit the input current to less than
10 mA.
Crossover Selection
A new feature available on the AD8027/AD8028, which is called
Crossover Selection, allows the user to choose the crossover
point between the PNP/NPN differential pairs. Although the
crossover region is small, operating in this region should be
avoided since it can introduce offset and distortion to the output signal. To help avoid operating in the crossover region, the
AD8027/AD8028 allows the user to select from two preset
crossover locations (i.e., voltage levels) using the SELECT pin.
Looking at the schematic in Figure 55, the crossover region is
about 200 mV and is defined by the voltage level at the base of
Q5. Internally, two separate voltage sources are created approximately 1.2 V from either rail. One or the other is connected to
Q5 based on the voltage applied to the SELECT pin. This allows
for either dominant PNP pair operation, when the SELECT pin
is left open, or dominant NPN pair operation, when the
SELECT pin is pulled high. This pin also provides the traditional power-down function when it is pulled low. This allows
the designer to achieve the best precision and ac performance
for high-side and low-side signal applications. See Figure 50
through Figure 53 for SELECT pin characteristics.
Input Stage
The rail-to-rail input performance is achieved by operating
complementary input pairs. Which pair is on is determined by
the common-mode level of the differential input signal. Looking at the schematic in Figure 55, a tail current (ITAIL) is generated that sources the PNP differential input structure consisting
of Q1 and Q2. A reference voltage is generated internally that is
connected to the base of Q5. This voltage is continually compared against the common-mode input voltage. When the
common-mode level exceeds the internal reference voltage, Q5
diverts the tail current (ITAIL) from the PNP input pair to a current mirror that sources the NPN input pair consisting of Q3
and Q4. The NPN input pair can now operate 200 mV above
VCC
+
ITAIL
1.2V
–
VOUTP
ICMFB
Q5
VSEL
VP
Q3
Q1
Q2
Q4
VN
VEE
LOGIC
VCC
ICMFB
+
1.2V
–
VEE
03327-A-054
Figure 55. Simplified Input Stage
Rev. B | Page 16 of 24
VOUTN
AD8027/AD8028
In the event that the crossover region cannot be avoided, specific attention has been given to the input stage to ensure constant transconductance and minimal offset in all regions of
operation. The regions are: PNP input pair running, NPN input
pair running, and both running at the same time (in the
200 mV crossover region). Maintaining constant transconductance in all regions ensures the best wideband distortion performance when going between these regions. With this technique, the AD8027/AD8028 can achieve greater than 80 dB
SFDR for a 2 V p-p, 1 MHz, G = +1 signal on ±1.5 V supplies.
Another requirement in achieving this level of distortion is the
offset of each pair must be laser trimmed to achieve greater
than 80 dB SFDR, even for low frequency signals.
Output Stage
The AD8027/AD8028 uses a common-emitter output structure
to achieve rail-to-rail output capability. The output stage is
designed to drive 50 mA of linear output current, 40 mA within
200 mV of the rail, and 2.5 mA within 35 mV of the rail.
Loading of the output stage, including any possible feedback
network, will lower the open-loop gain of the amplifier. Refer to
Figure 49 for the loading behavior. Capacitive load can degrade
the phase margin of the amplifier. The AD8027/AD8028 can
drive up to 20 pF, G = +1 as seen in Figure 10. A small (25 Ω to
50 Ω) series resistor (RSNUB) should be included if the capacitive
load is to exceed 20 pF for a gain of 1. Increasing the closedloop gain will increase the amount of capacitive load that can be
driven before a series resistor will need to be included.
DC Errors
(
)
 R + RF
VDIS = VOS, PNP − VOS, NPN ×  G
 RG




Using the crossover select feature of the AD8027/AD8028 helps
to avoid this region. In the event that the region cannot be
avoided, the quantity (VOS, PNP – VOS, NPN) is trimmed to minimize
this effect.
Because the input pairs are complementary, the input bias
current will reverse polarity when going through the cross
over region shown in Figure 37. The offset between pairs is
described by
(
)
  R + RF 

 − RF 
VOS,PNP − VOS,NPN = I B, PNP − I B, NPN × RS  G

  RG 

IB, PNP is the input bias current of either input when the PNP
input pair is active, and IB, NPN is the input bias current or either
input pair when the NPN pair is active. If RS is sized so that
when multiplied by the gain factor it equals RF, this effect will be
eliminated. It is strongly recommended to balance the impedances in this manner when traveling through the crossover
region to minimize the dc error and distortion. As an example,
assuming the PNP input pair has an input bias current of 6 µA
and the NPN input pair has an input bias current of –2 µA, a
200 µV shift in offset will occur when traveling through the
crossover region with RF equal to 0 Ω and RS equal to 25 Ω.
In addition to the input bias current shift between pairs, each
input pair has an input bias current offset that will contribute to
the total offset in the following manner
The AD8027/AD8028 uses two complementary input stages to
achieve rail-to-rail input performance, as mentioned in the
Input Stage section. To use the dc performance over the entire
common-mode range, the input bias current and input offset
voltage of each pair must be considered.
 R + RF
∆VOS = I B + RS  G
 RG

 − I B − RF


Referring to Figure 56, the output offset voltage of each pair is
calculated by
 R + RF
VOS , PNP ,OUT = VOS , PNP  G
 RG

,


 R + RF
VOS , NPN ,OUT = VOS , NPN  G
 RG




RF
RG
+
VOS
+V
–
IB–
–
where the difference of the two will be the discontinuity experienced when going through the crossover region. The size of the
discontinuity is defined as
Rev. B | Page 17 of 24
VI
+
RS
–
SELECT
+
IB+
VOUT
+
–
AD8027/
AD8028
–V
03327-A-055
Figure 56. Op Amp DC Error Sources
AD8027/AD8028
WIDEBAND OPERATION
CF
Voltage feedback amplifiers can use a wide range of resistor
values to set their gain. Proper design of the application’s feedback network requires consideration of the following issues:
•
•
RF
+V
Poles formed by the amplifier’s input capacitances
with the resistances seen at the amplifier’s input
terminals
VIN
Effects of mismatched source impedances
Resistor value impact on the application’s voltage noise
•
Amplifier loading effects
With a wide bandwidth of over 190 MHz, the AD8027/AD8028
has numerous applications and configurations. The
AD8027/AD8028 shown in Figure 57 is configured as a noninverting amplifier. The inverting configuration is shown in
Figure 58 and an easy selection table of gain, resistor values,
bandwidth, slew rate, and noise performance is presented in
Table 5.
VIN
Noise Gain
(Noninverting)
1
2
10
–
+
VOUT
C3
10µF
SELECT
C4
0.1µF
R1 = RF||RG
–V
R1
C4
0.1µF
03327-A-057
Table 5. Component Values, Bandwidth, and Noise
Performance (VS = ±2.5 V)
C1
0.1µF
AD8027/
AD8028
C3
10µF
SELECT
Figure 58. Wideband Inverting Gain Configuration
C2
10µF
R1
VOUT
–V
RF
RG
–
+
C5
The AD8027/AD8028 has an input capacitance of 2 pF. This
input capacitance will form a pole with the amplifier’s feedback
network, destabilizing the loop. For this reason, it is generally
desirable to keep the source resistances below 500 Ω, unless
some capacitance is included in the feedback network. Likewise,
keeping the source resistances low will also take advantage of
the AD8027/AD8028’s low input referred voltage noise of
4.3 nV/√Hz.
C2
10µF
AD8027/
AD8028
R1 = RF||RG
•
+V
RG
C1
0.1µF
03327-A-056
Figure 57. Wideband Noninverting Gain Configuration
Rev. B | Page 18 of 24
RSOURCE
(Ω)
50
50
50
RF
(Ω)
0
499
499
RG
(Ω)
N/A
499
54.9
–3 dB
SS BW
(MHz)
190
95
13
Output
Noise with
Resistors
(nV/√Hz)
4.4
10
45
AD8027/AD8028
Circuit Considerations
BALANCED INPUT IMPEDANCES
Balanced input impedances can help improve distortion performance. When the amplifier transitions from PNP pair to
NPN pair operation, a change in both the magnitude and direction of the input bias current will occur. When multiplied times
imbalanced input impedances, a change in offset will result. The
key to minimizing this distortion is to keep the input impedances balanced on both inputs. Figure 59 shows the effect of the
imbalance and degradation in distortion performance for a
50 Ω source impedance, with and without a 50 Ω balanced feedback path.
–20
G = +1
VOUT = 2V p-p
–30 RL = 1kΩ
VS = +3V
DISTORTION (dB)
–50
–60
RF = 0Ω
RF = 24.9Ω
–80
–90
To minimize parasitic inductances and ground loops in high
speed, densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the
parasitic inductances and thus the high frequency impedance of
the path. Fast current changes in an inductive ground return
will create unwanted noise and ringing.
POWER SUPPLY BYPASSING
RF = 49.9Ω
–100
0.1
GROUNDING
The length of the high frequency bypass capacitor pads and
traces is critical. A parasitic inductance in the bypass grounding
will work against the low impedance created by the bypass
capacitor. Because load currents flow from supplies as well as
ground, the load should be placed at the same physical location
as the bypass capacitor ground. For large values of capacitors,
which are intended to be effective at lower frequencies, the current return path length is less critical.
–40
–70
On multilayer boards, all layers underneath the op amp should
be cleared of metal to avoid creating parasitic capacitive
elements. This is especially true at the summing junction (i.e.,
the –input). Extra capacitance at the summing junction can
cause increased peaking in the frequency response and lower
phase margin.
1
FREQUENCY (MHz)
10
Power supply pins are actually inputs and care must be taken to
provide a clean, low noise dc voltage source to these inputs. The
bypass capacitors have two functions:
20
03327-A-058
Figure 59. SFDR vs. Frequency and Various RF
PCB LAYOUT
As with all high speed op amps, achieving optimum performance from the AD8027/AD8028 requires careful attention to
PCB layout. Particular care must be exercised to minimize lead
lengths of the bypass capacitors. Excess lead inductance can
influence the frequency response and even cause high frequency oscillations. The use of a multilayer board, with an
internal ground plane, will reduce ground noise and enable a
tighter layout.
To achieve the shortest possible lead length at the inverting
input, the feedback resistor, RF, should be located beneath the
board and span the distance from the output, Pin 6, to the input,
Pin 2. The return node of the resistor RG should be situated as
closely as possible to the return node of the negative supply
bypass capacitor connected to Pin 4.
1.
Provide a low impedance path for unwanted frequencies
from the supply inputs to ground, thereby reducing the
effect of noise on the supply lines.
2.
Provide sufficient localized charge storage, for fast
switching conditions and minimizing the voltage drop at
the supply pins and the output of the amplifier. This is
usually accomplished with larger electrolytic capacitors.
Decoupling methods are designed to minimize the bypassing
impedance at all frequencies. This can be accomplished with a
combination of capacitors in parallel to ground.
Good quality ceramic chip capacitors should be used and
always kept as close to the amplifier package as possible. A parallel combination of a 0.01 µF ceramic and a 10 µF electrolytic
covers a wide range of rejection for unwanted noise. The 10 µF
capacitor is less critical for high frequency bypassing, and in
most cases, one per supply line is sufficient.
Rev. B | Page 19 of 24
AD8027/AD8028
APPLICATIONS
Using the AD8027/AD8028 SELECT Pin
The AD8027/AD8028 features a unique SELECT pin with two
functions. The first is a power-down function that places the
AD8027/AD8028 into low power consumption mode. In the
power-down mode, the amplifier draws 450 µA (typ) of supply
current.
The second function, as mentioned in the Theory of Operation
section, shifts the crossover point (where the NPN/PNP input
differential pairs transition from one to the other) closer to
either the positive supply rail or the negative supply rail. This
selectable crossover point allows the user to minimize
distortion based on the input signal and environment. The
default state is 1.2 V from the positive power supply, with the
SELECT pin left floating or in tri-state.
other than the single 5 V supply already used by the ADC.
In this application, the SELECT pins are biased to avoid the
crossover region of the AD8028 for low distortion
operation.
+5V
0.1µF
–
ANALOG INPUT +
INPUT RANGE
(0.15V TO 2.65V)
+
2.7nF
4MHz LPF
03327-A-059
Figure 60. Unity Gain Differential Drive
1.7 to 5.0
1.7 to 3.0
When the input stage transitions from one input differential
pair to the other, there is virtually no noticeable change in the
output waveform.
As seen in Figure 61, the AD8028 and AD7677 combination
offers excellent integral nonlinearity (INL). Summary test data
for the schematic shown in Figure 60 is presented in Table 8.
Table 8. ADC Driver Performance,
fC = 100 kHz, VOUT = 4.7 V p-p
Parameter
Second Harmonic Distortion
Third Harmonic Distortion
THD
SFDR
The disable time of the AD8027/AD8028 amplifier is load
dependent. Typical data is presented in Table 7. See Figure 52
and Figure 53 for the actual switching measurements.
Measurement
–105dB
–102dB
–102 dB
105 dBc
1.0
Table 7. DISABLE Switching Speeds
0.5
+3 V
50 ns
1150 ns
INL (LSB)
tON
tOFF
16 BITS
15Ω
SELECT
(OPEN)
SELECT Pin Voltage (V)
VS = ±5 V
VS = +5 V VS = +3 V
–5 to –4.2
0 to 0.8
0 to 0.8
–4.2 to –3.3 0.8 to 1.7 0.8 to 1.7
Supply Voltages (RL = 1 kΩ)
±5 V
+5 V
45 ns
50 ns
980 ns
1100 ns
AD7677
0.1µF
AD8028
Table 6. SELECT Pin Mode Control
–3.3 to +5
SELECT
(OPEN)
–
ANALOG INPUT –
4MHz LPF +5V
2.7nF
+
+5V
Table 6 shows the required voltages and modes of the
SELECT pin.
Mode
Disable
Crossover Referenced
–1.2 V to Positive Supply
Crossover Referenced
+1.2 V to Negative Supply
15Ω
AD8028
0
–0.5
Driving a 16-Bit ADC
With the adjustable crossover distortion selection point and low
noise, the AD8028 is an ideal amplifier for driving or buffering
input signals into high resolution ADCs, such as the AD7677, a
16-Bit, 1 LSB INL, 1 MSPS differential ADC. Figure 60 shows
the typical schematic for driving the ADC. The AD8028
driving the AD7677 offers performance close to non-rail-torail amplifiers and avoids the need for an additional supply,
Rev. B | Page 20 of 24
–1.0
0
16384
32768
CODE
49152
Figure 61. Integral Nonlinearity
65536
03327-A-060
AD8027/AD8028
Band-Pass Filter
CH1 S21 LOG
In communication systems, active filters are used extensively in
signal processing. The AD8027/AD8028 is an excellent choice
for active filter applications. In realizing this filter, it is important that the amplifier has a large signal bandwidth of at least
10× the center frequency, fO. Otherwise, a phase shift can occur
in the amplifier, causing instability and oscillations.
0.1
The test data shown in Figure 63 indicates that this design
yielded a filter response with a center frequency fO = 1 MHz and
a bandwidth of 450 kHz.
f O (MHz)
C2 = 0.5C1
R1 = 2/k, R2 = 2/(3k), R3 = 4/k
H = 1/3(6.5 – 1/Q)
Figure 63. Band-Pass Filter Response
R5 = R4/(H – 1)
+5
R2
105Ω
C1
1000pF
C3
0.1µF
+
C2
500pF
10
03327-A-062
Analog Devices is committed to simplifying the design process
by providing technical support and online design tools. We offer
technical support via free evaluation boards, sample ICs, interactive evaluation tools, data sheets, spice models, application
notes, phone and email support, all of which are available at
www. analog.com.
k = 2πfOC1
VIN
1
FREQUENCY – MHz
Design Tools and Technical Support
Pass Band (MHz)
R1
316Ω
1:6.3348dB 1.00 000MHz
1
In the schematic shown in Figure 62, the AD8027/AD8028 is
configured as a 1 MHz band-pass filter. The target specifications
are fO = 1 MHz and a –3 dB pass band of 500 kHz. Start the
design by selecting the following: fO, Q, C1, and R4. Then using
the equations shown below, calculate the remaining variables.
Q=
5dB/REF 6.342dB
R3
634Ω
AD8027/
AD8028
VOUT
SELECT
–
C4
–5 0.1µF
R5
523Ω
R4
523Ω
03327-A-061
Figure 62. Band-Pass Filter Schematic
Rev. B | Page 21 of 24
AD8027/AD8028
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
4.00 (0.1574)
3.80 (0.1497) 1
6.20 (0.2440)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.50 (0.0196)
× 45°
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 64. 8-Lead Standard Small Outline Package, Narrow Body [SOIC]
(R-8)
Dimensions shown in millimeters and (inches)
2.90 BSC
6
5
4
1
2
3
2.80 BSC
1.60 BSC
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.50
0.30
0.15 MAX
0.22
0.08
10°
4°
0°
SEATING
PLANE
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178AB
Figure 65. 6-Lead Plastic Surface-Mount Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
3.00 BSC
10
6
4.90 BSC
3.00 BSC
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
0.15
0.00
1.10 MAX
0.27
0.17
SEATING
PLANE
0.23
0.08
8°
0°
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 66. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. B | Page 22 of 24
0.80
0.60
0.40
AD8027/AD8028
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Ordering Guide
Model
AD8027AR
AD8027AR-REEL
AD8027AR-REEL7
AD8027ART-R2
AD8027ART-REEL
AD8027ART-REEL7
AD8028AR
AD8028AR-REEL
AD8028AR-REEL7
AD8028ARM
AD8028ARM-REEL
AD8028ARM-REEL7
Minimum Ordering Quantity
1
2,500
1,000
250
10,000
3,000
1
2,500
1,000
1
3,000
1,000
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Rev. B | Page 23 of 24
Package Description
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Package Outline
R-8
R-8
R-8
RT-6
RT-6
RT-6
R-8
R-8
R-8
RM-10
RM-10
RM-10
Branding
H4B
H4B
H4B
H5B
H5B
H5B
AD8027/AD8028
NOTES
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
C03327–0–10/03(B)
Rev. B | Page 24 of 24