ON LC717A10AJ Capacitance-digital-converter Datasheet

LC717A10AJ
Capacitance‐Digital‐Converter
LSI for Electrostatic
Capacitive Touch Sensors
Overview
The LC717A10AJ is a high-performance and low-cost
capacitance-digital-converter LSI for electrostatic capacitive touch
sensor, especially focused on usability.
It has 16 channels capacitance-sensor input. This makes it ideal for
use in the products that need many switches. Since the calibration
function and the judgment of ON/OFF are automatically performed in
LSI internal, it can make development time more short. A detection
result (ON/OFF) for each input can be read out by the serial interface
(I2Ct compatible bus or SPI).
Also, measurement value of each input can be read out as 8-bit
digital data. Moreover, gain and other parameters can be adjusted
using serial interface.
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SSOP30 (225 mil)
CASE 565AZ
MARKING DIAGRAM
Features
• Detection System: Differential Capacitance Detection
•
•
•
•
•
•
•
(Mutual Capacitance Type)
Input Capacitance Resolution: Can Detect Capacitance Changes in
the Femto Farad Order
Measurement Interval (16 Differential Inputs):
♦ 30 ms (Typ) (at Initial Configuration)
♦ 6 ms (Typ) (at Minimum Interval Configuration)
External Components for Measurement: Not Required
Current Consumption:
♦ 570 mA (Typ) (VDD = 2.8 V)
♦ 1.3 mA (Typ) (VDD = 5.5 V)
Supply Voltage: 2.6 V to 5.5 V
Detection Operations: Switch
Interface: I2C Compatible Bus or SPI Selectable
© Semiconductor Components Industries, LLC, 2013
November, 2017 − Rev. 2
1
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Publication Order Number:
LC717A10AJ/D
LC717A10AJ
Specifications
Table 1. ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS = 0 V)
Symbol
Ratings
Unit
Supply Voltage
VDD
−0.3 to +6.5
V
Input Voltage
VIN
−0.3 to VDD + 0.3
V
(Note 1)
Output Voltage
VOUT
−0.3 to VDD + 0.3
V
(Note 2)
Power Dissipation
Pd max
160
mW
Tstg
−55 to +125
_C
Parameter
Storage Temperature
Remarks
TA = +105_C, Mounted on a substrate (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Apply to Cin0 to 15, Cref, CrefAdd, nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS.
2. Apply to Cdrv, SDA, SO, INTOUT.
3. Single-layer glass epoxy board (76.1 × 114.3 × 1.6t mm).
Table 2. RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Operating Supply Voltage
VDD
Conditions
2.6
−
5.5
V
Supply Ripple + Noise
VPP
−
−
±20
mV
Operating Temperature
Topr
−40
25
105
_C
Remarks
(Note 4)
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended. In this case, the small-valued
capacitor should be at least 0.1 mF, and is mounted near the LSI.
Table 3. ELECTRICAL CHARACTERISTICS
(VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143 kHz.
Not tested at low temperature before shipment.)
Parameter
Symbol
Capacitance Detection Resolution
N
Output Noise RMS
NRMS
Conditions
Minimum gain setting
Min
Typ
Max
Unit
−
−
8
bit
−
−
±1.0
LSB
(Notes 5, 7)
(Notes 5, 7)
Input Offset Capacitance
Adjustment Range
CoffRANGE
−
±8.0
−
pF
Input Offset Capacitance
Adjustment Resolution
CoffRESO
−
8
−
bit
Remarks
Cin Offset Drift
CinDRIFT
Minimum gain setting
−
−
±8
LSB
(Note 5)
Cin Detection Sensitivity
CinSENSE
Minimum gain setting
0.04
−
0.12
LSB/fF
(Note 6)
ICin
Cin = Hi−Z
−
±25
±500
nA
Cin Allowable Parasitic Input
Capacitance
CinSUB
Cin against VSS
−
−
30
pF
Cdrv Drive Frequency
fCDRV
100
143
186
kHz
Cdrv Pin Leak Current
ICDRV
−
±25
±500
nA
nRST Minimum Pulse Width
tNRST
1
−
−
ms
Power-on Reset Time
tPOR
−
−
20
ms
Power-on Reset Operation
Condition: Hold Time
tPOROP
10
−
−
ms
(Note 5)
Power-on Reset Operation
Condition: Input Voltage
VPOROP
−
−
0.1
V
(Note 5)
1
−
−
V/ms
(Note 5)
Cin Pin Leak Current
Power-on Reset Operation
Condition: Power Supply Rise Rate
tVDD
Cdrv = Hi−Z
0 V to VDD
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2
(Notes 5, 7)
LC717A10AJ
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143 kHz.
Not tested at low temperature before shipment.)
Parameter
Pin Input Voltage
Pin Output Voltage
SDA Pin Output Voltage
Pin Leak Current
Current Consumption
Symbol
Conditions
Min
Typ
Max
Unit
Remarks
VIH
High input
0.8 VDD
−
−
V
(Notes 5, 8)
VIL
Low input
−
−
0.2 VDD
VOH
High output
(IOH = +3 mA)
0.8 VDD
−
−
V
(Note 9)
VOL
Low output
(IOL = −3 mA)
−
−
0.2 VDD
VOL I2C
SDA Low output
(IOL = −3 mA)
−
−
0.4
V
−
−
±1
mA
(Note 10)
When initial setting
and non-touch
VDD = 2.8 V
−
570
700
mA
(Notes 5, 7)
When initial setting
and non-touch
VDD = 5.5 V
−
1.3
1.6
mA
During Sleep process
−
−
1
mA
ILEAK
IDD
ISTBY
(Note 7)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Design-guaranteed values (not tested before shipment).
6. Measurements conducted using the test mode in the LSI.
7. TA = +25_C.
8. Apply to nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS.
9. Apply to Cdrv, SO, INTOUT.
10. Apply to nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS.
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LC717A10AJ
Table 4. I2C COMPATIBLE BUS TIMING CHARACTERISTICS
(VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Not tested at low temperature before shipment.)
Min
Typ
Max
Unit
SCL
−
−
400
kHz
tHD;STA
SCL, SDA
0.6
−
−
ms
SCL Clock Low Period
tLOW
SCL
1.3
−
−
ms
SCL Clock High Period
tHIGH
SCL
0.6
−
−
ms
Repeated START Condition
Setup Time
tSU;STA
SCL, SDA
0.6
−
−
ms
Data Hold Time
tHD;DAT
SCL, SDA
0
−
0.9
ms
Data Setup Time
tSU;DAT
SCL, SDA
100
−
−
ns
(Note 11)
tr / tf
SCL, SDA
−
−
300
ns
(Note 11)
tSU;STO
SCL, SDA
0.6
−
−
ms
tBUF
SCL, SDA
1.3
−
−
ms
Parameter
SCL Clock Frequency
START Condition Hold Time
SDA, SCL Rise/Fall Time
STOP Condition Setup Time
STOP-to-START Bus Release Time
Symbol
Pin Name
fSCL
Conditions
Remarks
(Note 11)
(Note 11)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Design-guaranteed values (not tested before shipment).
Table 5. SPI BUS TIMING CHARACTERISTICS
(VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Not tested at low temperature before shipment.)
Parameter
SCK Clock Frequency
Symbol
Pin Name
Min
Typ
Max
Unit
fSCK
SCK
Conditions
−
−
5
MHz
Remarks
SCK Clock Low Time
tLOW
SCK
90
−
−
ns
(Note 12)
SCK Clock High Time
tHIGH
SCK
90
−
−
ns
(Note 12)
Input Signal Rise/Fall Time
tr / tf
nCS, SCK, SI
−
−
300
ns
(Note 12)
nCS Setup Time
tSU;NCS
nCS, SCK
90
−
−
ns
(Note 12)
SCK Clock Setup Time
tSU;SCK
nCS, SCK
90
−
−
ns
(Note 12)
Data Setup Time
tSU;SI
SCK, SI
20
−
−
ns
(Note 12)
Data Hold Time
tHD;SI
SCK, SI
30
−
−
ns
(Note 12)
nCS Hold Time
tHD;NCS
nCS, SCK
90
−
−
ns
(Note 12)
SCK Clock Hold Time
tHD;SCK
nCS, SCK
90
−
−
ns
(Note 12)
nCS Standby Pulse Width
tCPH
nCS
90
−
−
ns
(Note 12)
Output High Impedance Time
from nCS
tCHZ
nCS, SO
−
−
80
ns
(Note 12)
Output Data Determination Time
Output Data Hold Time
Output Low Impedance Time
from SCK Clock
tv
SCK, SO
−
−
80
ns
(Note 12)
tHD;SO
SCK, SO
0
−
−
ns
(Note 12)
tCLZ
SCK, SO
0
−
−
ns
(Note 12)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
12. Design-guaranteed values (not tested before shipment).
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LC717A10AJ
Power-On Reset (POR)
Since INTOUT pin changes from “High” to “Low” at the
same time as the released of power-on reset, it is possible to
verify the timing of release of power-on reset externally.
During power-on reset, Cin, Cref and CrefAdd are
unknown.
When power is turned on, power-on reset is enabled inside
the LSI and its state is released after a certain power-on reset
time, tPOR. Power-on reset operation condition: Power
supply rise rate tVDD must be at least 1 V/ms.
VDD
tVDD
VPOROP
tPOR
tPOR
tPOROP
POR
(LSI Internal
Signal)
RESET
UNKNOWN
RELEASE
INTOUT
VALID
Cin,
Cref,
CrefAdd
RESET
UNKNOWN
VALID
UNKNOWN
RELEASE
UNKNOWN
Figure 1.
I2C Compatible Bus Data Timing
90%
SDA
90%
10%
10%
tHD;DAT
tLOW
tSU;DAT
90% 90%
tSU;STA
10% 10%
tHD;STA
10%
tHIGH
tr
10%
tHD;STA
90%
90%
SCL
90%
10%
90%
90%
tBUF
10%
tSU;STO
90%
10%
tf
START
condition
Repeated START
condition
STOP
condition
START
condition
Figure 2.
I2C Compatible Bus Communication Formats
• Write format (data can be written into sequentially incremented addresses)
START
Slave Address
Write=L
ACK
Register Address (N)
ACK
Slave
Data written to Register Address (N)
Slave
ACK
Data written to Register Address (N+1) ACK
Slave
STOP
Slave
Figure 3.
• Read format (data can be read from sequentially incremented addresses)
START
Slave Address
Write=L
ACK
Register Address (N)
ACK
Slave
RESTART
Slave Address
Read=H ACK
Slave
Slave
Data read from Register Address (N)
ACK
Data read from Register Address (N+1)
Master
Figure 4.
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ACK Data read from Register Address (N+2) NACK STOP
Master
Master
LC717A10AJ
I2C Compatible Bus Slave Address
Selection of four kinds of addresses is possible through the SA0 and SA1 terminals.
Table 6.
SA1 Pin Input
SA0 Pin Input
7-bit Slave Address
Binary Notation
8-bit Slave Address
Low
Low
0x16
00101100b (Write)
0x2C
00101101b (Read)
0x2D
Low
High
0x17
00101110b (Write)
0x2E
00101111b (Read)
0x2F
High
Low
High
0x18
High
0x19
00110000b (Write)
0x30
00110001b (Read)
0x31
00110010b (Write)
0x32
00110011b (Read)
0x33
SPI Data Timing (SPI Mode 0 / Mode 3)
tCPH
nCS
tSU;SCK
tSU;NCS
tHIGH
tf
tr
tLOW
tHD;NCS
tHD;SCK
SCK
tSU;SI
tHD;SI
VALID
SI
tCLZ
SO
tHD;SO
tCHZ
VALID
Hi−Z
tV
Figure 5.
SPI Communication Formats (Example of Mode 0)
• Write format (data can be written into sequentially incremented addresses while preserving nCS = L)
nCS
SCK
Write=L
SI
7
6
5
4
3
2
1
0
Register Address(N)
SO
7
6
5
4
3
2
1
0
Data written to Register Address(N)
Hi−Z
7
6
5
4
3
2
1
0
Data written to Register Address(N+1)
Figure 6.
• Read format (data can be read from sequentially incremented addresses while preserving nCS = L)
nCS
SCK
SI
Read=H
7 6
5
4
3
2
1
0
Register Address(N)
SO
Hi−Z
7
6
5
4
3
2
1
0
Data read from Register Address(N)
Figure 7.
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6
7
6
5
4
3
2
1
0
Data read from Register Address(N+1)
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LC717A10AJ
Block Diagram
Cin0
Cin1
Cin2
Cin3
VDD
Cin4
VSS
Cin5
Cin6
1st
AMP
Cin7
Cin8
2nd
AMP
A/D
CONVERTER
MUX
Cin9
Cin10
Cin11
Cdrv
CONTROL
LOGIC
Cin12
INTOUT
Cin13
nRST
Cin14
Cin15
nCS
POR
OSCILLATOR
SCL/SCK
2
I C/SPI
Cref
CrefAdd
MUX
SDA/SI
SA0/SO
SA1
Figure 8. Simplified Block Diagram
LC717A10AJ is capacitance-digital-converter LSI
capable of detecting changes in capacitance in the order of
femto Farads. It consists of an oscillation circuit that
generates the system clock, a power-on reset circuit that
resets the system when the power is turned on, a multiplexer
that selects the input channels, a two-stage amplifier that
detects the changes in the capacitance and outputs
analog-amplitude values, a A/D converter that converts the
analog-amplitude values into digital data, an I2C compatible
bus or a SPI that enables serial communication with external
devices and a control logic that controls the entire chip.
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LC717A10AJ
Cin3
Cin2
Cin1
Cin0
Non Connect
nRST
nCS
SA0/SO
SDA/SI
SCL/SCK
SA1
INTOUT
Cdrv
CrefAdd
Cref
Pin Assignment
16
1
15
VDD
VSS
Non Connect
Cin4
Cin5
Cin6
Cin7
Cin8
Cin9
Cin10
Cin11
Cin12
Cin13
Cin14
Cin15
30
Figure 9. Pin Assignment (Top View)
Table 7. PIN ASSIGNMENT
Pin No.
Pin Name
Pin No.
Pin Name
1
VDD
16
Cref
2
VSS
17
CrefAdd
3
Non Connect (Note 13)
18
Cdrv
4
Cin4
19
INTOUT
5
Cin5
20
SA1
6
Cin6
21
SCL/SCK
7
Cin7
22
SDA/SI
8
Cin8
23
SA0/SO
9
Cin9
24
nCS
10
Cin10
25
nRST
11
Cin11
26
Non Connect (Note 13)
12
Cin12
27
Cin0
13
Cin13
28
Cin1
14
Cin14
29
Cin2
15
Cin15
30
Cin3
13. Connect to GND when mounted.
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LC717A10AJ
Table 8. PIN FUNCTION
Pin Name
I/O
Pin Functions
Cin0
I/O
Capacitance sensor input
Cin1
I/O
Capacitance sensor input
Cin2
I/O
Capacitance sensor input
Cin3
I/O
Capacitance sensor input
Cin4
I/O
Capacitance sensor input
Cin5
I/O
Capacitance sensor input
Cin6
I/O
Capacitance sensor input
Cin7
I/O
Capacitance sensor input
Cin8
I/O
Capacitance sensor input
Cin9
I/O
Capacitance sensor input
Cin10
I/O
Capacitance sensor input
Cin11
I/O
Capacitance sensor input
Cin12
I/O
Capacitance sensor input
Cin13
I/O
Capacitance sensor input
Cin14
I/O
Capacitance sensor input
Cin15
I/O
Capacitance sensor input
Cref
I/O
Reference capacitance input
CrefAdd
I/O
Reference capacitance input for addition
Cdrv
O
Output for capacitance sensors drive
INTOUT
O
Interrupt output
Pin Type
VDD
AMP
R
VSS
Buffer
VDD
Buffer
VSS
SCL/SCK
I
nCS
I
Clock input
(I2C)
/ Clock input (SPI)
VDD
Interface selection / Chip select
inverting input (SPI)
nRST
I
External reset signal inverting input
SA1
I
Slave address selection (I2C)
SDA/SI
I/O
Data input and output (I2C) /
Data input (SPI)
R
VSS
VDD
R
VSS
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LC717A10AJ
Table 8. PIN FUNCTION (continued)
Pin Name
I/O
Pin Functions
Pin Type
SA0/SO
I/O
Slave address selection (I2C) /
Data output (SPI)
VDD
R
VSS
VDD
Power supply (2.6 V to 5.5 V) (Note 14)
VSS
Ground (Earth) (Notes 14, 15)
Buffer
14. Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended. In this case, the small-valued
capacitor should be at least 0.1 mF, and is mounted near the LSI.
15. When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded.
Details of Pin Functions
However, if the difference between the parasitic
capacitance of each Cin pin is extremely large, it may not
detect capacitance change in each Cin pin correctly.
CrefAdd can be used as additional terminal for Cref.
Leave the CrefAdd open if not in used.
Cin0 to Cin15
These are the capacitance-sensor-input pins. These pins
are used by connecting them to the touch switch pattern. Cin
and the Cdrv wire patterns should be close to each other. By
doing so, Cdrv and Cin patterns are capacitively coupled.
Therefore, LSI can detect capacitance change near each
pattern as 8-bit digital data.
However, if the shape of each pattern or the capacitively
coupled value of Cdrv is not appropriate, it may not be able
to detect the capacitance change correctly.
In this LSI, there is a two-stage amplifier that detects the
changes in the capacitance and outputs analog-amplitude
values. Cin0 to Cin15 are connected to the inverting input of
the 1st amplifier.
During measurement process, channels other than the one
being measured are all in “Low” condition.
Leave the unused terminals open.
Cdrv
It is the output pin for capacitance sensors drive. It outputs
the pulse voltage which is needed to detect capacitance at
Cin0 to Cin15.
Cdrv and Cin wire patterns should be close to each other
so that they are capacitively coupled.
INTOUT
It is the interrupt-output pin. It is used by connecting to
a main microcomputer if necessary, and use as interrupt
signal. (High Active).
Leave the terminal open if not in used.
SCL/SCK
Clock input (I2C)/Clock input (SPI). It is the clock input
pin of the I2C compatible bus or the SPI depending on the
mode of operation.
Cref, CrefAdd
These are the reference-capacitance-input pins. These are
used by connecting to the wire pattern like Cin pins or are
used by connecting any capacitance between this pin and
Cdrv pin.
In this LSI, there is a two-stage amplifier that detects the
changes in the capacitance and outputs analog-amplitude
values. Cref is connected to the non-inverting input of the 1st
amplifier.
Due to the parasitic capacitance generated in the wire
connections of Cin pins and their patterns, as well as the one
generated between the wire patterns of Cin and Cdrv pins,
Cref may not detect capacitance change of each Cin pin
accurately. In this case, connect an appropriate capacitance
between Cref and Cdrv to detect capacitance change
accurately.
nCS
Interface selection/Chip-select-inverting input (SPI).
Selection of I2C compatible bus mode or SPI mode is
through this terminal. After initialization, the LSI is
automatically in I2C compatible bus mode. To continually
use I2C compatible bus mode, fix nCS pin to “High”. To
switch to SPI mode after LSI initialization, change the nCS
input “High” → “Low”. The nCS pin is used as the
chip-select-inverting input pin of SPI, and SPI mode is kept
until LSI is again initialized.
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LC717A10AJ
nRST
It is the external-reset-signal-inverting-input pin. When
nRST pin is “Low”, LSI is in the reset state.
Each pin (Cin0 to 15, Cref, CrefAdd) is “Hi−Z” during
reset state.
SA0/SO
Slave address selection (I2C)/Data output (SPI). It is the
slave address selection pin of the I2C compatible bus or the
data output pin of the SPI depending on the mode of
operation.
SDA/SI
Data input and output (I2C)/Data input (SPI). It is the data
input and output pin of the I2C compatible bus or the data
input pin of the SPI depending on the mode of operation.
SA1
Slave address selection (I2C). It is the slave address
selection pin of the I2C compatible bus.
When SPI mode, connect to the SA1 pin to GND.
Table 9. ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)†
LC717A10AJ−NH
SSOP30 (225 mil)
(Pb-Free / Halogen Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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LC717A10AJ
PACKAGE DIMENSIONS
SSOP30 (225 mil)
CASE 565AZ
ISSUE A
1.00
SOLDERING FOOTPRINT*
5.80
(Unit: mm)
0.50
0.32
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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LC717A10AJ
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