AVAGO AFBR-8420Z Pluggable 100g ethernet optical transceiver Datasheet

AFBR-8420Z
CFP2, 850 nm, 100GBASE-SR10 Compliant
Pluggable 100G Ethernet Optical Transceiver
Data Sheet
Description
Features
Avago Technologies’ AFBR-8420Z CFP2 SR10 is a ten channel pluggable, parallel, fiber optic transceiver for 100Gbps
Ethernet Applications. The transceiver supports high
speed serial links over multi-mode fiber at signalling rates
up to 103.125Gb/s (a serial line rate of 10.3125Gb/s per
channel) for link distances up to 100m with OM3 fiber or
150m with OM4 fiber. The product is compliant with the
CFP2 industry agreement for mechanical and low speed
electrical specifications. High speed electrical and optical
specifications are compliant with IEEE 802.3ba Clause 86
for 100GBase-SR10 media, Clause 86A for CPPI electrical
interface and Clause 45 for MDIO.
• Links up to 100m using OM3 fiber and 150m using
OM4 fiber
• CFP2 Power Dissipation Class 2 with CDRs in bypass.
CDRs are bypassed for lower power dissipation by
default
• CFP2 Power Dissipation Class 3 with CDRs ON
• Proven High Reliability 850nm technology: Avago
VCSEL array transmitter and Avago PIN array receiver.
• Compliant to 100GbE specifications 802.3ba
(100GBase-SR10 and CPPI) up to 100m OM3 and 150m
OM4 fiber.
• Compliant to 40GbE specifications 802.3ba (40GBaseSR4 and XLPPI) up to 100m OM3 and 150m OM4 fiber.
• Compatible with 10GE SR specifications per 802.3ae
(10GBASE-SR) up to 100m OM3 fiber.
• OTU4 Support at 11.18Gb/s per channel
• CFP2 10x10Gbit/s Host Pin Map
• Class 1 eye safe per IEC60825-1 and CDRH
• Wide case temperature range (0°C to 70°C)
• Utilizes standard 24 lane optical fiber with MTP® (MPO)
optical connector for high density and thin, lightweight cable management
• Diagnostic features per CFP2 using MDIO. Real time
monitoring of:
- Transmitter average optical power
- Received average optical power
- Laser bias current
- Temperature
- Supply Voltage
• Host Lane Loopback (eLoop) and Network Lane
Loopback (oLoop) functionality
• Integrated CDRs on each transmit and receive lane
• CDRs can be bypassed for lower power dissipation
• CFP Management Interface Specification Version 2.2
• CFP2 Hardware Specification Revision 1.0
• Compliant to RoHS directives
The transceiver electrical interface uses a 104 contact
edge type connector, as specified in the CFP2 industry
agreement. The optical interface uses a 24-fiber MTP®
(MPO) fiber optic connector. This transceiver incorporates
Avago Technologies proven integrated circuit and VCSEL
technologies to provide reliable, high performance and
consistent service.
Digital diagnostic monitoring information (DMI) is present in the AFBR-8420Z per the CFP2 industry agreement,
providing real time monitoring information of transmitter,
receiver and module operating conditions over the MDIO
interface.
Applications
• 100Gb/s Ethernet Interconnects (802.3ba Clause 86)
• 10 x 10Gb/s Ethernet Interconnects (802.3ae Clause 52)
• Datacom/Telecom Switch and Router Connections
• Data Aggregation and Density Applications
Transceiver Block Diagram
CDR By Pass
Electrical
Input
Electrical
Output
Rx CDRs
CDR By Pass
MDC
MDIO
MOD_RSTn
MOD_LO PWR
GLB TX DIS
PRG_CNTL [3:1]
PRG_ALRM [3:1]
GLB Rx_LOS
GLB_ALRMn
MOD_ABS
Tx Laser
Driver IC
VCSEL
Array
Rx Preamp +
PIN
Array
100 GBASE-SR10
Optical Output
Electrical Loop Back
Opticall Loop Back
Tx CDRs
Postamp IC
100 GBASE-SR10
Optical Output
MDIO + MDC Controller Block
CFP2 Electrical
Connector
2x12 MTP/MPO
Optical Connector
Transmitter Section:
The optical transmitter incorporates a 10-channel VCSEL
(Vertical Cavity Surface Emitting Laser) array, a 10-channel
input CDR/buffer and laser driver, diagnostic monitors, laser control and bias blocks. The transmitter is designed for
IEC-60825 and CDRH eye safety compliance. The Tx input
stage provides CPPI compliant differential inputs per IEEE
802.3ba.
In addition to module level temperature and Vcc monitors, Avago CFP2 SR10 transceivers provide per channel
monitors of VCSEL bias and transmitter optical output
power through the MDIO interface. Alarm thresholds are
established for the monitored diagnostics in CFP2 MDIO
non-volatile registers. Flags are set and linked to the module global alarm pin (GLB_ALRMn, pin 29) via configuration parameters in CFP2 MDIO volatile registers.
AC coupling capacitors are located inside the CFP2 transceiver and are not required on the host board. For module
control and interrogations, and MDIO+MDC two wire interface is provided.
Receiver Section:
The optical receiver incorporates a 10-channel PIN photodiode array, a 10-channel pre-amplifier and output CDR/
buffer, diagnostic monitors and control blocks. The Rx
output stage provides CPPI compliant differential inputs
per IEEE 802.3ba. AC coupling capacitors are located inside the CFP2 transceiver and are not required on the host
board.
2
In addition to module level temperature and Vcc monitors, Avago CFP2 SR10 transceivers provide per channel
monitors of receiver optical input power through the
MDIO interface. Alarm thresholds are established for the
monitored diagnostics in CFP2 MDIO non-volatile registers. Flags are set and linked to the module global alarm
pin (GLB_ALRMn, pin 29) via configuration parameters in
CFP2 MDIO volatile registers.
Low Speed I/O:
The CFP2 SR10 transceiver provides two low speed interfaces to the host for module control and monitoring, one
via LVCMOS hard pin signals and the other through an
802.3 compliant 1.2V CMOS MDIO+MDC two wire serial
interface.
Hard pin functions are available to support a Global Tx Disable control (pin 24, TX_DIS), a Global Low Power Mode
control (pin 26, MOD_LOPWR), a global module Reset control (pin 28, MOD_RSTn), a global module Rx LOS monitor
(pin 25, RX_LOS) and a global module Alarm monitor (pin
29, GLB_ALRMn). The pin functions can be customized via
configuration parameters in CFP2 MDIO volatile registers.
Soft functions are available to support many control and
monitoring behaviours via a two wire serial MDIO+MDC
interface. Avago’s CFP SR10 transceivers support clock
rates from 100kHz to 4MHz per the CFP2 industry agreement.
Regulatory Compliance Table
Feature
Test Method
Performance
Electrostatic Discharge (ESD)
to the Electrical Contacts
JEDEC Human Body Model (HBM)
(JESD22-A114-B)
High speed contacts shall withstand
1000V. All other contacts shall withstand
2000 V.
Electrostatic Discharge (ESD)
to the Optical Connector Receptacle
EN61000-4-2, Criterion B
When installed in a properly grounded
housing and chassis the units are
subjected to 15kV air discharges during
operation and 8kV direct discharges to
the case.
Electromagnetic Interference
(EMI)
FCC Part 15 CENELEC EN55022
(CISPR 22A) VCCI Class 1
System margins are dependent on
customer board and chassis design.
RF Immunity
Variation of IEC 61000-4-3
Typically shows no measurable effect
from a 10V/m field swept from 80 MHz
to 1 GHz applied to the module without
a chassis enclosure
Laser Eye Safety and
Equipment Type Testing
US FDA CDRH AEL Class 1
US21 CFP, Subchapter J per
Paragraphs 1002.10 and 1002.12
CDRH Certification 9720151-141
TUV File: R 72131700
(IEC) EN60825-1:1994 +A11 +A2
(IEC) EN60825-2:1994 +A1
(IEC) EN60950:1992 +A1 +A2 +A3 +A4 +A11
Component Recognition
Underwriters Laboratories (UL) and Canadian
Standards Association (CSA) Joint Component
Recognition for Information Technology Equipment including Electrical Business Equipment
RoHS Compliance
RoHS Directive 2002/95/EC and it’s amendment RoHS6 with exemption 7c-I
directives 6/6
Flammability
UL 94V-0
MPO Optical Lane Assignments
CFP2 Rx Optical Channel
MTP/MPO Fiber Number
MTP/MPO Fiber Number
CFP2 Tx Optical Channel
Unused Fibers
3
UL File: E173874
Unused Fibers
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Unit
Storage Temperature
TS
-40
85
°C
Absolute Maximum Operating Temperature
TC
85
°C
Note 2
3.3V Power Supply Voltage
VCC
-0.5
3.6
V
Per CFP2 MSA
-200
200
mA/µs
Per CFP2 MSA
3.75
A
Per CFP2 MSA
Vcc+0.5
V
1.0
V
Note 3
In Rush Current Rate (All pins, Class 3)
Operating Power Supply Current
ICC
Data Input Voltage – Single Ended
Data Input Voltage – Differential
-0.5
|Vdip-Vdin|
Notes
3.3V LVCMOS Control Pin Input Voltage
-0.3
Vcc+0.3
V
Per CFP2 MSA
3.3V LVCMOS Control Pin Output Current
-4.0
4.0
mA
Per CFP2 MSA
1.2V CMOS Control Pin Input Voltage
-0.3
1.5
V
Per CFP2 MSA
-4.0
4.0
mA
Per CFP2 MSA
1.2V CMOS Control Pin Output Current
Power Supply Noise
Vrip
Relative Humidity
RH
Receiver Optical Damage Threshold
Pr,max
2%
3%
5
DC – 1MHz
1 – 10MHz
85
%
+3.4
dBm,avg
802.3 Clause 86
Notes:
1. Absolute Maximum Ratings are those values beyond which damage to the device may occur if limits are exceeded for other than a short period of
time. See Reliability Data Sheet for specific reliability performance.
2. Electro-optical specifications are not guaranteed outside the recommended operating temperature range. Operation at or above the maximum
Absolute Maximum Case Temperature for extended periods of time may adversely impact reliability.
3. This is the maximum input voltage that can be applied across the differential inputs without damaging the input circuitry.
Recommended Operating Conditions
Parameter
Symbol
Minimum
Maximum
Unit
Notes
Case Operating Temperature
TC
0
70
°C
Note 1, 2
Total Power Dissipation CDRs in Bypass
(Default State - Class 2 CFP2)
Pdiss
6.0
W
Per CFP2 MSA
Total Power Dissipation CDRs ON (Class 3 CFP2)
Pdiss
9.0
W
Per CFP2 MSA
Total Power Dissipation (Low Power Mode)
Pdiss,lpwr
2.0
W
Per CFP2 MSA
Power Supply Voltage
VCC
3.465
V
3.135
Notes:
1. The Ambient Operating Temperature limitations are subject to the host system thermal design.
2. Recommended Operating Conditions are those values for which functional performance and device reliability is implied.
3. Per CFP2 industry agreement specifications.
4
Transmitter and Receiver Electrical Characteristics (CPPI Mode, Internal CDRs Off)
(Tc = 0 °C to 70 °C, Vcc = 3.3 V ± 0.1 V)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
High Speed Signalling Rate, Per Lane
10.3125
Gb/s
± 100 ppm
Per 802.3 Clause 86
High Speed Signalling Rate, Per Lane
11.18
Gb/s
Un-retimed OTU4
(OTL4.10) rate
V
802.3 Clause 86A
mV,rms
802.3 Clause 86A
Single Ended Input Voltage Tolerance, TP1a
-0.3
AC Common Mode Input Voltage
Tolerance, TP1a
15
Differential Input Return Loss, TP1
RL,diff
4
dB
802.3 Clause 86A
Differential to Common Mode Input
Return Loss, TP1
Equation
10
86A.4.1.1
dB
802.3 Clause 86A
J2 Jitter Tolerance, TP1a
0.17
UI
802.3 Clause 86A
J9 Jitter Tolerance, TP1a
0.29
UI
802.3 Clause 86A
Data Dependent Pulse Width Shrinkage
Tolerance, TP1a
0.07
UI
802.3 Clause 86A
UI
mV
802.3 Clause 86A
Hit Ratio = 5 x 10-5
Input Voltage Eye Mask TP1a (X1, X2)
Input Voltage Eye Mask TP1a (Y1, Y2)
0.11, 0.31
95, 350
Data Output Differential Peak-to-Peak
Voltage Swing, TP4
300
850
mV
Single Ended Output Voltage, TP4
-0.3
4
V
802.3 Clause 86A
7.5
mV,rms
802.3 Clause 86A
5
%
AC Common Mode Output Voltage, TP4
Termination mismatch at 1MHz, TP4
Differential Output Return Loss, TP4
RL,diff
Common Mode Output Return Loss, TP4
Output Transition Time, 20% to 80%, TP4
Tr, Tf
Equation
86A.4.2.1
dB
802.3 Clause 86A
Equation
86A.4.2.2
dB
802.3 Clause 86A
ps
802.3 Clause 86A
J2 Jitter Output, TP4
28
0.42
UI
802.3 Clause 86A
J9 Jitter Output, TP4
0.65
UI
802.3 Clause 86A
Data Dependent Pulse Width Shrinkage
(DDPWS), TP4
0.34
UI
802.3 Clause 86A
UI
mV
802.3 Clause 86A
Hit Ratio = 5 x 10-5
Output Voltage Eye Mask (X1, X2)
Output Voltage Eye Mask (Y1, Y2)
0.29, 0.5
150, 425
Notes:
1. Internally AC coupled and terminated (100 Ω differential).
2. CDRs bypassed result in CPPI compliance per 802.3ba Clause 86A.
Y2
Differential Amplitude [mV]
Differential amplitude (mV)
Y2
Y1
0
-Y1
-Y2
0
-Y1
-Y2
0
X1
X2
1-X2
Time (UI)
TP1a Electrical Input Eye Mask (CPPI)
Per 86A.5.3.6
5
Y1
1-X1
1
0
X1
X2
Normalized Time [UI]
TP4 Electrical Output Eye Mask (CPPI)
Per 86A.5.3.6
1-X1
1
Transmitter Optical Characteristics
(Tc = 0 °C to 70 °C, VccT, VccR = 3.3 V ± 0.1 V)
Parameter
Symbol
Min
Center Wavelength, TP2
lC
840
Spectral Width – rms, TP2
σrms
Average Optical Output Power, TP2
Pout
Modulated Optical Output Power (OMA), TP2
Tx,OMA
Max
Unit
Notes
860
nm
Per 802.3 Clause 86
0.65
nm
Per 802.3 Clause 86
-7.6
+2.4
dBm,avg
Note 1
-5.6
+3.0
dBm,oma
Per 802.3 Clause 86
OMA Optical Power Difference between
any two lanes, TP2
+4.0
dB
Per 802.3 Clause 86
Peak Optical Output Power, each lane, TP2
+4.0
dBm,pk
Per 802.3 Clause 86
dBm,oma
Per 802.3 Clause 86
dB
Per 802.3 Clause 86
dB
Per 802.3 Clause 86
dB
Per 802.3 Clause 86
Launched Power in OMA Minus TDP,
each lane, TP2
Typ
-6.5
Transmitter & Dispersion Penalty, TP2
TDP
Extinction Ratio, TP2
ER
3.5
3.0
Optical Return Loss Tolerance, TP2
12
≥ 86% at 19 µm
≤ 30% at 4.5 µm
Encircled Flux, TP2
Eye Mask coordinates:
X1, X2, X3, Y1, Y2, Y3, TP2
SPECIFICATION VALUES
0.23, 0.34, 0.43, 0.27, 0.35, 0.4
Average Optical Output Power Tx_DIS Asserted
Poff
Per 802.3 Clause 86
-30
UI
Hit Ratio = 5 x 10-5
dBm,avg
Per 802.3 Clause 86
Notes:
1. Max average Pout per 802.3ba Clause 86 is +2.4 dBm,avg. To interoperate with legacy 802.3ae Clause 52 devices the limit may need to be constrained
to no more than -1.0 dBm,avg.
1+Y3
Mask Coordinates
X1 = 0.23
X2 = 0.34
X3 = 0.43
Y1 = 0.27
Y2 = 0.35
Y3 = 0.40
Normalizd Amplitude
1
1-Y1
1-Y2
0.5
Y2
Y1
0
-Y3
0
X1
X2
X3 1-X3 1-X2
1-X1
Normalized Time (Unit Interval
1.0
Transmitter eye mask definitions (TP2) at Hit ratio 5 x 10-5 hits per sample
Per Table 86-6
6
Receiver Optical Characteristics
(Tc = 0 °C to 70 °C, VccT, VccR = 3.3 V ± 0.1 V)
Parameter
Symbol
Min
Center Wavelength, each lane, TP3
lC
840
Damage Threshold, TP3
Average Optical Input Power, Unstressed
Rx Sensitivity/Overload, each lane, TP3
Typ
Max
Unit
Notes
860
nm
Per 802.3 Clause 86
dBm,avg
Per 802.3 Clause 86
+3.4
PIN
-9.5
Receiver Reflectance, TP3
Modulated Optical Input Power (OMA) –
Overload, each lane, TP3
Rx OMA
Modulated Optical Input Power (OMA) –
Stressed Rx Sensitivity, each lane, TP3
Rx OMA
Stressed receiver sensitivity in OMA, each lane
PA
Loss of Signal – De-asserted, TP3
PD
Loss of Signal – Hysteresis, TP3
PA – PD
dBm,avg
-12
dB
Per 802.3 Clause 86
+3.0
dBm,oma
Per 802.3 Clause 86
-5.4
Peak Optical Input Power, each lane, TP3
Loss of Signal – Assert, TP3
+2.4
dBm,oma
Per 802.3 Clause 86
+4.0
dBm,pk
Per 802.3 Clause 86
-5.4
dBm,oma
Per 802.3 Clause 86
-30
dBm,oma
-8
0.5
Per 802.3 Clause 86
dBm,oma
dB
Conditions of stressed receiver sensitivity, TP3:
Per 802.3 Clause 86
Vertical eye closure penalty (VECP), each lane
1.9
dB
Per 802.3 Clause 86
Stressed eye J2, Jitter, each lane, TP3
0.30
UI
Per 802.3 Clause 86
Stressed eye J9, Jitter, each lane, TP3
0.47
UI
Per 802.3 Clause 86
OMA of each aggressor lane, TP3
-0.4
dBm
Per 802.3 Clause 86
Note:
1. Refer to IEEE 802.3 Clause 86 for conditions of Stressed Receiver Sensitivity Test and Conditions of Receiver Jitter Tolerance Test.
7
MDIO and MDC Electrical Characteristics
(Tc = 0 °C to 70 °C, VccT, VccR = 3.3 V ± 0.1 V)
Parameter
Symbol
MDC Clock Frequency
MDC Clock Period
t_prd
MDC Clock Duty Cycle
MDC Clock Pulse Width
Min
Typ
Max
Unit
0.1
4.0
MHz
0.25
10
µs
40
60
%
Notes
100
ns
MDIO Data Setup Time
t_setup
10
ns
MDIO Data Hold Tim
t_hold
10
ns
Delay From Rising Edge MDC to MDIO Data Change
t_delay
0
175
ns
MDIO, MDC and PRTADR2:0 Input Voltage, High
VIH
0.84
1.5
V
MDIO, MDC and PRTADR2:0 Input Voltage, Low
VIL
-0.3
0.36
V
MDIO Output Voltage, High
VOH
1
1.5
V
IOH = -100 µA
MDIO Output Voltage, Low
VOL
-0.3
0.2
V
IOL = 100 µA
MDIO Output Current, High
IOH
-4
mA
VOH = 1 V
MDIO Output Current, Low
IOL
mA
VOL = 0.2 V
4
Timing parameters
Parameter
Symbol
Hardware MOD_LOPWR assert
Hardware MOD_LOPWR deassert
Max
Unit
t_MOD_LOPWR_assert
1
ms
t_MOD_LOPWR_deassert
1
ms
Receiver Loss of Signal Assert Time
t_loss_assert
100
µs
Receiver Loss of Signal De-Assert Time
t_loss_deassert
100
µs
Global Alarm Assert Delay Time
GLB_ALRMn_assert
150
ms
Global Alarm De-Assert Delay Time
GLB_ALRMn_deassert
150
ms
Initialization time from Reset
t_initialize
2.5
s
Transmitter Disabled
(TX_DIS asserted)
t_deassert
100
µs
Transmitter Enabled
(TX_DIS de-asserted)
t_assert
20
ms
8
Min
Typ
Notes
This is a logical "OR" of
associated MDIO alarm
& status registers.
From TX-Off state.
Transceiver Contact Assignment and Signal Description
CFP2
Pin
Logic
Symbol
Electrical Pin Description
1
Gnd
GND
GND
1
2
CML
TX9n
High Speed Data Input -, Channel 9
4
3
CML
TX9p
High Speed Data Input +, Channel 9
4
4
Gnd
GND
GND
1
5
CML
TX8n
High Speed Data Input -, Channel 8
4
6
CML
TX8p
High Speed Data Input +, Channel 8
4
7
Gnd
GND
GND
1
8
Gnd
3.3V_GND
3.3V_GND (differs from standard GND)
2
9
VCC
VCC
3.3V Supply
2
10
VCC
VCC
3.3V Supply
2
11
VCC
VCC
3.3V Supply
2
12
VCC
VCC
3.3V Supply
2
13
Gnd
3.3V_GND
3.3V_GND (differs from standard GND)
2
14
Gnd
3.3V_GND
3.3V_GND (differs from standard GND)
2
15
No Connect
VND_IO_A
Module Vendor I/O A. For mfg use only. Do not connect.
3
16
No Connect
VND_IO_B
Module Vendor I/O B. For mfg use only. Do not connect.
3
17
LVCMOS
PRG_CNTL1
Programmable Control 1, set over MDIO. MSA Default is TRXIC_RSTn.
3
18
LVCMOS
PRG_CNTL2
Programmable Control 2, set over MDIO. MSA Default is Hardware Interlock LSB.
3
19
LVCMOS
PRG_CNTL3
Programmable Control 3, set over MDIO. MSA Default is Hardware Interlock MSB.
3
20
LVCMOS
PRG_ALRM1
Programmable Alarm 1, set over MDIO. MSA Default is HI PWR_ON 1
3
21
LVCMOS
PRG_ALRM2
Programmable Alarm 2, set over MDIO. MSA Default is MOD_READY
3
22
LVCMOS
PRG_ALRM3
Programmable Alarm 3, set over MDIO. MSA Default is MOD_FAULT
3
23
Gnd
GND
GND
1
24
LVCMOS
TX_DIS
Global Transmitter Disable (For all laser channels) "1" or NC = transmitter disabled,
"0" = transmitter enabled
3
25
LVCMOS
RX_LOS
Global Rx_LOS alarm (Logic OR of all optical RX channels LOS) "1": low optical
signal, "0": normal condition
3
26
LVCMOS
MOD_LO PWR
Module Low Power Mode [Achieves < 2 W) "1" or NC: module in low power (safe)
mode, "0": power-on enabled
4
27
GND
MOD_ABS
Module absent. Ground in transceiver. "1" or NC: module absent, "0": module
present, Pull Up Resistor on Host required.
4
28
LVCMOS
MOD_RSTn
Global Module reset. Pulled down inside module, resistor value of 4.7 kΩ to 10
kΩ. “0” resets the module, “1” or NC = module enabled. Hardware Reset: Asserting MOD_RSTn will cause a complete reset of the module. All VR values are lost
and must be re-written by the Host.
3
29
LVCMOS
GLB_ALRMn
Global Module alarm. Logic OR of Fault, Alarms, Warnings, and Status Flags. “0":
alarm condition in any MDIO Alarm register, "1": no alarm condition, Open Drain,
Pull Up Resistor on Host is required.
3
30
Gnd
GND
GND
1
31
1.2V CMOS
MDC
MDIO clock line (100 kHz to 4 MHz) per 802.3ae
3
32
1.2V CMOS
MDIO
MDIO data line per 802.3ae
3
33
1.2V CMOS
PRTADR0
MDIO Physical Port Address bit 0
3
34
1.2V CMOS
PRTADR1
MDIO Physical Port Address bit 1
3
35
1.2V CMOS
PRTADR2
MDIO Physical Port Address bit 2
3
36
No Connect
VND_IO_C
Module Vendor I/O C. For mfg use only. Do not connect.
3
37
No Connect
VND_IO_D
Module Vendor I/O D. For mfg use only. Do not connect.
3
38
No Connect
VND_IO_E
Module Vendor I/O E. For mfg use only. Do not connect.
3
39
Gnd
3.3V_GND
3.3V_GND (differs from standard GND)
2
40
Gnd
3.3V_GND
3.3V_GND (differs from standard GND)
2
41
VCC
VCC
3.3V Supply
2
42
VCC
VCC
3.3V Supply
2
43
VCC
VCC
3.3V Supply
2
44
VCC
VCC
3.3V Supply
2
45
Gnd
3.3V_GND
3.3V_GND (differs from standard GND)
2
46
Gnd
GND
GND
2
47
CML
RX9n
High Speed Data Output -, Channel 9
4
47
CML
RX9n
High Speed Data Output -, Channel 9
4
9
Plug Mating
Sequence
CFP2
Pin
Logic
Symbol
Electrical Pin Description
48
CML
RX9p
High Speed Data Output +, Channel 9
4
49
Gnd
GND
GND
1
50
CML
RX8n
High Speed Data Output -, Channel 8
4
51
CML
RX8p
High Speed Data Output +, Channel 8
4
52
Gnd
GND
GND
1
53
Gnd
GND
GND
1
54
CML
RX0p
High Speed Data Output +, Channel 0
4
55
CML
RX0n
High Speed Data Output -, Channel 0
4
56
Gnd
GND
GND
1
57
CML
RX1p
High Speed Data Output +, Channel 1
4
58
CML
RX1n
High Speed Data Output -, Channel 1
4
59
Gnd
GND
GND
1
60
CML
RX2p
High Speed Data Output +, Channel 2
4
61
CML
RX2n
High Speed Data Output -, Channel 2
4
62
Gnd
GND
GND
1
63
CML
RX3p
High Speed Data Output +, Channel 3
4
64
CML
RX3n
High Speed Data Output -, Channel 3
4
65
Gnd
GND
GND
1
66
CML
RX4p
High Speed Data Output +, Channel 4
4
67
CML
RX4n
High Speed Data Output -, Channel 4
4
68
Gnd
GND
GND
1
69
CML
RX5p
High Speed Data Output +, Channel 5
4
70
CML
RX5n
High Speed Data Output -, Channel 5
4
71
Gnd
GND
GND
1
72
CML
RX6p
High Speed Data Output +, Channel 6
4
73
CML
RX6n
High Speed Data Output -, Channel 6
4
74
Gnd
GND
GND
1
75
CML
RX7p
High Speed Data Output +, Channel 7
4
76
CML
RX7n
High Speed Data Output -, Channel 7
4
77
Gnd
GND
GND
1
78
CML
REFCLKp
No functionality in AFBR-8420Z
4
79
CML
REFCLKn
No functionality in AFBR-8420Z
4
80
Gnd
GND
GND
1
81
CML
TX0p
High Speed Data Input +, Channel 0
4
82
CML
TX0n
High Speed Data Input -, Channel 0
4
83
Gnd
GND
GND
1
84
CML
TX1p
High Speed Data Input +, Channel 1
4
85
CML
TX1n
High Speed Data Input -, Channel 1
4
86
Gnd
GND
GND
1
87
CML
TX2p
High Speed Data Input +, Channel 2
4
88
CML
TX2n
High Speed Data Input -, Channel 2
4
89
Gnd
GND
GND
1
90
CML
TX3p
High Speed Data Input +, Channel 3
4
91
CML
TX3n
High Speed Data Input -, Channel 3
4
92
Gnd
GND
GND
1
93
CML
TX4p
High Speed Data Input +, Channel 4
4
94
CML
TX4n
High Speed Data Input -, Channel 4
4
95
Gnd
GND
GND
1
96
CML
TX5p
High Speed Data Input +, Channel 5
4
97
CML
TX5n
High Speed Data Input -, Channel 5
4
98
Gnd
GND
GND
1
99
CML
TX6p
High Speed Data Input +, Channel 6
4
100
CML
TX6n
High Speed Data Input -, Channel 6
4
101
Gnd
GND
GND
1
102
CML
TX7p
High Speed Data Input +, Channel 7
4
103
CML
TX7n
High Speed Data Input -, Channel 7
4
104
Gnd
GND
GND
1
10
Plug Mating
Sequence
Host Lane Pins – 10x10G High Speed Electrical Interface
(Tx0-9, Rx0-9)
The AFBR-8420Z supports 10x10G CPPI compliant electrical interfaces as defined in Ethernet IEEE 803.ba specification. The electrical connector pinouts are per the CFP2
MSA 10x 10G specifications. A non-retimed CPPI interface
(per 802.3ba Clause 86A) is supported by bypassing the
internal per-channel CDRs. This reduces the current/power consumption and reduces the thermal impact to the
host system; this is the default state of the module.
All CDRs (Tx path, Rx path) as depicted in Transceiver Block
Diagram are bypassed by default. The user must access
the appropriate register to turn all CDRs on. CDR status is
controlled by MDIO CFP VR1 register A015 bits 7-0 (09h =
CPPI is the default for CDRs off, 01h = turn CDRs on).
All electrical inputs and outputs are internally ac coupled
with the CFP2 housing. Differential impedances are nominally 100 Ω.
Network Lanes – 10x10G High Speed Optical Interface (Tx0-9,
Rx0-9)
The AFBR-8420Z supports 10x10G SR10 multi-mode fiber
optic interfaces as defined in Ethernet IEEE 802.3 Clause
86, including optical lane assignments (MPO optical connector) and link specifications.
Global Alarm Pin: (GLB_ALRMn)
The GLB_ALRMn signal pin is an output from the CFP2
module to the host using active low logic (i.e., Logic Low is
an alarm condition, Logic High is normal operation). When
GLB_ALRMn is asserted (driven Low) it indicates a Fault,
Alarm, Warning or Status event has occurred. This reduces
the need for continuous polling of status and monitor registers, while maintaining timely alerts to significant events.
GLB_ALRMn can be programmed as the LOGIC OR of the
multiple inputs inputs (all of which can be read, cleared
and masked in the Memory Map), including
• Module Temperature Alarms
• Module Vcc Alarms
• Global Rx_LOS Alarm
Module Reset Pin: (MOD_RSTn)
The MOD_RSTn signal pin is an input pin from the host to
the CFP2 module using active low logic (i.e., Logic Low resets the CFP2 module). This pin is pulled down in the CFP2
with a resistor value of 4.7 kΩ to 10 kΩ.
Module Low Power Mode Enable Pin: (MOD_LOPWR)
The MOD_LOPWR signal pin is an input from the host to
the CFP2 module using active high logic (i.e., Logic High
sets the CFP2 to low power mode, Logic Low sets the CFP2
to high power mode). When the module is in low power
mode it has a maximum power consumption of 2 W.
11
Module Absent (Not Present) Pin: (MOD_ABS)
(i.e., Logic High indicates a CFP2 is absent in the port, Logic Low indicates a CFP2 is present in the port).
Optical Transmitter Disable Pin: (TX_DIS)
The TX_DIS signal pin is an input from the host to the CFP2
module using active high logic (i.e., Logic High disables
the CFP2 optical transmitters; Logic Low enables the CFP2
optical transmitters). This pin is pulled upside in the module and must be pulled down by the host to enable optical
transmission.
While in the disabled state, the transmitter alarm and
warning flags associated with transmit optical power and
laser current will assert. To mask these flags from alarming
the host, the user must configure the related masking bits
in A220-A229 and A240-A249.
Optical Receiver Loss of Signal Pin: (RX_LOS)
The RX_LOS signal pin is an output from the CFP2 module
to the host using active high logic (i.e., Logic High indicates one or more CFP2 optical inputs are not receiving
a valid signal; Logic Low indicates all CFP2 optical inputs
are receiving a valid signal).
The RX_LOS triggers on a loss of optical modulation as detected at the optical receiver.
Management Data I/O, Clock and Address Pins: (MDIO, MDC,
PRTADR0, PRTADR1, PRTADR2)
The CFP2 management data interface consists of 5 pins,
including 1 pin for a clock, 1 pin for data and 3 pins for a
physical port address definition.
• MDC is the MDIO clock line driven by the host
• MDIO is the bi-directional data line driven by both the
host and the CFP2, depending on data direction.
The MDIO bus structure follows specifications in IEEE
802.3 Clause 45 at a clock rate up to 4.0 MHz.
• PRTADR0, PRTADR1, PRTADR2 are the MDIO Physical
Port address bits 0, 1 and 2
These control pins are used for the system to address all
of the CFP ports contained within a host system. PRTADR0
corresponds to the LSB in the physical port addressing
scheme. The 5-wire Physical Port Address lines are driven
by host to set the module Physical Port Address which
should match the address specified in the MDIO Frame.
PRG_CNTLx Behavior:
PRG_CNTL2, PRG_CNTL3 are used as HW_IL_LSB and HW_
IL_MSB during the Initialize state (Hardware Interlock).
PRG_CNTL1 will be set as default = TXRXIC_RSTn.
After Initialization, the user may assign/un-assign TXRXIC_RSTn function to PRG_CNTL1 and/or PRG_CNTL2 and/
or PRG_CNTL3 using Registers A005h, A006h and A007h.
If TRXIC_RSTn is then asserted the signal integrity / loopback chips will be reset. For example, if the module is in
“CDRs ON Mode” and the user asserts TRXIC_RSTn, this will
cause a reset of the signal integrity chips. The module will
revert back to “CDRs Bypass Mode”, since “CDRs Bypass
Mode” is the DEFAULT state of the Module.
Hardware Interlock
The Hardware Interlock provides for four different power
consumption levels. The module shall compare the maximum power dissipation under vendor specified operating
conditions to the host system cooling capacity value communicated via the Hardware Interlock.
Hardware Interlock Description
Power
Dissipation (W)
Examples of features not required, and therefore, not implemented for this CFP2 100GBASE-SR10 Module media
are complex power on sequences related to managing internal laser cooling (section 4.1.2, 4.2 and 4.3), advanced
host and network lane considerations related to electrical
or optical multiplexers (section 4.9, 4.12), etc..
MSB
LSB
Power
Class
0
0
1
≤3
0
1
2
≤6
The CFP2 100GBASE-SR10 Module, AFBR-8420Z, provides
digital diagnostic functionality for parameters of laser
bias, laser optical power, received optical power, Vcc and
temperature. It has variable host lane equalization.
1
0
3
≤9
Enable and Disable CDRs
1
1
≥4
>9
All Tx CDRs and All Rx CDRs will be turned on with a single command to put the Transceiver into retimer mode.
These CDRs cannot be enabled on a per individual channel basis. Furthermore, the user cannot separately turn on
Tx CDRs or Rx CDRs.
PRG_ALRMx Behavior
PRG_ALRMx behavior can be assigned using Registers
A008, A009, A00A, per the CFP2 MSA definition. Note,
however, that some alarm capabilities do not exist in our
CFP2 SR10 module and therefore cannot be assigned to
the PRG_ALRMx pins. Below is a list of the possible PRG_
ALRMx assignments.
7:0 Alarm Source Code PRG_ALRMx;
Selects, and assigns, an alarm source for PRG_ALRMx
= 0: Not active, always de-asserted
NOT SUPPORTED
= 1: HIPWR_ON
SUPPORTED
= 2: Ready State
SUPPORTED
= 3: Fault State, MSA default setting
SUPPORTED
= 4: RX_ALRM = RX_LOS +
RX_NETWORK_LOL
SUPPORTED ONLY
FOR RX_LOS, NOT FOR
RX_NETWORK_LOL
= 5: TX_ALRM = TX_LOSF +
TX_HOST_LOL + TX_CMU_LOL
NOT SUPPORTED
= 6: RX_NETWORK_LOL
NOT SUPPORTED
= 7: TX_LOSF
NOT SUPPORTED
= 8: TX_HOST_LOL
NOT SUPPORTED
= 9: OOA, Out of alignment
NOT SUPPORTED
Other and Unused Pins:
REFCLKp, REFCLKn pins are not used in the AFBR-8420Z
and can be left Not Connected (NC). These pins are internally terminated with a capacitor and resistor to ground
internal to the CFP2 Module AFBR-8420Z.
Software Control/Status Indicators
Software feature sets for AFBR-8420Z are defined in the
CFP Management Interface Specification (MIS), Version
2.2. Software features are accessible using the MDIO interface per the CFP MSA.
12
This CFP2 100GBASE-SR10 Module is less complex than
other types of transceivers found in the CFP/CFP2 footprint; for example LR4-type modules. Therefore this module does not support many of the elaborate functions defined in the CFP MIS.
The CFP2 module is in CDR Bypass, CPPI mode by default;
the CDRs will be bypassed by default and 0x09h will be
the value in Register A015 bits 7-0 (CPPI mode).
To enable all CDRs and enter retimer mode, the user must
write value 0x01h to Register A015 bits 7-0.
Enable Network Lane Loopback (OLoop/OWrap)
The Network Lane Loopback will be disabled by default.
To enable the Network Lane Loopback (Oloop/Owrap)
write a value of ‘1’ to bit 10 in Register A012.
Enable Host Lane Loopback (ELoop/EWrap)
The Host Lane Loopback will be disabled by default. To
enable the Host Lane Loopback (Eloop/Ewrap) write a
value of ‘1’ to bit 10 in Register A014.
TX Squelch
Tx_LOS turns off the laser on a per channel basis when
there is no high-speed modulation on the electrical differential inputs on a per channel basis. This squelch feature
is always enabled.
RX LOS and Squelch
Rx_LOS is based on OMA level of the incoming optical signal. RX_LOS triggers on loss of modulation (as opposed to
a loss of average optical power)
Password Protected Fields
MSA specifies the default user password value as 0101
1100h. This opens up the User NVR1 and User NVR2 pages
only in Registers 8800h and 8880h.
Vendor NVR1 and 2 has a different password than the User
NVR. The default user password for the Vendor NVR1 and
NVR2 is 8101 1100h. This opens up the Vendor NVR1 and
Vendor NVR2 pages only in Registers 8400h and 8480h.
Memory Map
Block Hex
Name Addr
Size Access Type
NVR1
CFP
1
1
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009
1
1
1
1
1
1
1
1
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Register Name
Value
Description
LSB Unit
7-0
7-6
5-4
Module Identifier
Power Class
Lane Ratio Type
11h
A0h
n/a
n/a
3-1
0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-4
WDM type
CLEI Presence
Connector Type
Ethernet Application
Fibre Channel App
Copper Application
Sonet Application
OTN Application
Additional Rates
Network Lanes
3-0
Host Lanes
4Ah
38h
CFP2 Module Identifier
(10b bits 7-6) CFP2 Power Class 1 < 9 W
(10b bits 5-4) Host to Network Lane Ratio Type n:n
(10:10 parallel)
(000b bits 3-1) Non-WDM Type
(0b bit 0) No CLEI code present
MPO optical connector
Ethernet Application 100GE MMF 100GBASE-SR10
undefined
undefined
undefined
undefined
Not supported
(Ah bits 7-4) Decimal Value = 10
[10 network optical lanes]
(Ah bits 3-0) Decimal Value = 10
[10 host electrical lanes]
MMF (01b bits 7-6) for OM3/OM4.
0 b = Normal
0 b = WITHOUT optical Mux/Demux
(Ah bits 3-0) Decimal Value = 10
[i.e., 10 TxRx lanes active per connector ]
Decimal Value = 56
[i.e., 56 x 0.2 Gb/2 = 11.2 Gb/s lane rate]
Decimal Value = 56
[i.e., 56 x 0.2 Gb/2 = 11.2 Gb/s lane rate]
Undefined for MMF links
Decimal Value = 10
[i.e., 10 x 10 m = 100 m maximum MM OM3 length]
Maximum OM4 length is 150 m in register 8181.
Undefined for MMF links
Decimal Value = 10 Active Transmit Fibers
Per MSA, 00h represents 850 nm MMF source.
(Alt = 01h)
Per MSA, 00h represents MMF source.
(Alt = 8340h for Decimal Value = 33,600)
[ie. 33,600 x 0.025 nm = 840 nm]
Per MSA, 00h represents MMF source.
(Alt = 8660h for Decimal Value = 33,600)
[i.e., 34,400 x 0.025 nm = 860 nm]
Per MSA, 00h represents MMF source.
(Alt = 028Ah for Decimal Value = 650)
[i.e., 650 * .001 nm = 0.65 nm]
(0000b bits 7-4)
Per MSA for VCSEL source technology
(0000b bits 0-3)
DML - Direct modulation Tx technology
(0000b bits 7-4)
No VOA, tunable, cooling, wavelength ctrl
PIN detector (01b bits 3-2),
CDR without EDC (0b bit 1)
NRZ (01b bits 7-6)
n/a
09h
03h
00h
00h
00h
00h
00h
AAh
800A 1
Read Only
7-6
5
4
3-0
800B 1
Read Only
7-0
Media Type
Directionality
Optical Muxing
Active Fibers per Connector
Max Network Lane Rate
800C 1
Read Only
7-0
Max Host Lane Rate
800D 1
800E 1
Read Only
Read Only
7-0
7-0
Max SM fiber length
00h
Max MM OM3 fiber length 0Ah
800F
8010
8011
1
1
1
Read Only
Read Only
Read Only
7-0
7-0
7-0
Max Cu cable length
Number Tx Fibers
Number Tx Wavelengths
00h
0Ah
00h
8012
2
Read Only
7-0
Min Tx Wavelength
(MSB 8012, LSB 8013)
0000h
8014
2
Read Only
7-0
Max Tx Wavelength
(MSB 8014, LSB 8015)
0000h
8016
2
Read Only
7-0
Max Tx Optical Width
(MSB 8016, LSB 8017)
0000h
8018
1
Read Only
7-4
Laser Source Type
00h
3-0
Tx Modulation Type
7-4
Tx Device Technology
3-0
Detector Type, CDR Type
7-6
Signal Modulation
5-0
Signal Encoding
8019
1
801A 1
13
Read Only
Read Only
8
Bits
Read Only
Read Only
38h
04h
40h
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
0.2 Gb
0.2 Gb
1 km
10 m
1m
n/a
n/a
.025 nm
.025 nm
0.001 nm
n/a
n/a
Non-PSK coding (0000b bits 5-0)
801B 1
Read Only
7-0
Max Output Power
11h
Decimal Value = 17
[i.e., 17 * 0.1 mW = 1.74 mW = +2.4 dBm]
0.1 mW
801C 1
Read Only
7-0
Max Input Power
11h
Decimal Value = 17
[i.e., 17 * 0.1 mW = 1.74 mW = +2.4 dBm]
0.1 mW
Block Hex
Name Addr
NVR1
CFP
14
Size Access Type
8
Bits
Register Name
Description
LSB Unit
801D 1
801E 1
801F 1
Read Only
Read Only
Read Only
7-0
7-0
7-0
Max Power Consumption 2Dh
LOW Power Consumption 64h
Max Operating Case Temp 46h
Value
Decimal Value = 45 [i.e., 45 * 200 mW = 9 W]
Decimal Value = 100 [i.e., 100 * 20 mW = 2 W]
200 mW
20 mW
[i.e., 70 * 1 °C = 70 °C]. Signed Two’s compliment
1 °C
8020
1
Read Only
7-0
Min Operating Case Temp
00h
8021
8022
8023
8024
8025
8026
8027
8028
8029
802A
802B
802C
802D
802E
802F
8030
8031
8032
8033
8034
8035
8036
8037
8038
8039
803A
803B
803C
803D
803E
803F
8040
8041
8042
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read Only
7-0
Vendor Name
1 °C
n/a
Read Only
7-0
Vendor OUI
Read Only
7-0
Vendor Part Number
41h
56h
41h
47h
4Fh
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
00h
17h
6Ah
41h
46h
42h
52h
2Dh
38h
34h
32h
30h
5Ah
20h
20h
20h
20h
20h
[i.e., 0 * 1 °C = 0 °C]. Signed Two’s compliment
ASCII "A"
ASCII "V"
ASCII "A"
ASCII "G"
ASCII "O"
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
Avago OUI
Avago OUI
Avago OUI
ASCII "A"
ASCII "F"
ASCII "B"
ASCII "R"
ASCII "-"
ASCII "8"
ASCII "4"
ASCII "2"
ASCII "0"
ASCII "Z"
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
8043
8044
8045
8046
8047
8048
8049
804A
804B
804C
804D
804E
804F
8050
8051
8052
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
20h
ASCII blank
Read Only
7-0
Vendor Serial Number
8053
1
n/a
n/a
n/a
Block Hex
Name Addr
Size Access Type
NVR 1 8054
CFP
8055
8056
8057
8058
8059
805A
805B
805C
805D
805E
805F
8060
8061
8062
8063
8064
8065
8066
8067
8068
8069
806A
806C
806E
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
806F
1
Read Only
8070
15
1
8
Bits
Register Name
Read Only
7-0
Date Code
Read Only
7-0
Lot Code
Read Only
7-0
CLEI Code
Read Only
Read Only
Read Only
Read Only
Read Only
7-0
7-0
7-0
7-0
7-4
3
2
1-0
7-6
5-4
3
2
CFP2 MSA HW Spec Rev
CFP MSA MIS Spec Rev
Module Hardware Revision
Module Firmware Revision
Reserved
DDM Rx Opt PWR Monitor type
DDM Tx Opt PWR Monitor type
Reserved
DDM Capability - AUX 2
DDM Capability - AUX 1
Reserved
Transceiver SOA Bias Mon
1
0
7-4
3
Transceiver Vcc Monitor
Transceiver Temp Monitor
Reserved
Network Lane Rx Opt PWR
2
Network Lane Tx BIAS
1
Network Lane Tx Opt PWR
0
Network Lane Laser Temp
Read Only
Value Description
LSB
Unit
n/a
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
0Ah
16h
ASCII Blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII blank
ASCII Blank
Decimal Value = 10 [i.e., 10 * 0.1 rev = Revision 1.0]
Decimal Value = 22 [i.e., 22 * 0.1 rev = Revision 2.2]
0Ch
Reserved
Rx Power measurement type (1b = Average Power)
Tx Power measurement type (1b = Average Power)
Reserved
Auxiliary Monitor 2 (00b = Not Supported)
Auxiliary Monitor 1 (00b = Not Supported)
Reserved
Transceiver SOA Bias Current Monitor (0b = Not
Supported)
Transceiver Vcc Voltage Monitor (1b = Supported)
Transceiver Temperature Monitor (1b = Supported)
Reserved
Per Channel Rx Optical Power Monitor
(1b = Supported)
Per Channel Tx Laser Bias Monitor
(1b = Supported)
Per Channel Tx Optical Power Monitor
(1b = Supported)
Per Channel Laser Temperature Monitor
(0b = Not Supported)
03h
0Eh
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Block Hex
Name Addr
NVR 1 8071
CFP
Size Access Type
8
Bits
Register Name
Value Description
LSB
Unit
1
7
Host Lane Loop-back
B0h
n/a
6
Host Lane PRBS
5
4
Host Lane EMPHASIS
Network Lane Loop-back
3
Network Lane PRBS
2
FEC Decision V threshold
1
0
7-0
7-0
7-0
FEC Decision Ph Threshold
Unidirectional TXRX Modes
Maximum HIGH Power Up Time 03h
Maximum TX Turn On Time
03h
Host Lane Signal Specification FFh
7-1
0
7-0
7-0
Reserved
Heat Sink Type
Maximum TX Turn OFF Time
Maximum HIGH Power DOWN
Time
Reserved
Host lane EQ Control Function
Active Decision Voltage/Phase
Fnct
Rx FIFO Reset
Rx FIFO Auto Reset
Tx FIFO Reset
Tx FIFO Auto Reset
Tx MCLK Option 7
Tx MCLK Option 6
Tx MCLK Option 5
Tx MCLK Option 4
Reserved
Tx MCLK Option 2
Tx MCLK Option 1
Tx MCLK Monitor Option
Rx MCLK Option 7
Rx MCLK Option 6
Rx MCLK Option 5
Rx MCLK Option 4
Reserved
Rx MCLK Option 2
Rx MCLK Option 1
Rx MCLK Monitor Option
Module Firmware B Version
Electrical Lane Tx,in to Rx,out Loopback
(1b = Supported)
Electrical Lane PRBS Generator
(0b = Not Supported)
Rx Output Emphasis Control (1b = Supported)
Optical Lane Rx,in to Tx,out Loopback
(1b = Supported)
Optical Lane Tx PRBS Generator
(0b = Not Supported)
FEC Decision Voltage Threshold
(0b = not applicable)
FEC Decision Phase Threshold (0b = not applicable)
Uni-Directional Modes (0b = not applicable)
Decimal Value = 3 [i.e., 3 * 1 sec = 3 sec]
Decimal Value = 3 [i.e., 3 * 1 sec = 3 sec]
This is set to FFh and refer to address 81C7
for expanded capabilities. CPPI = 06h (CDR off )
and CDRs on = 01h
Reserved
Flat Top Heat Sink =0b.
Decimal Value = 100 [i.e., 100 * 1 ms = 100 ms]
Decimal Value = 1 [i.e., 1 * 1 sec = 1 sec]
Reserved
1b = Supported
0b = Not supported
n/a
8072
8073
8074
1
1
1
Read Only
Read Only
Read Only
8075
1
Read Only
8076
8077
1
1
Read Only
Read Only
8078
1
Read Only
8079
1
807A 1
16
Read Only
Read Only
Read Only
807B 1
807C 1
807D 1
Read Only
807E
1
Read Only
807F
1
Read Only
Read Only
7-6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7-0
7-0
7-0
Max MDIO Ready Time
7-6
5
Extended Power Class
MDIO Port Address Scheme
4-0
7-0
Reserved
CFP NVR1 Checksum
00h
64h
01h
20h
00h
00h
00h
00h
03h
20h
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
0b = Not supported
Two address register format x.y with x at lower, y at
higher.
3 sec
3 sec
n/a
n/a
1 ms
1 sec
n/a
n/a
n/a
3 sec = 03h. Max ready time due to software
upgrade
00b. Not needed. [See Address 8001 Bits 7-6 = 10b]
1b = CFP2/CFP4 common MDIO port address
scheme
03h
CHECKSUM for 8000-807Eh inclusive
n/a
20h
Block Hex
Name Addr
Size Access Type
8
Bits
Register Name
Value
Description
LSB
Unit
NVR 2 8080
CFP
8082
2
Read Only
7-0
Module Temp High Alarm Threshold
4B00h
Module Temp High Alarm Threshold: 75 °C
1/256°
2
Read Only
7-0
Module Temp High Warning Threshold 4600h
Module Temp High Warning Threshold: 70 °C
8084
2
Read Only
7-0
Module Temp Low Warning Threshold
0000h
Module Temp Low Warning Threshold: 0 °C
8086
2
Read Only
7-0
Module Temp Low Alarm Threshold
FB00h
8088
808A
808C
808E
8090
8092
9094
8096
8098
809A
809C
809E
2
2
2
2
2
2
2
2
2
2
2
2
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
Module Vcc High Alarm Threshold
Module Vcc High Warning Threshold
Module Vcc Low Warning Threshold
Module Vcc Low Alarm Threshold
SOA threshold
SOA threshold
SOA threshold
SOA threshold
AUX1 threshold
AUX1 threshold
AUX1 threshold
AUX1 threshold
8DCCh
875Ah
7A75h
7404h
00h
00h
00h
00h
00h
00h
00h
00h
Module Temp Low Alarm Threshold: -5 °C
Module Vcc High Alarm Threshold: 3.63 V
Module Vcc High Warning Threshold: 3.465 V
Module Vcc Low Warning Threshold: 3.315 V
Module Vcc Low Alarm Threshold: 2.97 V
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
80A0
80A2
80A4
80A6
80A8
80AA
80AC
80AE
80B0
2
2
2
2
2
2
2
2
2
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
AUX2 threshold
AUX2 threshold
AUX2 threshold
AUX2 threshold
Laser Bias High Alarm Threshold
Laser Bias High Warning Threshold
Laser Bias Low Warning Threshold
Laser Bias Low Alarm Threshold
Laser PWR High Alarm Threshold
00h
00h
00h
00h
1388h
128Eh
01F4h
00FAh
5575h
80B2
2
Read Only
7-0
Laser PWR High Warning Threshold
43E2h
80B4
2
Read Only
7-0
Laser PWR Low Warning Threshold
06C9h
80B6
2
Read Only
7-0
Laser PWR Low Alarm Threshold
0564h
80B8
80BA
80BC
80BE
80C0
2
2
2
2
2
Read Only
Read Only
Read Only
Read Only
Read Only
7-0
7-0
7-0
7-0
7-0
Laser Temp threshold
Laser Temp threshold
Laser Temp threshold
Laser Temp threshold
Receive PWR High Alarm Threshold
00h
00h
00h
00h
5575h
80C2
2
Read Only
7-0
Receive PWR High Warning Threshold
43E2h
80C4
2
Read Only
7-0
Receive PWR Low Warning Threshold
0462h
80C6
2
Read Only
7-0
Receive PWR Low Alarm Threshold
02C3h
17
not supported
not supported
not supported
not supported
Laser Bias High Alarm Threshold: 10 mA
Laser Bias High Warning Threshold: 9.5 mA
Laser Bias Low Warning Threshold: 1 mA
Laser Bias Low Alarm Threshold: 0.5 mA
Laser PWR High Alarm Threshold:
3.4 dBm (Average Power)
Laser PWR High Warning Threshold:
2.4 dBm (Average Power)
Laser PWR Low Warning Threshold:
-7.6 dBm (Average Power)
Laser PWR Low Alarm Threshold:
-8.6 dBm (Average Power)
not supported
not supported
not supported
not supported
Receive PWR High Alarm Threshold:
3.4 dBm (Average Power)
Receive PWR High Warning Threshold:
2.4 dBm (Average Power)
Receive PWR Low Warning Threshold:
-9.5 dBm (Average Power)
Receive PWR Low Alarm Threshold:
-11.5 dBm (Average Power)
0.1 mV
2 µA
0.1 µW
0.1 µW
Block Hex
Name Addr
Size Access Type
8
Bits
Register Name
Value
Description
LSB
Unit
NVR 2 80C8
CFP
80CA
80CC
80CE
80DO
80D2
80D4
80D6
80D8
80DA
80DC
80DE
80EO
80E2
80E4
80E6
80E8
80EA
80EC
80EE
80F0
80F2
80F4
80F6
80F8
80FF
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
7
1
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
Rx Laser Bias Current Alarm
Rx Laser Bias Current Warn
Rx Laser Bias Current Alarm
Rx Laser Bias Current Warn
Rx Laser Output Pwr Alarm
Rx Laser Output Pwr Warn
Rx Laser Output Pwr Alarm
Rx Laser Output Pwr Warn
Rx Laser Temperature Alarm
Rx Laser Temperature Warn
Rx Laser Temperature Alarm
Rx Laser Temperature Warn
Tx Modulator Bias Alarm
Tx Modulator Bias Warn
Tx Modulator Bias Alarm
Tx Modulator Bias Warn
Host RX Opt Pwr High Alarm
Host RX Opt Pwr High Warn
Host RX Opt Pwr Low Alarm
Host RX Opt Pwr Low Warn
Host RX Opt Pwr High Alarm
Host RX Opt Pwr High Warn
Host RX Opt Pwr Low Alarm
Host RX Opt Pwr Low Warn
Reserved
CFP NVR2 Checksum
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
not supported
CHECKSUM for 8080-80FEh inclusive
n/a
Block Hex
Name Addr
Size Access Type
8
Bits
Register Name
Value
Description
LSB
Unit
NVR 3 8100
CFP
8120
8140
8160
32
32
32
32
7-0
7-0
7-0
7-0
Rx Sensitivity Spec Network Lanes
Tx Power Spec Network Lanes
Measured ER Network Lanes
Path Penalty Network Lanes
00h
00h
00h
00h
Not supported
Not supported
Not supported
Not supported
0.01 dBm
0.01 dBm
0.01 dB
0.01 dB
18
Read Only
Read Only
Read Only
Read Only
Block Hex
Name Addr
Size Access Type
8
Bits
Register Name
Value
Description
LSB
Unit
NVR 4 8180
CFP
1
Read Only
7-0
Checksum for NVR 3
00h
8181
1
Read Only
7-0
Max MM OM4 fiber length
0Fh
8182
8184
8186
8188
818A
818C
818E
8190
8192
8194
8196
8198
81A0
81A8
81B0
81B8
81C0
81C6
81C7
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
8
6
1
1
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
15-0
15-0
15-0
15-0
15-0
15-0
15-0
15-0
15-0
15-0
15-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7
6
5
4
3
2
1
0
Extended Identifiers
Extended Max Network Lane Rate
Extended Max Power Consumption
Extended Max Power Low Mode
Tx/Rx Min Laser Frequency 1
Tx/Rx Min Laser Frequency 2
Tx/Rx Max Laser Frequency 1
Tx/Rx Max Laser Frequency 2
Rx Laser Fine Tune Freq Range
Tx Laser Fine Tune Freq Range
Laser Tuning Capabilities
Reserved
Network Lane n Vendor Specific
Network Lane n Vendor Specific
Network Lane n Vendor Specific
Network Lane n Vendor Specific
Reserved
Host Lane Signal Mode Bit Map 1
Host Lane Signal Mode Bit Map 0
[ Reference Address 8074, A015 ]
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
41h
81C8
81FF
47
1
Read Only
Read Only
7-0
7-0
Reserved
CFP NVR 4 Checksum
00h
The 8-bit unsigned sum of all CFP NVR 3
contents from address 8100h through 817Fh,
inclusive
Decimal Value = 15 [i.e., 15 x 10 m = 150 m
max OM4 length] Max OM3 length is 100 m in
register 800E.
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
(0b bit 7) MLG1.0 not supported
(1b bit 6) CPPI Supported (Default, CDRs off )
(0b bit 5) CEI-28G-VSR not supported
(0b bit 4) CAUI-4f not supported
(0b bit 3) CAUI-4 not supported
(0b bit 2) SFI 5.2 not supported
(0b bit 1) XLAUI not supported
(1b bit 0) CAUI compatible supported
(with CDRs on)
Reserved
The 8-bit unsigned sum of all CFP NVR 4
contents from address 8181h through 81FEh,
inclusive
Block Name
Hex Addr
Size
Access Type
8 Bits
Register Name Value
Reserved
8200-83FF
512
Read Only
7-0
Reserved
Description
Block Name
Hex Addr
Size
Access Type
8 Bits
Register Name Value
Vendor NVR1
8400-847F
128
Mixed
7-0
Vendor NVR
1. Vendor
Data Registers
0000h
Vendor NVR2
8480-84FF
128
Mixed
7-0
Vendor NVR
2. Vendor
Data Registers
0000h
10 m
Initial Value
0000h
Description
Initial Value
Vendor NVR 1 and Vendor NVR 2 tables are allocated for storing additional data that can be used by the vendor. These are non-volatile fields. These
fields can only be read it if the vendor password has been inputted. Default vendor password is defined in the MSA. The user cannot write to these
registers even with a vendor password (hardcoded at the factory).
19
Block Name
Hex Addr
Size
Access Type
8 Bits
Register Name Value
Description
Initial Value
Reserved
8500-87FF
768
Read Only
7-0
Reserved
Block Name
Hex Addr
Size
Access Type
8 Bits
Register Name Value
User NVR1
8800-887F
128
Mixed
7-0
User NVR 1.
User Data
Registers
0000h
User NVR2
8880-88FF
128
Mixed
7-0
User NVR 2.
User Data
Registers
0000h
0000h
Description
Initial Value
The User NVR 1 and User NVR 2 tables are allocated for module user to store data. User has the full read/write access to these tables. These registers
are password accessible. Without an appropriate password, a read attempt shall return FFh.
Read – only with password, returns FFFF if no password given.
Write – only with same password. Once values have been written to these fields they are stored as non-volatile bytes.
Block Name
Hex Addr
Size
Access Type
8 Bits
Register Name Value
Reserved
8900-9FFF
5888
Read Only
7-0
Reserved
Block Hex
Name Addr
VR 1
CFP
A000
Description
Initial Value
0000h
Size
Access Type
16
Bits
Register Name
Description
2
Write Only
15-0
Password Entry
Password for module registers access control. Two word value.
MSW is in the lower address. Reading these returns FFFFh.
Password allows Non-Volatile Writes to
8800 [128 Bytes User Data Registers NVR1]
8880 [128 Bytes User Data Registers NVR2]
Upon inputting the correct Password, the user has the full read/write
access to these registers.
Initial
Value
0000h
0000h
MSA specifies the default user password value as
0101 1100h. This opens up the User NVR1 and User NVR2 pages only
in Registers 8800h and 8880h.
Vendor NVR1 and 2 has a different password than the User NVR; it
is 8101 1100h. This opens up the Vendor NVR1 and Vendor NVR2
pages only in Registers 8400h and 8480h.
20
A002A003
2
Write Only
15-0
Password Change
New password entry. Two word value. MSW is in the lower address.
Reading these returns FFFFh.
The user password can be changed by writing the new value to the
Password Change registers A002h and A003h after a password entry
is successful. The new password value shall be stored and take effect
only after writing the Save User Password command to register
A004h.
0000h
0000h
A004
1
Read Write
15-9
Reserved
Not Supported.
0000h
Read Only
8-6
Reserved
Read Write
5
User Restore &
Save Command
Read Only
4
Reserved
Read Only
3-2
Command
Status
00b = Idle, 01b = Successful, 10b= In progress, 11 = Failed.
See MSA section 4.10.2 “User NVR Restore and Save Functions” for
proper operation
Read Write
1-0
Extended
Commands
00b = No effect. 11b = Restore/Save User NVRs
See MSA section 4.10.2 “User NVR Restore and Save Functions” for
proper operation
0= Restore User NVR Section, 1=Save User NVR Section
See MSA section 4.10.2 “User NVR Restore and Save Functions” for
proper operation
Block Hex
Name Addr
VR 1
CFP
A005
Size
Access Type
16
Bits
Register Name
1
Read Only
15-8
Reserved
Read Write
7-0
PRG_CNTL3
Function Select
Description
Initial
Value
0000h
7:0 RW This multi-function input is used as HW_IL_MSB during
the Initialize State and it can be programmed to other functions
afterward.
= 0: Assert/De-Assert of PRG_CNTL3 has no effect,
= 1: Assign TRXIC_RSTn function to hardware pins PRG_CNTL3.
When so assigned this pin uses the active low logic, that is, 0 =
Assert (Reset). Note that when so assigned, its soft counterpart Soft
PRG_CNTL3 Control (A010h.12) uses an active high logic, that is, 1 =
Assert (Reset).
= 2-255: Reserved.
A006
1
Read Only
15-8
Reserved
Read Write
7-0
PRG_CNTL2
Function Select
0000h
= 0: Assert/De-Assert of PRG_CNTL2 has no effect,
= 1: Assign TRXIC_RSTn function to hardware pins PRG_CNTL2.
When so assigned this pin uses the active low logic, that is, 0 =
Assert (Reset). Note that when so assigned, its soft counterpart Soft
PRG_CNTL2 Control (A010h.12) uses an active high logic, that is, 1 =
Assert (Reset).
= 2-255: Reserved.
A007
A008
1
1
Read Only
15-8
Reserved
Read Write
7-0
PRG_CNTL1
Function Select
Read Only
15-8
Reserved
Read Write
7-0
PRG_ALRM3
Function Source
0001h
TRXIC_RSTn is the CFP MSA default function for PRG_CNTL1.
= 0: Assert/De-Assert of PRG_CNTL1 has no effect,
= 1: Assign TRXIC_RSTn function to hardware pins PRG_CNTL1.
When so assigned this pin uses the active low logic, that is, 0 =
Assert (Reset). Note that when so assigned, its soft counterpart Soft
PRG_CNTL1 Control (A010h.12) uses an active high logic, that is, 1 =
Assert (Reset).
= 2-255: Reserved.
0003h
7-0 Alarm Source Code PRG_ALRM3; Selects, and assigns, an alarm
source for PRG_ALRM3
PRG_ALRM3 MSA default = MOD_FAULT Fault State
= 0: Not active, always de-asserted,[NOT SUPPORTED]
= 1: HIPWR_ON,[SUPPORTED]
= 2: Ready State,[SUPPORTED]
= 3: Fault State, MSA default setting,[SUPPORTED]
= 4: RX_ALRM = RX_LOS + RX_NETWORK_LOL,
[SUPPORTED ONLY FOR RX_LOS, NOT FOR RX_NETWORK_LOL]
= 5: TX_ALRM = TX_LOSF + TX_HOST_LOL + TX_CMU_LOL,
[NOT SUPPORTED]
= 6: RX_NETWORK_LOL,[NOT SUPPORTED]
= 7: TX_LOSF,[NOT SUPPORTED]
= 8: TX_HOST_LOL,[NOT SUPPORTED]
= 9: OOA, Out of alignment, [NOT SUPPORTED]
21
Block Hex
Name Addr
VR 1
CFP
A009
Size
Access Type
16
Bits
Register Name
1
Read Only
15-8
Reserved
Read Write
7-0
PRG_ALRM2
Function Source
Description
Initial
Value
0002h
7:0 Alarm Source Code PRG_ALRM2; Selects, and assigns, an alarm
source for PRG_ALRM2
PRG_ALRM2 MSA default = MOD_READY, Ready State (startup
sequence done),
= 0: Not active, always de-asserted,[NOT SUPPORTED]
= 1: HIPWR_ON,[SUPPORTED]
= 2: Ready State,[SUPPORTED]
= 3: Fault State, MSA default setting,[SUPPORTED]
= 4: RX_ALRM = RX_LOS + RX_NETWORK_LOL,
[SUPPORTED ONLY FOR RX_LOS, NOT FOR RX_NETWORK_LOL]
= 5: TX_ALRM = TX_LOSF + TX_HOST_LOL + TX_CMU_LOL,
[NOT SUPPORTED]
= 6: RX_NETWORK_LOL,[NOT SUPPORTED]
= 7: TX_LOSF,[NOT SUPPORTED]
= 8: TX_HOST_LOL,[NOT SUPPORTED]
= 9: OOA, Out of alignment, [NOT SUPPORTED]
A00A
1
Read Only
15-8
Reserved
Read Write
7-0
PRG_ALRM1
Function Source
0001h
7:0 Alarm Source Code PRG_ALRM1; Selects, and assigns, an alarm
source for PRG_ALRM1
PRG_ALRM1 MSA default = HIPWR_ON Module high-power-on
indicator.
= 0: Not active, always de-asserted,[NOT SUPPORTED]
= 1: HIPWR_ON,[SUPPORTED]
= 2: Ready State,[SUPPORTED]
= 3: Fault State, MSA default setting,[SUPPORTED]
= 4: RX_ALRM = RX_LOS + RX_NETWORK_LOL,
[SUPPORTED ONLY FOR RX_LOS, NOT FOR RX_NETWORK_LOL]
= 5: TX_ALRM = TX_LOSF + TX_HOST_LOL + TX_CMU_LOL,
[NOT SUPPORTED]
= 6: RX_NETWORK_LOL,[NOT SUPPORTED]
= 7: TX_LOSF,[NOT SUPPORTED]
= 8: TX_HOST_LOL,[NOT SUPPORTED]
= 9: OOA, Out of alignment, [NOT SUPPORTED]
A00B
A00CA00F
22
1
4
Read Only
15-3
Reserved
Read Write
2-0
Bi-Directional Mode
Select
Read Only
7-0
Reserved
0000h
Not supported.
0000h
Block Hex
Name Addr
VR 1
CFP
A010
Size
1
Access
Type
16
Bits
Register Name
Description
Initial
Value
Read
Write
15
Soft MOD_RST control
1= Assert (similar to pin 28)
0000h
14
Soft MOD_LO_PWR control
1= Assert (similar to pin 26)
13
Soft Tx DIS Control (Global)
1= Assert (similar to pin 24)
12
Soft PRG_CNTL3 Control
Register bit for PRG_CNTL3 control function.
1: Assert
11
Soft PRG_CNTL2 Control
Register bit for PRG_CNTL2 control function.
1: Assert.
10
Soft PRG_CNTL1 Control
Register bit for PRG_CNTL1 control function.
1: Assert.
9
Soft GLB_ALRM Test
1=Assert to Generate a GLB_ALRM signal on the pin
29
8-6
Reserved
5
Tx_DIS Pin Status (Global)
Echoes pin 24 (Transmit Disable)
4
MOD_LO_PWR Pin Status
Echoes pin 26 (Module Low Power Mode)
3
Soft PRG_CNTL3 Pin Status
Logical state of the PRG_CNTL3 pin. 1: Assert.
2
Soft PRG_CNTL2 Pin Status
Logical state of the PRG_CNTL2 pin. 1: Assert.
1
Soft PRG_CNTL1 Pin Status
Logical state of the PRG_CNTL1 pin. 1: Assert.
Read
Only
A011
A012
23
1
1
0
Reserved
Read Only
15
Reserved
Read
Write
14
TX PRBS Generator Enable
Not supported
1213
Tx PRBS Pattern Select
Not supported
11
Tx DeSkew Enable
Not supported
10
Tx FIFO Reset
Not supported
9
TX FIFO Auto Reset
Not supported
8
Tx Reset
Not supported
Not supported
0000h
7-5
TX Module MCLK Control
Read Only
4
Reserved
Read
Write
3-1
TX Rate Select
Not supported
0
TX REF CLK Rate Select
Not supported
Read
Write
15
Active Decision Voltage/Phase
Control
Not supported
14
RX PRBS Checker Enable
Not supported
1312
Rx PRBS Pattern Select
Not supported
11
Rx Lock RX Module CLK to REF CLK
Not supported
10
Network Lane Loopback (OWRAP)
0 = Normal Operation,
1 = Network lane OLoop/OWRAP Enable
9
RX FIFO Auto Reset
Not supported
8
Rx Reset
Not supported.
7-5
RX Module MCLK Control
Not supported
4
Rx FIFO Reset
Not supported
3-1
RX Rate Select (Host side)
Not supported
0
RX REF CLK Rate Select
Not supported
0000h
Block
Name
Hex
Addr
Size Access Type
VR 1
CFP
A013
1
A014
A015
24
1
1
16
Bits
Register Name
Description
15
14
13
12
11
10
Tx_Disable Lane 15 (Network Lane)
Tx_Disable Lane 14 (Network Lane)
Tx_Disable Lane 13 (Network Lane)
Tx_Disable Lane 12 (Network Lane)
Tx_Disable Lane 11 (Network Lane)
Tx_Disable Lane 10 (Network Lane)
9
Tx_Disable Lane 9 (Network Lane)
8
Tx_Disable Lane 8 (Network Lane)
7
Tx_Disable Lane 7 (Network Lane)
6
Tx_Disable Lane 6 (Network Lane)
5
Tx_Disable Lane 5 (Network Lane)
Not supported
Not supported
Not supported
Not supported
Not supported
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
4
Tx_Disable Lane 4 (Network Lane)
3
Tx_Disable Lane 3 (Network Lane)
2
Tx_Disable Lane 2 (Network Lane)
1
Tx_Disable Lane 1 (Network Lane)
0
Tx_Disable Lane 0 (Network Lane)
Read Only
Read Write
15
14
13
12
11
10
Reserved
Tx PRBS Checker Enable
Tx PRBS Pattern 2
Tx PRBS Pattern 1
Tx PRBS Pattern 0
Host Lane Loop-back enable (EWRAP)
Read Only
Read Write
9-8
7
6
5
4
3-0
15
14
13-12
11
10
9
8
7-0
Reserved
Rx PRBS Generator Enable
Rx PRBS Pattern 2
Rx PRBS Pattern 1
Rx PRBS Pattern 0
Reserved
Enable Tx Network PRBS Modes
Enable Rx Network PRBS Modes
MCLK Selection (CFP4)
Tx Lane Offset Enable
Rx Lane Offset Enable
Rx PWR Monitor A/W Threshold Select
Reserved
Electrical Interface Format Select
[ Reference Address 8074, 81C7 ]
Read Write
Read Only
Read Write
Initial
Value
0000h
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0 = Laser Enabled,
1 = Laser Disabled (Laser turned OFF)
0000h
Not supported
Not supported
Not supported
Not supported
0 = Normal Operation,
1 = Host lane ELoop/EWRAP Enable
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
01h = CDRs on
09h = CPPI (Default, CDRs off )
0009h
Block Hex
Name Addr
VR 1
CFP
Access 16
Size Type Bits
A016 1
A017 1
A018 1
Block Hex
Name Addr
VR 1
CFP
25
Read
Only
Read
Only
Read
Only
Access
Size Type
A019 1
Read
Only
Register Name
Description
15-9
8
7
6
5
Reserved
High Power Down State
TX Turn Off State
FAULT State (MOD_FAULT)
READY State (MOD_READY)
4
3
2
1
0
15-0
TX Turn Off State
TX Off State
High Power Up State
Low Power State
Initialize State.
Reserved
15
14
13
12
11
10
9
8
7
6-5
4
3
2-1
0
GLB_ALRM Assertion Status
Host Lane FAULT/STATUS summary
Network Lane FAULT/STATUS summary
Network Lane ALARM/WARNING Summary
Module ALARM/WARNING "2" Summary
Module ALARM/WARNING "1" Summary
Module FAULT Summary
Module GENERAL STATUS summary
Module STATE summary
Reserved
CDB Command Completed
Vendor Specific FAWS
Reserved
Soft GLM_ALRM Test Status
16
Bits
Register Name
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lane 15 Alarm & Warning Summary
Lane 14 Alarm & Warning Summary
Lane 13 Alarm & Warning Summary
Lane 12 Alarm & Warning Summary
Lane 11 Alarm & Warning Summary
Lane 10 Alarm & Warning Summary
Lane 9 Alarm & Warning Summary
Lane 8 Alarm & Warning Summary
Lane 7 Alarm & Warning Summary
Lane 6 Alarm & Warning Summary
Lane 5 Alarm & Warning Summary
Lane 4 Alarm & Warning Summary
Lane 3 Alarm & Warning Summary
Lane 2 Alarm & Warning Summary
Lane 1 Alarm & Warning Summary
Lane 0 Alarm & Warning Summary
Not supported
Not supported
Not supported
Not supported
Not supported
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Logic OR of enabled bits of Network Lane Alarms/Warnings
Initial
Value
0000h
Transient. Not supported.
Transient. Not supported
0b = No Fault. 1b = FAULT
0b = Not Ready. 1b = MODULE READY
Realtime indicator. Module Fault can be caused by
a Vcc Fault on internal indicator
Transient. Not supported.
0b = Tx ON.
1b = Tx OFF (ie. Transmitters Disabled)
Transient. Not supported.
0b = Full Operation. 1b = Low Power State Enabled
Transient. Not supported.
0000h
Echoes pin 29
Not supported
Logic OR: Tx Opt OUT and Rx Opt IN Stages
Logic OR: Tx Opt OUT and Rx Opt IN Flags
Logic OR: All Alarm and Warning "2" Flags
Logic OR: All Alarm and Warning "1" Flags
Logic OR: All enabled inputs to Module FAULT
Logic OR: All enabled inputs to Module GEN STATUS
Logic OR: All enabled inputs to Module STATE
0000h
Logic OR: CDB status, complete successful or failed
Logic OR: All enable vendor specific FAWS
Software GLB_ALRM Test bit Status
Initial
Value
0000h
Block Hex
Name Addr
VR 1
CFP
Access 16
Size Type
Bits
A01A 1
Read
Only
A01B 1
Read
Only
A01C 1
Read
Only
Read
Only
A01D 1
Register Name
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15-0
Lane 15 Network Lane FAULT & STATUS
Lane 14 Network Lane FAULT & STATUS
Lane 13 Network Lane FAULT & STATUS
Lane 12 Network Lane FAULT & STATUS
Lane 11 Network Lane FAULT & STATUS
Lane 10 Network Lane FAULT & STATUS
Lane 9 Network Lane FAULT & STATUS
Lane 8 Network Lane FAULT & STATUS
Lane 7 Network Lane FAULT & STATUS
Lane 6 Network Lane FAULT & STATUS
Lane 5 Network Lane FAULT & STATUS
Lane 4 Network Lane FAULT & STATUS
Lane 3 Network Lane FAULT & STATUS
Lane 2 Network Lane FAULT & STATUS
Lane 1 Network Lane FAULT & STATUS
Lane 0 Network Lane FAULT & STATUS
Lane 15 Host Lane FAULT & STATUS
Lane 14 Host Lane FAULT & STATUS
Lane 13 Host Lane FAULT & STATUS
Lane 12 Host Lane FAULT & STATUS
Lane 11 Host Lane FAULT & STATUS
Lane 10 Host Lane FAULT & STATUS
Lane 9 Host Lane FAULT & STATUS
Lane 8 Host Lane FAULT & STATUS
Lane 7 Host Lane FAULT & STATUS
Lane 6 Host Lane FAULT & STATUS
Lane 5 Host Lane FAULT & STATUS
Lane 4 Host Lane FAULT & STATUS
Lane 3 Host Lane FAULT & STATUS
Lane 2 Host Lane FAULT & STATUS
Lane 1 Host Lane FAULT & STATUS
Lane 0 Host Lane FAULT & STATUS
Reserved
Not supported
Not supported
Not supported
Not supported
Not supported
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Logic OR of enabled bits of Network Lane FAULT & STATUS
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
15-14
13
12-11
10
9
8
7
6
5
4
3
Reserved
HW_Interlock Status
Reserved
LOSS of REF_CLK Input Alarm
TX_JITTER_PLL_LOL Alarm
TX_CMU_LOL Alarm
TX_LOSF Alarm
TX_HOST_LOL Alarm
RX_LOS Alarm
RX_NETWORK_LOL Alarm
Out of Alignment Alarm (Host Lane
Skew)
Reserved
HI_PWR_ON Status
Reserved
2
1
0
26
Initial
Value
0000h
0000h
0000h
0000h
0 = Safe to use Module, 1= Hotter than System Cooling
Not supported
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = RxLOS Logic OR all Network Lane RX LOS
Not supported
Not supported
0= Lower Power Mode, 1= Module in HI PWR MODE
Block
Name
Hex
Addr
Size Access Type
VR 1
CFP
A01E
1
A01F
Read Only
A020
A021
A022
27
Read Only
Read Only
1
1
Read Only
Read/COR
16
Bits
Register Name
15-7
6
5
Reserved
PLD or FLASH Initialization FAULT Alarm
Power Supply FAULT Alarm
4-2
1
0
15-12
11
10
9
8
7
6
5
4
3
2
1
0
15-8
7
6
5
4
3
2
1
0
15-0
15-9
8
7
6
5
4
3
Reserved
CFP Checksum FAULT Alarm
Reserved
Reserved
Module Temperature HIGH Alarm
Module Temperature HIGH Warning
Module Temperature LOW Warning
Module Temperature LOW Alarm
Module Vcc HIGH Alarm
Module Vcc HIGH Warning
Module Vcc LOW Warning
Module Vcc LOW Alarm
Module SOA HIGH Alarm
Module SOA HIGH Warning
Module SOA LOW Warning
Module SOA LOW Alarm
Reserved
Module AUX1 HIGH Alarm
Module AUX1 HIGH Warning
Module AUX1 LOW Warning
Module AUX1 LOW Alarm
Module AUX2 HIGH Alarm
Module AUX2 HIGH Warning
Module AUX2 LOW Warning
Module AUX2 LOW Alarm
Reserved
Reserved
HI_PWR_DOWN Status latched
TX_TURN_OFF Status latched
FAULT Status latched
READY Status latched
TX_TURN_ON Status Latched
TX_OFF Status Latched
2
1
HI_PWR_UP Status Latched
LOW PWR Status latched
0
Initialize Status latched
Description
Initial
Value
0000h
Not supported
0=Normal, 1= Asserted:
Internal power regulators declares fault
status
0 =Normal, 1 = Asserted
0000h
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
Not supported
Not supported
Not supported
Not Supported
0000h
Not supported
Not supported
Not supported
Not Supported
Not supported
Not supported
Not supported
Not Supported
0000h
0000h
Transient. Not supported.
Transient. Not supported
0b = No Fault. 1b = FAULT
0b = Not Ready. 1b = MODULE READY
Transient. Not supported.
0b = Tx ON.
1b = Tx OFF (ie. Transmitters Disabled)
Transient. Not supported.
0b = Full Operation.
1b = Low Power State Enabled
Transient. Not supported.
Block
Name
Hex
Addr
Size Access Type
VR 1
CFP
A023
1
A024
1
A025
28
Read/COR
Read/COR
A026
A027
Read/COR
Read/COR
1
Read/COR
16
Bits
Register Name
15-14
13
Reserved
HW_Interlock Status latched
12-11
10
9
8
7
6
5
Reserved
LOSS of REF_CLK Alarm latched
TX_JITTER_PLL_LOL Alarm latched
TX_CMU_LOL Alarm latched
TX_LOSF Alarm latched
TX_HOST_LOL Alarm latched
RX_LOS Alarm latched
4
3
2-0
15-7
6
5
RX_NETWORK_LOL Alarm latched
Out of Alignment Alarm (Host Skew) latched
Reserved
Reserved
PLD or FLASH Init FAULT Alarm latched
Power Supply FAULT Alarm Latched
4-2
1
0
15-12
11
10
9
8
7
6
5
4
3
2
1
0
15-8
7
6
5
4
3
2
1
0
15-0
Reserved
CFP Checksum FAULT Alarm Latched
Reserved
Reserved
Module Temperature HIGH Alarm Latched
Module Temperature HIGH Warning Latched
Module Temperature LOW Warning Latched
Module Temperature LOW Alarm Latched
Module Vcc HIGH Alarm Latched
Module Vcc HIGH Warning Latched
Module Vcc LOW Warning Latched
Module Vcc LOW Alarm Latched
Module SOA HIGH Alarm Latched
Module SOA HIGH Warning Latched
Module SOA LOW Warning Latched
Module SOA LOW Alarm Latched
Reserved
Module AUX1 HIGH Alarm Latched
Module AUX1 HIGH Warning Latched
Module AUX1 LOW Warning Latched
Module AUX1 LOW Alarm Latched
Module AUX2 HIGH Alarm Latched
Module AUX2 HIGH Warning Latched
Module AUX2 LOW Warning Latched
Module AUX2 LOW Alarm Latched
Optional Vendor Specific FAWS Latch
Description
Initial
Value
0000h
0 = Safe to use Module, 1= Hotter
than System Cooling
Not supported
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Latched.
Note: Set to 1 on any change (0->1 or
1->0) of RxLOS
Not supported
Not supported
0000h
Not supported
0=Normal, 1= Asserted: Logic OR of
VCC Alarm High & Low
0 =Normal, 1 = Asserted
0000h
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
0 =Normal, 1 = Asserted
Not supported
Not supported
Not supported
Not Supported
0000h
Not supported
Not supported
Not supported
Not Supported
Not supported
Not supported
Not supported
Not Supported
Not Supported
0000h
Block
Name
Hex
Addr
Size Access Type
VR 1
CFP
A028
1
A029
A02A
A02B
A02C
29
1
1
1
1
Read Only
Read Write
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Only
Read Write
Read Only
Read Write
Read Only
Read Only
Read Only
16
Bits
Register Name
Description
Initial
Value
15-9
8
7
6
5
Reserved
HI_PWR_DOWN (enable to GLB_ALRM)
TX_TURN_OFF (enable to GLB_ALRM)
FAULT enable (enable to GLB_ALRM)
READY enable (enable to GLB_ALRM)
4
3
2
1
TX_TURN_ON (enable to GLB_ALRM)
FAULT enable (enable to GLB_ALRM)
HI_PWR_UP (enable to GLB_ALRM)
LO_PWR enable (enable to GLB_ALRM)
0
15
14
13
12-11
10
9
8
7
6
5
4
3
0-2
15-7
6
5
4-2
1
0
15-12
11
10
9
8
7
6
5
4
3
2
1
0
15-8
7
6
5
4
3
2
1
0
Initialize enable (enable to GLB_ALRM)
GLB_ALRM Master Enable
Reserved
HW_Interlock Enable to GLB_ALRM
Reserved
LOSS of REF_CLK (enable to GLB_ALRM)
TX_JITTER_PLL_LOL (enable GLB_ALRM)
TX_CMU_LOL Alarm (enable GLB_ALRM)
TX_LOSF Alarm (enable to GLB_ALRM)
TX_HOST_LOL Alarm (enable GLB_ALRM)
RX_LOS (enable to GLB_ALRM)
RX_NETWORK_LOL A (enable GLB_ALRM)
Out of Alignment (enable to GLB_ALRM)
Reserved
Reserved
PLD FLASH Init FAULT (enable GLB_ALRM)
Power Supply FAULT (enable GLB_ALRM)
Reserved
CFP Checksum FAULT (enable GLB_ALRM)
Reserved
Reserved
Module Temp HIGH Alarm (enable to GLB_ALRM)
Module Temp HIGH Warning (enable to GLB_ALRM)
Module Temp LOW Warning (enable to GLB_ALRM)
Module Temp LOW Alarm (enable to GLB_ALRM)
Module Vcc HIGH Alarm (enable to GLB_ALRM)
Module Vcc HIGH Warning (enable to GLB_ALRM)
Module Vcc LOW Warning (enable to GLB_ALRM)
Module Vcc LOW Alarm (enable to GLB_ALRM)
Module SOA HIGH Alarm (enable to GLB_ALRM)
Module SOA HIGH Warning (enable to GLB_ALRM)
Module SOA LOW Warning (enable to GLB_ALRM)
Module SOA LOW Alarm (enable to GLB_ALRM)
Reserved
Module AUX1 HIGH Alarm (enable to GLB_ALRM)
Module AUX1 HIGH Warning (enable to GLB_ALRM)
Module AUX1 LOW Warning (enable to GLB_ALRM)
Module AUX1 LOW Alarm (enable to GLB_ALRM)
Module AUX2 HIGH Alarm (enable to GLB_ALRM)
Module AUX2 HIGH Warning (enable to GLB_ALRM)
Module AUX2 LOW Warning (enable to GLB_ALRM)
Module AUX2 LOW Alarm (enable to GLB_ALRM)
006Ah
Transient. Not supported.
Transient. Not supported
0b = No Fault. 1b = FAULT
0b = Not Ready.
1b = MODULE READY
Transient. Not supported.
0b = No Fault. 1b = FAULT
Transient. Not supported.
0b = Full Operation.
1b = Low Power State Enabled
Transient. Not supported.
0=disable, 1=enable
A020h
0=disable, 1=enable
Not supported
Not supported
Not supported
Not supported
Not supported
0=disable, 1=enable
Not supported
Not supported
0022h
Not supported
0=disable, 1=enable
0=disable, 1=enable
0FF0h
0=disable, 1=enable
0=disable, 1=enable
0=disable, 1=enable
0=disable, 1=enable
0=disable, 1=enable
0=disable, 1=enable
0=disable, 1=enable
0=disable, 1=enable
Not supported
Not supported
Not supported
Not Supported
0000h
Not supported
Not supported
Not supported
Not Supported
Not supported
Not supported
Not supported
Not Supported
Block
Name
Hex
Addr
Size Access Type
16
Bits
Register Name
Description
VR 1
CFP
A02D
A02E
A02F
1
1
1
Read Write
Read Only
Read Only
15-0
15-0
15-0
Optional Vendor Specific FAWS Enable
Reserved
Module Temperature Monitor A/D Value
Not Supported
A030
1
Read Only
15-0
Module VCC Monitor A/D Value
Range 0 to 6.55 V. Accuracy ± 3%.
Resolution 0.1 mV.
0000h
A031
A032
A033
A034
A038
1
1
1
4
1
Read Only
Read Only
Read Only
Read Only
Read Only
0000h
0000h
0000h
00h
0000h
1
Read Only
A03A
A03C
A03D
A03E
A03F
A040
70
1
1
1
1
64
Read Only
Read Write
Read Write
Read Write
Read Write
Read Only
Module SOA Bias Current A/D Value
Module AUX1 Monitor A/D Value
Module AUX2 Monitor A/D Value
Reserved
Network Lane PRBS Data Count Exponent
Network Lane PRBS Data Count Mantissa
Host Lane PRBS Data Count Exponent
Host Lane PRBS Data Count Mantissa
Reserved
Host Configured Rx Opt Power Hi Alarm Thresh
Host Configured Rx Opt Power Hi Warn Thresh
Host Configured Rx Opt Power Lo Alarm Thresh
Host Configured Rx Opt Power Lo Warn Thresh
Reserved
Not supported
Not supported
Not supported
A039
15-0
15-0
15-0
15-0
15-10
0-9
15-10
0-9
15-0
15-0
15-0
15-0
15-0
7-0
Block
Name
Hex
Addr
Size Access Type
16
Bits
Register Name
Description
Initial
Value
VR 1
MLG
A080 A0FF
MLG Volatile Registers
MLG Not supported
0000h
Block
Name
Hex
Addr
Size Access Type
16
Bits
Register Name
Description
Initial
Value
VR 1
Network
Lanes
A200
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lane 0: Laser Bias High Alarm Flag
Lane 0: Laser Bias High Warning Flag
Lane 0: Laser Bias Low Warning Flag
Lane 0: Laser Bias Low Alarm Flag
Lane 0: Laser PWR High Alarm Flag
Lane 0: Laser PWR High Warning Flag
Lane 0: Laser PWR Low Warning Flag
Lane 0: Laser PWR Low Alarm Flag
Lane 0: Laser Temp High Alarm Flag
Lane 0: Laser Temp High Warning Flag
Lane 0: Laser Temp Low Warning Flag
Lane 0: Laser Temp Low Alarm Flag
Lane 0: Rx PWR High Alarm Flag
Lane 0: Rx PWR High Warning Flag
Lane 0: Rx PWR Low Warning Flag
Lane 0: Rx PWR Low Alarm Flag
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
30
128 Mixed
Read Only
Range -40/125 °C. Accuracy ± 3 °C.
Resolution 1/256 °C.
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Initial
Value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00h
00h
Block
Name
Hex
Addr
Size Access Type
VR 1
Network
Lanes
A201
1
Read Only
A202
1
Read Only
A203
1
Read Only
31
16
Bits
Register Name
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lane 1: Laser Bias High Alarm Flag
Lane 1: Laser Bias High Warning Flag
Lane 1: Laser Bias Low Warning Flag
Lane 1: Laser Bias Low Alarm Flag
Lane 1: Laser PWR High Alarm Flag
Lane 1: Laser PWR High Warning Flag
Lane 1: Laser PWR Low Warning Flag
Lane 1: Laser PWR Low Alarm Flag
Lane 1: Laser Temp High Alarm Flag
Lane 1: Laser Temp High Warning Flag
Lane 1: Laser Temp Low Warning Flag
Lane 1: Laser Temp Low Alarm Flag
Lane 1: RX PWR High Alarm Flag
Lane 1: RX PWR High Warning Flag
Lane 1: RX PWR Low Warning Flag
Lane 1: RX PWR Low Alarm Flag
Lane 2: Laser Bias High Alarm Flag
Lane 2: Laser Bias High Warning Flag
Lane 2: Laser Bias Low Warning Flag
Lane 2: Laser Bias Low Alarm Flag
Lane 2: Laser PWR High Alarm Flag
Lane 2: Laser PWR High Warning Flag
Lane 2: Laser PWR Low Warning Flag
Lane 2: Laser PWR Low Alarm Flag
Lane 2: Laser Temp High Alarm Flag
Lane 2: Laser Temp High Warning Flag
Lane 2: Laser Temp Low Warning Flag
Lane 2: Laser Temp Low Alarm Flag
Lane 2: RX PWR High Alarm Flag
Lane 2: RX PWR High Warning Flag
Lane 2: RX PWR Low Warning Flag
Lane 2: RX PWR Low Alarm Flag
Lane 3: Laser Bias High Alarm Flag
Lane 3: Laser Bias High Warning Flag
Lane 3: Laser Bias Low Warning Flag
Lane 3: Laser Bias Low Alarm Flag
Lane 3: Laser PWR High Alarm Flag
Lane 3: Laser PWR High Warning Flag
Lane 3: Laser PWR Low Warning Flag
Lane 3: Laser PWR Low Alarm Flag
Lane 3: Laser Temp High Alarm Flag
Lane 3: Laser Temp High Warning Flag
Lane 3: Laser Temp Low Warning Flag
Lane 3: Laser Temp Low Alarm Flag
Lane 3: RX PWR High Alarm Flag
Lane 3: RX PWR High Warning Flag
Lane 3: RX PWR Low Warning Flag
Lane 3: RX PWR Low Alarm Flag
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Initial
Value
00h
00h
00h
Block
Name
Hex
Addr
Size Access Type
VR 1
Network
Lanes
A204
1
Read Only
A205
1
Read Only
A206
1
Read Only
32
16
Bits
Register Name
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lane 4: Laser Bias High Alarm Flag
Lane 4: Laser Bias High Warning Flag
Lane 4: Laser Bias Low Warning Flag
Lane 4: Laser Bias Low Alarm Flag
Lane 4: Laser PWR High Alarm Flag
Lane 4: Laser PWR High Warning Flag
Lane 4: Laser PWR Low Warning Flag
Lane 4: Laser PWR Low Alarm Flag
Lane 4: Laser Temp High Alarm Flag
Lane 4: Laser Temp High Warning Flag
Lane 4: Laser Temp Low Warning Flag
Lane 4: Laser Temp Low Alarm Flag
Lane 4: RX PWR High Alarm Flag
Lane 4: RX PWR High Warning Flag
Lane 4: RX PWR Low Warning Flag
Lane 4: RX PWR Low Alarm Flag
Lane 5: Laser Bias High Alarm Flag
Lane 5: Laser Bias High Warning Flag
Lane 5: Laser Bias Low Warning Flag
Lane 5: Laser Bias Low Alarm Flag
Lane 5: Laser PWR High Alarm Flag
Lane 5: Laser PWR High Warning Flag
Lane 5: Laser PWR Low Warning Flag
Lane 5: Laser PWR Low Alarm Flag
Lane 5: Laser Temp High Alarm Flag
Lane 5: Laser Temp High Warning Flag
Lane 5: Laser Temp Low Warning Flag
Lane 5: Laser Temp Low Alarm Flag
Lane 5: RX PWR High Alarm Flag
Lane 5: RX PWR High Warning Flag
Lane 5: RX PWR Low Warning Flag
Lane 5: RX PWR Low Alarm Flag
Lane 6: Laser Bias High Alarm Flag
Lane 6: Laser Bias High Warning Flag
Lane 6: Laser Bias Low Warning Flag
Lane 6: Laser Bias Low Alarm Flag
Lane 6: Laser PWR High Alarm Flag
Lane 6: Laser PWR High Warning Flag
Lane 6: Laser PWR Low Warning Flag
Lane 6: Laser PWR Low Alarm Flag
Lane 6: Laser Temp High Alarm Flag
Lane 6: Laser Temp High Warning Flag
Lane 6: Laser Temp Low Warning Flag
Lane 6: Laser Temp Low Alarm Flag
Lane 6: RX PWR High Alarm Flag
Lane 6: RX PWR High Warning Flag
Lane 6: RX PWR Low Warning Flag
Lane 6: RX PWR Low Alarm Flag
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Initial
Value
0000h
0000h
0000h
Block
Name
Hex
Addr
Size Access Type
VR 1
Network
Lanes
A207
1
Read Only
A208
1
Read Only
A209
1
Read Only
A20A
A20B
A20C
A20D
A20E
A20F
1
1
1
1
1
1
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
33
16
Bits
Register Name
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15-0
15-0
15-0
15-0
15-0
15-0
Lane 7: Laser Bias High Alarm Flag
Lane 7: Laser Bias High Warning Flag
Lane 7: Laser Bias Low Warning Flag
Lane 7: Laser Bias Low Alarm Flag
Lane 7: Laser PWR High Alarm Flag
Lane 7: Laser PWR High Warning Flag
Lane 7: Laser PWR Low Warning Flag
Lane 7: Laser PWR Low Alarm Flag
Lane 7: Laser Temp High Alarm Flag
Lane 7: Laser Temp High Warning Flag
Lane 7: Laser Temp Low Warning Flag
Lane 7: Laser Temp Low Alarm Flag
Lane 7: RX PWR High Alarm Flag
Lane 7: RX PWR High Warning Flag
Lane 7: RX PWR Low Warning Flag
Lane 7: RX PWR Low Alarm Flag
Lane 8: Laser Bias High Alarm Flag
Lane 8: Laser Bias High Warning Flag
Lane 8: Laser Bias Low Warning Flag
Lane 8: Laser Bias Low Alarm Flag
Lane 8: Laser PWR High Alarm Flag
Lane 8: Laser PWR High Warning Flag
Lane 8: Laser PWR Low Warning Flag
Lane 8: Laser PWR Low Alarm Flag
Lane 8: Laser Temp High Alarm Flag
Lane 8: Laser Temp High Warning Flag
Lane 8: Laser Temp Low Warning Flag
Lane 8: Laser Temp Low Alarm Flag
Lane 8: RX PWR High Alarm Flag
Lane 8: RX PWR High Warning Flag
Lane 8: RX PWR Low Warning Flag
Lane 8: RX PWR Low Alarm Flag
Lane 9: Laser Bias High Alarm Flag
Lane 9: Laser Bias High Warning Flag
Lane 9: Laser Bias Low Warning Flag
Lane 9: Laser Bias Low Alarm Flag
Lane 9: Laser PWR High Alarm Flag
Lane 9: Laser PWR High Warning Flag
Lane 9: Laser PWR Low Warning Flag
Lane 9: Laser PWR Low Alarm Flag
Lane 9: Laser Temp High Alarm Flag
Lane 9: Laser Temp High Warning Flag
Lane 9: Laser Temp Low Warning Flag
Lane 9: Laser Temp Low Alarm Flag
Lane 9: RX PWR High Alarm Flag
Lane 9: RX PWR High Warning Flag
Lane 9: RX PWR Low Warning Flag
Lane 9: RX PWR Low Alarm Flag
Lane 10: Network Lane Alarm/Warning Flags
Lane 11: Network Lane Alarm/Warning Flags
Lane 12: Network Lane Alarm/Warning Flags
Lane 13: Network Lane Alarm/Warning Flags
Lane 14: Network Lane Alarm/Warning Flags
Lane 15: Network Lane Alarm/Warning Flags
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Initial
Value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Block
Name
Hex
Addr
Size Access Type
VR 1
Network
Lanes
A210
1
A211
A212
A213
A214
A215
A216
A217
34
1
1
1
1
1
1
1
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
16
Bits
Register Name
Description
Initial
Value
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
Lane 0: TEC, Wavelength, APD Faults
Reserved
Lane 0: TX_LOSF, TX_LOL Faults
Reserved
Lane 0: Rx_LOS
Lane 0: Rx_LOL, RX_FIFO Fault
Reserved
Lane 1: TEC, Wavelength, APD Faults
Reserved
Lane 1: TX_LOSF, TX_LOL Faults
Reserved
Lane 1: Rx_LOS
Lane 1: Rx_LOL, RX_FIFO Fault
Reserved
Lane 2: TEC, Wavelength, APD Faults
Reserved
Lane 2: TX_LOSF, TX_LOL Faults
Reserved
Lane 2: Rx_LOS
Lane 2: Rx_LOL, RX_FIFO Fault
Reserved
Lane 3: TEC, Wavelength, APD Faults
Reserved
Lane 3: TX_LOSF, TX_LOL Faults
Reserved
Lane 3: Rx_LOS
Lane 3: Rx_LOL, RX_FIFO Fault
Reserved
Lane 4: TEC, Wavelength, APD Faults
Reserved
Lane 4: TX_LOSF, TX_LOL Faults
Reserved
Lane 4: Rx_LOS
Lane 4: Rx_LOL, RX_FIFO Fault
Reserved
Lane 5: TEC, Wavelength, APD Faults
Reserved
Lane 5: TX_LOSF, TX_LOL Faults
Reserved
Lane 5: Rx_LOS
Lane 5: Rx_LOL, RX_FIFO Fault
Reserved
Lane 6: TEC, Wavelength, APD Faults
Reserved
Lane 6: TX_LOSF, TX_LOL Faults
Reserved
Lane 6: Rx_LOS
Lane 6: Rx_LOL, RX_FIFO Fault
Reserved
Lane 7: TEC, Wavelength, APD Faults
Reserved
Lane 7: TX_LOSF, TX_LOL Faults
Reserved
Lane 7: Rx_LOS
Lane 7: Rx_LOL, RX_FIFO Fault
Reserved
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
00000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
0000h
Block
Name
Hex
Addr
Size Access Type
VR 1
Network
Lanes
A218
1
A219
35
1
Read Only
Read Only
A21A
A21B
A21C
A21D
A21E
A21F
A220
1
1
1
1
1
1
1
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/COR
A221
1
Read/COR
16
Bits
Register Name
Description
Initial
Value
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-0
15-0
15-0
15-0
15-0
15-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lane 8: TEC, Wavelength, APD Faults
Reserved
Lane 8: TX_LOSF, TX_LOL Faults
Reserved
Lane 8: Rx_LOS
Lane 8: Rx_LOL, RX_FIFO Fault
Reserved
Lane 9: TEC, Wavelength, APD Faults
Reserved
Lane 9: TX_LOSF, TX_LOL Faults
Reserved
Lane 9: Rx_LOS
Lane 9: Rx_LOL, RX_FIFO Fault
Reserved
Lane 10: Network Lane Fault Status
Lane 11: Network Lane Fault Status
Lane 12: Network Lane Fault Status
Lane 13: Network Lane Fault Status
Lane 14: Network Lane Fault Status
Lane 15: Network Lane Fault Status
Lane 0: Laser Bias High Alarm Latch
Lane 0: Laser Bias High Warning Latch
Lane 0: Laser Bias Low Warning Latch
Lane 0: Laser Bias Low Alarm Latch
Lane 0: Laser PWR High Alarm Latch
Lane 0: Laser PWR High Warning Latch
Lane 0: Laser PWR Low Warning Latch
Lane 0: Laser PWR Low Alarm Latch
Lane 0: Laser Temp High Alarm Latch
Lane 0: Laser Temp High Warning Latch
Lane 0: Laser Temp Low Warning Latch
Lane 0: Laser Temp Low Alarm Latch
Lane 0: RX PWR High Alarm Latch
Lane 0: RX PWR High Warning Latch
Lane 0: RX PWR Low Warning Latch
Lane 0: RX PWR Low Alarm Latch
Lane 1: Laser Bias High Alarm Latch
Lane 1: Laser Bias High Warning Latch
Lane 1: Laser Bias Low Warning Latch
Lane 1: Laser Bias Low Alarm Latch
Lane 1: Laser PWR High Alarm Latch
Lane 1: Laser PWR High Warning Latch
Lane 1: Laser PWR Low Warning Latch
Lane 1: Laser PWR Low Alarm Latch
Lane 1: Laser Temp High Alarm Latch
Lane 1: Laser Temp High Warning Latch
Lane 1: Laser Temp Low Warning Latch
Lane 1: Laser Temp Low Alarm Latch
Lane 1: RX PWR High Alarm Latch
Lane 1: RX PWR High Warning Latch
Lane 1: RX PWR Low Warning Latch
Lane 1: RX PWR Low Alarm Latch
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Block
Name
Hex
Addr
Size Access Type
VR 1
Network
Lanes
A222
1
Read/COR
A223
1
Read/COR
A224
1
Read/COR
36
16
Bits
Register Name
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lane 2: Laser Bias High Alarm Latch
Lane 2: Laser Bias High Warning Latch
Lane 2: Laser Bias Low Warning Latch
Lane 2: Laser Bias Low Alarm Latch
Lane 2: Laser PWR High Alarm Latch
Lane 2: Laser PWR High Warning Latch
Lane 2: Laser PWR Low Warning Latch
Lane 2: Laser PWR Low Alarm Latch
Lane 2: Laser Temp High Alarm Latch
Lane 2: Laser Temp High Warning Latch
Lane 2: Laser Temp Low Warning Latch
Lane 2: Laser Temp Low Alarm Latch
Lane 2: RX PWR High Alarm Latch
Lane 2: RX PWR High Warning Latch
Lane 2: RX PWR Low Warning Latch
Lane 2: RX PWR Low Alarm Latch
Lane 3: Laser Bias High Alarm Latch
Lane 3: Laser Bias High Warning Latch
Lane 3: Laser Bias Low Warning Latch
Lane 3: Laser Bias Low Alarm Latch
Lane 3: Laser PWR High Alarm Latch
Lane 3: Laser PWR High Warning Latch
Lane 3: Laser PWR Low Warning Latch
Lane 3: Laser PWR Low Alarm Latch
Lane 3: Laser Temp High Alarm Latch
Lane 3: Laser Temp High Warning Latch
Lane 3: Laser Temp Low Warning Latch
Lane 3: Laser Temp Low Alarm Latch
Lane 3: RX PWR High Alarm Latch
Lane 3: RX PWR High Warning Latch
Lane 3: RX PWR Low Warning Latch
Lane 3: RX PWR Low Alarm Latch
Lane 4: Laser Bias High Alarm Latch
Lane 4: Laser Bias High Warning Latch
Lane 4: Laser Bias Low Warning Latch
Lane 4: Laser Bias Low Alarm Latch
Lane 4: Laser PWR High Alarm Latch
Lane 4: Laser PWR High Warning Latch
Lane 4: Laser PWR Low Warning Latch
Lane 4: Laser PWR Low Alarm Latch
Lane 4: Laser Temp High Alarm Latch
Lane 4: Laser Temp High Warning Latch
Lane 4: Laser Temp Low Warning Latch
Lane 4: Laser Temp Low Alarm Latch
Lane 4: RX PWR High Alarm Latch
Lane 4: RX PWR High Warning Latch
Lane 4: RX PWR Low Warning Latch
Lane 4: RX PWR Low Alarm Latch
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Initial
Value
0000h
0000h
0000h
Block
Name
Hex
Addr
Size Access Type
VR 1
Network
Lanes
A225
1
Read/COR
A226
1
Read/COR
A227
1
Read/COR
37
16
Bits
Register Name
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lane 5: Laser Bias High Alarm Latch
Lane 5: Laser Bias High Warning Latch
Lane 5: Laser Bias Low Warning Latch
Lane 5: Laser Bias Low Alarm Latch
Lane 5: Laser PWR High Alarm Latch
Lane 5: Laser PWR High Warning Latch
Lane 5: Laser PWR Low Warning Latch
Lane 5: Laser PWR Low Alarm Latch
Lane 5: Laser Temp High Alarm Latch
Lane 5: Laser Temp High Warning Latch
Lane 5: Laser Temp Low Warning Latch
Lane 5: Laser Temp Low Alarm Latch
Lane 5: RX PWR High Alarm Latch
Lane 5: RX PWR High Warning Latch
Lane 5: RX PWR Low Warning Latch
Lane 5: RX PWR Low Alarm Latch
Lane 6: Laser Bias High Alarm Latch
Lane 6: Laser Bias High Warning Latch
Lane 6: Laser Bias Low Warning Latch
Lane 6: Laser Bias Low Alarm Latch
Lane 6: Laser PWR High Alarm Latch
Lane 6: Laser PWR High Warning Latch
Lane 6: Laser PWR Low Warning Latch
Lane 6: Laser PWR Low Alarm Latch
Lane 6: Laser Temp High Alarm Latch
Lane 6: Laser Temp High Warning Latch
Lane 6: Laser Temp Low Warning Latch
Lane 6: Laser Temp Low Alarm Latch
Lane 6: RX PWR High Alarm Latch
Lane 6: RX PWR High Warning Latch
Lane 6: RX PWR Low Warning Latch
Lane 6: RX PWR Low Alarm Latch
Lane 7: Laser Bias High Alarm Latch
Lane 7: Laser Bias High Warning Latch
Lane 7: Laser Bias Low Warning Latch
Lane 7: Laser Bias Low Alarm Latch
Lane 7: Laser PWR High Alarm Latch
Lane 7: Laser PWR High Warning Latch
Lane 7: Laser PWR Low Warning Latch
Lane 7: Laser PWR Low Alarm Latch
Lane 7: Laser Temp High Alarm Latch
Lane 7: Laser Temp High Warning Latch
Lane 7: Laser Temp Low Warning Latch
Lane 7: Laser Temp Low Alarm Latch
Lane 7: RX PWR High Alarm Latch
Lane 7: RX PWR High Warning Latch
Lane 7: RX PWR Low Warning Latch
Lane 7: RX PWR Low Alarm Latch
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Initial
Value
0000h
0000h
0000h
Block
Name
Hex
Addr
Size Access Type
VR 1
Network
Lanes
A228
1
Read/COR
A229
1
Read/COR
A22A
A22B
A22C
A22D
A22E
A22F
A230
1
1
1
1
1
1
1
Read/COR
Read/COR
Read/COR
Read/COR
Read/COR
Read/COR
Read/COR
A231
38
1
Read/COR
16
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15-0
15-0
15-0
15-0
15-0
15-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
Register Name
Description
Lane 8: Laser Bias High Alarm Latch
Lane 8: Laser Bias High Warning Latch
Lane 8: Laser Bias Low Warning Latch
Lane 8: Laser Bias Low Alarm Latch
Lane 8: Laser PWR High Alarm Latch
Lane 8: Laser PWR High Warning Latch
Lane 8: Laser PWR Low Warning Latch
Lane 8: Laser PWR Low Alarm Latch
Lane 8: Laser Temp High Alarm Latch
Lane 8: Laser Temp High Warning Latch
Lane 8: Laser Temp Low Warning Latch
Lane 8: Laser Temp Low Alarm Latch
Lane 8: RX PWR High Alarm Latch
Lane 8: RX PWR High Warning Latch
Lane 8: RX PWR Low Warning Latch
Lane 8: RX PWR Low Alarm Latch
Lane 9: Laser Bias High Alarm Latch
Lane 9: Laser Bias High Warning Latch
Lane 9: Laser Bias Low Warning Latch
Lane 9: Laser Bias Low Alarm Latch
Lane 9: Laser PWR High Alarm Latch
Lane 9: Laser PWR High Warning Latch
Lane 9: Laser PWR Low Warning Latch
Lane 9: Laser PWR Low Alarm Latch
Lane 9: Laser Temp High Alarm Latch
Lane 9: Laser Temp High Warning Latch
Lane 9: Laser Temp Low Warning Latch
Lane 9: Laser Temp Low Alarm Latch
Lane 9: RX PWR High Alarm Latch
Lane 9: RX PWR High Warning Latch
Lane 9: RX PWR Low Warning Latch
Lane 9: RX PWR Low Alarm Latch
Lane 10: Network Lane Alarm/Warning Latch
Lane 11: Network Lane Alarm/Warning Latch
Lane 12: Network Lane Alarm/Warning Latch
Lane 13: Network Lane Alarm/Warning Latch
Lane 14: Network Lane Alarm/Warning Latch
Lane 15: Network Lane Alarm/Warning Latch
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Lane 0: TEC, APD, λ Fault Latch
Reserved
Lane 0: TX_LOSF,TX_LOL Fault Latch
Reserved
Lane 0: Rx_LOS Latch
Lane 0: RX_LOL, RX_FIFO Fault Latch
Reserved
Lane 1: TEC, APD, λ Fault Latch
Reserved
Lane 1: TX_LOSF,TX_LOL Fault Latch
Reserved
Lane 1: Rx_LOS Latch
Lane 1: RX_LOL, RX_FIFO Fault Latch
Reserved
Initial
Value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
0000h
Block
Name
Hex
Addr
Size
Access Type
VR 1
Network
Lanes
A232
1
Read/COR
A233
A234
A235
A236
A237
A238
39
1
1
1
1
1
1
Read/COR
Read/COR
Read/COR
Read/COR
Read/COR
Read/COR
16
Bits
Register Name
Description
Initial
Value
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
15-13
12-8
7-6
5
4
3-2
1-0
Lane 2: TEC, APD, λ Fault Latch
Reserved
Lane 2: TX_LOSF,TX_LOL Fault Latch
Reserved
Lane 2: Rx_LOS Latch
Lane 2: RX_LOL, RX_FIFO Fault Latch
Reserved
Lane 3: TEC, APD, λ Fault Latch
Reserved
Lane 3: TX_LOSF,TX_LOL Fault Latch
Reserved
Lane 3: Rx_LOS Latch
Lane 3: RX_LOL, RX_FIFO Fault Latch
Reserved
Lane 4: TEC, APD, λ Fault Latch
Reserved
Lane 4: TX_LOSF,TX_LOL Fault Latch
Reserved
Lane 4: Rx_LOS Latch
Lane 4: RX_LOL, RX_FIFO Fault Latch
Reserved
Lane 5: TEC, APD, λ Fault Latch
Reserved
Lane 5: TX_LOSF,TX_LOL Fault Latch
Reserved
Lane 5: Rx_LOS Latch
Lane 5: RX_LOL, RX_FIFO Fault Latch
Reserved
Lane 6: TEC, APD, λ Fault Latch
Reserved
Lane 6: TX_LOSF,TX_LOL Fault Latch
Reserved
Lane 6: Rx_LOS Latch
Lane 6: RX_LOL, RX_FIFO Fault Latch
Reserved
Lane 7: TEC, APD, λ Fault Latch
Reserved
Lane 7: TX_LOSF,TX_LOL Fault Latch
Reserved
Lane 7: Rx_LOS Latch
Lane 7: RX_LOL, RX_FIFO Fault Latch
Reserved
Not supported
0000h
15-13
Lane 8: TEC, APD, λ Fault Latch
Not supported
12-8
Reserved
7-6
Lane 8: TX_LOSF,TX_LOL Fault Latch
5
Reserved
4
Lane 8: Rx_LOS Latch
0 = Normal, 1 = Flag Asserted
3-2
Lane 8: RX_LOL, RX_FIFO Fault Latch
Not supported
1-0
Reserved
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Not supported
0 = Normal, 1 = Flag Asserted
Not supported
Not supported
0000h
Block
Name
Hex
Addr
Size
Access Type
16
Bits
Register Name
Description
Initial
Value
VR 1
Network
Lanes
A239
1
Read/COR
15-13
Lane 9: TEC, APD, λ Fault Latch
Not supported
0000h
12-8
Reserved
7-6
Lane 9: TX_LOSF,TX_LOL Fault Latch
5
Reserved
4
Lane 9: Rx_LOS Latch
0 = Normal, 1 = Flag Asserted
3-2
Lane 9: RX_LOL, RX_FIFO Fault Latch
Not supported
40
Not supported
1-0
Reserved
A23A
1
Read/COR
15-0
Lane 10: Network Lane Fault Status Latch
Not supported
0000h
A23B
1
Read/COR
15-0
Lane 11: Network Lane Fault Status Latch
Not supported
0000h
A23C
1
Read/COR
15-0
Lane 12: Network Lane Fault Status Latch
Not supported
0000h
A23D
1
Read/COR
15-0
Lane 13: Network Lane Fault Status Latch
Not supported
0000h
A23E
1
Read/COR
15-0
Lane 14: Network Lane Fault Status Latch
Not supported
0000h
A23F
1
Read/COR
15-0
Lane 15: Network Lane Fault Status Latch
Not supported
0000h
A240
1
Read Write
1
Read Write
Lane 0: Laser Bias High Alarm Enable
Lane 0: Laser Bias High Warning Enable
Lane 0: Laser Bias Low Warning Enable
Lane 0: Laser Bias Low Alarm Enable
Lane 0: Laser PWR High Alarm Enable
Lane 0: Laser PWR High Warning Enable
Lane 0: Laser PWR Low Warning Enable
Lane 0: Laser PWR Low Alarm Enable
Lane 0: Laser Temp High Alarm Enable
Lane 0: Laser Temp High Warning Enable
Lane 0: Laser Temp Low Warning Enable
Lane 0: Laser Temp Low Alarm Enable
Lane 0: RX PWR High Alarm Enable
Lane 0: RX PWR High Warning Enable
Lane 0: RX PWR Low Warning Enable
Lane 0: RX PWR Low Alarm Enable
Lane 1: Laser Bias High Alarm Enable
Lane 1: Laser Bias High Warning Enable
Lane 1: Laser Bias Low Warning Enable
Lane 1: Laser Bias Low Alarm Enable
Lane 1: Laser PWR High Alarm Enable
Lane 1: Laser PWR High Warning Enable
Lane 1: Laser PWR Low Warning Enable
Lane 1: Laser PWR Low Alarm Enable
Lane 1: Laser Temp High Alarm Enable
Lane 1: Laser Temp High Warning Enable
Lane 1: Laser Temp Low Warning Enable
Lane 1: Laser Temp Low Alarm Enable
Lane 1: RX PWR High Alarm Enable
Lane 1: RX PWR High Warning Enable
Lane 1: RX PWR Low Warning Enable
Lane 1: RX PWR Low Alarm Enable
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
FF0Fh
A241
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FF0Fh
Bloc
Name
Hex
Addr
Size Access Type
VR 1
A242
Network
Lanes
1
Read Write
A243
1
Read Write
A244
1
Read Write
41
16
Bits
Register Name
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lane 2: Laser Bias High Alarm Enable
Lane 2: Laser Bias High Warning Enable
Lane 2: Laser Bias Low Warning Enable
Lane 2: Laser Bias Low Alarm Enable
Lane 2: Laser PWR High Alarm Enable
Lane 2: Laser PWR High Warning Enable
Lane 2: Laser PWR Low Warning Enable
Lane 2: Laser PWR Low Alarm Enable
Lane 2: Laser Temp High Alarm Enable
Lane 2: Laser Temp High Warning Enable
Lane 2: Laser Temp Low Warning Enable
Lane 2: Laser Temp Low Alarm Enable
Lane 2: RX PWR High Alarm Enable
Lane 2: RX PWR High Warning Enable
Lane 2: RX PWR Low Warning Enable
Lane 2: RX PWR Low Alarm Enable
Lane 3: Laser Bias High Alarm Enable
Lane 3: Laser Bias High Warning Enable
Lane 3: Laser Bias Low Warning Enable
Lane 3: Laser Bias Low Alarm Enable
Lane 3: Laser PWR High Alarm Enable
Lane 3: Laser PWR High Warning Enable
Lane 3: Laser PWR Low Warning Enable
Lane 3: Laser PWR Low Alarm Enable
Lane 3: Laser Temp High Alarm Enable
Lane 3: Laser Temp High Warning Enable
Lane 3: Laser Temp Low Warning Enable
Lane 3: Laser Temp Low Alarm Enable
Lane 3: RX PWR High Alarm Enable
Lane 3: RX PWR High Warning Enable
Lane 3: RX PWR Low Warning Enable
Lane 3: RX PWR Low Alarm Enable
Lane 4: Laser Bias High Alarm Enable
Lane 4: Laser Bias High Warning Enable
Lane 4: Laser Bias Low Warning Enable
Lane 4: Laser Bias Low Alarm Enable
Lane 4: Laser PWR High Alarm Enable
Lane 4: Laser PWR High Warning Enable
Lane 4: Laser PWR Low Warning Enable
Lane 4: Laser PWR Low Alarm Enable
Lane 4: Laser Temp High Alarm Enable
Lane 4: Laser Temp High Warning Enable
Lane 4: Laser Temp Low Warning Enable
Lane 4: Laser Temp Low Alarm Enable
Lane 4: RX PWR High Alarm Enable
Lane 4: RX PWR High Warning Enable
Lane 4: RX PWR Low Warning Enable
Lane 4: RX PWR Low Alarm Enable
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Initial
Value
FF0Fh
FF0Fh
FF0Fh
Block
Name
Hex
Addr
Size
Access Type
16 Bits
Register Name
Description
VR 1
Network
Lanes
A245
1
Read Write
A246
1
Read Write
A247
1
Read Write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Lane 5: Laser Bias High Alarm Enable
Lane 5: Laser Bias High Warning Enable
Lane 5: Laser Bias Low Warning Enable
Lane 5: Laser Bias Low Alarm Enable
Lane 5: Laser PWR High Alarm Enable
Lane 5: Laser PWR High Warning Enable
Lane 5: Laser PWR Low Warning Enable
Lane 5: Laser PWR Low Alarm Enable
Lane 5: Laser Temp High Alarm Enable
Lane 5: Laser Temp High Warning Enable
Lane 5: Laser Temp Low Warning Enable
Lane 5: Laser Temp Low Alarm Enable
Lane 5: RX PWR High Alarm Enable
Lane 5: RX PWR High Warning Enable
Lane 5: RX PWR Low Warning Enable
Lane 5: RX PWR Low Alarm Enable
Lane 6: Laser Bias High Alarm Enable
Lane 6: Laser Bias High Warning Enable
Lane 6: Laser Bias Low Warning Enable
Lane 6: Laser Bias Low Alarm Enable
Lane 6: Laser PWR High Alarm Enable
Lane 6: Laser PWR High Warning Enable
Lane 6: Laser PWR Low Warning Enable
Lane 6: Laser PWR Low Alarm Enable
Lane 6: Laser Temp High Alarm Enable
Lane 6: Laser Temp High Warning Enable
Lane 6: Laser Temp Low Warning Enable
Lane 6: Laser Temp Low Alarm Enable
Lane 6: RX PWR High Alarm Enable
Lane 6: RX PWR High Warning Enable
Lane 6: RX PWR Low Warning Enable
Lane 6: RX PWR Low Alarm Enable
Lane 7: Laser Bias High Alarm Enable
Lane 7: Laser Bias High Warning Enable
Lane 7: Laser Bias Low Warning Enable
Lane 7: Laser Bias Low Alarm Enable
Lane 7: Laser PWR High Alarm Enable
Lane 7: Laser PWR High Warning Enable
Lane 7: Laser PWR Low Warning Enable
Lane 7: Laser PWR Low Alarm Enable
Lane 7: Laser Temp High Alarm Enable
Lane 7: Laser Temp High Warning Enable
Lane 7: Laser Temp Low Warning Enable
Lane 7: Laser Temp Low Alarm Enable
Lane 7: RX PWR High Alarm Enable
Lane 7: RX PWR High Warning Enable
Lane 7: RX PWR Low Warning Enable
Lane 7: RX PWR Low Alarm Enable
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
42
Initial
Value
FF0Fh
FF0Fh
FF0Fh
Block
Name
Hex
Addr
Size
Access Type
16 Bits Register Name
Description
VR 1
Network
Lanes
A248
1
Read Write
A249
1
Read Write
A24A
A24B
A24C
A24D
A24E
A24F
A250
1
1
1
1
1
1
1
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15-0
15-0
15-0
15-0
15-0
15-0
15-13
12-8
7-6
5
4
3
2
1-0
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
43
Lane 8: Laser Bias High Alarm Enable
Lane 8: Laser Bias High Warning Enable
Lane 8: Laser Bias Low Warning Enable
Lane 8: Laser Bias Low Alarm Enable
Lane 8: Laser PWR High Alarm Enable
Lane 8: Laser PWR High Warning Enable
Lane 8: Laser PWR Low Warning Enable
Lane 8: Laser PWR Low Alarm Enable
Lane 8: Laser Temp High Alarm Enable
Lane 8: Laser Temp High Warning Enable
Lane 8: Laser Temp Low Warning Enable
Lane 8: Laser Temp Low Alarm Enable
Lane 8: RX PWR High Alarm Enable
Lane 8: RX PWR High Warning Enable
Lane 8: RX PWR Low Warning Enable
Lane 8: RX PWR Low Alarm Enable
Lane 9: Laser Bias High Alarm Enable
Lane 9: Laser Bias High Warning Enable
Lane 9: Laser Bias Low Warning Enable
Lane 9: Laser Bias Low Alarm Enable
Lane 9: Laser PWR High Alarm Enable
Lane 9: Laser PWR High Warning Enable
Lane 9: Laser PWR Low Warning Enable
Lane 9: Laser PWR Low Alarm Enable
Lane 9: Laser Temp High Alarm Enable
Lane 9: Laser Temp High Warning Enable
Lane 9: Laser Temp Low Warning Enable
Lane 9: Laser Temp Low Alarm Enable
Lane 9: RX PWR High Alarm Enable
Lane 9: RX PWR High Warning Enable
Lane 9: RX PWR Low Warning Enable
Lane 9: RX PWR Low Alarm Enable
Lane 10: Alarm/Warning Enable
Lane 11: Alarm/Warning Enable
Lane 12: Alarm/Warning Enable
Lane 13: Alarm/Warning Enable
Lane 14: Alarm/Warning Enable
Lane 15: Alarm/Warning Enable
Lane 0: TEC, Wavelength, APD Fault
Reserved
Lane 0: TX_LOSF, TX_LOL Fault Enables
Reserved
Lane 0: Rx_LOS Enable
Lane 0: Rx_LOL Enable
Lane 0: RX_FIFO Fault Enable
Reserved
Not supported
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Initial
Value
FF0Fh
FF0Fh
0000h
0000h
0000h
0000h
0000h
0000h
0010h
Block
Name
Hex
Addr
Size Access Type
VR 1
Network
Lanes
A251
1
A252
A253
A254
A255
A256
44
1
1
1
1
1
Read Write
Read Write
Read Write
Read Write
Read Write
Read Write
16
Bits
Register Name
Description
Initial
Value
15-13
12-8
7-6
5
4
3
2
1-0
15-13
12-8
7-6
5
4
3
2
1-0
15-13
12-8
7-6
5
4
3
2
1-0
15-13
12-8
7-6
5
4
3
2
1-0
15-13
12-8
7-6
5
4
3
2
1-0
15-13
12-8
7-6
5
4
3
2
1-0
Lane 1: TEC, Wavelength, APD Fault
Reserved
Lane 1: TX_LOSF, TX_LOL Fault Enables
Reserved
Lane 1: Rx_LOS Enable
Lane 1: Rx_LOL Enable
Lane 1: RX_FIFO Fault Enable
Reserved
Lane 2: TEC, Wavelength, APD Fault Enables
Reserved
Lane 2: TX_LOSF, TX_LOL Fault Enables
Reserved
Lane 2: Rx_LOS Enable
Lane 2: Rx_LOL Enable
Lane 2: RX_FIFO Fault Enable
Reserved
Lane 3: TEC, Wavelength, APD Fault
Reserved
Lane 3: TX_LOSF, TX_LOL Fault Enables
Reserved
Lane 3: Rx_LOS Enable
Lane 3: Rx_LOL Enable
Lane 3: RX_FIFO Fault Enable
Reserved
Lane 4: TEC, Wavelength, APD Fault
Reserved
Lane 4: TX_LOSF, TX_LOL Fault Enables
Reserved
Lane 4: Rx_LOS Enable
Lane 4: Rx_LOL Enable
Lane 4: RX_FIFO Fault Enable
Reserved
Lane 5: TEC, Wavelength, APD Fault
Reserved
Lane 5: TX_LOSF, TX_LOL Fault Enables
Reserved
Lane 5: Rx_LOS Enable
Lane5: Rx_LOL Enable
Lane 5: RX_FIFO Fault Enable
Reserved
Lane 6: TEC, Wavelength, APD Fault
Reserved
Lane 6: TX_LOSF, TX_LOL Fault Enables
Reserved
Lane 6: Rx_LOS Enable
Lane 6: Rx_LOL Enable
Lane 6: RX_FIFO Fault Enable
Reserved
Not supported
0010h
Not supported
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
0010h
Not supported
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
0010h
Not supported
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
0010h
Not supported
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
0010h
Not supported
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
Not supported
Not supported
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
0010h
Block
Name
Hex
Addr
Size Access Type
16
Bits
Register Name
Description
Initial
Value
VR 1
Network
Lanes
A257
1
15-13
12-8
7-6
5
4
3
2
1-0
Lane 7: TEC, Wavelength, APD Fault
Reserved
Lane 7: TX_LOSF, TX_LOL Fault Enables
Reserved
Lane 7: Rx_LOS Enable
Lane 7: Rx_LOL Enable
Lane 7: RX_FIFO Fault Enable
Reserved
Not supported
0010h
15-13
Lane 8: TEC, Wavelength, APD Fault Enables
Not supported
12-8
Reserved
7-6
Lane 8: TX_LOSF, TX_LOL Fault Enables
5
Reserved
4
Lane 8: Rx_LOS Enable
0 = Normal, 1 = Enable Asserted
3
Lane 8: Rx_LOL Enable
Not supported
2
Lane 8: RX_FIFO Fault Enable
Not supported
1-0
Reserved
15-13
Lane 9: TEC, Wavelength, APD Fault Enables
12-8
Reserved
7-6
Lane 9: TX_LOSF, TX_LOL Fault Enables
5
Reserved
4
Lane 9: Rx_LOS Enable
0 = Normal, 1 = Enable Asserted
3
Lane 9: Rx_LOL Enable
Not supported
2
Lane 9: RX_FIFO Fault Enable
Not supported
A258
A259
45
1
1
Read Write
Read Write
Read Only
Not supported
0 = Normal, 1 = Enable Asserted
Not supported
Not supported
0010h
Not supported
Not supported
0010h
Not supported
1-0
Reserved
A25A
1
Read Only
15-0
Lane 10: Extra Alarm/Warning Flag Enable
Not supported
0000h
A25B
1
Read Only
15-0
Lane 11: Extra Alarm/Warning Flag Enable
Not supported
0000h
A25C
1
Read Only
15-0
Lane 12: Extra Alarm/Warning Flag Enable
Not supported
0000h
A25D
1
Read Only
15-0
Lane 13: Extra Alarm/Warning Flag Enable
Not supported
0000h
A25E
1
Read Only
15-0
Lane 14: Extra Alarm/Warning Flag Enable
Not supported
0000h
A25F
1
Read Only
15-0
Lane 15: Extra Alarm/Warning Flag Enable
Not supported
0000h
A260
32
Read Only
15-0
Reserved
0000h
Block
Name
Hex
Addr
Size
16
Access Type Bits
Register Name
Description
VR 2
Network
Lanes
A280
A290
A2A0
16
16
1
Read Only
Read Only
Read Only
15-0
15-0
15-0
Network Lane FEC Controls
Network Lane PRBS Rx Error Count
Lane 0: TX Bias Current Monitor A/D Value
A2A1
15-0
Lane 1: TX Bias Current Monitor A/D Value
A2A2
15-0
Lane 2: TX Bias Current Monitor A/D Value
A2A3
15-0
Lane 3: TX Bias Current Monitor A/D Value
A2A4
15-0
Lane 4: TX Bias Current Monitor A/D Value
A2A5
15-0
Lane 5: TX Bias Current Monitor A/D Value
A2A6
15-0
Lane 6: TX Bias Current Monitor A/D Value
A2A7
15-0
Lane 7: TX Bias Current Monitor A/D Value
A2A8
15-0
Lane 8: TX Bias Current Monitor A/D Value
A2A9
15-0
Lane 9: TX Bias Current Monitor A/D Value
15-0
15-0
15-0
15-0
15-0
15-0
15-0
Lane 10: TX Bias Current Monitor A/D Value
Lane 11: TX Bias Current Monitor A/D Value
Lane 12: TX Bias Current Monitor A/D Value
Lane 13: TX Bias Current Monitor A/D Value
Lane 14: TX Bias Current Monitor A/D Value
Lane 15: TX Bias Current Monitor A/D Value
Lane 0: Tx Optical PWR Monitor A/D Value
Not supported
Not supported
Range 0 - 131 mA.
Accuracy ± 10%. Resolution 2 µA.
Range 0 - 131 mA.
Accuracy ± 10%. Resolution 2 µA.
Range 0 - 131 mA.
Accuracy ± 10%. Resolution 2 µA.
Range 0 - 131 mA.
Accuracy ± 10%. Resolution 2 µA.
Range 0 - 131 mA.
Accuracy ± 10%. Resolution 2 µA.
Range 0 - 131 mA.
Accuracy ± 10%. Resolution 2 µA.
Range 0 - 131 mA.
Accuracy ± 10%. Resolution 2 µA.
Range 0 - 131 mA.
Accuracy ± 10%. Resolution 2 µA.
Range 0 - 131mA.
Accuracy ± 10%. Resolution 2 µA.
Range 0 - 131 mA.
Accuracy ± 10%. Resolution 2 µA.
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
A2B1
15-0
Lane 1: Tx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2B2
15-0
Lane 2: Tx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2B3
15-0
Lane 3: Tx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2B4
15-0
Lane 4: Tx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2B5
15-0
Lane 5: Tx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2B6
15-0
Lane 6: Tx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2B7
15-0
Lane 7: Tx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2B8
15-0
Lane 8: Tx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2B9
15-0
Lane 9: Tx Optical PWR Monitor A/D Value
0000h
15-0
15-0
15-0
15-0
15-0
15-0
15-0
Lane 10: Tx Optical PWR Monitor A/D Value
Lane 11: Tx Optical PWR Monitor A/D Value
Lane 12: Tx Optical PWR Monitor A/D Value
Lane 13: Tx Optical PWR Monitor A/D Value
Lane 14: Tx Optical PWR Monitor A/D Value
Lane 15: Tx Optical PWR Monitor A/D Value
Network Lane Tx Laser Temperature A/D
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
A2AA
A2AB
A2AC
A2AD
A2AE
A2AF
A2B0
A2BA
A2BB
A2BC
A2BD
A2BE
A2BF
A2C0
46
1
1
1
1
1
1
1
1
1
1
1
1
1
16
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
Initial
Value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Block
Name
Hex
Addr
Size
16
Access Type Bits
Register Name
Description
Initial
Value
VR 2
Network
Lanes
(Cont.)
A2D0
1
Read Only
15-0
Lane 0: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2D1
15-0
Lane 1: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2D2
15-0
Lane 2: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2D3
15-0
Lane 3: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2D4
15-0
Lane 4: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2D5
15-0
Lane 5: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2D6
15-0
Lane 6: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2D7
15-0
Lane 7: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2D8
15-0
Lane 8: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
0000h
A2D9
15-0
Lane 9: Rx Optical PWR Monitor A/D Value
Range 0 to 6.5 mW. Accuracy ± 2 dB.
Resolution 0.1 µW. Average Power.
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
0000h
A2DA
A2DB
A2DC
A2DD
A2DE
A2DF
A2E0
1
1
1
1
1
1
32
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
15-0
15-0
15-0
15-0
15-0
15-0
15-0
Lane 10: Rx Optical PWR Monitor A/D Value
Lane 11: Rx Optical PWR Monitor A/D Value
Lane 12: Rx Optical PWR Monitor A/D Value
Lane 13: Rx Optical PWR Monitor A/D Value
Lane 14: Rx Optical PWR Monitor A/D Value
Lane 15: Rx Optical PWR Monitor A/D Value
Reserved
Block
Name
Hex
Addr
Size
Access Type
16
Bits
Register Name
Description
Initial
Value
VR 3
Network
Lanes
A300 A3FF
128
Mixed
15-0
Optional Network Lane VR 3 Registers
Not supported
0000h
47
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Block
Name
Hex
Addr
Size
Access Type
16
Bits
Register Name
Description
Initial Value
VR 1
Host
Lanes
A400
A410
A420
A430
A440
16
16
16
16
1
Read Only
Read, COR
Read Write
Read Only
Read Write
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
15-0
15-0
15-0
15-0
15
14-8
7-4
3-0
15
14-8
7-4
3-0
15
14-8
7-4
3-0
15
14-8
7-4
3-0
15
14-8
7-4
3-0
15
14-8
7-4
3-0
15
14-8
7-4
3-0
15
14-8
7-4
3-0
15
14-8
7-4
3-0
15
14-8
7-4
3-0
15-0
15-0
15-0
15-0
15-0
15-0
15-0
Host Lane FAWS Registers
Host Lane FAWS Registers - Latched
Host Lane FAWS Registers - Enable
Host Lane PRBS Tx Error Count
Lane 0: Host Lane EQ Control Mode
Lane 0: Host Lane Equalization Value
Reserved
Lane 0: Host Lane Pre/De Emphasis Value
Lane 1: Host Lane EQ Control Mode
Lane 1: Host Lane Equalization Value
Reserved
Lane 1: Host Lane Pre/De Emphasis Value
Lane 2: Host Lane EQ Control
Lane 2: Host Lane Equalization
Reserved
Lane 2: Host Lane Pre/De Emphasis
Lane 3: Host Lane EQ Control
Lane 3: Host Lane Equalization
Reserved
Lane 3: Host Lane Pre/De Emphasis
Lane 4: Host Lane EQ Control
Lane 4: Host Lane Equalization
Reserved
Lane 4: Host Lane Pre/De Emphasis
Lane 5: Host Lane EQ Control
Lane 5: Host Lane Equalization
Reserved
Lane 5: Host Lane Pre/De Emphasis
Lane 6: Host Lane EQ Control
Lane 6: Host Lane Equalization
Reserved
Lane 6: Host Lane Pre/De Emphasis
Lane 7: Host Lane EQ Control
Lane 7: Host Lane Equalization
Reserved
Lane 7: Host Lane Pre/De Emphasis
Lane 8: Host Lane EQ Control
Lane 8: Host Lane Equalization
Reserved
Lane 8: Host Lane Pre/De Emphasis
Lane 9: Host Lane EQ Control
Lane 9: Host Lane Equalization
Reserved
Lane 9: Host Lane Pre/De Emphasis
Lane 10: Host Lane Pre/De Emphasis
Lane 11: Host Lane Pre/De Emphasis
Lane 12: Host Lane Pre/De Emphasis
Lane 13: Host Lane Pre/De Emphasis
Lane 14: Host Lane Pre/De Emphasis
Lane 15: Host Lane Pre/De Emphasis
Reserved
Not supported
Not supported
Not supported
Not supported
1b = Fixed in manual mode
0000h
0000h
0000h
0000h
D807h
A441
A442
A443
A444
A445
A446
A447
A448
A449
A44A
A44B
A44C
A44D
A44E
A44F
A450
48
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
48
Not supported
1b = Fixed in manual mode
D807h
Not supported
1b = Fixed in manual mode
D807h
Not supported
1b = Fixed in manual mode
D807h
Not supported
1b = Fixed in manual mode
D807h
Not supported
1b = Fixed in manual mode
D807h
Not supported
1b = Fixed in manual mode
D807h
Not supported
1b = Fixed in manual mode
D807h
Not supported
1b = Fixed in manual mode
D807h
Not supported
1b = Fixed in manual mode
D807h
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
00h
00h
00h
00h
00h
00h
( 20.75 )
Case Temperature Definition
41.50
CASE TEMPERATURE
( 36.52 )
CFP2 Mechanical Outline
Bail Latch Color is Beige with one center black band to indicate 10G/fiber operation, 100GE-SR10 compliance and 100 m
OM3 Multi-Mode fiber (150 m OM4) capability
8.05
12.40 0.2
16.15
2.5 MAX
91.70
54.10
1.30
8.10
7.51
41.50 0.2
CFP2 MODULE DRAWING
31.40
38.50
107.50
ALL DIMENSIONS ARE IN MM
CFP2 Module Insertion, Extraction Forces
Parameter
Maximum
Unit
Notes
Maximum Insertion Force
80
N
Without Heat Sink
Maximum Extraction Force**
50
N
Without Heat Sink
Minimum Retention Force
90
N
No damage to module below 90 N
Minimum Cage Retention Force
180
N
No damage to cage latch below 180 N
** In order to extract the module, the latch bar needs to be pulled out and rotated all the way downward. By design, the latch bar needs to rotate 90
degrees for the module to be extracted.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved.
AV02-4410EN - December 23, 2014