Holtek HT86070 Voice synthesizer 8-bit mcu Datasheet

HT86030/HT86070
Voice Synthesizer 8-Bit MCU
Technical Document
· Tools Information
· FAQs
Features
· Operating voltage: 2.4V~5.2V
· Built-in voice ROM in various capacity
· System clock: 4MHz~8MHz
· One 8-bit counter with 3-bit prescaler
· Crystal or RC oscillator for system clock
· Watchdog Timer
· 16 I/O pins
· 8-level subroutine nesting
· 8K´16-bit program ROM
· HALT function and wake-up feature reduce power
consumption
· 208´8-bit RAM
· Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)
· One external interrupt input
system clock
· Two 16-bit programmable timer counter and overflow
· Support 16-bit table read instruction (TBLP, TBHP)
interrupts
· 63 powerful and efficient instructions
· 12-bit high quality D/A output by transistor or
· 28-pin SOP package
HT82V733
Applications
· Intelligent educational leisure products
· High end leisure product controllers
· Alert and warning systems
· Sound effect generators
General Description
be triggered with falling edge pulse or falling/rising edge
pulse.
The HT86030/HT86070 series are 8-bit high performance microcontroller with voice synthesizer and tone
generator. The HT86030/HT86070 is designed for applications on multiple I/Os with sound effects, such as
voice and melody. It can provide various sampling rates
and beats, tone levels, tempos for speech synthesizer
and melody generator. It has a single built-in high quality, D/A output. There is an external interrupt which can
The HT86030/HT86070 is excellent for versatile voice
and sound effect product applications. The efficient
MCU instructions allow users to program the powerful
custom applications. The system frequency of
HT86030/HT86070 can be up to 8MHz under 2.4V and
include a HALT function to reduce power consumption.
Selection Table
Body
HT86030
HT86070
768K-bit
1536K-bit
Voice length
36 sec
72 sec
Voice ROM address latch
17-bit
18-bit
Voice ROM size
Note: * Voice length is estimated by 18K-bit data rate
Rev. 1.10
1
May 25, 2006
HT86030/HT86070
Block Diagram
S T A C K 0
IN T
T M R 0
S T A C K 1
S T A C K 2
S T A C K 4
S T A C K 5
S T A C K 6
P ro g ra m
R O M
T M R 0 C
In te r r u p t
C ir c u it
S T A C K 3
P ro g ra m
C o u n te r
M
U
D A T A
M e m o ry
X
S T A T U S
P A
O S
R E
V D
V S
S
D
S
P O R T A
¸ 2 5 6
U
W D T R C
O S C
X
S Y S C L K /4
P B 0 ~ P B 7
P A 0 ~ P A 7
S h ifte r
T M R 3
O S C 2
P O R T B
P B
P A C
T im in g
G e n e r a tio n
M
W D T P r e s c a le r
M U X
A L U
1 6 b it
W D T S
P B C
In s tr u c tio n
D e c o d e r
S Y S C L K /4
T M R 1
T M R 1 C
M P 0
M P 1
1 6 b it
IN T C
S T A C K 7
In s tr u c tio n
R e g is te r
S Y S C L K /4
C 1
8 -s ta g e
P r e s c a le r
S Y S C L K /4
A C C
T M R 3 C
8 - b it
3 - b it
V o lu m e
C o n tro l
1 2 - b it
D /A
Pin Assignment
N C
1
2 8
N C
N C
2
2 7
N C
N C
3
2 6
N C
N C
4
2 5
N C
P A 7
5
2 4
N C
P A 6
6
2 3
O S C 2
P A 5
7
2 2
O S C 1
P A 4
8
2 1
IN T
P A 3
9
2 0
R E S
P A 2
1 0
1 9
A U D
P A 1
1 1
1 8
T E S T
P A 0
1 2
1 7
V D D A
N C
1 3
1 6
V D D
V S S
1 4
1 5
V S S A
H T 8 6 0 3 0 /H T 8 6 0 7 0
2 8 S O P -A
Rev. 1.10
2
May 25, 2006
HT86030/HT86070
Pad Assignment
HT86030
(0 ,0 )
1
P A 7
P A 6
P A 5
2
P A 4
P A 3
4
P A 2
P A 1
P A 0
6
3
5
7
8
2 1
O S C 2
2 4
O S C 1
2 2 2 3
IN T
6
5
4
3
2
1
0
R E S
7
1 8 1 9 2 0
A U D
P B
P B
P B
P B
P B
P B
P B
P B
1 7
V D D A
V D D
V S S
1 0 1 1 1 2 1 3 1 4 1 5 1 6
V S S A
9
2 5
Chip size: 2180´2095 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
HT86070
(0 ,0 )
P A
P A
P A
P A
P A
P A
P A
P A
6
4
0
2
1
7
1
2
3
5
4
5
3
6
2 5
2 4
7
8
S
2 1
IN T
R E S
A U D
P B
P B
P B
P B
P B
P B
P B
P B
1 7 1 8 1 9 2 0
V D
V D
V S
V S
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
O S C 2
O S C 1
2 2 2 3
6
5
4
3
2
1
0
D
D A
S A
7
Chip size: 2180´2500 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.10
3
May 25, 2006
HT86030/HT86070
Pad Coordinates
HT86030
Pad No.
X
Y
Pad No.
X
Y
1
-940.200
-3.100
14
-444.300
-897.100
2
-940.200
-98.200
15
-341.300
-897.100
3
-940.200
-201.200
16
-940.200
-296.300
17
-246.200
255.700
-897.100
4
5
-940.200
-399.300
18
365.000
-796.050
6
-940.200
-494.400
19
465.000
-796.050
7
-940.200
-597.400
20
565.100
-796.050
8
-940.200
-692.500
21
690.250
-828.350
9
-935.600
-897.100
22
824.350
-832.150
10
-840.500
-897.100
23
927.350
-832.150
11
-737.500
-897.100
24
924.100
-618.924
12
-642.400
-897.100
25
924.100
-514.624
13
-539.400
-897.100
Pad No.
X
Y
Pad No.
X
Y
1
-940.200
-205.600
14
-444.300
-1099.600
2
-940.200
-300.700
15
-341.300
-1099.600
3
-940.200
-403.700
16
-1099.600
4
-940.200
-498.800
17
-246.200
255.700
5
-940.200
-601.800
18
365.000
-998.550
6
-940.200
-696.900
19
465.000
-998.550
7
-940.200
-799.900
20
565.100
-998.550
8
-940.200
-895.000
21
690.250
-1030.850
-830.550
HT86070
-1033.050
9
-935.600
-1099.600
22
824.350
-1034.650
10
-840.500
-1099.600
23
927.350
-1034.650
11
-737.500
-1099.600
24
924.100
-821.424
12
-642.400
-1099.600
25
924.100
-717.124
13
-539.400
-1099.600
Rev. 1.10
4
May 25, 2006
HT86030/HT86070
Pad Description
Pad Name
I/O
Mask Option
Description
PA0~PA7
I/O
Wake-up,
Pull-high
or None
Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input
by mask option. Software instructions determine the CMOS output or
Schmitt trigger input with or without pull-high resistor (mask option).
PB0~PB7
I/O
Pull-high
or None
Bidirectional 8-bit I/O port. Software instructions determine the CMOS
output or Schmitt trigger input (pull-high resistor depending on mask option).
VSS
¾
¾
Negative power supply, ground
VDD
¾
¾
Positive power supply
VDDA
¾
¾
DAC power supply
VSSA
¾
¾
DAC negative power supply, ground
I
¾
Schmitt trigger reset input, active low
RES
INT
OSC1
OSC2
AUD
I
External interrupt Schmitt trigger input without pull-high resistor. Choice
Falling Edge Trigger
falling edge trigger or falling/rising edge trigger by mask option. Falling
or Falling/Rising Edge
edge triggered active on a high to low transition. Rising edge triggered
Trigger
active on a low to high transition.
¾
RC or Crystal
O
¾
OSC1 and OSC2 are connected to an RC network or a crystal (by mask
option) for the internal system clock. In the case of RC operation, OSC2
is the output terminal for 1/4 system clock.
The system clock may come from the crystal, the two pins cannot be
floating.
Audio output for driving a external transistor or for driving HT82V733
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+5.5V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..........................-20°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.10
5
May 25, 2006
HT86030/HT86070
D.C. Characteristics
Symbol
Ta=25°C
Parameter
VDD
Operating Voltage
ISTB1
Standby Current (Watchdog Off)
ISTB2
Standby Current(Watchdog On)
IDD
Operating Current (RC OSC)
IOL
I/O Port Sink Current
IOH
I/O Port Source Current
IO
AUD Source Current
VIL1
Input Low Voltage for I/O Ports
VIH1
Input High Voltage for I/O Ports
VIL2
Reset Low Voltage (RES)
VIH2
Reset High Voltage (RES)
RPH
Pull-high Resistance
Test Conditions
VDD
¾
Conditions
fSYS=4MHz/8MHz
3V
No load, system HALT
5V
3V
No load, system HALT
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
No load, fSYS=8MHz
VOL=0.1VDD
VOH=0.9VDD
VOH=0.9VDD
¾
¾
¾
¾
¾
Min.
Typ.
Max.
Unit
2.4
¾
5.2
V
¾
¾
1
¾
¾
2
¾
¾
7
¾
¾
10
¾
¾
3.5
¾
¾
8
¾
11
¾
¾
25
¾
¾
-6
¾
¾
-15
¾
¾
-3
¾
¾
-7
¾
¾
1.3
¾
¾
2.3
¾
¾
1.8
¾
¾
2.9
¾
¾
1.4
¾
¾
3
¾
¾
2.4
¾
¾
3.9
¾
20
60
100
10
30
50
mA
mA
A.C. Characteristics
Symbol
mA
mA
mA
mA
V
V
V
V
kW
Ta=25°C
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS1
System Clock (RC OSC)
¾
2.4V~5.2V
4
¾
8
MHz
fSYS2
System Clock (Crystal OSC)
¾
2.4V~5.2V
4
¾
8
MHz
fTIMER
Timer Input Frequency
¾
2.4V~5.2V
0
¾
8
MHz
ms
tWDTOSC Watchdog Oscillator Period
tWDT1
Watchdog Time-out Period (WDT OSC)
3V
¾
45
90
180
5V
¾
32
65
130
ms
11
23
46
ms
8
17
33
ms
3V
5V
Without WDT prescaler
tWDT2
Watchdog Time-out Period (System Clock)
¾
Without WDT prescaler
¾
1024
¾
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
1
¾
¾
ms
Rev. 1.10
6
Wake-up from HALT
¾
May 25, 2006
HT86030/HT86070
Characteristics Curves
HT86030/HT86070 R vs. F Characteristics Curve
H T 8 6 0 3 0 /H T 8 6 0 7 0 R
v s . F C h a rt
F re q u e n c y (M H z )
1 2
1 0
8
6
3 V
4
4 .5 V
2
1 2 0
1 5 0
1 8 0
2 0 0
2 2 0
2 4 0
2 7 0
3 0 0
(k W )
R
HT86030/HT86070 V vs. F Characteristics Curve
H T 8 6 0 3 0 /H T 8 6 0 7 0 V v s . F C h a r t (F o r 3 .0 V )
F re q u e n c y (M H z )
1 0
8
8 M H z /1 5 5 k W
6
6 M H z /2 0 5 k W
4
4 M H z /2 9 7 k W
2
2 .4
2 .8
3 .2
4 .5
3 .6
V
4
D D
4 .8
5 .2
(V )
H T 8 6 0 3 0 /H T 8 6 0 7 0 V v s . F C h a r t (F o r 4 .5 V )
F re q u e n c y (M H z )
1 0
8 M H z /1 4 5 k W
8
6 M H z /1 9 2 k W
6
4 M H z /2 8 0 k W
4
2
2 .4
2 .8
3 .2
3 .6
V
Rev. 1.10
4
D D
4 .5
4 .8
5 .2
(V )
7
May 25, 2006
HT86030/HT86070
Functional Description
Execution Flow
Program Counter - PC
The system clock for the HT86030/HT86070 series is
derived from either a crystal or an RC oscillator. It is internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are executed.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are
required to complete the instruction.
S y s te m
C lo c k
O S C (R C
o n ly )
T 1
T 2
T 3
T 4
T 1
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
T 2
T 3
T 4
T 1
T 2
T 3
T 4
P 1
In te rn a l
P h a s e
C lo c k s
P 2
P 3
P 4
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
External or Serial Input Interrupt
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Timer Counter 3 Overflow
0
0
0
0
0
0
0
0
1
0
1
0
0
Skip
Program Counter+2
Loading PCL
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Program Counter
Note: *12~*0: Program counter bits
S12~S0: Stack register bits
#12~#0: Instruction code bits
Rev. 1.10
@7~@0: PCL bits
8
May 25, 2006
HT86030/HT86070
· Location 008H
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle takes its place while the correct instruction is obtained.
This area is reserved for the 16-bit Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program will jump to location 008H and begins execution.
The lower byte of the program counter (PCL) is a
read/write register (06H). Moving data into the PCL performs a short jump. The destination must be within 256
locations.
· Location 00CH
This area is reserved for the 16-bit Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program will jump to location 00CH and begins execution.
When a control transfer takes place, an additional
dummy cycle is required.
Program Memory - ROM
· Location 014H
The program memory stores the program instructions
that are to be executed. It also includes data, table and
interrupt entries, addressed by the program counter
along with the table pointer. The program memory size
for HT86030/HT86070 is 8192´16 bits. Certain locations in the program memory are reserved for special
usage:
This area is reserved for the 8-bit Timer Counter 3 interrupt service program. If a timer interrupt results
from a Timer Counter 3 overflow, and if the interrupt is
enabled and the stack is not full, the program will jump
to location 014H and begins execution.
Table location
· Location 000H
Any location in the ROM space can be used as look up
tables. The instructions TABRDC [m] (used for any
bank) and TABRDL [m] (only used for last page of program ROM) transfer the contents of the lower-order byte
to the specified data memory [m], and the higher-order
byte to TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined. The
higher-order bytes of the table word are transferred to
the TBLH. The table higher-order byte register (TBLH)
is read only.
This area is reserved for program initialization. The
program always begins execution at location 000H
each time the system is reset.
· Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, and the interrupt is enabled and the stack is not full, the program
will jump to location 004H and begins execution.
0 0 0 0 H
0 0 0 4 H
0 0 0 8 H
0 0 0 C H
0 0 1 4 H
In itia l A d d r e s s
The table pointer (TBHP, TBLP) is a read/write register,
which indicates the table location. Because TBHP is unknown after power on reset, TBHP must be set specified.
E x te r n a l In te r r u p t S u b r o u tin e
T im e r 0 In te r r u p t S u b r o u tin e
P ro g ra m
R O M
T im e r 1 In te r r u p t S u b r o u tin e
Stack Register - Stack
T im e r 3 In te r r u p t S u b r o u tin e
The stack register is a special part of the memory used
to save the contents of the program counter. This stack
is organized into eight levels. It is neither part of the data
nor part of the program space, and cannot be read or
written to. Its activated level is indexed by a stack
pointer (SP) and cannot be read or written to. At a subroutine call or interrupt acknowledgment, the contents of
the program counter are pushed onto the stack.
0 0 1 5 H
1 F F F H
Program Memory
Instruction
Table Location
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *12~*0: Current program ROM table
@7~@0: Write @7~@0 to TBLP pointer register
P12~P8: Write P12~P8 to TBHP pointer register
Rev. 1.10
9
May 25, 2006
HT86030/HT86070
control register 0 (INTC:0BH), Timer/Event Counter 0
(TMR0H:0CH,TMR0L:0DH), Timer/Event Counter 0
control register (TMR0C:0EH), Timer/Event Counter 1
(TMR1H:0FH, TMR1L:10H), Timer/Event Counter 1
co n t r o l r e g i st e r ( T M R 1 C : 1 1 H ) , I / O r e g i st e r s
(PA:12H,PB:14H), I/O control registers (PAC:13H,
P B C : 1 5 H ) , vo i ce R O M a d d r e ss l a t ch 0 [ 1 7 : 0 ]
(LATCH0H:18H, LATCH0M:19H, LATCH0L:1AH),
voice ROM address latch1[17:0] (LATCH1H:1BH,
LATCH1M:1CH, LATCH1L:1DH), interrupt control register 1 (INTCH:1EH), table pointer higher-order byte
register (TBHP:1FH), Timer Counter 3 (TMR3L:24H),
Timer Counter 3 control register (TMR3C:25H), voice
co n t r o l r e g i st e r ( V O I C E C : 2 6 H ) , D A C o u t p u t
(DAH:27H,DAL:28H), volume control register
( V O L : 2 9 H ) , vo i ce R O M l a t ch d a t a r e g i st e r
(LATCHD:2AH).
The program counter is restored to its previous value
from the stack at the end of subroutine or interrupt routine, which is signaled by return instruction (RET or
RETI). After a chip resets, SP will point to the top of the
stack.
The interrupt request flag will be recorded but the acknowledgment will be inhibited when the stack is full and
a non-masked interrupt takes place. After the stack
pointer is decremented (by RET or RETI), the interrupt
request will be serviced. This feature prevents stack
overflow and allows programmers to use the structure
more easily. In a similar case, if the stack is full and a
²CALL² is subsequently executed, stack overflow occurs and the first entry is lost.
Data Memory - RAM
The data memory is designed with 208´8 bits. The data
memory is further divided into two functional groups,
namely, special function registers (00H~2AH) and general purpose user data memory (30H~FFH). Although
most of them can be read or be written to, some are read
only.
The general purpose data memory, addressed from
30H~FFH, is used for data and control information under instruction commands.
The areas in the RAM can directly handle the arithmetic,
logic, increment, decrement, and rotate operations. Except some dedicated bits, each bit in the RAM can be
set and reset by ²SET [m].i² and ²CLR [m].i². They are
also indirectly accessible through the memory pointer
register 0 (MP0:01H) or the Memory Pointer register 1
(MP1:03H).
The special function registers include an indirect addressing register (R0:00H), memory pointer register
(MP0:01H), accumulator (ACC:05H), program counter
lower-order byte register (PCL:06H), table pointer
(TBLP:07H), table higher-order byte register
(TBLH:08H), status register (STATUS:0AH), interrupt
Address RAM Mapping
Read/Write
Description
00H
R0
R/W
Indirect addressing register 0
01H
MP0
R/W
Memory pointer 0
02H
R1
R/W
Indirect addressing register 1
03H
MP1
R/W
Memory pointer 1
04H
Unused
05H
ACC
R/W
Accumulator
06H
PCL
R/W
Program counter lower-order byte address
07H
TBLP
R/W
Table pointer lower-order byte address
08H
TBLH
R
Table higher-order byte content register
09H
WDTS
R/W
Watchdog Timer option setting register
0AH
STATUS
R/W
Status register
0BH
INTC
R/W
Interrupt control register 0
0CH
TMR0H
R/W
Timer/Event counter 0 higher-byte register
0DH
TMR0L
R/W
Timer/Event counter 0 lower-byte register
0EH
TMR0C
R/W
Timer/Event counter 0 control register
0FH
TMR1H
R/W
Timer/Event counter 1 higher-byte register
10H
TMR1L
R/W
Timer/Event counter 1 lower-byte register
11H
TMR1C
R/W
Timer/Event counter 1 control register
12H
PA
R/W
Port A I/O data register
Rev. 1.10
10
May 25, 2006
HT86030/HT86070
Address RAM Mapping
Read/Write
Description
13H
PAC
R/W
Port A I/O control register
14H
PB
R/W
Port B I/O data register
15H
PBC
R/W
Port B I/O control register
18H
LATCH0H
R/W
Voice ROM address latch 0 [A17~A16]
19H
LATCH0M
R/W
Voice ROM address latch 0 [A15~A8]
1AH
LATCH0L
R/W
Voice ROM address latch 0 [A7~A0]
1BH
LATCH1H
R/W
Voice ROM address latch 1 [A17~A16]
1CH
LATCH1M
R/W
Voice ROM address latch 1 [A15~A8]
1DH
LATCH1L
R/W
Voice ROM address latch 1 [A7~A0]
1EH
INTCH
R/W
Interrupt control register 1
1FH
TBHP
R/W
Table pointer higher-order byte register
23H
Unused
24H
TMR3L
R/W
Timer Counter 3 lower-byte register
25H
TMR3C
R/W
Timer Counter 3 control register
26H
VOICEC
R/W
Voice control register
27H
DAL
28H
DAH
29H
VOL
2AH
LATCHD
R/W, higher-nibble
DAC output data D3~D0 to DAL7~DAL4
available only
R/W
DAC output data D11~D4 to DAH7~DAH0
R/W, higher-nibble
Volume control register, and volume controlled by VOL7~VOL5
available only
R
Voice ROM data register
2BH~2FH Unused
30H~FFH User data RAM
R/W
User data RAM
Indirect Addressing Register
Arithmetic and Logic Unit - ALU
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining the corresponding indirect addressing registers.
· Branch decision (SZ, SNZ, SIZ, SDZ etc)
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
Status Register - STATUS
This 8-bit STATUS register (0AH) consists of a zero flag
(Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
Accumulator - ACC (05H)
The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Rev. 1.10
Except the TO and PDF flags, bits in the status register
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PDF flags. Operations related to the status register,
11
May 25, 2006
HT86030/HT86070
pushed onto the stack. The programmer must save the
contents of the register or status register (STATUS) in
advance if they are altered by an interrupt service program which corrupts the desired control sequence.
however, may yield different results from those intended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the
latest operations.
External interrupt is triggered by a high-to-low/
low-to-high transition of INT pin which sets the related
interrupt request flag (EIF:bit 4 of INTC). When the interrupt is enabled, and the stack is not full and the external
interrupt is active, a subroutine call to location 04H will
occur. The interrupt request flag (EIF) and EMI bits will
be cleared to disable other interrupts.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event counter 0 interrupt request flag (T0F:bit 5 of INTC), caused by a Timer/Event
Counter 0 overflow. When the interrupt is enabled, and
the stack is not full and the T0F bit is set, a subroutine
call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to
disable further interrupts.
Interrupts
The HT86030/HT86070 provides an external interrupt,
three 16-bit programmable timer interrupts, and an 8-bit
programmable timer interrupt. The Interrupt Control registers (INTC:0BH, INTCH:1EH) contain the interrupt
control bits to set to enable/disable and the interrupt request flags.
The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (T1F:bit 6 of INTC), caused by a Timer/Event
Counter 1 overflow. When the interrupt is enabled, and
the stack is not full and the T1F bit is set, a subroutine
call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to
disable further interrupts.
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the
EMI bit and the corresponding INTC/INTCH bit may be
set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be prevented from becoming full.
The internal Timer Counter 3 interrupt is initialized by
setting the Timer Counter 3 interrupt request flag
(T3F:bit 1 of INTCH), caused by a Timer Counter 3 overflow. When the interrupt is enabled, and the stack is not
full and the T3F bit is set, a subroutine call to location
14H will occur. The related interrupt request flag (T3F)
will be reset and the EMI bit cleared to disable further interrupts.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at the specified location(s) in
the program memory. Only the program counter is
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.10
12
May 25, 2006
HT86030/HT86070
During the execution of an interrupt subroutine, other interrupt acknowledges are held until the RETI instruction
is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To
return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
1
EEI
Controls the external interrupt
(1= enabled; 0= disabled)
2
ET0I
Controls the timer 0 interrupt
(1= enabled; 0= disabled)
3
ET1I
Controls the timer 1 interrupt
(1= enabled; 0= disabled)
4
EIF
External interrupt request flag
(1= active; 0= inactive)
5
T0F
Timer 0 request flag
(1= active; 0= inactive)
6
T1F
Timer 1 request flag
(1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
¾
1
ET3I
Controls the timer 3 interrupt
(1= enabled; 0= disabled)
5
T3F
Timer 3 interrupt request flag
(1= active; 0= inactive)
Unused bit, read as ²0²
Priority
Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
Timer Counter 3 Overflow
4
14H
The HT86030/HT86070 provides two types of oscillator
circuit for the system clock, i.e., RC oscillator and crystal
oscillator. No matter what type of oscillator, the signal is
used for the system clock. The HALT mode stops the
system oscillator and ignores external signal to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the
range of the resistance should be from 30kW to 680kW.
The system clock, divided by 4, is available on OSC2
with pull-high resistor, which can be used to synchronize
external logic. The RC oscillator provides the most cost
effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself
due to process variations. It is therefore not suitable for
timing sensitive operations where accurate oscillator
frequency is desired.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
Function
Controls the master (global) interrupt
(1= enabled; 0= disabled)
0, 2~4, 6~7
Oscillator Configuration
It is recommended that application programs do not use
CALL subroutines within an interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and the interrupt enable is not well controlled, once a CALL subroutine if used in the interrupt
subroutine will corrupt the original control sequence.
EMI
Function
Interrupt Source
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F) which enables Timer/Event Counter 0/1 control bit (ET0I/ET1I), the Timer Counter 3 interrupt request flag (T3F) which enables Timer Counter 3 control
bit (ET3I), and external interrupt request flag (EIF)
which enables external interrupt control bit (EEI) form
the interrupt control register (INTC:0BH and
INTCH:1EH). EMI, EEI, ET0I, ET1I and ET3I are used
to control the enabling/disabling of interrupts. These bits
prevent the requested interrupt begin serviced. Once
the interrupt request flags (T0F, T1F, T3F, EIF) are set,
they will remain in the INTC/INTCH register until the interrupts are serviced or cleared by a software instruction.
0
Label
INTCH (1EH) 1 Register
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Bit No. Label
Bit No.
O S C 1
V
fS
O S C 2
C r y s ta l O s c illa to r
Y S
O S C 1
D D
/4
O S C 2
R C
O s c illa to r
System Oscillator
INTC (0BH) Register
Rev. 1.10
13
May 25, 2006
HT86030/HT86070
Watchdog Timer - WDT
Power Down - HALT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled
by mask option. If the Watchdog Timer is disabled, all
the executions related to the WDT result in no operation.
The HALT mode is initialized by a HALT instruction and
results in the following:
The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected).
Once the internal WDT oscillator (RC oscillator with period 78ms normally) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approximately 20 ms. This time-out period may vary with temperature, VDD and process variations. By invoking the
WDT prescaler, longer time-out period can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of
WDTS(09H)) can give different time-out period.
· All I/O ports maintain their their original status.
· The contents of the on chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and recount
again.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². By examining the TO and PDF
flags, the reason for the chip reset can be determined.
The PDF flag is cleared when the system powers-up or
executes the ²CLR WDT² instruction, and is set when
the ²HALT² instruction is executed. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP. The other maintain
their original status.
If WS2, WS1, WS0 all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.6 seconds.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by a mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled
or the interrupt is enabled by the stack is full, the program will resume execution at the next instruction. If the
interrupt is enabled and the stack is not full, the regular
interrupt response takes place.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². Whereas in
the HALT mode, the overflow will initialize a ²warm re set² only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset
(external reset (a low level to RES), software instructions, or a HALT instruction. The software instruction is
²CLR WDT² and execution of the ²CLR WDT² instruction will clear the WDT.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
Once a wake-up event occurs, it takes 1024 system
clock period to resume normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period is finished. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled. To minimize power consumption, all I/O pins
should be carefully managed before entering the HALT
status.
WDTS (09H) Register
S y s te m
C lo c k /4
W D T
O S C
W D T P r e s c a le r
M a s k
O p tio n
S e le c t
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.10
14
May 25, 2006
HT86030/HT86070
H A L T
Reset
There are 3 ways in which a reset can occur:
W D T
· RES reset during normal operation
· RES reset during HALT
W a rm
W D T
R e s e t
T im e - o u t
R e s e t
R E S
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during any other reset
conditions. Most registers are reset to their ²initial condition² when the reset conditions are met. By examining
the PDF flag and TO flag, the program can distinguish
between different ²chip resets².
TO PDF
O S C I
C o ld
R e s e t
S S T
1 0 -s ta g e
R ip p le C o u n te r
P o w e r - o n D e te c tin g
Reset Configuration
The function unit chip reset status are shown below.
RESET Conditions
Program Counter
000H
Interrupt
Disable
Clear
0
0
RES reset during power-up
Prescaler
u
u
RES reset during normal operation
WDT
Clear. After master reset,
WDT begins counting
0
1
RES wake-up HALT
Timer/event counter
Off
1
u
WDT time-out during normal operation
Input/output ports
Input mode
1
1
WDT wake-up HALT
Stack Pointer
Points to the top of the stack
Note: ²u² stands for ²unchanged²
Timer/Event Counter 0/1
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses after a system
power up or when awakening from a HALT state.
There are four timer counters are implemented in the
HT86030/HT86070. The Timer/Event Counter 0 and 1
contain 16-bit programmable count-up counters whose
clock may come from an external source or the system
clock divided by 4 (T1). Using the internal instruction
clock (T1), there is only one reference time base. The
external clock input allows the user to count external
events, measure time intervals or pulse width, or to generate an accurate time base.
When a system power up occurs, the SST delay is
added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
V D D
R E S
tS
There are three registers related to Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH).
Writing to TMR0L only writes the data into a low byte
buffer. Writing to TMR0H will write the data and the contents of the low byte buffer into the Timer/Event Counter
0 preload register (16-bit) simultaneously. The
Timer/Event Counter 0 preload register is changed only
by a write to TMR0H operation. Writing to TMR0L will
keep the Timer/Event Counter 0 preload register unchanged.
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
V
D D
Reading TMR0H will also latch the TMR0L into the low
byte buffer to avoid false timing problems. Reading the
TMR0L only returns the value from the low byte buffer
which may be a previously loaded value. In other words,
the low byte of Timer/Event Counter 0 cannot be read directly. It must read the TMR0H first to ensure that the
low byte contents of Timer/Event Counter 0 are latched
into the buffer.
R E S
Reset Circuit
Rev. 1.10
15
May 25, 2006
HT86030/HT86070
There are three registers related to the Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).
The Timer/Event Counter 1 operates in the same manner as Timer/Event Counter 0.
overflow occurs, the counter is reloaded from the
timer/event counter preload register and generates a
corresponding interrupt request flag (T0F/T1F; bit 5/6 of
INTC) at the same time.
Bit No. Label
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR0/TMR1 has received a transient from low to high (or high to low; if the
TE bit is 0) it will start counting until the TMR0/TMR1 returns to the original level and resets TON. The measured result will remain in the timer/event counter even if
the activated transient occurs again. In other words,
only one cycle measurement can be done. When TON
is set again, the cycle measurement will function again
as long as it receives further transient pulses. Note that,
in this operating mode, the timer/event counter starts
counting not according to the logic level but according to
the transient edges. In the case of counter overflows,
the counter is reloaded from the timer/event counter
preload register and issues the interrupt request just like
in the other two modes.
¾
0~2, 5
Function
Unused bit, read as ²0²
3
TE
To define the TMR0/TMR1 active
edge of timer/event counter
(0=active on low to high;
1=active on high to low)
4
TON
To enable/disable timer counting
(0=disabled; 1=enabled)
TM0,
TM1
To define the operating mode
(TMR1, TMR0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
TMR0C (0EH)/TMR1C (11H) Register
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the
pulse width measurement mode, TON will be cleared
automatically after the measurement cycle is complete.
But in the other two modes TON can only be reset by instruction. The overflow of the timer/event counter is one
of the wake-up sources. No matter what the operation
mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service.
The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options.
The Timer/Event Counter 1 has the same options as the
Timer/Event Counter 0 and is defined by TMR1C.
The timer/event counter control registers define the operating mode, counting enable or disable and active
edge.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which implies that the clock source comes from an external pin. The timer mode functions as a normal timer
with the clock source coming from the instruction clock.
The pulse width measurement mode can be used to
count the high or low level duration of an external signal
(TMR0/TMR1). The counting method is based on the instruction clock.
In the case of a Timer/Event Counter OFF condition,
writing data to the timer/event counter preload register
will also reload that data to the timer/event counter. But
if the timer/event counter is turned on, data written to the
timer/event counter will only be kept in the timer/event
counter preload register. The timer/event counter will
continue to operate until an overflow occurs.
When the timer/event counter (reading TMR0H/
TMR1H) is read, the clock will be blocked to avoid errors. As this may result in a counting error, this must be
taken into consideration by the programmer.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once an
S y s te m
C lo c k /4
T M R 0
T M R 1
D a ta B u s
T M 1
T M 0
T im e r /E v e n t C o u n te r 0 /1
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /E v e n t
C o u n te r 0 /1
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
L o w B y te
B u ffe r
Timer/Event Counter 0/1
Rev. 1.10
16
May 25, 2006
HT86030/HT86070
Timer Counter 3
The TMR3 is internal clock source only, i.e.
(TM1,TM0)=(1,0). There is a 3-bit prescaler
(TMR3S2,TMR3S1,TMR3S0) which defines different
division ratio of TMR3¢s clock source.
The timer counter TMR3 is an 8-bit programmable
count-up counter. Its counting is as the same manner as
Timer Event Counter 0/1, but the clock source of TMR3
can be from internal instruction cycle (T1).
Bit No.
0~2
Label
3
TE
4
TON
5
¾
6
7
Function
To define the operating clock source
(TMR3S2, TMR3S1, TMR3S0)
000: clock source/2
001: clock source/4
TMR3S2,
010: clock source/8
TMR3S1,
011: clock source/16
TMR3S0
100: clock source/32
101: clock source/64
110: clock source/128
111: clock source/256
TM0,
TM1
To define the TMR3 active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
To enable/disable timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
To define the operating mode
(TM1, TM0)
01=Unused
10=Timer mode (internal clock)
11=Unused
00=Unused
TMR3C (25H) Register
(T M R 3 S 2 , T M R 3 S 1 , T M R 3 S 0 )
S y s te m
C lo c k /4
D a ta B u s
8 -S ta g e
P r e s c a le r
T im e r C o u n te r 3
P r e lo a d R e g is te r
R e lo a d
T O N
T im e r C o u n te r 3
O v e r flo w
to In te rru p t
Timer Counter 3
Rev. 1.10
17
May 25, 2006
HT86030/HT86070
The registers states are summarized in the following table.
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
Program Counter
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR0L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR0C
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR1C
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
LATCH0H
---- --xx
---- --uu
---- --uu
---- --uu
---- --uu
LATCH0M
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1H
---- --xx
---- --uu
---- --uu
---- --uu
---- --uu
LATCH1M
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
INTCH
-000 ---0
-000 ---0
-000 ---0
-000 ---0
-uuu ---u
TBHP
---x xxxx
---u uuuu
---u uuuu
---u uuuu
---u uuuu
TMR3L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMR3C
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
VOICEC
0--0 -00-
u--u -uu-
u--u -uu-
u--u -uu-
u--u -uu-
DAL
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
VOL
LATCHD
xxx- ----
uuu- ----
uuu- ----
uuu- ----
uuu- ----
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note: ²u² means ²unchanged²
²x² means ²unknown²
²-² means ²undefined²
Rev. 1.10
18
May 25, 2006
HT86030/HT86070
Each line of port A has the capability of waking-up the
device. The wake-up capability of port A is determined
by mask option. There is a pull-high option available for
all I/O lines. Once the pull-high option is selected, all I/O
lines have pull-high resistors. Otherwise, the pull-high
resistors are absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
Input/Output Ports
There are 16 bidirectional input/output lines in the
microcontroller, labeled from PA to PB, which are
mapped to the data memory of [12H] and [14H] respectively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A, [m]² (m=12H or 14H).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Audio Output and Volume Control - DAL, DAH, VOL
The HT86030/HT86070 provides one 12-bit voltage
type DAC device for driving external 8W speaker
through an external NPN transistor. The programmer
must write the voice data to register DAL (27H) and DAH
(28H). The 12-bit audio output will be written to the
higher nibble of DAL and the whole byte of DAH, and the
DAL3~0 is always read as 0H. There are 8 scales of volume controllable level that are provided for the voltage
type DAC output. The programmer can change the volume by only writing the volume control data to the
higher-nibble of the VOL (29H), and the lower-nibble of
VOL (29H) is always read as 0H.
Each I/O line has its own control register (PAC, PBC) to
control the input/output configuration. With this control
register, CMOS output or Schmitt trigger input with or
without pull-high resistor structures can be reconfigured
dynamically (i.e. on-the-fly) under software control. To
function as an input, the corresponding latch of the control register must write ²1². The input source also depends on the control register. If the control register bit is
²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the
in t e rn a l b u s . Th e l at t er i s p o s s i bl e i n t h e
²read-modify-write² instruction.
Voice Control Register
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H
and 15H.
The voice control register controls the voice ROM circuit
and DAC circuit, selects voice ROM latch counter. If the
DAC circuit is not enabled, any DAH/DAL output is invalid. Writing a ²1² to DAC bit is to enable DAC circuit,
and writing a ²0² to DAC bit is to disable DAC circuit. If
the voice ROM circuit is not enabled, then voice ROM
data cannot be accessed at all. Writing a ²1² to VROMC
bit is to enable the voice ROM circuit, and writing a ²0² to
VROMC bit is to disable the voice ROM circuit. The bit 4
(LATCHC) is to determine what voice ROM address
latch counter will be adopted as voice ROM address
latch counter.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
D a ta B u s
D
Q
C K
W r ite C o n tr o l R e g is te r
V
Q
S
V
C h ip R e s e t
D
P A 0 ~ P A 7
P B 0 ~ P B 7
Q
C K
S
Q
M
R e a d I/O
S y s te m
W e a k
P u ll- u p
M a s k O p tio n
R e a d C o n tr o l R e g is te r
W r ite I/O
D D
D D
U
X
W a k e - U p ( P A o n ly )
M a s k O p tio n
Input/Output Ports
Rev. 1.10
19
May 25, 2006
HT86030/HT86070
Bit No.
Label
0, 3, 5~6
¾
1
DAC
Function
Unused bit, read as ²0²
Enable/disable DAC circuit (0= disable DAC circuit; 1= enable DAC circuit)
The DAC circuit is not affected by the HALT instruction.
The software controls bit DAC (VoiceC.1) whether to enable/disable.
2
VROMC Enable/disable voice ROM circuit (0= disable voice ROM circuit; 1= enable voice ROM circuit)
4
LATCHC Select voice ROM counter (0= voice ROM address latch 0; 1= voice ROM address latch 1)
VOICEC (26H) Register
Voice ROM Data Address Latch Counter
Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0
LATCH0H(18H)/LATCH0M(19H)/LATCH0L(1AH),
LATCH1H(1BH)/LATCH1M(1CH)/LATCH1L(1DH) and
voice ROM data register(2AH)
The voice ROM data address latch counter is the handshaking between the microcontroller and voice ROM,
where the voice codes are stored. One 8-bit of voice
ROM data will be addressed by setting 18-bit address
latch counter LATCH0H/LATCH0M/LATCH0L or
LATCH1H/LATCH1M/LATCH1L. After the 8-bit voice
ROM data is addressed, a few instruction cycles (4ms at
least) will be cost to latch the voice ROM data, then the
microcontroller can read the voice data from
LATCHD(2AH).
set
[26H].2
; Enable voice ROM circuit
clr
[26H].4
; Select voice ROM address
; latch counter 0
mov
A, 07H
;
mov
LATCH0L, A ; Set LATCH0L to 07H
mov
A, 00H
mov
LATCH0M, A ; Set LATCH0M to 00H
mov
A, 00H
mov
LATCH0H, A ; Set LATCH0H to 00H
call
Delay Time
; Delay a short period of time
mov
A, LATCHD
; Get voice data at 000007H
;
;
Mask Option
Mask Option
Description
PA Wake-up
Enable/disable PA wake-up function
Watchdog Timer (WDT)
Enable/disable WDT function
One or two CLR instruction
WDT clock source is from WDTOSC or T1
External INT Trigger Edge
External INT is triggered on falling edge only, or is triggered on falling and rising
edge.
External Timer 0/1 Clock Source Enable/disable external timer of timer 0 and timer 1.
PA Pull-high
Enable/disable PA pull-high
PB Pull-high
Enable/disable PB pull-high
fOSC - ROSC Table (VDD=3V)
Rev. 1.10
fOSC
ROSC
4MHz±10%
6MHz±10%
8MHz±10%
300kW
200kW
150kW
20
May 25, 2006
HT86030/HT86070
Application Circuits
V
D D
1 0 W
4 7 m F
0 .1 m F
V D D A
O S C 2
O S C 1
V
D D
V D D
1 0 0 m F
P A 0 ~ P A 7
V
P B 0 ~ P B 7
1 0 0 k W
R E S
V
0 .1 m F
D D
S P K
0 .1 m F
(8 W /1 6 W )
D D
A U D
8 0 5 0
V S S
R 1
R 2
V S S A
IN T
H T 8 6 0 3 0 /H T 8 6 0 7 0
N o te : R 1 > R 2
V
D D
1 0 W
4 7 m F
0 .1 m F
V D D A
O S C 2
4 M H z ~ 8 M H z
O S C 1
V
D D
P A 0 ~ P A 7
V D D
1 0 0 m F
C E
1 0 0 k W
V
A U D
A u d io In
0 .1 m F
2
A u d io In
D D
3
IN T
V R E F
N C
H T 8 6 0 3 0 /H T 8 6 0 7 0
21
6
D D
8
H T 8 2 V 7 3 3
1 0 m F
V S S A
V
O U T N
V D D
O U T P
V S S
Rev. 1.10
1
5
R E S
0 .1 m F
P B 0 ~ P B 7
4 7 m F
S P K
(8 W /1 6 W )
4
7
May 25, 2006
HT86030/HT86070
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.10
22
May 25, 2006
HT86030/HT86070
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
Rev. 1.10
23
May 25, 2006
HT86030/HT86070
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
24
May 25, 2006
HT86030/HT86070
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
25
May 25, 2006
HT86030/HT86070
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
26
May 25, 2006
HT86030/HT86070
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
27
May 25, 2006
HT86030/HT86070
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
28
May 25, 2006
HT86030/HT86070
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
29
May 25, 2006
HT86030/HT86070
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
May 25, 2006
HT86030/HT86070
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
31
May 25, 2006
HT86030/HT86070
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
May 25, 2006
HT86030/HT86070
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
May 25, 2006
HT86030/HT86070
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
May 25, 2006
HT86030/HT86070
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
May 25, 2006
HT86030/HT86070
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
36
May 25, 2006
HT86030/HT86070
Package Information
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.10
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
37
May 25, 2006
HT86030/HT86070
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
330±1
2±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.10
38
May 25, 2006
HT86030/HT86070
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24±0.3
P
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.10
21.3
39
May 25, 2006
HT86030/HT86070
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 0755-8616-9908, 8616-9308
Fax: 0755-8616-9533
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 028-6653-6590
Fax: 028-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
40
May 25, 2006