LTC4307 Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery U FEATURES DESCRIPTIO ■ The LTC®4307 hot swappable, 2-wire bus buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. The LTC4307 provides bidirectional buffering, keeping the backplane and card capacitances isolated. Low offset and high VOL tolerance allows multiple devices to be cascaded on the clock and data busses. If SDAOUT or SCLOUT are low for 30ms, the LTC4307 will automatically break the bus connection. At this time the LTC4307 automatically generates up to 16 clock pulses on SCLOUT in an attempt to free the bus. A connection will resume if the stuck bus is cleared. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Bidirectional Buffer with Stuck Bus Recovery 60mV Buffer Offset Independent of Load 30ms Stuck Bus Timeout Compatible with Non-Compliant VOL I2C Devices Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane ±5kV Human Body Model ESD Protection Isolates Input SDA and SCL Line from Output Compatible with I2CTM, I2C Fast Mode and SMBus READY Open-Drain Output 1V Precharge on All SDA and SCL Lines High Impedance SDA, SCL Pins for VCC = 0V Small 8-Lead (3mm × 3mm) DFN and 8-Lead MSOP Packages U APPLICATIO S ■ ■ ■ ■ ■ Live Board Insertion Servers Capacitance Buffer/Bus Extender RAID Systems ATCA During insertion, the SDA and SCL lines are pre-charged to 1V to minimize bus disturbances. When driven high, the ENABLE input allows the LTC4307 to connect after a stop bit or bus idle. Driving ENABLE low breaks the connection between SDAIN and SDAOUT, SCLIN and SCLOUT. READY is an open-drain output which indicates that the backplane and card sides are connected. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7032051, 6356140, 6650174 U TYPICAL APPLICATIO 3.3V Rising Edge from Asserted Low 0.01μF 10k VCC 2.7k 2.7k VCC 100k LTC4307 MICROCONTROLLER 10k 10k 0.01μF ENABLE ENABLE SCLIN SCLOUT SDAIN SDAOUT 800 LTC4307 SCLIN SCLOUT SDAIN SDAOUT CARD_SCL CARD_SDA 3.3V 3.3V 200mV/DIV 10k 1000 600 LOW OFFSET SDAOUT 400 SDAIN 10k 10k READY GND READY GND 4307 TA01a 200 0 0 CARD BACKPLANE CONNECTOR CONNECTOR 100 200 300 400 100ns/DIV 500 600 4307 TA01b CARD 4307f 1 LTC4307 U W W W ABSOLUTE AXI U RATI GS (Notes 1, 7) VCC to GND ................................................. – 0.3V to 6V SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE .......................................... –0.3V to 6V Maximum Sink Current (SDAIN, SCLIN, SDAOUT, SCLOUT, READY) .............................................. 50mA Operating Temperature Range LTC4307C ................................................ 0°C to 70°C LTC4307I .............................................– 40°C to 85°C Storage Temperature Range DFN....................................................– 65°C to 125°C MSOP ................................................– 65°C to 150°C Lead Temperature (Soldering, 10 sec) MSOP ............................................................... 300°C U W U PACKAGE/ORDER I FOR ATIO ENABLE 1 8 VCC SCLOUT 2 7 SDAOUT 6 SDAIN 5 READY SCLIN 3 9 GND 4 ORDER PART NUMBER ORDER PART NUMBER TOP VIEW DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 9) CONNECTION TO GND IS OPTIONAL LTC4307CDD LTC4307IDD DD PART* MARKING TOP VIEW ENABLE SCLOUT SCLIN GND LBTW LBTW 1 2 3 4 8 7 6 5 VCC SDAOUT SDAIN READY LTC4307CMS8 LTC4307IMS8 MS8 PART* MARKING MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 200°C/W LTBTV LTBTV Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply ● VCC Positive Supply Voltage ICC Supply Current VCC = 5.5V, VSCLOUT = VSDAOUT = 0V (Note 6) ISD Shutdown Supply Current VCC = 5.5V, ENABLE = GND, SDA, SCL = 5.5V ● SDA, SCL Floating 2.3 ● 5.5 V 8 11 mA 900 1200 μA ● 0.8 1 1.2 V ● 55 95 175 μs 0.8 1.4 2 V 0.1 ±5 μA VPRE Precharge Voltage tIDLE Bus Idle Time VTHR_ENABLE ENABLE Threshold IENABLE ENABLE Input Current ENABLE from 0V to VCC tPLH_EN ENABLE Delay Off-On VCC = 3.3V (Figure 1) 95 μs ● tPHL_EN ENABLE Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns tPLH_READY READY Delay Off-On VCC = 3.3V (Note 3) (Figure 1) 10 ns tPHL_READY READY Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns VOL_READY READY Output Low Voltage IPULLUP = 3mA, VCC = 2.3V ● IOFF_READY READY Off Leakage Current VCC = READY = 5.5V ● 0.1 0.4 V ±5 μA 4307f 2 LTC4307 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Propagation Delay and Rise-Time Accelerators tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL, VCC = 3.3V (Notes 2, 3) (Figure 1) 70 ns tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL, VCC = 3.3V (Notes 2, 3) (Figure 1) 10 ns tRISE SDA/SCL Transition Time Low to High CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC = 3.3V (See Notes 3, 4) (Figure 1) 30 300 ns tFALL SDA/SCL Transition Time High to Low CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC = 3.3V (See Notes 3, 4) (Figure 1) 30 300 ns IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, VCC = 3.3V (Note 5) 5 8 20 60 mA Input-Output Connection ● VOS Input-Output Offset Voltage 2.7k to VCC on SDA, SCL, VCC = 3.3V, Driven SDA/SCL = 0.2V VTHR SDA, SCL Logic Input Threshold Voltage Rising Edge VHYS SDA, SCL Logic Input Threshold Voltage Hysteresis (Note 3) CIN Digital Input Capacitance SDAIN, SDAOUT, SCLIN, SCLOUT (Note 3) ILEAK Input Leakage Current SDA, SCL, Pins ● VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA, Driven SDA/SCL = 0.2V, VCC = 2.7V ● 0 2.7k to VCC on SDA, SCL, VCC = 3.3V, Driven SDA/SCL = 0.1V ● 120 VCC = 3.3V ● VCC = 3.3V, SDAOUT, SCLOUT = 0V ● VILMAX Buffer Input Logic Low Voltage 100 mV 0.45VCC 0.55VCC 0.65VCC 50 160 V mV 10 pF ±5 μA 0.4 V 205 mV 1.2 V 35 ms Bus Stuck Low Timeout tTIMEOUT Bus Stuck Low Timer 25 30 400 600 Timing Characteristics fI2C,MAX I2C Maximum Operating Frequency (Note 3) tBUF Bus Free Time Between Stop and Start Condition (Note 3) 1.3 μs tHD,STA Hold Time After (Repeated) Start Condition (Note 3) 100 ns tSU,STA Repeated Start Condition Set-Up Time (Note 3) 0 ns tSU,STO Stop Condition Set-Up Time (Note 3) 0 ns tHD,DATI Data Hold Time Input (Note 3) 0 ns tSU,DAT Data Set-Up Time (Note 3) 100 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: See “Propagation Delays” in the Operations section for a discussion of tPHL and tPLH as a function of pull-up resistance and bus capacitance. Note 3: Determined by design, not tested in production. kHz Note 4: Measure points are 0.3 • VCC and 0.7 • VCC. Note 5: IPULLUP varies with temperature and VCC voltage as shown in the Typical Performance Characteristics section. Note 6: ICC test performed with connection circuitry active. Note 7: All currents into pins are positive; all voltages are referenced to GND unless otherwise specified. 4307f 3 LTC4307 TIMING DIAGRAMS ENABLE, CONNECT, READY Timing tPHL_READY tPHL_EN tPLH_READY tPLH_EN ENABLE CONNECT READY 4307 TD01 Rising and Falling Propagation Delay and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT tRISE tPLH tPHL tRISE tFALL tFALL SDAIN/SCLIN SDAOUT/SCLOUT 4307 TD02 Figure 1. Timing Diagrams 4307f 4 LTC4307 U W TYPICAL PERFOR A CE CHARACTERISTICS ICC vs Temperature TA = 25°C, VCC = 3.3V, unless otherwise indicated. ISD vs Temperature IPULLUPAC vs Temperature 20 8.3 950 VCC = 5.5V 8.0 16 7.1 6.8 VCC = 2.3V 6.5 12 ISD (μA) IPULLUPAC (mA) VCC = 3.3V VCC = 3.3V 8 4 850 VCC = 3.3V 800 750 VCC = 2.3V 6.2 0 50 25 TEMPERATURE (°C) 75 0 –50 100 –25 25 50 0 TEMPERATURE (°C) 75 700 –50 100 –25 25 50 0 TEMPERATURE (°C) 4307 G02 4307 G01 75 100 4307 G02 Input-Output High to Low Propagation Delay vs COUT Input-Output High to Low Propagation Delay vs Temperature 130 100 VCC = 5.5V CIN = 50pF RPULLUPIN = RPULLUPOUT = 10k 120 VCC = 2.3V 80 110 VCC = 5.5V VCC = 3.3V tPHL (ns) 60 40 100 90 VCC = 3.3V 80 20 70 CIN = COUT = 50pF RPULLUPIN = RPULLUPOUT = 10k 0 –50 –25 60 0 25 50 TEMPERATURE (°C) 75 0 100 200 400 600 COUT (pF) 1000 800 4307 G07 4307 G04 Connection Circuitry VOUT – VIN (VOS) Bus Stuck Low Timeout vs VCC 85 34 75 32 tTIMEOUT (ms) –25 tPHL (ns) 5.9 –50 VOUT – VIN (mV) ICC (mA) 7.4 VCC = 5.5V 900 VCC = 5.5V 7.7 65 30 28 55 26 45 1 2 3 4 5 6 7 RPULLUP (kΩ) 8 9 10 4307 G05 2 2.5 3 4 3.5 VCC (V) 4.5 5 5.5 4307 G06 4307f 5 LTC4307 U U U PI FU CTIO S ENABLE (Pin 1): Connection Enable Input. This is a 1.4V digital threshold input pin. For normal operation pull or tie ENABLE high. Driving ENABLE below 0.8V isolates SDAIN from SDAOUT, SCLIN from SCLOUT and asserts READY low. A rising edge on ENABLE after a fault has occurred forces a connection between SDAIN, SDAOUT and SCLIN, SCLOUT. Connect to VCC if unused. connection sequence described in the Operation section has not been completed. READY also goes low when the LTC4307 disconnects the inputs from the outputs due to the bus being stuck low for at least 30ms. READY goes high when ENABLE is high and a connection is made. Connect a pull-up resistor, typically 10k, from this pin to VCC to provide the pull-up. This pin can be floated if unused. SCLOUT (Pin 2): Serial Clock Output. Connect this pin to an SCL bus segment where stuck bus recovery is needed. A pull-up resistor should be connected between this pin and VCC. SDAIN (Pin 6): Serial Data Input. Connect this pin to an SDA bus segment that needs to be isolated from stuck bus problems. A pull-up resistor should be connected between this pin and VCC. SCLIN (Pin 3): Serial Clock Input. Connect this pin to an SCL bus segment that needs to be isolated from stuck bus problems. A pull-up resistor should be connected between this pin and VCC. SDAOUT (Pin 7): Serial Data Output. Connect this pin to the SDA bus segment where stuck bus recovery is needed. A pull-up resistor should be connected between this pin and VCC. GND (Pin 4): Device Ground. Connect this pin to a ground plane for best results. VCC (Pin 8): Supply Voltage Input. Place a bypass capacitor of at least 0.01μF close to VCC for best results. READY (Pin 5): Connection READY Status Output. The READY pin is an open-drain N-channel MOSFET output that pulls low when ENABLE is low, or when the start-up and Exposed Pad (Pin 9, DFN Package Only): Exposed Pad may be left open or connected to device ground. 4307f 6 LTC4307 W BLOCK DIAGRA Low Offset 2-Wire Bus Buffer with Stuck Low Timeout 8mA 8mA CONNECT IBOOSTSDA 6 VCC 8 IBOOSTSDA SDAIN SDAOUT SLEW RATE DETECTOR 7 SLEW RATE DETECTOR 100k 100k CONNECT PRECHARGE 100k PC_CONNECT PC_CONNECT 8mA CONNECT IBOOSTSCL 3 100k 8mA IBOOSTSCL SCLIN SCLOUT SLEW RATE DETECTOR 2 SLEW RATE DETECTOR + CONNECT – 0.55VCC 30ms TIMER + + 0.55VCC – IBOOSTSCL IBOOSTSDA + – 0.55VCC LOGIC 0.55VCC – READY PC_CONNECT 1 ENABLE CONNECT 5 + 1.4V – UVLO 95μs DELAY CONNECT GND 4 4307 BD OPERATION Start-Up When the LTC4307 first receives power on its VCC pin, either during power-up or live insertion, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2V (typ). This is to ensure that the LTC4307 does not try to function until it has enough voltage to do so. During this time, the 1V precharge circuitry is active and forces 1V through 100k nominal resistors to the SDA and SCL pins. Because the I/O card is being plugged into a live backplane, the voltage on the backplane SDA and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the worst-case voltage differential these pins will see at the 4307f 7 LTC4307 OPERATION moment of connection, therefore minimizing the amount of disturbance caused by the I/O card. Once the LTC4307 comes out of UVLO, it monitors both the backplane and card sides for either a stop bit or bus idle condition to indicate the completion of data transactions. When both sides are idle or one side has a stop bit condition while the other is idle, the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with those on the backplane. In addition, the precharge circuitry is deactivated and will not be reactivated unless the VCC voltage falls below the UVLO threshold. Connection Circuitry Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages being low. The LTC4307 is tolerant of I2C bus DC logic low voltages up to the 0.3VCC VIL I2C specification. When the LTC4307 senses a rising edge on the bus, it deactivates its pull-down devices for bus voltages as low as 0.48V and activates its accelerators. This methodology maximizes the effectiveness of the rise time accelerator circuitry and maintains compatibility with the other devices in the LTC4300 bus buffer family. Care must be taken to ensure that devices participating in clock stretching or arbitration force logic low voltages below 0.48V at the LTC4307 inputs. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the LTC4307. Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and card capacitances isolated. Because of this isolation, the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms as described here. Input to Output Offset Voltage When a logic low voltage, VLOW1, is driven on any of the LTC4307’s data or clock pins, the LTC4307 regulates the voltage on the opposite data or clock pins to a slightly higher voltage, typically 60mV above VLOW1. This offset is practically independent of pull-up current (see the Typical Performance curves). Propagation Delays During a rising edge, the rise time on each side is determined by the bus pull-up resistor and the equivalent capacitance on the line. If the pull-up resistors are the same, a difference in rise time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure 2 for VCC = 5.5V and a 10k pull-up resistor on each side (50pF on one side and 150pF on the other). Since the output side has less capacitance than the input, it rises faster and the effective propagation delay is negative. There is a finite propagation delay through the connection circuitry for falling waveforms. Figure 3 shows the falling edge waveforms for the same pull-up resistors and equivalent capacitance conditions as used in Figure 2. An external N-channel MOSFET device pulls down the voltage on the side with 150pF capacitance; the LTC4307 pulls down the voltage on the opposite side with a delay of 80ns. This delay is always positive and is a function of supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows propagation delay as a function of temperature and voltage for 10k pull-up resistors and 50pF equivalent capacitance on both sides of the part. Also, the tPHL vs COUT curve for VCC = 5.5V shows that increasing the capacitance from 50pF to 150pF results in a tPHL increase from 81ns to 91ns. Larger output capacitances translate to longer delays (up to 125ns). Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. 4307f 8 LTC4307 OPERATION OUTPUT SIDE 50pF 1V/DIV INPUT SIDE 150pF 1V/DIV 200ns/DIV INPUT SIDE 150pF 1V/DIV 4307 F02 Figure 2. Input-Output Rising Edge Waveforms Bus Stuck Low Timeout When SDAOUT or SCLOUT is low, an internal timer is started. The timer is only reset by that respective input going high. If it does not go high within 30ms (typical) the connection between SDAIN and SDAOUT, and between SCLIN and SCLOUT is broken. After at least 40μs, the LTC4307 automatically generates up to 16 clock pulses at 8.5kHz (typical) on SCLOUT in an attempt to unstick the bus. When the clock pulses are completed, a stop bit will be generated on SCLOUT and SDAOUT to reset any circuity on that bus. When the low SDAOUT or SCLOUT pin goes high, a connection is enabled waiting for a stop bit or a bus idle to make a connection. When powering up into a bus stuck low condition, the connection circuitry joining the SDA and SCL busses on the I/O card with those on the backplane is not activated and is only reset when SDAOUT and SCLOUT are high. 30ms after UVLO, automatic clocking takes place as described above. READY Digital Output This pin provides a digital flag which is low when either ENABLE is low, the start-up sequence described earlier in this section has not been completed, or the LTC4307 has disconnected due to a stuck bus condition. READY goes high when ENABLE is high and the backplane and card sides are connected. The pin is driven by an open-drain pull-down capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor to VCC to provide the pull-up. ENABLE When the ENABLE pin is driven below 0.8V with respect to the LTC4307’s ground, the backplane side is disconnected from the card side and the READY pin is internally pulled OUTPUT SIDE 50pF 1V/DIV 200ns/DIV 4307 F03 Figure 3. Input-Output Falling Edge Waveforms low. When the pin is driven above 2V, the part waits for data transactions on both the backplane and card sides to be complete (as described in the Start-Up section) before connecting the two sides. At this time the internal pulldown on READY releases. When ENABLE is low, automatic clocking is disabled. A rising edge on ENABLE after a bus stuck low condition has occurred forces a connection between SDAIN, SDAOUT, and SCLIN, SCLOUT even if the bus stuck low condition has not been cleared. At this time the 30ms timer is reset but not disabled. Rise Time Accelerators Once connection has been established, rise time accelerator circuits on all four SDA and SCL pins are enabled. During positive bus transitions, the rise time accelerators provide strong, slew-limited pull-up currents that make the bus voltage rise at a rate of 100V/μs. The rise time accelerators significantly improve system reliability in two ways. First, they provide smooth, controlled transitions during rising edges for both small and large systems. Because the accelerator pull-up impedance is significantly lower than the bus pull-up resistance, the system is much less susceptible to noise on rising edges. Second, the accelerators allow users to choose large bus pull-up resistors, reducing power consumption and improving logic low noise margin. For these reasons, it is strongly recommended that users choose bus pull-up resistors so that the bus will rise on its own at a rate of at least 0.8V/μs to guarantee activation of the accelerators. The rise time accelerators are disabled until the sequence of events described in the start-up section has been completed. They are also disabled during automatic clocking. 4307f 9 LTC4307 APPLICATIONS INFORMATION Live Insertion and Capacitance Buffering Application Figures 4 and 5 illustrate applications of the LTC4307 that take advantage of the LTC4307’s Hot SwapTM , capacitance buffering and precharge features. If the I/O cards were plugged directly into the backplane without the LTC4307 buffer, all of the backplane and card capacitances would add directly together, making rise-time and fall-time requirements difficult to meet. Placing an LTC4307 on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the LTC4307 drives the capacitance of everything on the card and the backplane must drive only the capacitance of the LTC4307, which is less than 10pF. Hot Swap is a trademark of Linear Technology Corporation. In most applications the LTC4307 will be used with a staggered connector where VCC and GND will be long pins. SDA and SCL are medium length pins to ensure that the VCC and GND pins make contact first. This will allow the precharge circuitry to be activated on SDA and SCL before they make contact. ENABLE is a short pin that is pulled down when not connected. This is to ensure that the connection between the backplane and the card’s data and clock busses is not is not enabled until the transients associated with live insertion have settled. Figure 4 shows the LTC4307 in an application with a staggered connector. The LTC4307 receives its VCC voltage from one of the long “early power” pins. Establishing early power VCC ensures that the 1V precharge voltage is present at SDAIN and SCLIN before they make contact. BACKPLANE CARD CONNECTOR CONNECTORS BACKPLANE I/O PERIPHERAL CARD 1 VCC R1 10k R2 10k C1 0.01μF R3 10k R5 10k VCC SDA SCL ENA1 READY R4 10k R6 10k SDAIN SDAOUT SCLIN SCLOUT LTC4307 ENABLE READY GND CARD1_SDA CARD1_SCL • • • I/O PERIPHERAL CARD N C2 0.01μF VCC ENAn R7 10k SDAIN SDAOUT SCLIN SCLOUT LTC4307 ENABLE READY GND R8 10k R9 10k CARDn_SDA CARDn_SCL 4307 F04 Figure 4. The LTC4307 in an Application with a Staggered Connector 4307f 10 LTC4307 APPLICATIONS INFORMATION The ENABLE pin is driven using a short pin. This is to ensure that a connection is not enabled until the transients associated with live insertion have settled. Figure 5 shows the LTC4307 in an application where all of the pins have the same length. In this application a resistor is used to hold the ENABLE pin low during live insertion, until the backplane control circuitry can enable the device. Repeater/Bus Extender Applications Users who wish to connect two 2-wire systems separated by a distance can do so by connecting two LTC4307s backto-back, as shown in Figure 6. The I2C specification allows for 400pF maximum bus capacitance, severely limiting the length of the bus. The SMBus specification places no restriction on bus capacitance, but the limited impedances of devices connected to the bus require systems to remain small if rise time and fall time specifications are to be met. In this situation, the differential ground voltage between the two systems may limit the allowed distance, because a valid logic-low voltage with respect to the ground at one end of the system may violate the allowed VOL specification with respect to the ground at the other end. In addition, the connection circuitry offset voltages of the back-to-back LTC4307s add together, directly contributing to the same problem. Figure 7 further illustrates a repeater application. This circuit could be used in an AdvancedTCA system. In AdvancedTCA applications, the bus pull-up resistance on the backplane is quite small. Since there is no effect on the offset due to the pull-up impedance, multiple LTC4307 buffers can be used in a single system. This allows the user to divide the line and device capacitances into more sections with buffering and meet rise and fall times. The LTC4307 disconnects when both bus I/Os are above 0.48V and rising. In systems with large ground bounce, if many devices are cascaded, the 0.48V threshold can be exceeded and the transients associated with the ground bounce can appear to be a rising edge. Under this condition, the LTC4307 with inputs above 0.48V may disconnect. BACKPLANE CARD CONNECTOR CONNECTORS BACKPLANE I/O PERIPHERAL CARD 1 VCC R1 10k R2 10k C1 0.01μF R3 10k R5 10k VCC SDA SCL ENA1 READY R4 10k R6 10k SDAIN SDAOUT SCLIN SCLOUT LTC4307 ENABLE READY GND CARD1_SDA CARD1_SCL • • • I/O PERIPHERAL CARD N C2 0.01μF VCC ENAn R7 10k R8 10k R9 10k SDAIN SDAOUT SCLIN SCLOUT LTC4307 ENABLE READY GND CARDn_SDA CARDn_SCL 4307 F05 Figure 5. The LTC4307 in an Application Where All the Pins Have the Same Length 4307f 11 LTC4307 APPLICATIONS INFORMATION Systems with Supply Voltage Droop millivolts or more. This situation is modeled by a series resistor in the VCC line, as shown in Figure 8. For proper operation, make sure that the VCC(LTC4307) is ≥ 2.3V. In large 2-wire systems, the VCC voltages seen by devices at various points in the system can differ by a few hundred 3.3V C1 0.01μF R1 10k R2 10k R3 10k SDA1 SCL1 VCC LTC4307 ENABLE READY SDAIN SDAOUT SCLIN SCLOUT C2 0.01μF R4 10k R5 10k R6 10k VCC LTC4307 ENABLE READY SDAIN SDAOUT SCLIN SCLOUT GND R7 10k R8 10k SDA2 SCL2 GND 4307 F06 Figure 6. The LTC4307 in a Repeater/Bus Extender Application Where Two 2-Wire Systems are Separated by a Distance VCC R1 2.7k SDA1 SCL1 R2 2.7k C1 0.01mF VCC LTC4307 ENABLE READY SDAOUT SDAIN SCLOUT SCLIN R3 10k R4 2.7k R5 2.7k R6 10k GND C2 0.01mF VCC LTC4307 ENABLE READY SDAIN SDAOUT SCLIN SCLOUT R7 2.7k R8 2.7k C3 0.01mF R9 10k GND VCC LTC4307 ENABLE READY SDAIN SDAOUT SCLIN SCLOUT R10 2.7k R11 2.7k SDA2 SCL2 GND 4307 F07 Figure 7. The LTC4307 in a Repeater Application. The LTC4307’s Low Offset Allows Cascading of Multiple Devices RDROOP VCC(LTC4307) VCC(BUS) C1 0.01μF R1 10k READY SDA1 SCL1 R2 10k R3 10k VCC LTC4307 ENABLE READY SDAIN SDAOUT SCLIN SCLOUT GND R4 10k R5 10k SDA2 SCL2 4307 F08 Figure 8. System with Voltage Droop 4307f 12 LTC4307 TYPICAL APPLICATIONS High VIL Application 5V R1 1.8k R2 1.8k R3 200Ω R5 10k R6 10k ENABLE SCLIN TEMPERATURE SENSOR C1 0.01μF VCC R4 200Ω SCL SCLOUT LTC4307 SDAIN SDAOUT SDA 5V R7 10k READY GND READY 4307 TA02 Simplified ATCA IPMB Application SHELF MANAGER –48V DC/DC 3.3V R1 10k VCC ShMC C1 0.01μF R2 10k ENABLE ATCA BOARD –48V –48V R3 2.7k DC/DC C2 0.01μF R4 2.7k VCC SDAOUT LTC4307 SCLOUT SCLIN IPM BUS (1 OF 2) R5 10k R6 10k VCC ENABLE VCC SDAOUT LTC4307 SCLOUT SCLIN IPMC SDAIN SDAIN 3.3V 4307 TA03 4307f 13 LTC4307 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.38 ± 0.10 8 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 1203 0.25 ± 0.05 0.200 REF 0.50 BSC 2.38 ±0.05 (2 SIDES) 0.75 ±0.05 0.00 – 0.05 4 0.25 ± 0.05 1 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 4307f 14 LTC4307 PACKAGE DESCRIPTION MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 0.254 (.010) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.52 (.0205) REF 0° – 6° TYP GAUGE PLANE 5.23 (.206) MIN 1 3.20 – 3.45 (.126 – .136) 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 1.10 (.043) MAX 2 3 4 0.86 (.034) REF 0.18 (.007) RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS8) 0307 REV F 4307f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC4307 TYPICAL APPLICATION The LTC4307 in a Repeater Application. The LTC4307’s Low Offset Allows Cascading of Multiple Devices VCC R1 2.7k R2 2.7k SDA1 SCL1 C1 0.01mF VCC LTC4307 ENABLE READY SDAOUT SDAIN SCLOUT SCLIN R4 2.7k R3 10k R5 2.7k R6 10k C2 0.01mF VCC LTC4307 ENABLE READY SDAIN SDAOUT SCLIN SCLOUT GND R7 2.7k GND R8 2.7k C3 0.01mF R9 10k VCC LTC4307 ENABLE READY SDAIN SDAOUT SCLIN SCLOUT R10 2.7k R11 2.7k SDA2 SCL2 GND 4307 F07 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1380/LTC1393 Single-Ended 8-Channel/Differential 4-Channel Analog MUX with SMBus Interface Low RON: 35Ω Single Ended/70Ω Differential, Expandable to 32 Single or 16 Differential Channels LTC1427-50 Micropower, 10-Bit Current Output DAC with SMBus Interface Precision 50μA ±2.5% Tolerance Over Temperature, Four Selectable SMBus Addresses, DAC Powers Up at Zero or Midscale LTC1623 Dual High Side Switch Controller with SMBus Interface Eight Selectable Addresses/16-Channel Capability LTC1663 SMBus Interface 10-Bit Rail-to-Rail Micropower DAC DNL < 0.75LSB Max, 5-Lead SOT-23 Package LTC1694/LTC1694-1 SMBus Accelerator Improved SMBus/I2C Rise Time, Ensures Data Integrity with Multiple SMBus/I2C Devices LTC1695 SMBus/I2C Fan Speed Controller in ThinSOTTM Package 0.75Ω PMOS 180mA Regulator, 6-Bit DAC LT1786F SMBus Controlled CCFL Switching Regulator 1.25A, 200kHz Floating or Grounded Lamp Configurations LTC1840 Dual I2C Fan Speed Controller Two 100μA 8-Bit DACs, Two Tach Inputs, Four GPIO LTC4300A-1/ LTC4300A-2/ LTC4300A-3 Hot Swappable 2-Wire Bus Buffers LTC4300A-1: Bus Buffer with READY, ACC and ENABLE LTC4300A-2: Dual Supply Bus Buffer with READY and ACC LTC4300A-3: Dual Supply Bus Buffer with READY and ENABLE LTC4301 Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent LTC4301L Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Translation Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN LTC4302-1/LTC4302-2 Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled LTC4303/LTC4304 Hot Swappable 2-Wire Bus Buffers with Stuck Bus Recovery Provides Automatic Clocking to Free Stuck I2C Busses LTC4305/LTC4306 2-/4-Channel, 2-Wire Bus Multiplexers with Capacitance Buffering 2/4 Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time Accelerators, Fault Reporting, ±10kV HBM ESD Tolerance ThinSOT is a trademark of Linear Technology Corporation 4307f 16 Linear Technology Corporation LT 0507 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007