ON MC74HC74ADTR2G Dual d flip-flop with set and reset Datasheet

MC74HC74A
Dual D Flip-Flop with Set
and Reset
High−Performance Silicon−Gate CMOS
The MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
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MARKING
DIAGRAMS
14
14
1
Features
•
•
•
•
•
•
•
•
PDIP−14
N SUFFIX
CASE 646
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 128 FETs or 32 Equivalent Gates
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
MC74HC74AN
AWLYYWWG
1
14
SOIC−14
D SUFFIX
CASE 751A
14
1
HC74AG
AWLYWW
1
14
14
1
HC
74A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
14
14
1
SOEIAJ−14
F SUFFIX
CASE 965
74HC74A
ALYWG
1
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 12
1
Publication Order Number:
MC74HC74A/D
MC74HC74A
PIN ASSIGNMENT
LOGIC DIAGRAM
RESET 1
1
14
VCC
DATA 1
2
13
RESET 2
RESET 1
DATA 1
CLOCK 1
3
12
DATA 2
SET 1
4
11
CLOCK 2
Q1
5
10
SET 2
Q1
6
9
Q2
GND
7
8
Q2
CLOCK 1
SET 1
RESET 2
DATA 2
FUNCTION TABLE
Inputs
Set Reset Clock Data
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
CLOCK 2
Outputs
X
X
X
L
H
X
X
X
H
L
X
X
X
Q
Q
SET 2
1
2
5
3
6
Q1
Q1
4
13
12
9
11
8
Q2
Q2
10
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
PIN 14 = VCC
PIN 7 = GND
*Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
Plastic DIP†
SOIC Package†
TSSOP Package†
_C
260
300
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figures 1, 2, 3)
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
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2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC74A
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Vin = VIH or VIL
VOL
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
Vin = VIH or VIL
|Iout| v 20 mA
Maximum Low−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
2.0
20
80
mA
VCC
V
– 55 to
25_C
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
100
75
20
17
125
90
25
21
150
120
30
26
ns
tPLH,
tPHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
105
80
21
18
130
95
26
22
160
130
32
27
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Cin
Parameter
Typical @ 25°C, VCC = 5.0 V
CPD
32
Power Dissipation Capacitance (Per Flip−Flop)*
* Used to determine the no−load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC .
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3
pF
MC74HC74A
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
tsu
Minimum Setup Time, Data to Clock
(Figure 3)
2.0
3.0
4.5
6.0
80
35
16
14
100
45
20
17
120
55
24
20
ns
th
Minimum Hold Time, Clock to Data
(Figure 3)
2.0
3.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
ns
trec
Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
tw
Minimum Pulse Width, Set or Reset
(Figure 2)
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
(Figures 1, 2, 3)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
ORDERING INFORMATION
Package
Shipping†
MC74HC74ANG
PDIP−14
(Pb−Free)
25 Units / Rail
MC74HC74ADG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74HC74ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74HC74ADTR2G
TSSOP−14*
2500 / Tape & Reel
MC74HC74AFG
SOEIAJ−14
(Pb−Free)
50 Units / Rail
MC74HC74AFELG
SOEIAJ−14
(Pb−Free)
2000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74HC74A
SWITCHING WAVEFORMS
tf
CLOCK
tw
tr
VCC
90%
50%
10%
tw
SET OR
RESET
GND
Q or Q
GND
tPHL
50%
Q OR Q
1/fmax
tPHL
tPLH
tPLH
90%
50%
10%
50%
Q OR Q
tTLH
VCC
50%
tTHL
trec
VCC
50%
CLOCK
GND
Figure 1.
Figure 2.
TEST POINT
VALID
VCC
DATA
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tsu
th
VCC
CL*
50%
CLOCK
GND
*Includes all probe and jig capacitance
Figure 3.
SET
Figure 4.
4, 10
2, 12
5, 9
Q
DATA
3, 11
CLOCK
6, 8
Q
1, 13
RESET
Figure 5. EXPANDED LOGIC DIAGRAM
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5
MC74HC74A
PACKAGE DIMENSIONS
PDIP−14
N SUFFIX
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
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6
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
MC74HC74A
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
B
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
M
S
SOLDERING FOOTPRINT
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
http://onsemi.com
7
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC74HC74A
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
http://onsemi.com
8
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HC74A
PACKAGE DIMENSIONS
SOEIAJ−14
F SUFFIX
CASE 965−01
ISSUE B
14
LE
8
Q1
E HE
M_
L
7
1
DETAIL P
Z
D
VIEW P
A
e
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--1.42
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.056
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MC74HC74A/D