AD ADSP-21061LKS-160 Dsp microcomputer family Datasheet

a
ADSP-2106x SHARC®
DSP Microcomputer Family
ADSP-21061/ADSP-21061L
Pin-Compatible with ADSP-21060 (4 Mbit) and
ADSP-21062 (2 Mbit)
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with 80-Bit Accumulators
SUMMARY
High Performance Signal Computer for Speech, Sound,
Graphics and Imaging Applications
Super Harvard Architecture Computer (SHARC)—
Four Independent Buses for Dual Data, Instructions,
and I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU and Shifter
1 Megabit On-Chip SRAM Memory and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)
KEY FEATURES
50 MIPS, 20 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and BitReverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead MQFP Package
225-Ball Plastic Ball Grid Array (PBGA)
1 Megabit Configurable On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Configurable as 32K Words Data Memory (32-Bit), 16K
Words Program Memory (48-Bit) or Combinations of
Both Up to 1 Mbit
Off-Chip Memory Interfacing
4-Gigawords Addressable (32-Bit Address)
Programmable Wait State Generation, Page-Mode DRAM
Support
INSTRUCTION
CACHE
TWO INDEPENDENT
DUAL-PORTED BLOCKS
32 x 48-BIT
PROCESSOR PORT
ADDR
DATA
ADDR
DAG1
DAG2
8 x 4 x 32
8 x 4 x 24
I/O PORT
DATA
DATA
BLOCK 1
TIMER
BLOCK 0
DUAL-PORTED SRAM
CORE PROCESSOR
ADDR
DATA
DM ADDRESS BUS
IOD
48
24
7
ADDR
PROGRAM
SEQUENCER
PM ADDRESS BUS
JTAG
TEST &
EMULATION
IOA
17
EXTERNAL
PORT
ADDR BUS
MUX
32
32
MULTIPROCESSOR
INTERFACE
BUS
CONNECT
(PX)
PM DATA BUS
48
DM DATA BUS
40/32
DATA BUS
MUX
48
HOST PORT
DATA
REGISTER
FILE
MULTIPLIER
16 x 40-BIT
IOP
REGISTERS
BARREL
SHIFTER
ALU
(MEMORY MAPPED)
CONTROL,
STATUS &
DATA BUFFERS
DMA
CONTROLLER
4
6
SERIAL PORTS
(2)
6
I/O PROCESSOR
Figure 1. ADSP-21061/ADSP-21061L Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
ADSP-21061/ADSP-21061L
DMA Controller
6 DMA Channels
Background DMA Transfers at 50 MHz, in Parallel with
Full-Speed Processor Execution
Performs Transfers Between ADSP-21061 Internal Memory
and External Memory, External Peripherals, Host
Processor, or Serial Ports
Multiprocessing
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up To Six ADSP-21061s Plus Host
300 Mbytes/s Transfer Rate Over Parallel Bus
Serial Ports
Two 40 Mbit/s Synchronous Serial Ports
Independent Transmit and Receive Functions
3- to 32-Bit Data Word Width
␮-Law/A-Law Hardware Companding
TDM Multichannel Mode
Multichannel Signaling Protocol
Host Processor Interface
Efficient Interface to 16- and 32-Bit Microprocessors
Host can Directly Read/Write ADSP-21061 Internal Memory
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3
ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4
ADSP-21061 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ADDITIONAL INFORMATION . . . . . . . . . . . . . . . . . . . . . 8
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TARGET BOARD CONNECTOR FOR EZ-ICE®
PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RECOMMENDED OPERATING CONDITIONS (5 V) . 14
ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 14
POWER DISSIPATION ADSP-21061 (5 V) . . . . . . . . . . . . 15
RECOMMENDED OPERATING CONDITIONS (3.3 V) 16
ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 16
POWER DISSIPATION ADSP-21061L (3.3 V) . . . . . . . . . 17
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 18
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 21
Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 22
Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 23
Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 25
Multiprocessor Bus Request and Host Bus Request . . . . . 26
Asynchronous Read/Write—Host to ADSP-21061 . . . . . . 28
Three-State Timing—Bus Master, Bus Slave,
HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 37
OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 38
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 41
240-LEAD METRIC MQFP PIN CONFIGURATIONS . . 42
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . 43, 44
ADSP-21061L 225-Ball Plastic Ball Grid Array (PBGA)
Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
225-Ball Plastic Ball Grid Array (PBGA) Package Pinout . . . . . 46
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 47
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ADSP-21061L EZ-ICE Emulator (Jumpers in Place) . . . 12
Figure 6. JTAG Scan Path Connections for Multiple
ADSP-21061/ADSP-21061L Systems . . . . . . . . . . . . . . . 12
Figure 7. JTAG Clocktree for Multiple ADSP-21061/
ADSP-21061L Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Memory Read—Bus Master . . . . . . . . . . . . . . . . 21
Figure 14. Memory Write—Bus Master . . . . . . . . . . . . . . . 22
Figure 15. Synchronous Read/Write—Bus Master . . . . . . . 24
Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 25
Figure 17. Multiprocessor Bus Request and Host Bus
Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 28
Figure 18b. Asynchronous Read/Write—Host to
ADSP-21061/ADSP-21061L . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19a. Three-State Timing (Bus Transition Cycle,
SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19b. Three-State Timing (Host Transition Cycle) . . 31
Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 33
Figure 21. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. External Late Frame Sync . . . . . . . . . . . . . . . . . 36
Figure 23. JTAG Test Access Port and Emulation . . . . . . . 37
Figure 24. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 39
Figure 25. Equivalent Device Loading for AC Measurements
(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 26. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . . 39
Figure 27. ADSP-2106x Typical Drive Currents
(VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 28. Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . . 40
Figure 29. Typical Output Rise Time (0.8 V–2.0 V) vs. Load
Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 30. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (VDD = 5 V) . . . . . . . . 40
Figure 31. ADSP-2106x Typical Drive Currents
(VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 32. Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . 40
Figure 33. Typical Output Rise Time (0.8 V–2.0 V) vs. Load
Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 34. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (VDD = 3.3 V) . . . . . . . 41
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
ADSP-21061/ADSP-21061L Block Diagram . . . .
ADSP-21061/ADSP-21061L System . . . . . . . . . . .
Multiprocessing System . . . . . . . . . . . . . . . . . . . . .
ADSP-21061/ADSP-21061L Memory Map . . . . .
Target Board Connector For ADSP-21061/
1
4
6
7
EZ-ICE is a registered trademark of Analog Devices, Inc.
–2–
REV. B
ADSP-21061/ADSP-21061L
S
®
GENERAL NOTE
This data sheet represents production released specifications
for the ADSP-21061 5 V and ADSP-21061L 3.3 V processors. ADSP-21061 is used throughout this data sheet to refer to
both devices unless expressly noted.
Figure 1 shows a block diagram of the ADSP-21061/ADSP21061L, illustrating the following architectural features:
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
1 Mbit On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port & Multiprocessor Interface
DMA Controller
Serial Ports
JTAG Test Access Port
GENERAL DESCRIPTION
The ADSP-21061 is a member of the powerful SHARC family
of floating point processors. The SHARC—Super Harvard
Architecture Computer—are signal processing microcomputers
that offer new capabilities and levels of integration and performance. The ADSP-21061 is a 32-bit processor optimized for
high performance DSP applications. The ADSP-21061 combines the ADSP-21000 DSP core with a dual-ported on-chip
SRAM and an I/O processor with a dedicated I/O bus to form a
complete system-in-a-chip.
Fabricated in a high-speed, low-power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time operating at up
to 50 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table I shows performance benchmarks for the ADSP-21061/ADSP-21061L.
The ADSP-21061 SHARC combines a high-performance floating-point DSP core with integrated, on-chip system features,
including a 1 Mbit SRAM memory, host processor interface,
DMA controller, serial ports and parallel bus connectivity for
glueless DSP multiprocessing.
REV. B
Figure 2 shows a typical single-processor system. A multiprocessing system is shown in Figure 3.
Table I. ADSP-21061/ADSP-21061L Benchmarks (@ 50 MHz)
1024-Pt. Complex FFT
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide (y/x)
Inverse Square Root (1/√x)
DMA Transfer Rate
–3–
0.37 ms
18,221 Cycles
20 ns
80 ns
120 ns
180 ns
300 Mbytes/s
1 Cycle
4 Cycles
6 Cycles
9 Cycles
ADSP-21061/ADSP-21061L
ADSP-21000 FAMILY CORE ARCHITECTURE
Instruction Cache
The ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 is code and
function compatible with the ADSP-21060/ADSP-21062 and
the ADSP-21020.
The ADSP-21061 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all perform single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. These computation units support IEEE 32-bit singleprecision floating-point, extended precision 40-bit floatingpoint and 32-bit fixed-point data formats.
Data Address Generators with Hardware Circular Buffers
The ADSP-21061’s two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The ADSP-21061 two
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers (16 primary register sets, 16 secondary). The
DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance and simplifying implementation. Circular buffers can start and end at any memory
location.
ADSP-21061/
ADSP-21061L
4
IRQ2-0
FLAG3-0
TIMEXP
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
RPBA
ID2-0
RESET
CS
ADDR
DATA
3
BMS
ADDRESS
TO GND
CLKIN
EBOOT
LBOOT
CONTROL
1x CLOCK
DATA
Flexible Instruction Set
ADDR31-0
ADDR
DATA47-0
DATA
RD
WR
ACK
MS3-0
PAGE
SBTS
SW
ADRCLK
BOOT
EPROM
(OPTIONAL)
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP21061 can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
MEMORY
AND
OE PERIPHERALS
WE
(OPTIONAL)
ACK
CS
ADSP-21061 FEATURES
Augmenting the ADSP-21000 family core, the ADSP-21061
adds the following architectural features:
DMA DEVICE
(OPTIONAL)
DATA
DMAR1-2
Dual-Ported On-Chip Memory
DMAG1-2
The ADSP-21061 contains 1 megabit of on-chip SRAM, organized as two banks of 0.5 Mbits each. Each bank has eight 16bit columns with 4K 16-bit words per column. Each memory
block is dual-ported for single-cycle, independent accesses by
the core processor and I/O processor or DMA controller. The
dual-ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle
(see Figure 4 for the ADSP-21061 Memory Map).
CS
HBR
HBG
REDY
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
BR1-6
ADDR
CPA
DATA
JTAG
7
On the ADSP-21061, the memory can be configured as a maximum of 32K words of 32-bit data, 64K words for 16-bit data,
16K words of 48-bit instructions (and 40-bit data) or combinations of different word sizes up to 1 megabit. All the memory
can be accessed as 16-bit, 32-bit or 48-bit.
Figure 2. ADSP-21061/ADSP-21061L System
Data Register File
A general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the ADSP21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on chip.
Conversion between the 32-bit floating-point and 16-bit floatingpoint formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores instructions and data, using the PM bus for transfers. Using the
DM and PM buses in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP21061’s external port.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21061 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from the cache),
all in a single cycle.
–4–
REV. B
ADSP-21061/ADSP-21061L
Off-Chip Memory and Peripherals Interface
The ADSP-21061’s external port provides the processor’s interface to off-chip memory and peripherals. The 4-gigaword offchip address space is included in the ADSP-21061’s unified
address space. The separate on-chip buses—for program
memory, data memory and I/O—are multiplexed at the external
port to create an external system bus with a single 32-bit address
bus and a single 48-bit (or 32-bit) data bus. The on-chip
Super Harvard Architecture provides three-bus performance,
while the off-chip unified address space gives flexibility to the
designer.
Addressing of external memory devices is facilitated by on-chip
decoding of high order address lines to generate memory bank
select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The ADSP-21061
provides programmable memory wait states and external memory
acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold and disable time requirements.
Host Processor Interface
Six channels of DMA are available on the ADSP-21061—four
via the serial ports, and two via the processor’s external port (for
either host processor, other ADSP-21061s, memory or I/O
transfers). Programs can be downloaded to the ADSP-21061
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(DMAR1-2, DMAG1-2). Other DMA features include interrupt
generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers.
Serial Ports
The ADSP-21061 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maximum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
The ADSP-21061’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21061’s external port and is memory-mapped into the unified address space.
Two channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from three
bits to 32 bits. They offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding.
Serial port clocks and frame syncs can be internally or externally
generated. The serial ports also include keyword and keymask
features to enhance interprocessor communication.
The host processor requests the ADSP-21061’s external bus
with the host bus request (HBR), host bus grant (HBG) and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21061, and can access the
DMA channel setup and mailbox registers. Vector interrupt
support is provided for efficient execution of host commands.
The ADSP-21061 offers powerful features tailored to multiprocessing DSP systems. The unified address space allows direct
interprocessor accesses of each ADSP-21061’s internal memory.
Distributed bus arbitration logic is included on-chip for simple,
glueless connection of systems containing up to six ADSP-21061s
and a host processor. Master processor changeover incurs only
one cycle of overhead. Bus arbitration is selectable as either
fixed or rotating priority. Bus lock allows indivisible read-modifywrite sequences for semaphores. A vector interrupt is provided
for interprocessor commands. Maximum throughput for interprocessor data transfer is 500 Mbytes/sec over the external port.
Broadcast writes allow simultaneous transmission of data to
all ADSP-21061s and can be used to implement reflective
semaphores.
DMA Controller
The ADSP-21061’s on-chip DMA controller allows zerooverhead, nonintrusive data transfers without processor intervention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions.
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32or 48-bit words is performed during DMA transfers.
REV. B
Multiprocessing
Program Booting
The internal memory of the ADSP-21061 can be booted at
system power-up from either an 8-bit EPROM or a host processor. Selection of the boot source is controlled by the BMS (Boot
Memory Select), EBOOT (EPROM Boot), and LBOOT (Host
Boot) pins. 32-bit and 16-bit host processors can be used for
booting. See the BMS pin in the Pin Function Descriptions
section of this data sheet.
–5–
ADDRESS
DATA
ADDRESS
DATA
ADSP-2106x #3
CONTROL
ADSP-2106x #6
ADSP-2106x #5
ADSP-2106x #4
CONTROL
ADSP-21061/ADSP-21061L
ADDR31-0
CLKIN
DATA47-0
RESET
RPBA
011
3
ID 2-0
CONTROL
CPA
BR1-2, BR4-6
BR3
5
ADSP-2106x #2
CLKIN
RESET
ADDR31-0
DATA47-0
RPBA
3
010
ID 2-0
CONTROL
CPA
BR1, BR3-6
5
BR2
ADSP-2106x #1
1x
CLOCK
CLKIN
RESET
RESET
RPBA
3
001
ID 2-0
CONTROL
ADDR31-0
ADDR
DATA47-0
DATA
OE
WE
ACK
CS
RD
WR
ACK
MS3-0
CS
BMS
PAGE
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
CPA
BR2-6
ADDR
DATA
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
5
DATA
BR1
Figure 3. Multiprocessing System
–6–
REV. B
ADSP-21061/ADSP-21061L
0x0000 0000
0x0040 0000
IOP REGISTERS
INTERNAL
MEMORY
SPACE
0x0002 0000
BANK 0
0x0004 0000
DRAM
(OPTIONAL)
NORMAL WORD ADDRESSING
MS0
SHORT WORD ADDRESSING
0x0008 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=001
BANK 1
MS1
0x0010 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=010
0x0018 0000
BANK 2
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=011
EXTERNAL
MEMORY
SPACE
0x0020 0000
MULTIPROCESSOR
MEMORY SPACE
MS2
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=100
BANK 3
0x0028 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=101
MS3
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.
0x0030 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=110
0x0038 0000
BROADCAST WRITE
TO ALL
ADSP-2106xs
NONBANKED
0x003F FFFF
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
0xFFFF FFFF
Figure 4. ADSP-21061/ADSP-21061L Memory Map
REV. B
–7–
ADSP-21061/ADSP-21061L
Porting Code from ADSP-21060 or ADSP-21062 to the
ADSP-21061
The same EZ-ICE hardware can be used for the ADSP-21060/
ADSP-21062, to fully emulate the ADSP-21061, with the exception of displaying and modifying the two new SPORTS
registers. The emulator will not display these two registers,
but your code can use them.
The ADSP-21061 is pin compatible with the ADSP-21060/
ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins
that correspond to the Link Port pins of the ADSP-21060/
ADSP-21062 are no-connects.
Analog Devices ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
Assembly Library/Librarian, Linker, instruction-level Simulator,
an ANSI C optimizing Compiler, the CBUG™ C Source—
Level Debugger and a C Runtime Library including DSP and
mathematical functions. The Optimizing Compiler includes
Numerical C extensions based on the work of the ANSI Numerical C Extensions Group. Numerical C provides extensions
to the C language for array selections, vector math operations,
complex data types, circular pointers and variably dimensioned
arrays. The ADSP-21000 Family Development Software is
available for both the PC and Sun platforms.
The ADSP-21061 is object code compatible with the ADSP21060/ADSP-21062 except for the following functional
changes:
The ADSP-21061 memory is organized into two blocks
with eight columns that are 4K deep per block. The
ADSP-21060/ADSP-21062 memory has 16 columns per block.
Link port functions are not available.
Handshake external port DMA pins DMAR2 and DMAG2
are assigned to external port DMA Channel 6 instead of
Channel 8.
2-D DMA capability of the SPORT is not available.
The modify registers in SPORT DMA are not programmable.
The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access
port of the ADSP-21061 processor to monitor and control the
target board processor during emulation. The EZ-ICE provides
full-speed emulation, allowing inspection and modification of
memory, registers, and processor stacks. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or
timing.
On the ADSP-21061, Block 0 starts at the beginning of internal
memory, normal word address 0x0002 0000. Block 1 starts at
the end of Block 0, with contiguous addresses. The remaining
addresses in internal memory are divided into blocks that alias
into Block 1. This allows any code or data stored in Block 1 on
the ADSP-21062 to retain the same addresses on the ADSP21061—these addresses will alias into the actual Block 1 of each
processor.
Further details and ordering information are available in the
ADSP-21000 Family Hardware and Software Development Tools
data sheet (ADDS-210xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office or distributor.
If you develop your application using the ADSP-21062, but will
migrate to the ADSP-21061, use only the first eight columns of
each memory bank. Limit your application to 8K of instructions
or up to 16K of data in each bank of the ADSP-21062, or any
combinations of instructions or data that does not exceed the
memory bank.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hardware tools include SHARC PC plug-in cards multiprocessor
SHARC VME boards, and daughter and modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third Party software
tools include an Ada compiler, DSP libraries, operating systems
and block diagram design tools.
DEVELOPMENT TOOLS
The ADSP-21061 is supported with a complete set of software
and hardware development tools, including an EZ-ICE InCircuit Emulator, EZ-Kit Lite, and development software. The
SHARC EZ-Kit Lite (ADDS-2106x-EZ-Lite) is a complete low
cost package for DSP evaluation and prototyping. The EZ-Kit
Lite contains an evaluation board with an ADSP-21061 (5 V)
processor and provides a serial connection to your PC. The EZKit Lite also includes an optimizing compiler, assembler, instruction level simulator, run-time libraries, diagnostic utilities
and a complete set of example programs.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21061
architecture and functionality. For detailed information on the
ADSP-21000 Family core architecture and instruction set, refer to
the ADSP-2106x SHARC User’s Manual, Second Edition.
CBUG and SHARCPAC are trademarks of Analog Devices, Inc.
–8–
REV. B
ADSP-21061/ADSP-21061L
PIN DESCRIPTIONS
ADSP-21061 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to IVDD or IGND,
except for ADDR31-0, DATA47-0, FLAG3-0, SW and inputs that
have internal pull-up or pull-down resistors (CPA, ACK, DTx,
DRx, TCLKx, RCLKx, TMS and TDI)—these pins can be left
floating. These pins have a logic-level hold circuit that prevents
the input from floating internally.
I = Input
S = Synchronous
P = Power Supply
(O/D) = Open Drain O = Output
A = Asynchronous
G = Ground
(A/D) = Active Drive
T = Three-State (when SBTS is asserted, or when the
ADSP-2106x is a bus slave)
PIN FUNCTION DESCRIPTIONS
Pin
Type
Function
ADDR31-0
I/O/T
DATA47-0
I/O/T
MS3-0
O/T
RD
I/O/T
WR
I/O/T
PAGE
O/T
ADRCLK
O/T
SW
I/O/T
ACK
I/O/S
External Bus Address. The ADSP-21061 outputs addresses for external memory and peripherals
on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the
internal memory or IOP registers of other ADSP-2106xs. The ADSP-21061 inputs addresses when a
host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
External Bus Data. The ADSP-21061 inputs and outputs data and instructions on these pins.
The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-point
data over Bits 47-16. 40-bit extended-precision floating-point data is transferred over Bits 47-8 of
the bus. 16-bit short word data is transferred over Bits 31-16 of the bus. Pull-up resistors on unused DATA pins are not necessary.
Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks
of external memory. Memory bank size must be defined in the ADSP-21061’s system control register (SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as
the other address lines. When no external memory access is occurring the MS3-0 lines are inactive;
they are active, however, when a conditional memory access instruction is executed, whether or not the
condition is true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory
(Bank 0). In a multiprocessor system the MS3-0 lines are output by the bus master.
Memory Read Strobe. This pin is asserted (low) when the ADSP-21061 reads from external
memory devices or from the internal memory of other ADSP-21061s. External devices (including
other ADSP-21061s) must assert RD to read from the ADSP-21061’s internal memory. In a multiprocessor system RD is output by the bus master and is input by all other ADSP-21061s.
Memory Write Strobe. This pin is asserted (low) when the ADSP-21061 writes to external memory
devices or to the internal memory of other ADSP-21061s. External devices must assert WR to write to
the ADSP-21061’s internal memory. In a multiprocessor system WR is output by the bus master and is
input by all other ADSP-21061s.
DRAM Page Boundary. The ADSP-21061 asserts this pin to signal that an external DRAM page
boundary has been crossed. DRAM page size must be defined in the ADSP-21061’s memory control register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE
signal can only be activated for Bank 0 accesses. In a multiprocessor system PAGE is output by the
bus master.
Address Clock for synchronous external memories. Addresses on ADDR31-0 are valid before the
rising edge of ADRCLK. In a multiprocessing system ADRCLK is output by the bus master.
Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous memory
devices (including other ADSP-21061s). The ADSP-21061 asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g. in a conditional
write instruction). In a multiprocessor system, SW is output by the bus master and is input by all other
ADSP-21061s to determine if the multiprocessor memory access is a read or write. SW is asserted at the
same time as the address output. A host processor using synchronous writes must assert this pin when
writing to the ADSP-21061(s).
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers or other peripherals to hold off
completion of an external memory access. The ADSP-21061 deasserts ACK as an output to add
wait states to a synchronous access of its internal memory. In a multiprocessor system, a slave
ADSP-21061 deasserts the bus master’s ACK input to add wait state(s) to an access of its internal
memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level it
was last driven to.
REV. B
–9–
ADSP-21061/ADSP-21061L
Pin
Type
Function
SBTS
I/S
IRQ2-0
FLAG3-0
I/A
I/O/A
TIMEXP
O
HBR
I/A
HBG
I/O
CS
REDY (O/D)
I/A
O
DMAR1
DMAR2
DMAG1
DMAG2
BR6-1
I/A
I/A
O/T
O/T
I/O/S
ID2-0
I
RPBA
I/S
CPA (O/D)
I/O
DTx
DRx
TCLKx
O
I
I/O
Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address,
data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061
attempts to access external memory while SBTS is asserted, the processor will halt and the memory
access will not be completed until SBTS is deasserted. SBTS should only be used to recover from
PAGE faults or host processor/ADSP-21061 deadlock.
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or an output. As an input, it can be
tested as a condition. As an output, it can be used to signal external peripherals.
Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to
zero.
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21061’s
external bus. When HBR is asserted in a multiprocessing system, the ADSP-21061 that is bus master
will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address,
data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-21061 bus
requests (BR6-1) in a multiprocessing system.
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take
control of the external bus. HBG is asserted (held low) by the ADSP-21061 until HBR is released. In a
multiprocessing system, HBG is output by the ADSP-21061 bus master and is monitored by all others.
Chip Select. Asserted by host processor to select the ADSP-21061.
Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can
be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be
output if the CS and HBR inputs are asserted.
DMA Request 1 (DMA Channel 7).
DMA Request 2 (DMA Channel 6).
DMA Grant 1 (DMA Channel 7).
DMA Grant 2 (DMA Channel 6).
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21061s to arbitrate for bus mastership. An ADSP-21061 only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BRx pins
should be tied high; the processor’s own BRx line must not be tied high or low because it is an output.
Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used by ADSP21061. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor
systems. These lines are a system configuration selection which should be hardwired or only changed at
reset.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor
bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every ADSP-21061. If the value of RPBA is
changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.
Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21061 bus slave
to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain
output that is connected to all ADSP-2106Ls in the system. The CPA pin has an internal 5 kΩ pull-up
resistor. If core access priority is not required in a system, the CPA pin should be left unconnected.
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
RCLKx
I/O
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
–10–
REV. B
ADSP-21061/ADSP-21061L
Pin
Type
Function
TFSx
RFSx
EBOOT
I/O
I/O
I
LBOOT
I
Transmit Frame Sync (Serial Ports 0, 1).
Receive Frame Sync (Serial Ports 0, 1).
EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table
below. This signal is a system configuration selection which should be hardwired.
Link Boot—Must be tied to GND.
BMS
I/O/T*
CLKIN
I
RESET
I/A
TCK
TMS
I
I/S
TDI
I/S
TDO
TRST
O
I/A
EMU
ICSA
VDD
GND
NC
O
O
P
G
REV. B
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will occur and that ADSP-21061 will begin executing instructions from external
memory. See table below. This input is a system configuration selection which should be hardwired.
*Three-statable only in EPROM boot mode (when BMS is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
0
Output
1 (Input)
0 (Input)
EPROM (Connect BMS to EPROM chip select.)
Host Processor
No Booting. Processor executes from external memory.
Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN.
CLKIN may not be halted, changed, or operated below the specified frequency.
Processor Reset. Resets the ADSP-21061 to a known state and begins execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up
resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal
pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after powerup or held low for proper operation of the ADSP-21061. TRST has a 20 kΩ internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21061 EZ-ICE target board connector only.
Reserved, leave unconnected.
Power Supply; nominally +3.3 V dc for ADSP-21061L, +5.0 V dc for ADSP-21061.
Power Supply Return.
Do Not Connect. Reserved pins which must be left open and unconnected.
–11–
ADSP-21061/ADSP-21061L
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and control
the target board processor during emulation. The EZ-ICE
probe requires the ADSP-2106x’s CLKIN, TMS, TCK,
TRST, TDI, TDO, EMU, and GND signals be made accessible on the target system via a 14-pin connector (a 2 row × 7
pin strip header) such as that shown in Figure 5. The EZ-ICE
probe plugs directly onto this connector for chip-on-board
emulation. You must add this connector to your target board
design if you intend to use the ADSP-2106x EZ-ICE. The total
trace length between the EZ-ICE connector and the furthest
device sharing the EZ-ICE JTAG pins should be limited to 15
inches maximum for guaranteed operation. This length restriction must include EZ-ICE JTAG signals that are routed to one
or more ADSP-2106x devices, or a combination of ADSP2106x devices and other JTAG devices on the chain.
1
2
3
4
5
6
7
8
9
10
GND
The BTMS, BTCK, BTRST and BTDI signals are provided so
the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If the test
access port will not be used for board testing, tie BTRST to GND
and tie or pull BTCK up to VDD. The TRST pin must be
asserted after power-up (through BTRST on the connector) or
held low for proper operation of the ADSP-2106x. None of the
Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as
follows:
Signal
Driven through 22 Ω Resistor (16 mA Driver)
Driven at 10 MHz through 22 Ω Resistor (16 mA
Driver)
TRST* Active Low Driven through 22 Ω Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 kΩ Resistor)
TDI
Driven by 22 Ω Resistor (16 mA Driver)
TDO
One TTL Load, Split Termination (160/220)
CLKIN One TTL Load, Split Termination (160/220)
EMU
Active Low 4.7 kΩ Pull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
EMU
KEY (NO PIN)
TMS
TCK
CLKIN (OPTIONAL)
BTMS
TMS
BTCK
TCK
BTRST
9
11
TRST
12
BTDI
13
TDI
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
TDO
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
14
GND
Termination
TOP VIEW
Figure 5. Target Board Connector For ADSP-21061/ADSP21061L EZ-ICE Emulator (Jumpers in Place)
OTHER
JTAG
CONTROLLER
TRST
TDO
EMU
TDI
TMS
TDO
TCK
ADSP-2106x
#n
TRST
TDI
TMS
TDO
TCK
TMS
EMU
EZ-ICE
JTAG
CONNECTOR
TDI
TCK
TDI
JTAG
DEVICE
(OPTIONAL)
TRST
ADSP-2106x
#1
TCK
TMS
EMU
TRST
TDO
CLKIN
OPTIONAL
Figure 6. JTAG Scan Path Connections for Multiple ADSP-21061/ADSP-21061L Systems
–12–
REV. B
ADSP-21061/ADSP-21061L
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform operations such as starting, stopping and single-stepping multiple
ADSP-2106x in a synchronous manner. If you do not need these
operations to occur synchronously on the multiple processors,
simply tie Pin 4 of the EZ-ICE header to ground.
should be laid out as short as possible on your board. If TCK,
TMS and CLKIN are driving a large number of ADSP-2106x
(more than eight) in your system, then treat them as a clock tree
using multiple drivers to minimize skew. (See Figure 7, JTAG
Clock Tree, and Clock Distribution in the High Frequency
Design Considerations section of the ADSP-2106x User’s
Manual, Second Edition.)
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple ADSP21061x processors and the CLKIN pin on the EZ-ICE header
must be minimal. If the skew is too large, synchronous operations
may be off by one or more cycles between processors. For synchronous multiprocessor operation TCK, TMS, CLKIN and
EMU should be treated as critical signals in terms of skew, and
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the ADSP21000 Family JTAG EZ-ICE User’s Guide and Reference.
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
5k⍀
*
TDI
EMU
5k⍀
*
TCK
TMS
TRST
TDO
SYSTEM
CLKIN
CLKIN
*OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
EMU
Figure 7. JTAG Clocktree for Multiple ADSP-21061/ADSP-21061L Systems
REV. B
–13–
ADSP-21061/ADSP-21061L
ADSP-21061–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (5 V)
Parameter
VDD
TCASE
VIH1
VIH2
VIL
Supply Voltage
Case Operating Temperature
High Level Input Voltage1
High Level Input Voltage2
Low Level Input Voltage1, 2
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
4.75
0
2.0
2.2
–0.5
K Grade
Max
5.25
+85
VDD + 0.5
VDD + 0.5
0.8
Unit
V
°C
V
V
V
NOTES
1
Applies to input and bidirectional pins: DATA 47-0, ADDR 31-0, RD, WR, SW, ACK, SBTS, IRQ 2-0, FLAG 3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
2
Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (5 V)
Parameter
V OH
VOL
IIH
IIL
IILP
IOZH
IOZL
IOZHP
IOZLC
IOZLA
IOZLAR
IOZLS
CIN
Test Conditions
1
High Level Output Voltage
Low Level Output Voltage1
High Level Input Current3, 4
Low Level Input Current3
Low Level Input Current4
Three-State Leakage Current5, 6, 7, 8
Three-State Leakage Current5, 9
Three-State Leakage Current9
Three-State Leakage Current7
Three-State Leakage Current10
Three-State Leakage Current8
Three-State Leakage Current6
Input Capacitance11, 12
Min
2
@ VDD = min, IOH = –2.0 mA
@ VDD = min, IOL = 4.0 mA2
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
Max
Unit
0.4
10
10
150
10
10
350
1.5
350
4.2
150
4.7
V
V
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
pF
4.1
NOTES
Applies to output and bidirectional pins: DATA 47-0, ADDR 31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR 6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
12
See Output Drive Currents section for typical drive current capabilities.
13
Applies to input pins: ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK. Note that ACK is pulled up
internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.)
14
Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
15
Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG 3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,
TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another ADSP-2106x is
not requesting bus mastership.)
16
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
17
Applies to CPA pin.
18
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another
ADSP-21061x is not requesting bus mastership).
19
Applies to three-statable pins with internal pull-downs: LxDAT3-0, LxCLK, LxACK.
10
Applies to ACK pin when keeper latch enabled.
11
Applies to all signal pins.
12
Guaranteed but not tested.
Specifications subject to change without notice.
11
–14–
REV. B
ADSP-21061/ADSP-21061L
POWER DISSIPATION ADSP-21061 (5 V)
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calculation of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
Operation
Peak Activity (IDDINPEAK)
High Activity (IDDINHIGH)
Low Activity (IDDINLOW)
Instruction Type
Multifunction
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
Internal Memory
Core Memory Access
2 per Cycle (DM and PM)
1 per Cycle (DM)
None
Internal Memory DMA
1 per Cycle
1 per 2 Cycles
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE + %IDLE16 × IDDIDLE16 = power consumption
Parameter
I DDINPEAK
Supply Current (Internal)1
IDDINHIGH
Supply Current (Internal)2
IDDINLOW
Supply Current (Internal)3
IDDIDLE
IDDIDLE16
Supply Current (Idle)4
Supply Current (Idle16)5
Test Conditions
Max
Unit
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
tCK = 20 ns, VDD = max
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
tCK = 20 ns, VDD = max
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
tCK = 20 ns, VDD = max
VDD = max
VDD = max
595
680
850
460
540
670
270
320
390
200
55
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
1
The test program used to measure I DDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2
IDDINHIGH is a composite average based on a range of high activity code.
3
IDDINLOW is a composite average based on a range of low activity code.
4
Idle denotes ADSP-21061 state during execution of IDLE instruction.
5
Idle16 denotes ADSP-21061 state during execution of IDLE16 instruction.
REV. B
–15–
ADSP-21061/ADSP-21061L
ADSP-21061L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (3.3 V)
Parameter
V DD
TCASE
VIH1
VIH2
VIL
Supply Voltage
Case Operating Temperature
High Level Input Voltage1
High Level Input Voltage2
Low Level Input Voltage1, 2
Test Conditions
A Grade
Min
Max
K Grade
Min
Max
Unit
@ VDD = max
@ VDD = max
@ VDD = min
3.15
–40
2.0
2.2
–0.5
3.15
0
2.0
2.2
–0.5
V
°C
V
V
V
3.45
+85
VDD + 0.5
VDD + 0.5
0.8
3.45
+85
VDD + 0.5
VDD + 0.5
0.8
NOTES
1
Applies to input and bidirectional pins: DATA 47-0, ADDR 31-0, RD, WR, SW, ACK, SBTS, IRQ 2-0, FLAG 3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
2
Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (3.3 V)
Parameter
V OH
VOL
IIH
IIL
IILP
IOZH
IOZL
IOZHP
IOZLC
IOZLA
IOZLAR
IOZLS
CIN
High Level Output Voltage1
Low Level Output Voltage1
High Level Input Current3, 4
Low Level Input Current3
Low Level Input Current4
Three-State Leakage Current5, 6, 7, 8
Three-State Leakage Current5, 9
Three-State Leakage Current9
Three-State Leakage Current7
Three-State Leakage Current10
Three-State Leakage Current8
Three-State Leakage Current6
Input Capacitance11, 12
Test Conditions
Min
@ VDD = min, IOH = –2.0 mA2
@ VDD = min, IOL = 4.0 mA2
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
2.4
Max
Unit
0.4
10
10
150
10
10
350
1.5
350
4.2
150
4.7
V
V
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
pF
NOTES
Applies to output and bidirectional pins: DATA 47-0, ADDR 31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR 6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
12
See “Output Drive Currents” for typical drive current capabilities.
13
Applies to input pins: ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK. Note that ACK is pulled up
internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.)
14
Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
15
Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG 3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,
TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another ADSP-2106x is
not requesting bus mastership.)
16
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
17
Applies to CPA pin.
18
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another
ADSP-21061L is not requesting bus mastership).
19
Applies to three-statable pins with internal pull-downs: LxDAT3-0, LxCLK, LxACK.
10
Applies to ACK pin when keeper latch enabled.
11
Applies to all signal pins.
12
Guaranteed but not tested.
Specifications subject to change without notice.
11
–16–
REV. B
ADSP-21061/ADSP-21061L
POWER DISSIPATION ADSP-21061L (3.3 V)
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calculation of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,
see the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
Operation
Peak Activity (IDDINPEAK)
High Activity (IDDINHIGH)
Low Activity (IDDINLOW)
Instruction Type
Multifunction
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
Internal Memory
Core Memory Access
2 per Cycle (DM and PM)
1 per Cycle (DM)
None
Internal Memory DMA
1 per Cycle
1 per 2 Cycles
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE + %IDLE16 × IDDIDLE16 = power consumption
Parameter
IDDINPEAK
Supply Current (Internal)1
IDDINHIGH
Supply Current (Internal)2
IDDINLOW
Supply Current (Internal)3
IDDIDLE
IDDIDLE16
Supply Current (Idle)4
Supply Current (Idle16)5
Test Conditions
Max
Unit
tCK = 25 ns, VDD = max
tCK = 22.5 ns, VDD = max
tCK = 25 ns, VDD = max
tCK = 22.5 ns, VDD = max
tCK = 25 ns, VDD = max
tCK = 22.5 ns, VDD = max
VDD = max
VDD = max
480
535
380
425
220
245
180
50
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
1
The test program used to measure I DDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2
IDDINHIGH is a composite average based on a range of high activity code.
3
IDDINLOW is a composite average based on a range of low activity code.
4
Idle denotes ADSP-21061L state during execution of IDLE instruction.
5
Idle16 denotes ADSP-21061L state during execution of IDLE16 instruction.
REV. B
–17–
ADSP-21061/ADSP-21061L
ABSOLUTE MAXIMUM RATINGS (5 V DEVICE)*
ABSOLUTE MAXIMUM RATINGS (3.3 V DEVICE)*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2106x features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
GENERAL NOTES
The following timing specifications are target specifications and
are based on device simulation only.
The timing specifications shown are based on a CLKIN frequency
of 40 MHz (tCK = 25 ns). The DT derating allows specifications
at other CLKIN frequencies (within the min–max range of the
tCK specification; see Clock Input below). DT is the difference between the actual CLKIN period and a CLKIN period
of 25 ns:
DT = tCK – 25 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
WARNING!
ESD SENSITIVE DEVICE
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
See Figure 26 under Test Conditions for voltage reference
levels.
–18–
REV. B
ADSP-21061/ADSP-21061L
33 MHz
Min
Max
Parameter
Clock Input
Timing Requirements:
tCK
CLKIN Period
tCKL
CLKIN Width Low
CLKIN Width High
tCKH
tCKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
30
7
5
ADSP-21061 (5 V)
40 MHz
Min
Max
100
25
7
5
3
50 MHz
Min
Max
100
20
7
5
100
3
3
ADSP-21061L (3.3 V)
40 MHz
44 MHz
Min
Max
Min
Max
Parameter
Clock Input
Timing Requirements:
CLKIN Period
tCK
tCKL
CLKIN Width Low
CLKIN Width High
tCKH
tCKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
25
7
5
100
22.5
7
5
100
3
3
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
t CK
CLKIN
t CKH
t CKL
Figure 8. Clock Input
Parameter
ADSP-21061 (5 V)
Min
Max
ADSP-21061L (3.3 V)
Min
Max
Unit
Reset
Timing Requirements:
RESET Pulsewidth Low1
tWRST
tSRST
RESET Setup before CLKIN High2
4tCK
14 + DT/2
4tCK
14 + DT/2
ns
ns
tCK
tCK
NOTES
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable V DD and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
t SRST
t WRST
RESET
Figure 9. Reset
Parameter
Interrupts
Timing Requirements:
IRQ2-0 Setup before CLKIN High1
tSIR
tHIR
IRQ2-0 Hold before CLKIN High1
tIPW
IRQ2-0 Pulsewidth2
ADSP-21061 (5 V)
Min
Max
ADSP-21061L (3.3 V)
Min
Max
18 + 3DT/4
18 + 3DT/4
12 + 3DT/4
2 + tCK
NOTES
1
Only required for IRQx recognition in the following cycle.
2
Applies only if tSIR and tHIR requirements are not met.
REV. B
–19–
12 + 3DT/4
2 + tCK
Unit
ns
ns
ns
ADSP-21061/ADSP-21061L
CLKIN
t SIR
t HIR
IRQ2-0
t IPW
Figure 10. Interrupts
ADSP-21061 (5 V)
Min
Max
Parameter
Timer
Switching Characteristics:
tDTEX
CLKIN High to TIMEXP
ADSP-21061L (3.3 V)
Min
Max
15
15
Unit
ns
CLKIN
t DTEX
t DTEX
TIMEXP
Figure 11. Timer
Parameter
Timing Requirements:
tSFI
FLAG3-0IN Setup before CLKIN High1
FLAG3-0IN Hold after CLKIN High1
tHFI
tDWRFI
FLAG3-0IN Delay after RD/WR Low1
FLAG3-0IN Hold after RD/WR Deasserted1
tHFIWR
ADSP-21061 (5 V)
Min
Max
ADSP-21061L (3.3 V)
Min
Max
8 + 5DT/16
0 – 5DT/16
8 + 5DT/16
0 – 5DT/16
5 + 7DT/16
0
Switching Characteristics:
tDFO
FLAG3-0OUT Delay after CLKIN High
tHFO
FLAG3-0OUT Hold after CLKIN High
CLKIN High to FLAG3-0OUT Enable
tDFOE
tDFOD
CLKIN High to FLAG3-0OUT Disable
5 + 7DT/16
0
16
16
4
3
4
3
14
14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
1
Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
CLKIN
t DFOE
t DFO
t HFO
t DFO
tDFOD
FLAG3-0OUT
FLAG OUTPUT
CLKIN
t SFI
t HFI
FLAG3-0I N
t DWRFI
t HFIWR
RD, WR
FLAG INPUT
Figure 12. Flags
–20–
REV. B
ADSP-21061/ADSP-21061L
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write—Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is
the bus master accessing external memory space. These switching
Parameter
Min
Timing Requirements:
Address, Selects Delay to Data Valid1, 2
tDAD
RD Low to Data Valid1
tDRLD
Data Hold from Address, Selects3
tHDA
Data Hold from RD High3
tHDRH
ACK Delay from Address, Selects2, 4
tDAAK
ACK Delay from RD Low4
tDSAK
Switching Characteristics:
Address, Selects Hold after RD High
tDRHA
Address, Selects to RD Low2
tDARL
RD Pulsewidth
tRW
RD High to WR, RD, DMAGx Low
tRWR
tSADADC Address, Selects Setup before
ADRCLK High2
ADSP-21061 (5 V)
Max
Min
ADSP-21061L (3.3 V)
Max
18 + DT + W
12 + 5DT/8 + W
0.5
2.0
18 + DT + W
12 + 5DT/8 + W
0.5
2.0
15 + 7DT/8 + W
8 + DT/2 + W
15 + 7DT/8 + W
8 + DT/2 + W
Unit
ns
ns
ns
ns
ns
ns
0+H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0+H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
ns
ns
ns
ns
0 + DT/4
0 + DT/4
ns
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
Data Delay/Setup: User must meet t DAD or tDRLD or synchronous specification t SSDATI.
2
The falling edge of MSx, SW, and BMS is referenced.
3
Data Hold: User must meet t HDA or tHDRH or synchronous specification t HSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold
times given capacitive and dc loads.
4
ACK Delay/Setup: User must meet t DAAK or tDSAK or synchronous specification t SACKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
1
ADDRESS
MSx, SW
BMS
t DARL
t RW
t DRHA
RD
t HDA
t DRLD
t DAD
t HDRH
DATA
t DSAK
t RWR
t DAAK
ACK
WR, DMAG
t SADADC
ADRCLK
(OUT)
Figure 13. Memory Read—Bus Master
REV. B
–21–
ADSP-21061/ADSP-21061L
Memory Write—Bus Master
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write—Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is
the bus master accessing external memory space. These switching
Parameter
ADSP-21061 (5 V)
Max
Min
Timing Requirements:
ACK Delay from Address, Selects1, 2
tDAAK
ACK Delay from WR Low1
tDSAK
Min
ADSP-21061L (3.3 V)
Max
15 + 7DT/8 + W
8 + DT/2 + W
Switching Characteristics:
Address, Selects to WR Deasserted2
tDAWH
Address, Selects to WR Low2
tDAWL
WR Pulsewidth
tWW
Data Setup before WR High
tDDWH
Address Hold after WR Deasserted
tDWHA
tDATRWH Data Disable after WR Deasserted3
WR High to WR, RD, DMAGx Low
tWWR
Data Disable before WR or RD Low
tDDWR
WR Low to Data Enabled
tWDE
tSADADC Address, Selects to ADRCLK High2
17 + 15DT/16 + W
3 + 3DT/8
13 + 9DT/16 + W
7 + DT/2 + W
1 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
15 + 7DT/8 + W
8 + DT/2 + W
17 + 15DT/16 + W
3 + 3DT/8
13 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
6 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
6 + DT/16 + H
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
ACK Delay/Setup: User must meet t DAAK or tDSAK or synchronous specification t SACKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High)
2
The falling edge of MSx, SW, and BMS is referenced.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
1
ADDRESS
MSx , SW
BMS
t DWHA
t DAWH
t WW
t DAWL
WR
t WWR
t DDWH
t WDE
t DATRWH
t DDWR
DATA
t DSAK
t DAAK
ACK
RD, DMAG
t SADADC
ADRCLK
(OUT)
Figure 14. Memory Write—Bus Master
–22–
REV. B
ADSP-21061/ADSP-21061L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-21061 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes (see Memory Read—
Bus Master and Memory Write—Bus Master).
Parameter
Timing Requirements:
Data Setup before CLKIN
tSSDATI
tSSDATI (50 MHz) Data Setup before CLKIN,
tCK = 20 ns1
Data Hold after CLKIN
tHSDATI
ACK Delay after Address, MSx,
tDAAK
SW, BMS2, 3
ACK Setup before CLKIN2
tSACKC
ACK Hold after CLKIN
tHACK
Switching Characteristics:
tDADRO
Address, MSx, BMS, SW Delay
after CLKIN2
Address, MSx, BMS, SW Hold
tHADRO
after CLKIN
PAGE Delay after CLKIN
tDPGC
RD High Delay after CLKIN
tDRDO
WR High Delay after CLKIN
tDWRO
tDWRO (50 MHz) WR High Delay after CLKIN,
tCK = 20 ns1
RD/WR Low Delay after CLKIN
tDRWL
Data Delay after CLKIN
tSDDATO
Data Disable after CLKIN4
tDATTR
ADRCLK Delay after CLKIN
tDADCCK
ADRCLK Period
tADRCK
ADRCLK Width High
tADRCKH
tADRCKL
ADRCLK Width Low
Min
When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-21061 must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
ADSP-21061 (5 V)
Max
Min
ADSP-21061L (3.3 V)
Max
Unit
2 + DT/8
2 + DT/8
ns
1.5 + DT/8
3.5 – DT/8
3.5 – DT/8
ns
ns
15 + 7 DT/8 + W
6.5 + DT/4
–1 – DT/4
6.5 – DT/8
–1 – DT/8
9 + DT/8
–1.5 – DT/8
–2.5 – 3DT/16
–1.5 – 3DT/16
8 + DT/4
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
15 + 7 DT/8 + W
ns
ns
ns
6.5 – DT/8
ns
16 + DT/8
4 – DT/8
4 – 3DT/16
ns
ns
ns
ns
6.5 + DT/4
–1 – DT/4
16 + DT/8
4 – DT/8
4 – 3DT/16
4 – 3DT/16
12 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
–1 – DT/8
9 + DT/8
–1.5 – DT/8
–2.5 – 3DT/16
8 + DT/4
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
12 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
ns
ns
ns
ns
ns
ns
ns
ns
W = (number of Wait states specified in WAIT register) × tCK.
NOTES
1
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t CK < 25 ns. For all other devices, use the preceding timing specification of the
same name.
2
ACK Delay/Setup: User must meet t DAAK or tDSAK or synchronous specification t SACKC for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).
3
Data Hold: User must meet t HDA or tHDRH or synchronous specification t HDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold
times given capacitive and dc loads.
4
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
REV. B
–23–
ADSP-21061/ADSP-21061L
CLKIN
t ADRCK
t ADRCKL
t ADRCKH
t DADCCK
ADRCLK
t HADRO
t DAAK
t DADRO
ADDRESS
SW
t DPGC
PAGE
t HACK
t SACKC
ACK
(IN)
READ CYCLE
t DRWL
t DRDO
RD
t HSDATI
t SSDATI
DATA
(IN)
WRITE CYCLE
t DWRO
t DRWL
WR
t DATTR
t SDDATO
DATA
(OUT)
Figure 15. Synchronous Read/Write—Bus Master
–24–
REV. B
ADSP-21061/ADSP-21061L
memory space). The bus master must meet these (bus slave)
timing requirements.
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21061 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
Parameter
Min
Timing Requirements:
Address, SW Setup before CLKIN
tSADRI
Address, SW Hold before CLKIN
tHADRI
RD/WR Low Setup before CLKIN1
tSRWLI
RD/WR Low Hold after CLKIN
tHRWLI
RD/WR Low Hold after CLKIN
tHRWLI
44 MHz/50 MHz2
RD/WR Pulse High
tRWHPI
Data Setup before WR High
tSDATWH
Data Hold after WR High
tHDATWH
Switching Characteristics:
tSDDATO
Data Delay after CLKIN
Data Disable after CLKIN3
tDATTR
ACK Delay after Address, SW4
tDACKAD
tACKTR
ACK Disable after CLKIN4
ADSP-21061 (5 V)
Max
ADSP-21061L (3.3 V)
Min
Max
14 + DT/2
14 + DT/2
5 + DT/2
8.5 + 5DT/16
–4 – 5DT/16
–3.5 – 5DT/16
3
3
1
8 + 7DT/16
8 + 7DT/16
19 + 5DT/16
7 – DT/8
8
6 – DT/8
0 – DT/8
–1 – DT/8
5 + DT/2
8.5 + 5DT/16
–4 – 5DT/16
–3.5 – 5DT/16
3
3
1
0 – DT/8
–1 – DT/8
8 + 7DT/16
Unit
ns
ns
ns
ns
8 + 7DT/16
ns
ns
ns
ns
19 + 5DT/16
7 – DT/8
8
6 – DT/8
ns
ns
ns
ns
NOTES
1
tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t SRWLI (min)
= 4 + DT/8.
2
This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), o perating at tCK <25 ns. For all other devices,
use the preceding timing specification of the same name.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
4
tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT/4, then ACK is valid 15.5 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t ACKTR.
CLKIN
t SADRI
t HADRI
ADDRESS
SW
t DACKAD
t ACKTR
ACK
READ ACCESS
t SRWLI
t HRWLI
t RWHPI
RD
t SDDATO
t DATTR
DATA
(OUT)
WRITE ACCESS
t SRWLI
t HRWLI
WR
t SDATWH
DATA
(IN)
REV. B
–25–
t HDATWH
t RWHPI
ADSP-21061/ADSP-21061L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-21061s (BRx) or a host processor
(HBR, HBG).
Parameter
Timing Requirements:
HBG Low to RD/WR/CS Valid1
tHBGRCSV
HBR Setup before CLKIN2
tSHBRI
HBR Hold before CLKIN2
tHHBRI
HBG Setup before CLKIN
tSHBGI
HBG Hold before CLKIN High
tHHBGI
BRx, CPA Setup before CLKIN3
tSBRI
BRx, CPA Hold before CLKIN High
tHBRI
RPBA Setup before CLKIN
tSRPBAI
RPBA Hold before CLKIN
tHRPBAI
Switching Characteristics:
tDHBGO
HBG Delay after CLKIN
HBG Hold after CLKIN
tHHBGO
BRx Delay after CLKIN
tDBRO
BRx Hold after CLKIN
tHBRO
CPA Low Delay after CLKIN
tDCPAO
CPA Disable after CLKIN
tTRCPA
REDY (O/D) or (A/D) Low from
tDRDYCS
CS and HBR Low4
REDY (O/D) Disable or REDY (A/D)
tTRDYHG
High from HBG4
REDY (A/D) Disable from CS or
tARDYTR
HBR High4
ADSP-21061 (5 V)
Min
Max
ADSP-21061L (3.3 V)
Min
Max
20+ 5DT/4
20 + 3DT/4
20 + 5DT/4
20 + 3DT/4
14 + 3DT/4
13 + DT/2
14 + 3DT/4
13 + DT/2
6 + DT/2
13 + DT/2
6 + DT/2
13 + DT/2
6 + DT/2
20 + 3DT/4
6 + DT/2
20 + 3DT/4
12 + 3DT/4
12 + 3DT/4
7 – DT/8
–2 – DT/8
7 – DT/8
5.5 – DT/8
–2 – DT/8
8.5 – DT/8
4.5 – DT/8
12
ns
5.5 – DT/8
–2 – DT/8
6.5 – DT/8
4.5 – DT/8
–2 – DT/8
8
44 + 27DT/16
40 + 27DT/16
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2 – DT/8
–2 – DT/8
Unit
ns
10
ns
NOTES
1
For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 t CK before RD or WR goes low or by t HBGRCSV after HBG goes
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-2106x section in the
ADSP-2106x SHARC User’s Manual, Second Edition.
2
Only required for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
(O/D) = open drain, (A/D) = active drive.
–26–
REV. B
ADSP-21061/ADSP-21061L
CLKIN
t SHBRI
t HHBRI
HBR
t HHBGO
t DHBGO
HBG
(OUT)
t DBRO
t HBRO
BRx
(OUT)
t DCPAO
t TRCPA
CPA (OUT)
(O/D)
t SHBGI
t HHBGI
HBG (IN)
t SBRI
t HBRI
BRx (IN)
CPA (IN) (O/D)
t SRPBAI
t HRPBAI
RPBA
HBR
CS
t TRDYHG
t DRDYCS
REDY (O/D)
t ARDYTR
REDY (A/D)
t HBGRCSV
HBG (OUT)
RD
WR
CS
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 17. Multiprocessor Bus Request and Host Bus Request
REV. B
–27–
ADSP-21061/ADSP-21061L
drive the RD and WR pins to access the ADSP-21061’s internal
memory or IOP registers. HBR and HBG are assumed low for
this timing.
Asynchronous Read/Write—Host to ADSP-21061
Use these specifications for asynchronous host processor accesses
of an ADSP-21061, after the host has asserted CS and HBR
(low). After HBG is returned by the ADSP-21061, the host can
Parameter
ADSP-21061 (5 V)
Min
Max
ADSP-21061L (3.3 V)
Min
Max
Unit
Read Cycle
Timing Requirements:
Address Setup/CS Low before RD Low1
tSADRDL
Address Hold/CS Hold Low after RD
tHADRDH
RD/WR High Width
tWRWH
RD High Delay after REDY (O/D) Disable
tDRDHRDY
RD High Delay after REDY (A/D) Disable
tDRDHRDY
0
0
6
0
0
0
0
6
0
0
ns
ns
ns
ns
ns
Switching Characteristics:
tSDATRDY
Data Valid before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay after RD Low
tDRDYRDL
REDY (O/D) or (A/D) Low Pulsewidth for Read
tRDYPRD
Data Disable after RD High
tHDARWH
45 + DT
2
Write Cycle
Timing Requirements:
CS Low Setup before WR Low
tSCSWRL
CS Low Hold after WR High
tHCSWRH
Address Setup before WR High
tSADWRH
Address Hold after WR High
tHADWRH
WR Low Width
tWWRL
RD/WR High Width
tWRWH
WR High Delay after REDY (O/D) or (A/D) Disable
tDWRHRDY
Data Setup before WR High
tSDATWH
tSDATWH (50 MHz) Data Setup before WR High, tCK = 20 ns2
Data Hold after WR High
tHDATWH
0
0
5
2
8
6
0
3
2.5
1
Switching Characteristics:
tDRDYWRL
REDY (O/D) or (A/D) Low Delay after WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
tRDYPWR
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
15
1 + 7DT/16
2
2
10
8
13.5
45 + DT
2
8
0
0
5
2
8
6
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
11
8 + 7DT/16
ns
ns
ns
ns
13.5
15
1 + 7DT/16
ns
ns
8 + 7DT/16 ns
NOTES
1
Not required if RD and address are valid t HBGRCSV after HBG goes low. For first access after HBR asserted, ADDR 31-0 must be a non-MMS value 1/2 t CLK before RD
or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-2106x section in the ADSP-2106x SHARC User’s Manual, Second Edition.
2
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t CK < 25 ns. For all other devices, use the preceding timing specification of the
same name.
CLKIN
t SRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18a. Synchronous REDY Timing
–28–
REV. B
ADSP-21061/ADSP-21061L
READ CYCLE
ADDRESS/CS
tHADRDH
tSADRDL
tWRWH
RD
tHDARWH
DATA (OUT)
tSDATRDY
tDRDYRDL
tDRDHRDY
tRDYPRD
REDY (O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
tSADWRH
tSCSWRL
tHADWRH
tHCSWRH
CS
tWWRL
tWRWH
WR
tHDATWH
tSDATWH
DATA (IN)
tDWRHRDY
tDRDYWRL
tRDYPWR
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18b. Asynchronous Read/Write—Host to ADSP-2106x
REV. B
–29–
ADSP-21061/ADSP-21061L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
ADSP-21061 (5 V)
Max
Parameter
Min
Timing Requirements:
SBTS Setup before CLKIN
tSTSCK
SBTS Hold before CLKIN
tHTSCK
12 + DT/2
Switching Characteristics:
Address/Select Enable after CLKIN
tMIENA
Strobes Enable after CLKIN1
tMIENS
HBG Enable after CLKIN
tMIENHG
Address/Select Disable after CLKIN
tMITRA
Strobes Disable after CLKIN1
tMITRS
HBG Disable after CLKIN
tMITRHG
Data Enable after CLKIN2
tDATEN
Data Disable after CLKIN2
tDATTR
ACK Enable after CLKIN2
tACKEN
ACK Disable after CLKIN2
tACKTR
ADRCLK Enable after CLKIN
tADCEN
ADRCLK Disable after CLKIN
tADCTR
Memory Interface Disable before HBG Low3
tMTRHBG
tMENHBG
Memory Interface Enable after HBG High3
ADSP-21061L (3.3 V)
Min
Max
12 + DT/2
6 + DT/2
–1 – DT/8
–1.5 – DT/8
–1.5 – DT/8
6 + DT/2
–1 – DT/8
–1.5 – DT/8
–1.5 – DT/8
0 – DT/4
1.5 – DT/4
2 – DT/4
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
7 – DT/8
6 – DT/8
0 – DT/4
1.5 – DT/4
2 – DT/4
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
8 – DT/4
0 + DT/8
19 + DT
7 – DT/8
6 – DT/8
8 – DT/4
0 + DT/8
19 + DT
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Strobes = RD, WR, MSx, SW, PAGE, DMAG, BMS.
2
In addition to bus master transition cycles, these specifications also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
–30–
REV. B
ADSP-21061/ADSP-21061L
CLKIN
t STSCK
t HTSCK
SBTS
t MITRA, t MITRS, t MITRHG
t MIEN
MEMORY
INTERFACE
t DATTR
t DATEN
DATA
t ACKTR
t ACKEN
ACK
t ADCEN
t ADCTR
ADRCLK
Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
HBG
tMTRHBG
t MENHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 19b. Three-State Timing (Host Transition Cycle)
REV. B
–31–
ADSP-21061/ADSP-21061L
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0,
ACK and DMAG signals. For Paced Master mode, the data
Parameter
transfer is controlled by ADDR31-0, RD, WR, MS3-0 and ACK
(not DMAG). For Paced Master mode, the Memory Read–Bus
Master, Memory Write–Bus Master, and Synchronous Read/
Write–Bus Master timing specifications for ADDR31-0, RD,
WR, MS3-0, SW, PAGE, DATA47-0 and ACK also apply.
ADSP-21061 (5 V)
Min
Max
ADSP-21061L (3.3 V)
Min
Max
5
5
6
5
5
6
Timing Requirements:
DMARx Low Setup before CLKIN1
tSDRLC
DMARx High Setup before CLKIN1
tSDRHC
DMARx Width Low (Nonsynchronous)
tWDR
tSDATDGL Data Setup after DMAGx Low2
tHDATIDG Data Hold after DMAGx High
Data Valid after DMARx High2
tDATDRH
DMAGx Low Edge to Low Edge
tDMARLL
DMAGx Width High
tDMARH
23 + 7DT/8
6
Switching Characteristics:
tDDGL
DMAGx Low Delay after CLKIN
DMAGx High Width
tWDGH
DMAGx Low Width
tWDGL
DMAGx High Delay after CLKIN
tHDGC
Address Select Valid to DMAGx High
tDADGH
Address Select Hold to DMAGx High
tDDGHA
tVDATDGH Data Valid before DMAGx High3
tDATRDGH Data Disable after DMAGx High4
WR Low before DMAGx Low
tDGWRL
DMAGx Low before WR High
tDGWRH
WR High before DMAGx High
tDGWRR
RD Low before DMAGx Low
tDGRDL
RD Low before DMAGx High
tDRDGH
RD High before DMAGx High
tDGRDR
tDGWR
DMAGx High to WR, RD, DMAGx Low
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
17 + DT
–0.5
8 + 9DT/16
0
0
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
5 + 3DT/8 + HI
10 + 5DT/8
2
10 + 5DT/8
2
16 + 7DT/8
16 + 7DT/8
23.5 + 7DT/8
6
15 + DT/4
6 – DT/8
7
2
3 + DT/16
2
3
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
17 + DT
–1.0
8 + 9DT/16
0
0
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
5 + 3DT/8 + HI
15 + DT/4
6 – DT/8
7
2
3 + DT/16
2
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
Only required for recognition in the current cycle.
tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven t DATDRH after DMARx is brought high.
3
tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t VDATDGH = 8 + 9DT/16 + (n × tCK) where
n equals the number of extra cycles that the access is prolonged.
4
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
1
2
–32–
REV. B
ADSP-21061/ADSP-21061L
CLKIN
t SDRLC
t DMARLL
t SDRHC
t WDR
t DMARH
DMARx
t HDGC
t DDGL
t WDGL
t WDGH
DMAGx
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
t VDATDGH
t DATRDGH
DATA (FROM
ADSP-2106x TO
EXTERNAL DRIVE)
t DATDRH
t HDATIDG
t SDATDGL
DATA (FROM
EXTERNAL DRIVE
TO ADSP-2106x)
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
t DGWRL
WR
(EXTERNAL DEVICE
TO EXTERNAL
MEMORY)
RD
(EXTERNAL
MEMORY TO
EXTERNAL DEVICE)
t DGWRH
t DGWRR
t DGRDR
t DGRDL
t DRDGH
t DADGH
t DDGHA
ADDRESS
SW, MSx
*“MEMORY READ – BUS MASTER,” “MEMORY WRITE – BUS MASTER” AND “SYNCHRONOUS READ/WRITE – BUS MASTER”
TIMING SPECIFICATIONS FOR ADDR31-0, RD, WR, SW, MS3-0 AND ACK ALSO APPLY HERE.
Figure 20. DMA Handshake Timing
REV. B
–33–
ADSP-21061/ADSP-21061L
Serial Ports
Parameter
ADSP-21061 (5 V)
Min
Max
ADSP-21061L (3.3 V)
Min
Max
Unit
External Clock
Timing Requirements:
TFS/RFS Setup before TCLK/RCLK1
tSFSE
TFS/RFS Hold after TCLK/RCLK1, 2
tHFSE
Receive Data Setup before RCLK1
tSDRE
Receive Data Hold after RCLK1
tHDRE
TCLK/RCLK Width
tSCLKW
TCLK/RCLK Period
tSCLK
3.5
4
1.5
4
9
tCK
3.5
4
1.5
4
9
tCK
ns
ns
ns
ns
ns
ns
Internal Clock
Timing Requirements:
TFS Setup before TCLK1; RFS Setup before RCLK1
tSFSI
TFS/RFS Hold after TCLK/RCLK1, 2
tHFSI
Receive Data Setup before RCLK1
tSDRI
Receive Data Hold after RCLK1
tHDRI
8
1
3
3
8
1
3
3
ns
ns
ns
ns
External or Internal Clock
Switching Characteristics:
RFS Delay after RCLK (Internally Generated RFS)3
tDFSE
RFS Hold after RCLK (Internally Generated RFS)3
tHOFSE
3
13
13
ns
ns
13
ns
ns
ns
ns
3
External Clock
Switching Characteristics:
tDFSE
tHOFSE
tDDTE
tHODTE
TFS Delay after TCLK (Internally Generated TFS)3
TFS Hold after TCLK (Internally Generated TFS)3
Transmit Data Delay after TCLK3
Transmit Data Hold after TCLK3
Internal Clock
Switching Characteristics:
TFS Delay after TCLK (Internally Generated TFS)3
tDFSI
TFS Hold after TCLK (Internally Generated TFS)3
tHOFSI
Transmit Data Delay after TCLK3
tDDTI
Transmit Data Hold after TCLK3
tHDTI
tSCLKIW TCLK/RCLK Width
Enable and Three-State
Switching Characteristics:
tDDTEN Data Enable from External TCLK3
Data Disable from External TCLK3
tDDTTE
Data Enable from Internal TCLK3
tDDTIN
Data Disable from Internal TCLK3
tDDTTI
TCLK/RCLK Delay from CLKIN
tDCLK
SPORT Disable after CLKIN
tDPTR
External Late Frame Sync
Switching Characteristics:
tDDTLFSE Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 04
tDDTENFS Data Enable from late FS or MCE = 1, MFD = 04
13
3
3
16
5
16
5
4.5
–1.5
4.5
–1.5
7.5
0
(tSCLK/2) – 2.5
(tSCLK/2) + 2.5
4.5
7.5
0
(tSCLK/2) – 2.5
(tSCLK/2) + 2.5
3.5
3
22 + 3DT/8
17
3
22 + 3DT/8
17
ns
ns
ns
ns
ns
ns
12
12
ns
10.5
0
10.5
–0.5
3.5
ns
ns
ns
ns
ns
3.5
ns
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
NOTES
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external. TFS is 0 ns minimum from drive edge.
3
Referenced to drive edge.
4
MCE = 1, TFS enable and TFS valid follow t DDTLFSE and t DDTENFS.
–34–
REV. B
ADSP-21061/ADSP-21061L
DATA RECEIVE– INTERNAL CLOCK
DATA RECEIVE– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
t SCLKIW
t SCLKW
RCLK
RCLK
t DFSE
t HOFSE
t SFSI
t DFSE
t HOFSE
t HFSI
RFS
t SFSE
t HFSE
t SDRE
t HDRE
RFS
t SDRI
t HDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
t SCLKIW
t SCLKW
TCLK
TCLK
t DFSI
t HOFSI
t SFSI
t DFSE
t HOFSE
t HFSI
TFS
t SFSE
TFS
t HDTI
t DDTI
t HDTE
t DDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK (EXT)
TFS ("LATE" EXT)
TCLK / RCLK
t DDTEN
t DDTTE
DT
DRIVE
EDGE
TCLK (INT)
TFS ("LATE", INT)
DRIVE
EDGE
TCLK / RCLK
t DDTIN
t DDTTI
DT
CLKIN
t DPTR
TCLK, RCLK
TFS, RFS, DT
SPORT DISABLE DELAY
FROM INSTRUCTION
t DCLK
TCLK (INT)
RCLK (INT)
LOW TO HIGH ONLY
Figure 21. Serial Ports
REV. B
–35–
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
t HFSE
ADSP-21061/ADSP-21061L
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RCLK
t SFSE / I
t HFSE /I*
RFS
t DDTE/I
t DDTENFS
t HDTE/I
DT
1ST BIT
2ND BIT
t DDTLFSE
LATE EXTERNAL TFS
SAMPLE
DRIVE
DRIVE
TCLK
t SFSE / I
t HFSE/I*
TFS
t DDTE/I
t DDTENFS
t HDTE/I
DT
1ST BIT
2ND BIT
t DDTLFSE
*RFS HOLD AFTER RCK WHEN MCE = 1, MFD = 0 IS 0ns MINIMUM FROM DRIVE EDGE.
TFS HOLD AFTER TCK FOR LATE EXTERNAL. TFS IS 0ns MINIMUM FROM DRIVE EDGE.
Figure 22. External Late Frame Sync
–36–
REV. B
ADSP-21061/ADSP-21061L
JTAG Test Access Port and Emulation
Parameter
ADSP-21061 (5 V)
Min
Max
ADSP-21061L (3.3 V)
Min
Max
Unit
Timing Requirements:
tTCK
TCK Period
TDI, TMS Setup before TCK High
tSTAP
TDI, TMS Hold after TCK High
tHTAP
tSSYS
System Inputs Setup before TCK Low1
System Inputs Hold after TCK Low1
tHSYS
tTRSTW TRST Pulsewidth
tCK
tCK
6
7
18
4tCK
tCK
tCK
6
7
18
4tCK
ns
ns
ns
ns
ns
ns
Switching Characteristics:
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay after TCK Low2
13
18.5
13
18.5
ns
ns
NOTES
1
System Inputs = DATA 47-0, ADDR 31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR 6-1, ID2-0, RPBA, IRQ 2-0, FLAG3-0, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, EBOOT, LBOOT, BMS, CLKIN, RESET.
2
System Outputs = DATA 47-0, ADDR 31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR 6-1, CPA, FLAG3-0, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS.
t TCK
TCK
t STAP
t HTAP
TMS
TDI
t DTDO
TDO
t SSYS
SYSTEM
INPUTS
t DSYS
SYSTEM
OUTPUTS
Figure 23. JTAG Test Access Port and Emulation
REV. B
–37–
t HSYS
ADSP-21061/ADSP-21061L
OUTPUT DRIVE CURRENTS
Table III. External Power Calculations (3.3 V Device)
Figure 27 shows typical I-V characteristics for the output drivers
of the ADSP-2106x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
POWER DISSIPATION
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Internal power dissipation is calculated in the following way:
Pin
Type
# of
Pins
%
Switching ⴛ C
Address
MS0
WR
Data
ADDRCLK
15
1
1
32
1
50
0
–
50
–
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
and is calculated by:
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2tCK). The write strobe
can switch every cycle at a frequency of 1/tCK. Select pins switch
at 1/(2tCK), but selects can switch on each cycle.
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ∆V is dependent on the capacitive load, CL and
the load current, IL. This decay time can be approximated by
the following equation:
Example:
t DECAY =
Estimate PEXT with the following assumptions:
–A system with one bank of external data memory RAM (32-bit)
–Four 128K × 8 RAM chips are used, each with a load of 10 pF
–External data memory writes occur every other cycle, a rate
of 1/(4tCK), with 50% of the pins switching
–The instruction cycle rate is 40 MHz (tCK = 25 ns).
The PEXT equation is calculated for each class of pins that can
drive:
50
0
–
50
–
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
ⴛf
ⴛ VDD2 = PEXT
× 10 MHz
× 10 MHz
× 20 MHz
× 10 MHz
× 20 MHz
× 25 V
× 25 V
× 25 V
× 25 V
× 25 V
C L ∆V
IL
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 24. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and
IL, and with ∆V equal to 0.5 V.
Output Enable Time
Table II. External Power Calculations (5 V Device)
15
1
1
32
1
= 0.037 W
= 0.000 W
= 0.010 W
= 0.026 W
= 0.001 W
TEST CONDITIONS
Output Disable Time
PEXT = O × C × VDD2 × f
Address
MS0
WR
Data
ADDRCLK
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
PTOTAL = PEXT + (IDDIN2 × 5.0 V )
– the number of output pins that switch during each cycle (O)
– the maximum frequency at which they can switch (f)
– their load capacitance (C)
– their voltage swing (VDD)
%
Switching ⴛ C
× 10 MHz
× 10 MHz
× 20 MHz
× 10 MHz
× 20 MHz
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
# of
Pins
ⴛ VDD2 = PEXT
PEXT = 0.074 W
PINT = IDDIN × VDD
Pin
Type
ⴛf
= 0.084 W
= 0.000 W
= 0.022 W
= 0.059 W
= 0.002 W
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 24). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
PEXT = 0.167 W
–38–
REV. B
ADSP-21061/ADSP-21061L
Example System Hold Time Calculation
Capacitive Loading
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-2106x’s output voltage
and the input threshold for the device requiring the hold time. A
typical ∆V will be 0.4 V. CL is the total bus capacitance (per
data line), and IL is the total leakage or three-state current (per
data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tDATRWH for the write cycle).
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 25). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 28–29,
32–33 show how output rise time varies with capacitance. Figures 30, 34 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time under Test Conditions.) The graphs of
Figures 28, 29 and 30 may not be linear outside the ranges
shown.
REFERENCE
SIGNAL
t MEASURED
INPUT OR
OUTPUT
t ENA
t DIS
VOH (MEASURED)
OUTPUT
VOH (MEASURED) – ⌬V
2.0V
VOL (MEASURED) + ⌬V
1.0V
VOL (MEASURED)
VOL (MEASURED)
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
Figure 24. Output Enable/Disable
IOL
TO
OUTPUT
PIN
+1.5V
50pF
IOH
Figure 25. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
REV. B
1.5V
Figure 26. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
VOH (MEASURED)
t DECAY
1.5V
–39–
ADSP-21061/ADSP-21061L
100
5
75
25
5.25V, –40ⴗC
5.0V, +25ⴗC
0
4.75V, +85ⴗC
–25
–50
4.75V, +85ⴗC
–75
5.0V, +25ⴗC
–100
4
OUTPUT DELAY OR HOLD – ns
SOURCE CURRENT – mA
50
5.25V, –40ⴗC
–125
–150
3
Y = 0.03X –1.45
2
1
NOMINAL
–175
–200
0
0.75
1.50
2.25
3.00
3.75
SOURCE VOLTAGE – V
4.50
–1
5.25
Figure 27. ADSP-2106x Typical Drive Currents (VDD = 5 V)
50
75
100
125
150
LOAD CAPACITANCE – pF
175
200
Figure 30. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (VDD = 5 V)
16.0
120
100
14.0
80
12.0
SOURCE CURRENT – mA
RISE AND FALL TIMES – ns
(0.5V – 4.5V, 10% – 90%)
25
RISE TIME
10.0
Y = 0.005X + 3.7
8.0
FALL TIME
6.0
4.0
2.0
40
3.0V +85ⴗC
VOH
20
0
–20
–40
3.0V +85ⴗC
–60
–80
Y = 0.0031X + 1.1
3.3V +25ⴗC
VOL
–100
0
0
20
40
60
80
100 120 140
LOAD CAPACITANCE – pF
160
180
–120
200
Figure 28. Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 5 V)
1
1.5
2
2.5
SOURCE VOLTAGE – Volts
0.5
3
3.6
18
RISE AND FALL TIMES – ns (10% – 90%)
RISE AND FALL TIMES – ns (0.8V – 2.0V)
0
3.6V –40ⴗC
Figure 31. ADSP-2106x Typical Drive Currents (VDD = 3.3 V)
3.5
3.0
2.5
RISE TIME
2.0
Y = 0.009X + 1.1
1.5
FALL TIME
1.0
Y = 0.005X + 0.6
0.5
0
3.6V –40ⴗC
3.3V +25ⴗC
60
16
14
Y = 0.0796X + 1.17
12
10
RISE TIME
8
6
Y = 0.0467X + 0.55
4
FALL TIME
2
0
0
20
40
60
80
100 120 140
LOAD CAPACITANCE – pF
160
180
0
200
20
40
60
80
100
120
140
160
180
200
LOAD CAPACITANCE – pF
Figure 29. Typical Output Rise Time (0.8 V–2.0 V) vs.
Load Capacitance (VDD = 5 V)
Figure 32. Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 3.3 V)
–40–
REV. B
ADSP-21061/ADSP-21061L
ENVIRONMENTAL CONDITIONS
Thermal Characteristics
RISE AND FALL TIMES – ns (0.8V – 2.0V)
9
8
7
Y = 0.0391X + 0.36
6
5
RISE TIME
4
Y = 0.0305X + 0.24
3
FALL TIME
2
1
0
0
20
40
60
80
100
120
140
160
180
200
LOAD CAPACITANCE – pF
Figure 33. Typical Output Rise Time (0.8 V–2.0 V) vs.
Load Capacitance (VDD = 3.3 V)
OUTPUT DELAY OR HOLD – ns
5
4
TCASE = Case temperature (measured on top surface of package)
PD =
Power dissipation in W (this value depends upon the
specific application; a method for calculating PD is
shown under Power Dissipation).
θCA =
Value from tables below.
Y = 0.0329X –1.65
ADSP-21061 (5 V MQFP Package)
3
2
1
␪JC = 0.3ⴗC/W
Airflow
(Linear Ft./Min.)
0
100
200
400
600
θCA (°C/W)
10
9
8
7
6
NOTES
This represents thermal resistance at total power of 5 W.
With air flow, no variance is seen in θCA with power.
θCA at 0 LFM varies with power: at 2W, θCA = 14°C/W, at 3W θCA = 11°C/W.
NOMINAL
–1
The ADSP-21061KS (5 V) device is packaged in a 240-lead
thermally enhanced MQFP. The top surface of the package
contains a copper slug from which most of the die heat is dissipated. The slug is flush with the top surface of the package.
Note that the copper slug is internally connected to GND
through the device substrate. The ADSP-21061LKS is packaged
in a 240-lead MQFP without a copper heat slug. The ADSP21061L is also available in a 225-Ball PBGA package. The
PBGA has a θJC of 1.7°C/W. The ADSP-2106x is specified for a
case temperature (TCASE). To ensure that the TCASE data sheet
specification is not exceeded, a heatsink and/or an air flow
source may be used. A heatsink should be attached with a thermal adhesive.
TCASE = TAMB + ( PD × θCA )
25
50
75
100
125
150
LOAD CAPACITANCE – pF
175
200
Figure 34. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (VDD = 3.3 V)
ADSP-21061L (3.3 V MQFP Package)
␪JC = 6.3ⴗC/W
Airflow
(Linear Ft./Min.)
0
100
200
400
600
θCA (°C/W)
19.6
17.6
15.6
13.9
12.2
NOTE
With air flow, no variance is seen in θCA with power.
ADSP-21061L (3.3 V PBGA Package)
␪JC = 1.7ⴗC/W
Airflow
(Linear Ft./Min.)
0
200
400
θCA (°C/W)
19.0
13.6
11.2
NOTE
With air flow, no variance is seen in θCA with power.
REV. B
–41–
ADSP-21061/ADSP-21061L
240-LEAD METRIC MQFP PIN CONFIGURATIONS
240
1
181
180
TOP VIEW
60
121
61
120
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TDI
TRST
VDD
TDO
TIMEXP
EMU
ICSA
FLAG3
FLAG2
FLAG1
FLAG0
GND
ADDR0
ADDR1
VDD
ADDR2
ADDR3
ADDR4
GND
ADDR5
ADDR6
ADDR7
VDD
ADDR8
ADDR9
ADDR10
GND
ADDR11
ADDR12
ADDR13
VDD
ADDR14
ADDR15
GND
ADDR16
ADDR17
ADDR18
VDD
VDD
ADDR19
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
ADDR20
ADDR21
GND
ADDR22
ADDR23
ADDR24
VDD
GND
VDD
ADDR25
ADDR26
ADDR27
GND
MS3
MS2
MS1
MS0
SW
BMS
ADDR28
GND
VDD
VDD
ADDR29
ADDR30
ADDR31
GND
SBTS
DMAR2
DMAR1
HBR
DT1
TCLK1
TFS1
DR1
RCLK1
RFS1
GND
CPA
DT0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
TCLK0
TFS0
DR0
RCLK0
RFS0
VDD
VDD
GND
ADRCLK
REDY
HBG
CS
RD
WR
GND
VDD
GND
CLKIN
ACK
DMAG2
DMAG1
PAGE
VDD
BR6
BR5
BR4
BR3
BR2
BR1
GND
VDD
GND
DATA47
DATA46
DATA45
VDD
DATA44
DATA43
DATA42
GND
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
DATA41
DATA40
DATA39
VDD
DATA38
DATA37
DATA36
GND
NC
DATA35
DATA34
DATA33
VDD
VDD
GND
DATA32
DATA31
DATA30
GND
DATA29
DATA28
DATA27
VDD
VDD
DATA26
DATA25
DATA24
GND
DATA23
DATA22
DATA21
VDD
DATA20
DATA19
DATA18
GND
DATA17
DATA16
DATA15
VDD
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DATA14
DATA13
DATA12
GND
DATA11
DATA10
DATA9
VDD
DATA8
DATA7
DATA6
GND
DATA5
DATA4
DATA3
VDD
DATA2
DATA1
DATA0
GND
GND
NC
NC
NC
NC
NC
NC
VDD
NC
NC
NC
NC
NC
NC
GND
GND
VDD
NC
NC
NC
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
–42–
NC
NC
NC
NC
VDD
NC
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
VDD
GND
VDD
NC
NC
NC
NC
NC
NC
GND
ID2
ID1
ID0
LBOOT
RPBA
RESET
EBOOT
IRQ2
IRQ1
IRQ0
TCK
TMS
REV. B
ADSP-21061/ADSP-21061L
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
240-Lead Metric Thermally Enhanced MQFP (5 V Device Only)
1.372 (34.85)
1.362 (34.60) TYP SQ
1.352 (34.35)
1.264 (32.10)
1.260 (32.00) TYP SQ
1.256 (31.90)
0.161 (4.10)
MAX
0.030 (0.75)
0.024 (0.60) TYP
0.020 (0.50)
1.161 (29.50) BSC SQ
240
181
1
180
240 LEAD METRIC MQFP
TOP VIEW (PINS DOWN)
SEATING
PLANE
LEAD PITCH
0.01969 (0.50)
TYP
HEAT
SLUG
LEAD WIDTH
0.011 (0.27)
0.009 (0.22) TYP
0.007 (0.17)
GND
0.003 (0.08)
MAX
0.010 (0.25)
MIN
0.138 (3.50)
0.134 (3.40) TYP
0.130 (3.30)
REV. B
INCHES (MILLIMETERS)
60
61
121
120
THE THERMALLY ENHANCED MQFP PACKAGE CONTAINS A
COPPER HEAT SLUG FLUSH WITH ITS TOP SURFACE; THE
SLUG IS EITHER CONNECTED TO GROUND OR FLOATING.
THE HEAT SLUG DIAMETER IS 24.1 (0.949) mm.
NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)
0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
–43–
ADSP-21061/ADSP-21061L
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
240-Lead Metric MQFP (3.3 V Device Only)
1.372 (34.85)
1.362 (34.60) TYP SQ
1.352 (34.35)
1.264 (32.10)
1.260 (32.00) TYP SQ
1.256 (31.90)
0.161 (4.10)
MAX
0.030 (0.75)
0.024 (0.60) TYP
0.020 (0.50)
1.161 (29.50) BSC SQ
240
181
180
1
240 LEAD METRIC MQFP
TOP VIEW (PINS DOWN)
SEATING
PLANE
LEAD PITCH
0.01969 (0.50)
TYP
LEAD WIDTH
0.011 (0.27)
0.009 (0.22) TYP
0.007 (0.17)
INCHES (MILLIMETERS)
60
0.003 (0.08)
MAX
61
121
120
0.010 (0.25)
MIN
0.138 (3.50)
0.134 (3.40) TYP
0.130 (3.30)
NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)
0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
–44–
REV. B
ADSP-21061/ADSP-21061L
ADSP-21061L 225-Ball Plastic Ball Grid Array (PBGA) Package Pinout
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
BMS
ADDR30
DMAR2
DT1
RCLK1
TCLK0
RCLK0
ADRCLK
CS
CLKIN
PAGE
BR3
DATA47
DATA44
DATA42
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
ADDR25
ADDR26
MS2
ADDR29
DMAR1
TFS1
CPA
HBG
DMAG2
BR5
BR1
DATA40
DATA37
DATA35
DATA34
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
ADDR14
ADDR15
ADDR16
ADDR19
GND
VDD
VDD
VDD
VDD
VDD
GND
DATA22
DATA25
DATA24
DATA23
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
ADDR6
ADDR5
ADDR3
ADDR0
ICSA
GND
VDD
VDD
VDD
GND
GND
DATA8
DATA11
DATA13
DATA14
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
EMU
TDO
IRQ0
IRQ1
ID2
NC
NC
NC
NC
NC
NC
NC
NC
DATA1
DATA3
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
MS0
SW
ADDR31
HBR
DR1
DT0
DR0
REDY
RD
ACK
BR6
BR2
DATA45
DATA43
DATA39
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
ADDR21
ADDR22
ADDR24
ADDR27
GND
GND
GND
GND
GND
GND
NC
DATA33
DATA30
DATA32
DATA31
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
ADDR12
ADDR11
ADDR13
ADDR10
GND
VDD
VDD
VDD
VDD
VDD
GND
DATA18
DATA19
DATA21
DATA20
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
ADDR2
ADDR1
FLAG0
FLAG3
RPBA
GND
GND
GND
GND
GND
NC
DATA4
DATA7
DATA9
DATA10
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
TRST
TMS
EBOOT
ID0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DATA0
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
MS3
MS1
ADDR28
SBTS
TCLK1
RFS1
TFS0
RFS0
WR
DMAG1
BR4
DATA46
DATA41
DATA38
DATA36
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
ADDR17
ADDR18
ADDR20
ADDR23
GND
GND
VDD
VDD
VDD
GND
GND
DATA29
DATA26
DATA28
DATA27
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
ADDR9
ADDR8
ADDR7
ADDR4
GND
VDD
VDD
VDD
VDD
VDD
GND
DATA12
DATA15
DATA16
DATA17
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
FLAG1
FLAG2
TIMEXP
TDI
GND
NC
NC
NC
NC
NC
NC
NC
DATA2
DATA5
DATA6
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
TCK
IRQ2
RESET
ID1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
REV. B
–45–
ADSP-21061/ADSP-21061L
225-Ball Plastic Ball Grid Array (PBGA) Package Pinout
Bottom View
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DATA42
DATA44
DATA47
BR3
PAGE
CLKIN
CS
ADRCLK
RCLK0
TCLK0
RCLK1
DT1
DMAR2
ADDR30
BMS
A
DATA39
DATA43
DATA45
BR2
BR6
ACK
RD
REDY
DR0
DT0
DR1
HBR
ADDR31
SW
MS0
B
DATA36
DATA38
DATA41
DATA46
BR4
DMAG1
WR
RFS0
TFS0
RFS1
TCLK1
SBTS
ADDR28
MS1
MS3
C
DATA34
DATA35
DATA37
DATA40
BR1
BR5
DMAG2
HBG
CPA
TFS1
DMAR1
ADDR29
MS2
ADDR26
ADDR25
D
DATA31
DATA32
DATA30
DATA33
NC
GND
GND
GND
GND
GND
GND
ADDR27
ADDR24
ADDR22
ADDR21
E
DATA27
DATA28
DATA26
DATA29
GND
GND
VDD
VDD
VDD
GND
GND
ADDR23
ADDR20
ADDR18
ADDR17
F
DATA23
DATA24
DATA25
DATA22
GND
VDD
VDD
VDD
VDD
VDD
GND
ADDR19
ADDR16
ADDR15
ADDR14
G
DATA20
DATA21
DATA19
DATA18
GND
VDD
VDD
VDD
VDD
VDD
GND
ADDR10
ADDR13
ADDR11
ADDR12
H
DATA17
DATA16
DATA15
DATA12
GND
VDD
VDD
VDD
VDD
VDD
GND
ADDR4
ADDR7
ADDR8
ADDR9
J
DATA14
DATA13
DATA11
DATA8
GND
GND
VDD
VDD
VDD
GND
ICSA
ADDR0
ADDR3
ADDR5
ADDR6
K
DATA10
DATA9
DATA7
DATA4
NC
GND
GND
GND
GND
GND
RPBA
FLAG3
FLAG0
ADDR1
ADDR2
L
DATA6
DATA5
DATA2
NC
NC
NC
NC
NC
NC
NC
GND
TDI
TIMEXP
FLAG2
FLAG1
M
DATA3
DATA1
NC
NC
NC
NC
NC
NC
NC
NC
ID2
IRQ1
IRQ0
TDO
EMU
N
DATA0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ID0
EBOOT
TMS
TRST
P
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ID1
RESET
IRQ2
TCK
R
NC = NO CONNECT
–46–
REV. B
ADSP-21061/ADSP-21061L
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.913 (23.20)
0.906 (23.00)
0.898 (22.80)
0.791 (20.10)
0.787 (20.00)
0.783 (19.90)
C3244b–2.5–6/00 (rev. B) 00170
Plastic Ball Grid Array (PBGA)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0.700
(17.78)
BSC
0.913 (23.20)
0.906 (23.00)
0.898 (22.80)
TOP VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
0.050
(1.27)
BSC
0.791 (20.10)
0.787 (20.00)
0.783 (19.90)
0.050 (1.27) BSC
0.700 (17.78) BSC
DETAIL A
DETAIL A
0.101 (2.57)
0.091 (2.32)
0.081 (2.06)
0.051 (1.30)
0.047 (1.20)
0.043 (1.10)
0.026 (0.65)
0.024 (0.61)
0.022 (0.57)
SEATING
NOTE
PLANE
THE ACTUAL POSITION OF THE BALL GRID IS WITHIN
0.012 (0.30) OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE
EDGES. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.004 (0.10)
OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.
0.006 (0.15) MAX
0.035 (0.90)
0.030 (0.75)
0.024 (0.60)
BALL DIAMETER
Part Number
Case Temperature
Range
Instruction Rate
On-Chip
SRAM
Operating
Voltage
Package
Option
ADSP-21061KS-133
ADSP-21061KS-160
ADSP-21061KS-200
ADSP-21061LKS-160
ADSP-21061LKS-176
ADSP-21061LAS-160
ADSP-21061LAS-176
ADSP-21061LKB-160
ADSP-21061LKB-176
0°C to +85°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
–40°C Case to +85°C Case
–40°C Case to +85°C Case
0°C to +85°C
0°C to +85°C
33 MHz
40 MHz
50 MHz
40 MHz
44 MHz
40 MHz
44 MHz
40 MHz
44 MHz
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
1 Mbit
5V
5V
5V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
MQFP
MQFP
MQFP
MQFP
MQFP
MQFP
MQFP
PBGA
PBGA
The package options are as follows: the ADSP-21061 (5 V) is available in the 240-lead thermally enhanced package and the ADSP-21061L (3.3 V) is available in the
240-lead standard (no heat slug) package, and 225-Ball PBGA.
REV. B
–47–
PRINTED IN U.S.A.
ORDERING GUIDE