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DATA SHEET MOS INTEGRATED CIRCUIT MC-10118B MULTIMEDIA PROCESSOR FOR MOBILE APPLICATIONS DESCRIPTION EMMA Mobile1-D512 (EM1-D512) (SIP: MC-10118B) is a multimedia processor for mobile applications that integrates a logic chip incorporating a CPU and DSP, and a Mobile DDR SDRAM chip, in one package. As multimedia processor functions, EM1-D512 incorporates one CPU (ARM1176JZF-STM) and one DSP (SPXK701), achieving high-speed, power-efficient application processing. EM1-D512 also incorporates image processors with various functions to accelerate image processing. Various power save modes enable the power to be controlled according to application processing. Moreover, power consumption can be reduced during standby by using sequences independent from the system. FEATURES CPU: ARM1176JZF-S (Max. 500 MHz, I-cache: 32 KB, D-cache: 32 KB) DSP: SPXK701 (Max. 500 MHz, I-cache: 32 KB, D-cache: 32 KB) Mobile DDR SDRAM (512Mb) DMA controller: Memory memory and memory peripheral interface Timers: General-purpose timers, watchdog timer (WDT) Image processing Image processor (resizing, filtering, etc.) Image rotator (0, 90, 180, 270) Graphics DMA (ROP and FILL) Image composer (LCD output image synthesis) H.264/MPEG-4 AVC accelerator application performance H.264/MPEG-4 AVC Encode/Decode: D1 30 fps Peripheral interfaces Memory interface: External bus interface (16 bits: Flash memory, etc.), NAND interface Serial interfaces: UART, I2C, audio/voice, SPI, IrDA SD card interface Image-related interfaces: LCD interface, terrestrial digital TV interface (DTV), ITU-R.BT656 interface (NTS), camera interface General-purpose I/O interface USB interface Power supply voltage Core power supply : V (1.2 V system : 1.1V - 1.3V) IO power supply : VIO18 (1.8 V system : 1.7V - 1.9V), VIO3 (3 V system : 2.7V - 3.6V) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. R19DS0008EJ0700 (7th edition) (S19657EJ7V0DS00) Date Published March 2010 Printed in Japan 2010 MC-10118B Order Information 2 Order name Package MC-10118BF1-ENY-A 481-pin FPBGA (12.7mm×12.7mm) Data Sheet R19DS0008EJ0700 MC-10118B RELATED DOCUMENTS The functions of the multimedia processor for mobile applications are described in the following documents. Refer to these documents together with this data sheet during design operations. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Multimedia Processor for Mobile Applications User’s Manual Audio/Voice and PWM Interfaces (R19UH0027EJ) DDR SDRAM Interface (R19UH0028EJ) DMA Controller (S19255E) I2C Interface (S19256E) ITU-R BT.656 Interface (S19257E) LCD Controller (S19258E) MICROWIRE (S19259E) NAND Flash Interface (S19260E) SPI (S19261E) UART Interface (S19262E) Image Composer (S19263E) Image Processor Unit (S19264E) System Control/General-Purpose I/O Interface (R19UH0029EJ) Timer (S19266E) Terrestrial Digital TV Interface (S19267E) Camera Interface (S19285E) USB Interface (S19359E) SD Memory Card Interface (S19361E) PDMA (S19373E) One Chip (R19UH0030EJ) Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. Data Sheet R19DS0008EJ0700 3 MC-10118B BLOCK DIAGRAM EM1-D512 EM1-Logic SD SD/MMC CAM IF ARM1176 OFDM IF 1-seg I2S Audio DAC I2S Mic NTSC IF NTSC dec 500MHz WiFi SDIO FM Tuner UART Blue Tooth DSP K701 UART 500MHz GPS UART DMA IPU LCD IF USB2.0 HS Link PMU Rotator GPIO INT Timer*14 SPI SDRAM IF NAND/ eMMC IF Async IF JAIRO I2C SPI Video Engine DDR 166M 512Mbit NAND eMMC 4 Data Sheet R19DS0008EJ0700 NOR LCD MC-10118B PIN LAYOUT 481-pin fine-pitch BGA package (12.7 12.7 mm) （Top View） （Bottom View） 23 21 19 17 15 13 11 9 7 5 3 1 INDEX MARK 24 22 20 18 16 14 12 10 8 6 4 2 AC AA W U R N L J G E C A AD AB Y V T P M K H F D B Data Sheet R19DS0008EJ0700 5 MC-10118B Pin Assignment (1/5) Pin No. Type A1 − Pin Name A2 − G B16 D A3 − G B17 A4 D PWM0 G URT0_SRIN Pin No. Type B15 － Pin Name G Pin No. Type Pin Name D5 D URT0_CTSB JT0_TMS D6 − G A DET1 D7 － VIO3 B18 J LCD_HSYNC D8 D SP0_SO B19 − G D9 D PM0_SEN B20 − V D10 C IIC_SCL VA1 A5 D A6 − A7 − V B21 − VIO18 D11 − A8 C PM0_CLK B22 J LCD_G1 D12 E BOOTSEL2 A9 B C32K B23 − G D13 D GIO_P3 A10 − VA2 B24 − G D14 － VIO3 A11 − G C1 − G D15 − G A12 − VA3 C2 D DTV_DATA D16 D JT0_TDO A13 − V C3 D URT2_SRIN D17 C JT0_TRSTB A14 − VIO3 C4 D URT2_RTSB D18 J LCD_ENABLE A15 − G C5 D URT0_RTSB D19 J LCD_B4 A16 D REFCLKO C6 − G D20 J LCD_B1 A17 Z OSC12M_CKO C7 − VIO3 D21 J LCD_G4 A18 Z OSC12M_CKI C8 D SP0_SI D22 J LCD_R5 A19 − G C9 C IIC2_SCL D23 J LCD_R4 A20 − V C10 C IIC_SDA D24 J LCD_PXCLK A21 − C11 − E1 − V A22 − E2 − V A23 − E3 − VIO18 A24 − E4 − VIO18 B1 − B2 − B3 G VIO18 G E BOOTSEL1 C13 D C14 － VIO3 G C15 － G E5 D GIO_P6 G C16 D JT0_TDI E6 D GIO_P5 D URT2_SOUT C17 D JT0_RTCK E7 D GIO_P4 B4 D PWM1 C18 J LCD_VSYNC E8 D SP0_CS2 B5 D URT0_SOUT C19 J LCD_B3 E9 D SP0_CS0 B6 － G C20 J LCD_B0 E10 D PM0_SI B7 － V C21 J LCD_G3 E11 R TE2 B8 D SP0_CLK C22 J LCD_G2 E12 E BOOTSEL3 B9 C IIC2_SDA C23 J LCD_G0 E13 E BOOTSEL0 B10 − VA2 C24 － G E14 D GIO_P0 B11 − G D1 C DTV_BCLK E15 － G B12 − VA3 D2 D DTV_PSYNC E16 C JT0_TCK B13 − V D3 D DTV_VLD E17 N TESTRSTB B14 − VIO3 D4 D URT2_CTSB E18 M TRSTB 6 G C12 VA1 G GIO_P2 Data Sheet R19DS0008EJ0700 MC-10118B (2/5) Pin No. Type E19 J E20 J Pin Name LCD_B5 LCD_B2 Pin No. Type H14 D H15 － Pin Name GIO_P1 G Pin No. Type Pin Name K12 − G K13 − G G E21 J LCD_G5 H16 J DEBUG_EN K14 − E22 J LCD_R3 H17 E UTEST K15 − G E23 J LCD_R2 H20 M AB0_CSB0 K16 － G E24 J LCD_R1 H21 − VDD_DDR K17 － IC F1 − G H22 − VDD_DDR K20 M AB0_A24 F2 − G H23 − VDD_DDR K21 M AB0_A23 F3 − G H24 − VDD_DDR K22 M AB0_A22 F4 − G J1 D NTS_DATA1 K23 M AB0_A21 F5 D GIO_P7 J2 D NTS_DATA2 K24 M AB0_A20 F6 − G J3 D NTS_DATA3 L1 D SD1_DATA1 F20 J LCD_R0 J4 D NTS_DATA4 L2 D SD1_DATA2 F21 M AB0_CSB3 J5 D NTS_DATA6 L3 D SD1_DATA3 J8 − G L4 D SD0_CMD J9 − G L5 D SD0_DATA0 J10 − L8 − G J11 − L9 − G J12 − L10 − G J13 − L11 − G G F22 M F23 − F24 − G1 − G2 − G3 − G4 − VDD_DDR J14 − G L12 − G5 D GIO_P8 J15 − G L13 − G G20 M AB0_CSB1 J16 − G L14 − G G21 − G J17 − G L15 − G G22 − G J20 M AB0_WAIT L16 － G G23 − G J21 M AB0_BEN1 L17 − G G24 − G J22 M AB0_BEN0 L20 M AB0_A19 H1 C NTS_CLK J23 M AB0_A26 L21 − V H2 D NTS_VS J24 M AB0_A25 L22 − V H3 D NTS_HS K1 C SD1_CKI L23 − VIO18 H4 D NTS_DATA0 K2 D SD1_CMD L24 − VIO18 M1 − VIO3 M2 − VIO3 M3 − VIO3 − VIO3 H5 H8 H9 D D D H10 D H11 − H12 H13 Remark Q C AB0_CSB2 V V VDDQ_DDR VDDQ_DDR VDD_DDR NTS_DATA5 SP0_CS1 PM0_SO ERR_RST_REQB G TE1 A_RESETB K3 K4 D D G G G G SD1_CKO SD1_DATA0 K5 D K8 − NTS_DATA7 G M4 K9 − G M5 D SD0_DATA1 K10 － M8 － G K11 － M9 － G G G IC : Internally-connected pins (Leave open) Data Sheet R19DS0008EJ0700 7 MC-10118B (3/5) Pin No. Type M10 − M11 − M12 − M13 − M14 Pin No. Type Pin No. Type Pin Name P8 − P9 − G T4 D SD2_DATA2 G P10 − G T5 D GIO_P10 G T8 − G P11 − G G T9 − G − G P12 − G T10 − G M15 − G P13 − G T11 − G M16 − G P14 − G T12 − IC M17 − G P15 − G T13 − IC M20 M AB0_A18 P16 − G T14 − G M21 − G P17 − G T15 − G M22 − G P20 M AB0_WRB T16 － G M23 − G P21 M AB0_RDB T17 － G M24 − G P22 P AB0_AD15 T20 P AB0_AD8 N1 − G P23 P AB0_AD14 T21 P AB0_AD7 N2 − G P24 P AB0_AD13 T22 P AB0_AD6 N3 − G R1 C SD0_CKI T23 P AB0_AD5 N4 − G R2 D SD0_DATA2 T24 P AB0_AD4 N5 − U1 − V N8 − U2 − V N9 − U3 − V N10 − V N11 − N12 − N13 G G G G G R3 R4 D D Pin Name SD0_DATA3 SD2_CMD R5 D G R8 − G U4 − G R9 − G U5 − V G R10 − G U8 − G − G R11 − G U9 − G N14 − G R12 − G U10 − G N15 － G R13 − G U11 − G N16 － G R14 − G U12 − IC N17 － G R15 − G U13 − IC N20 M AB0_A17 R16 － G U14 − IC N21 − VDD_DDR R17 － G U15 － IC N22 − VDD_DDR R20 P AB0_AD12 U16 － IC N23 − VDD_DDR R21 P AB0_AD11 U17 － G N24 − VDD_DDR R22 P AB0_AD10 U20 P AB0_AD3 P1 − U21 − V P2 − U22 − V P3 − U23 − VIO18 P4 − U24 − VIO18 P5 − V1 － G Remark 8 Pin Name VDD_DDR VDD_DDR VDDQ_DDR VDDQ_DDR VDDQ_DDR R23 R24 T1 T2 T3 P J D D D GIO_P9 AB0_AD9 AB0_CLK SD0_CKO SD2_DATA0 SD2_DATA1 IC : Internally-connected pins (Leave open) Data Sheet R19DS0008EJ0700 MC-10118B (4/5) Pin No. Type Pin No. Type V2 − AB12 − V3 − IC AB13 − V4 − IC USB_STP AB14 − G Y23 G V5 − G Y24 G IC USB_CLK AB15 − G V20 P AB0_AD2 AA1 C SD2_CKI AB16 − IC V21 − G AA2 D SD2_DATA3 AB17 − IC V22 − G AA3 − IC AB18 − VIO18 V23 − G AA4 − IC AB19 − G V24 − G AA5 − IC AB20 − IC W1 − VDDQ_DDR AA6 − G AB21 G USB_DATA4 W2 − VDDQ_DDR AA7 − IC AB22 G USB_DIR W3 − VDD_DDR AA8 − IC AB23 G USB_DATA3 W4 − VDD_DDR AA9 − IC AB24 − G AA10 − AC1 − G AA11 − AC2 − G AA12 − AC3 − IC AA13 − AC4 − IC AA14 − AC5 − V AA15 − AC6 − G AA16 − AC7 − VIO18 IC W5 － Pin Name G G IC AB0_AD1 Pin No. Type Y21 P Y22 G Pin Name AB0_AD0 AB0_ADV G W20 P W21 − W22 − W23 − W24 − Y1 − Y2 − VIO3 AA17 − IC AC8 − Y3 − VIO3 AA18 − VIO18 AC9 − IC Y4 − VIO3 AA19 − G AC10 − G Y5 − IC AA20 − IC AC11 − VIO18 Y6 − IC AA21 G USB_DATA7 AC12 − IC Y7 − IC AA22 G USB_DATA6 AC13 − IC Y8 − IC AA23 G USB_DATA5 AC14 − IC Y9 − IC AA24 G USB_NXT AC15 − G Y10 − IC AB1 − G AC16 − IC Y11 − V AB2 D SD2_CKO AC17 − IC Y12 − IC AB3 − IC AC18 − V Y13 − AB4 − AC19 − G Y14 − AB5 − IC AC20 − IC Y15 − AB6 − G AC21 G USB_DATA1 Y16 − AB7 − VIO18 AC22 G USB_DATA2 Y17 − AB8 − AC23 − G Y18 − AB9 − AC24 − G Y19 − AB10 − AD1 − G Y20 − AB11 − AD2 − G VDD_DDR VDD_DDR VDD_DDR VDD_DDR VIO3 IC IC IC IC IC IC IC IC V Pin Name IC IC IC G IC IC IC IC G VIO18 Data Sheet R19DS0008EJ0700 9 MC-10118B (5/5) Pin No. Type AD3 − G AD4 − IC AD5 − V AD6 − G AD7 − VIO18 AD8 − IC AD9 − IC AD10 − G AD11 − VIO18 AD12 − IC AD13 − IC AD14 − IC AD15 − G AD16 − IC AD17 − IC AD18 − V AD19 − G AD20 － IC AD21 G USB_DATA0 AD22 － G AD23 － G AD24 － G 10 Pin Name Data Sheet R19DS0008EJ0700 MC-10118B CONTENTS 1. PIN FUNCTIONS ...................................................................................................................................12 1.1 Pin Configuration ........................................................................................................................12 1.2 Pin Functions ..............................................................................................................................13 1.3 I/O Circuits ...................................................................................................................................27 2. ELECTRICAL SPECIFICATIONS .........................................................................................................31 2.1 Absolute Maximum Ratings .......................................................................................................31 2.2 Recommended Operating Conditions ......................................................................................31 2.3 Capacitance .................................................................................................................................32 2.4 DC Characteristics ......................................................................................................................33 2.5 AC Characteristics ......................................................................................................................36 3. PACKAGE DRAWING...........................................................................................................................60 Data Sheet R19DS0008EJ0700 11 MC-10118B 1. PIN FUNCTIONS 1.1 Pin Configuration 16 10 2 External bus interface 4 AB0_CLK BOOTSEL[3:0] AB0_AD[15:0] 4 DET1 A_RESETB C32K REFCLKO PLL2OUT OSC12M_OUT ERR_RST_REQB OSC12M_CKI AB0_A[26:17] AB0_BEN[1:0] AB0_CSB[3:0] AB0_WAIT AB0_WRB AB0_RDB AB0_ADV System interface OSC12M_CKO LCD_PXCLK x：0～1 SPI interface x：0～2 3 SP0_CS[2:0] SP1_CS[5:0] SP2_CS0 DTV_BCLK DTV_DATA DTV_PSYNC DTV_VLD Terrestrial digital TV interface NTS_CLK NTS_VS NTS_HS ITU-R BT.656 interface 8 NTS_DATA[7:0] SDx_CKO SDx_CMD SD interface 4 8 NAND Flash interface 4 4 12 LCD_B[5:0] LCD_HSYNC LCD_VSYNC LCD_ENABLE 6 6 LCD interface 6 USB_CLK EM1-D512 USB_DATA[7:0] USB_DIR USB_STP USB_NXT USB_WAKEUP USB_PWR_FAULTZ 8 USB interface IIC_SCL IIC_SDA IIC2_SCL IIC2_SDA IIC interface URTx_SRIN URTx_SOUT URT0_CTSB URT0_RTSB URT2_RTSB URT2_CTSB SDx_DATA[3:0] SDx_CKI NAND_ALE NAND_CLE JTAG pins LCD_G[5:0] SPx_CLK SPx_SI SPx_SO 6 x：0～2 LCD_R[5:0] PMx_CLK PMx_SEN PMx_SI PMx_SO Audio/Voice interface UART interface x：0～2 PWM interface x：0～1 PWMx GIO_P[117:0] 118 MWI_SK MWI_SI MWI_SO MWI_CS NAND_D[7:0] NAND_OE NAND_WE General-purpose I/O interface MICROWIRE interface NAND_RB[3:0] NAND_CE[3:0] DEBUG_EN JT0_TCK JT0_TRSTB JT0_TMS JT0_TDI JT0_TDO JT0_RTCK CAM＿SCLK CAM_YUV[7:0] CAM_VS CAM_HS CAM_CLKI UTEST TESTRSTB TRSTB TE1 TE2 Data Sheet R19DS0008EJ0700 8 Camera interface Test pins MC-10118B 1.2 Pin Functions (1) Boot select signals (VIO18) Pin Name Pin No. I/O Function Alternate Pin Type Function Handling When Not Used BOOTSEL3 E12 Input Boot mode selection 3 E BOOTSEL2 D12 Input Boot mode selection 2 E BOOTSEL1 C12 Input Boot mode selection 1 E BOOTSEL0 E13 Input Boot mode selection 0 E Alternate Pin Type Handling When (2) System control signals (VIO3 / VIO18) Pin Name Pin No. I/O Function Function Not Used Power-on reset A Input System reset C . Input Reference clock (32.768 kHz) B −. PLL2OUT D Leave open. D Leave open. D Leave open. DET1 B17 Input A_RESETB H13 C32K A9 REFCLKO A16 Output Reference clock OSC12M_OUT PLL2OUT A16 Output Internal PLL2 output REFCLKO OSC12M_OUT OSC12M_OUT A16 Output Internal OSC output REFCLKO ERR_RST_REQB H10 Output Error reset request D Leave open. A18 Input OSC XT1 Z Leave open. A17 Output OSC XT2 Z Leave open. PLL2OUT OSC12M_CKI NOTE OSC12M_CKO Note NOTE VIO18 Data Sheet R19DS0008EJ0700 13 MC-10118B (3) External bus interface signals (VIO18) Pin Name Pin No. I/O Function Alternate Pin Type Function AB0_CLK R24 Output Clock GIO_P11 Handling When Not Used J Leave open. NTS_CLK AB0_AD[15:0] P22, P23, P24, I/O Data GIO_P[27:12] P Leave open. Output Address GIO_P[37:31] M Leave open. M Leave open. M Leave open M Leave open R20, R21, R22, R23, T20, T21, T22, T23, T24, U20, V20, W20, Y21 AB0_A[26:20] J23, J24, K20, K21, K22, K23, K24 AB0_A[19:17] L20, M20, N20 AB0_A[10:4] Output Address GIO_P[30:28] NTS_DATA[2:0] AB0_A[3:1] AB0_A[10:4] J23, J24, K20, K21, Output Address K22, K23, K24 AB0_A[3:1] L20, M20, N20 GIO_P[37:31] AB0_A[26:20] Output Address GIO_P[30:28] NTS_DATA[2:0] AB0_A[19:17] AB0_BEN[1:0] J21, J22 Output Byte enable GIO_P[47:46] M Leave open. AB0_CSB3 F21 Output Chip select GIO_P45 M Leave open. M Leave open. M Leave open. M Leave open. M Leave open. M Leave open. M Leave open. G Leave open. NTS_HS AB0_CSB2 F22 Output Chip select GIO_P44 NTS_VS AB0_CSB1 G20 Output Chip select GIO_P43 NTS_DATA7 AB0_CSB0 H20 Output Chip select GIO_P42 NTS_DATA6 AB0_WAIT J20 Input Wait GIO_P41 NTS_DATA5 AB0_WRB P20 Output Write strobe GIO_P40 NTS_DATA4 AB0_RDB P21 Output Read strobe GIO_P39 NTS_DATA3 AB0_ADV 14 Y22 Output Address enable Data Sheet R19DS0008EJ0700 GIO_P38 MC-10118B (4) Audio interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Type Function PM0_CLK A8 I/O PM0_SEN D9 I/O Handling When Not Used PCM0 clock (default input) C Leave open. PCM0 frame synchronization (default D Leave open. input) PM0_SI E10 Input PCM0 data GIO_P87 D Leave open. PM0_SO H9 Output PCM0 data D Leave open. PM1_CLK H1 I/O PCM1 clock (default input) GIO_P72 C Leave open. PM1_SEN H5 I/O PCM1 frame synchronization (default GIO_P80 D Leave open. input) NTS_DATA5 D Leave open. D Leave open. NTS_CLK SP1_CS4 PM1_SI J5 Input PCM1 data GIO_P81 NTS_DATA6 SP1_CS5 PM1_SO K5 Output PCM1 data GIO_P82 NTS_DATA7 (5) Camera interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Function Type Handling When Not Used CAM_SCLK E6 Output Camera clock GIO_P5, NAND_RB2 D Leave open. CAM_CLKI K1 Input Camera interface GIO_P92, SD1_CKI C Leave open. CAM_YUV7 L1 Input Camera interface SD1_DATA1 D Leave open. CAM_YUV6 K4 Input Camera interface SD1_DATA0 D Leave open. CAM_YUV5 K2 Input Camera interface SD1_CMD D Leave open. CAM_YUV4 J4 Input Camera interface NTS_DATA4, SP1_CS3 D Leave open. D Leave open. D Leave open. D Leave open D Leave open GIO_P79 CAM_YUV3 J3 Input Camera interface NTS_DATA3, SP1_CS2 GIO_P78 CAM_YUV2 J2 Input Camera interface NTS_DATA2, SP1_CS1 GIO_P77 CAM_YUV1 J1 Input Camera interface NTS_DATA1, SP1_CS0 GIO_P76 CAM_YUV0 H4 Input Camera interface NTS_DATA0, SP1_SO GIO_P75 CAM_HS L3 Input Camera interface SD1_DATA3 D Leave open CAM_VS L2 Input Camera interface SD1_DATA2 D Leave open Data Sheet R19DS0008EJ0700 15 MC-10118B (6) SPI interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Type Function Handling When Not Used SP0_CLK B8 I/O SPI0 clock output MWI_SK D Leave open. SP0_SI C8 Input SPI0 data MWI_SI D Leave open. SP0_SO D8 Output SPI0 data MWI_SO D Leave open. SP0_CS0 E9 I/O SPI0 chip select MWI_CS D Leave open. SP0_CS[2:1] E8, H8 Output SPI0 chip select GIO_P[49:48] D Leave open. SP1_CLK H2 I/O SPI1 clock input GIO_P73 D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. NTS_VS SP1_SI H3 Input SPI1 data GIO_P74 NTS_HS SP1_SO H4 Output SPI1 data GIO_P75 NTS_DATA0 CAM_YUV0 SP1_CS5 J5 Output SPI1 chip select GIO_P81 NTS_DATA6 PM1_SI SP1_CS4 H5 Output SPI1 chip select GIO_P80 NTS_DATA5 PM1_SEN SP1_CS[3:1] J4, J3, J2 Output SPI1 chip select GIO_P[79:77] NTS_DATA[4:2] CAM_YUV[4:2] SP1_CS0 J1 I/O SPI1 chip select GIO_P76 NTS_DATA1 CAM_YUV1 SP2_CLK D1 I/O SPI2 clock input DTV_BCLK C Leave open. SP2_SI C2 Input SPI2 data DTV_DATA D Leave open. SP2_SO D2 Output SPI2 data DTV_PSYNC D Leave open. SP2_CS0 D3 I/O SPI2 chip select DTV_VLD D Leave open. (7) Terrestrial digital TV interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Type Function Handling When Not Used DTV_BCLK D1 Input Clock SP2_CLK C Leave open. DTV_DATA C2 Input YUV data SP2_SI D Leave open. DTV_PSYNC D2 Input Vertical synchronization SP2_SO D Leave open. DTV_VLD D3 Input Horizontal synchronization SP2_CS0 D Leave open. 16 Data Sheet R19DS0008EJ0700 MC-10118B (8) LCD interface signals (VIO18) Pin Name Pin No. I/O Function Alternate Pin Type Function Handling When Not Used LCD_PXCLK D24 Output Pixel clock GIO_P50 J Leave open. LCD_R[5:0] D22, D23, E22, Output Red data GIO_P[56:51] J Leave open. Output Green data GIO_P[62:57] J Leave open. Output Blue data GIO_P[68:63] J Leave open. Horizontal GIO_P69 J Leave open. E23, E24, F20 LCD_G[5:0] E21, D21, C21, C22, B22, C23 LCD_B[5:0] E19, D19, C19, E20, D20, C20 LCD_HSYNC B18 Output synchronization LCD_VSYNC C18 Output Vertical synchronization GIO_P70 J Leave open. LCD_ENABLE D18 Output Data enable GIO_P71 J Leave open. (9) USB interface signals (VIO18 / VIO3) Pin Name Pin No. I/O Function Alternate Pin Type Function Handling When Not Used USB_CLK Y24 Input Clock GIO_P96 G Leave open. USB_DATA[7:0] AA21, AA22, I/O USB data GIO_P[104:97] G Leave open. AA23, AB21, AB23, AC22, AC21, AD21 USB_DIR AB22 Input USB DIR input GIO_P105 G Leave open. USB_STP Y23 Output USB STOP output GIO_P106 G Leave open. AA24 Input USB NXT input GIO_P107 G Leave open. H14 Output Suspend wakeup GIO_P1 D Leave open. D Leave open. USB_NXT USB_WAKEUP NOTE USB_PWR_FAULT USB_PWR_FAULT NOTE H14 Input Power fault GIO_P1 USB_WAKEUP Note VIO3 Data Sheet R19DS0008EJ0700 17 MC-10118B (10) ITU-R BT.656 interface signals (VIO3 / VIO18) Pin Name Pin No. I/O Function Alternate Pin Function Type Handling When Not Used NTS_CLK H1 Input R24 NTS_VS H2 Output H3 Output K5 Output NTSC data Note G20 NTS_DATA6 Horizontal synchronization Note F21 NTS_DATA7 Vertical synchronization Note F22 NTS_HS Clock Note J5 Output NTSC data GIO_P72, PM1_CLK C Leave open. AB0_CLK, GIO_P11 J Leave open GIO_P73, SP1_CLK D Leave open. AB0_CSB2, GIO_P44 M Leave open. GIO_P74, SP1_SI D Leave open. AB0_CSB3, GIO_P45 M Leave open. GIO_P82, PM1_SO D Leave open. AB0_CSB1, GIO_P43 M Leave open GIO_P81, SP1_CS5 D Leave open. AB0_CSB0, GIO_P42 M Leave ope GIO_P80, SP1_CS4 D Leave open. AB0_WAIT, GIO_P41 M Leave open. GIO_P79, SP1_CS3 D Leave open. PM1_SI Note H20 NTS_DATA5 H5 Output NTSC data PM1_SEN J20 NTS_DATA4 Note J4 Output NTSC data CAM_YUV4 P20 NTS_DATA3 Note J3 Output NTSC data AB0_WRB, GIO_P40 M Leave open. GIO_P78, SP1_CS2 D Leave open. AB0_RDB, GIO_P39 M Leave open GIO_P77, SP1_CS1 D Leave open. M Leave open D Leave open. M Leave ope D Leave open. M Leave open. CAM_YUV3 P21 NTS_DATA2 Note J2 Output NTSC data CAM_YUV2 L20 Note AB0_A3, AB0_A19, GIO_P30 NTS_DATA1 J1 Output NTSC data GIO_P76, SP1_CS0 CAM_YUV1 M20 Note AB0_A2, AB0_A18, GIO_P29 NTS_DATA0 H4 Output NTSC data GIO_P75, SPI_SO CAM_YUV0 N20 Note AB0_A1, AB0_A17, GIO_P28 Note 18 VIO18 Data Sheet R19DS0008EJ0700 MC-10118B (11) IIC interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Function Type Handling When Not Used IIC_SCL D10 Output Serial clock input GIO_P83 C Leave open. IIC_SDA C10 I/O Serial data input GIO_P84 C Leave open. IIC2_SCL C9 Output Serial clock input NAND_WE C Leave open. IIC2_SDA B9 I/O Serial data input NAND_RB0 C Leave open. (12) UART interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Type Function Handling When Not Used URT0_SRIN A5 Input Serial data D Leave open. URT0_SOUT B5 Output Serial data D Leave open. URT0_CTSB D5 Input Data transmission/reception ready in GIO_P85 D Leave open. destination device URT1_SRIN Data transmission/reception ready GIO_P86 D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. URT0_RTSB C5 Output URT1_SOUT URT1_SRIN D5 Input Serial data GIO_P85 URT0_CTSB URT1_SOUT C5 Output Serial data GIO_P86 URT2_SRIN C3 Input Serial data GIO_P108 URT0_RTSB NAND_ALE URT2_SOUT B3 Output Serial data GIO_P109 NAND_CLE URT2_CTSB URT2_RTSB D4 C4 Input Output Data transmission/reception ready in GIO_P110 destination device NAND_D0 Data transmission/reception ready GIO_P111 NAND_D1 Data Sheet R19DS0008EJ0700 19 MC-10118B (13) Memory card interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Type Function Handling When Not Used SD0_CKO T1 Output Clock − D Leave open. SD0_CMD L4 I/O Command response − D Leave open. SD0_DATA[3:1] R3, R2, I/O Data D Leave open. D Leave open. GIO_P91 C Leave open. D Leave open. GIO_P[90:88] M5 − SD0_DATA0 L5 I/O Data SD0_CKI R1 Input Loop back SD1_CKO K3 Output Clock SD1_CMD K2 I/O Command response CAM_YUV5 D Leave open. SD1_DATA3 L3 I/O Data CAM_HS D Leave open. SD1_DATA2 L2 I/O Data CAM_VS D Leave open. SD1_DATA1 L1 I/O Data CAM_YUV7 D Leave open. SD1_DATA0 K4 I/O Data CAM_YUV6 D Leave open. SD1_CKI K1 Input Loop back GIO_P92 C Leave open. D Leave open. D Leave open. D Leave open. C Leave open. CAM_CLKI SD2_CKO AB2 Output Clock GIO_P112 NAND_D2 SD2_CMD R4 I/O Command response GIO_P113 NAND_D3 SD2_DATA[3:0] AA2, T4, I/O Data GIO_P[117:114] T3, T2 SD2_CKI AA1 NAND_D[7:4] Input Loop back GPIO_P93 NAND_OE (14) PWM interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Type Function Handling When Not Used PWM0 A4 Output PWM output GIO_P94 D Leave open. PWM1 B4 Output PWM output GIO_P95 D Leave open. 20 Data Sheet R19DS0008EJ0700 MC-10118B (15) General-purpose I/O interface signals (VIO18 / VIO3) (1/3) Pin Name Pin No. I/O Function Alternate Pin Type Function GIO_P[117:114] AA2, T4, T3, T2 I/O General-purpose IO SD2_DATA[3:0] Handling When Not Used D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. NAND_D[7:4] GIO_P113 R4 I/O General-purpose IO SD2_CMD NAND_D3 GIO_P112 AB2 I/O General-purpose IO SD2_CKO NAND_D2 GIO_P111 C4 I/O General-purpose IO URT2_RTSB NAND_D1 GIO_P110 D4 I/O General-purpose IO URT2_CTSB GIO_P109 B3 I/O General-purpose IO URT2_SOUT NAND_D0 NAND_CLE GIO_P108 C3 I/O General-purpose IO URT2_SRIN NAND_ALE GIO_P107 Note AA24 I/O General-purpose IO USB_NXT G Leave open. GIO_P106 Note Y23 I/O General-purpose IO USB_STP G Leave open. GIO_P105 Note AB22 I/O General-purpose IO USB_DIR G Leave open. AA21, AA22, I/O General-purpose IO USB_DATA[7:0] G Leave open. Y24 I/O General-purpose IO USB_CLK G Leave open. GIO_P[95:94] B4, A4 I/O General-purpose IO PWM[1:0] D Leave open. GIO_P93 AA1 I/O General-purpose IO SD2_CKI C Leave open. GIO_P92 K1 I/O General-purpose IO C Leave open. GIO_P[104:97] Note AA23, AB21, AB23, AC22, AC21, AD21 GIO_P96 Note NAND_OE SD1_CKI CAM_CLKI GIO_P91 R1 I/O General-purpose IO SD0_CKI C Leave open. GIO_P[90:88] R3, R2, M5 I/O General-purpose IO SD0_DATA[3:1] D Leave open. GIO_P87 E10 I/O General-purpose IO PM0_SI D Leave open. GIO_P86 C5 I/O General-purpose IO URT0_RTSB D Leave open. D Leave open. URT1_SOUT GIO_P85 D5 I/O General-purpose IO URT0_CTSB URT1_SRIN GIO_P84 C10 I/O General-purpose IO IIC_SDA C Leave open. GIO_P83 D10 I/O General-purpose IO IIC_SCL C Leave open. Data Sheet R19DS0008EJ0700 21 MC-10118B (2/3) Pin Name Pin No. I/O Function Alternate Pin Type Function GIO_P82 K5 I/O General-purpose IO NTS_DATA7 Handling When Not Used D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. C Leave open. PM1_SO GIO_P81 J5 I/O General-purpose IO NTS_DATA6 SP1_CS5 PM1_SI GIO_P80 H5 I/O General-purpose IO NTS_DATA5 SP1_CS4 PM1_SEN GIO_P[79:76] J4, J3, J2, J1 I/O General-purpose IO NTS_DATA[4:1] SP1_CS[3:0] CAM_YUV[4:1] GIO_P75 H4 I/O General-purpose IO NTS_DATA0 SP1_SO CAM_YUV0 GIO_P74 H3 I/O General-purpose IO NTS_HS SP1_SI GIO_P73 H2 I/O General-purpose IO NTS_VS SP1_CLK GIO_P72 H1 I/O General-purpose IO NTS_CLK PM1_CLK GIO_P71 Note D18 I/O General-purpose IO LCD_ENABLE J Leave open. GIO_P70 Note C18 I/O General-purpose IO LCD_VSYNC J Leave open. GIO_P69 Note B18 I/O General-purpose IO LCD_HSYNC J Leave open. E19, D19, C19, I/O General-purpose IO LCD_B[5:0] J Leave open. I/O General-purpose IO LCD_G[5:0] J Leave open. I/O General-purpose IO LCD_R[5:0] J Leave open. GIO_P[68:63] Note GIO_P[62:57] Note GIO_P[56:51] Note E20, D20, C20 E21, D21, C21, C22, B22, C23 D22, D23, E22, E23, E24, F20 GIO_P50 Note D24 I/O General-purpose IO LCD_PXCLK J Leave open. GIO_P[49:48] Note E8, H8 I/O General-purpose IO SP0_CS[2:1] D Leave open. GIO_P[47:46] Note J21,J22 I/O General-purpose IO AB0_BEN[1:0] M Leave open. F21 I/O General-purpose IO AB0_CSB3 M Leave open. M Leave open. M Leave open. M Leave open. GIO_P45 Note GIO_P44 Note GIO_P43 Note NTS_HS F22 I/O General-purpose IO AB0_CSB2 NTS_VS G20 I/O General-purpose IO AB0_CSB1 NTS_DATA7 GIO_P42 Note H20 I/O General-purpose IO AB0_CSB0 NTS_DATA6 22 Data Sheet R19DS0008EJ0700 MC-10118B (3/3) Pin Name Pin No. I/O Function Alternate Pin Type Function GIO_P41 Note GIO_P40 Note J20 I/O General-purpose IO AB0_WAIT Handling When Not Used M Leave open. M Leave open. M Leave open. NTS_DATA5 P20 I/O General-purpose IO AB0_WRB NTS_DATA4 GIO_P39 Note GIO_P38 Note P21 I/O General-purpose IO AB0_RDB NTS_DATA3 GIO_P[37:31] Note Y22 I/O General-purpose IO AB0_ADV G Leave open. J23, J24, K20, I/O General-purpose IO AB0_A[26:20] M Leave open. M Leave open. AB0_AD[15:0] P Leave open. AB0_CLK J Leave open. K21, K22, K23, AB0_A[10:4] K24 GIO_P[30:28] Note L20, M20, N20 I/O General-purpose IO AB0_A[19:17] NTS_DATA[2:0] AB0_A[3:1] GIO_P[27:12] Note P22, P23, P24, I/O General-purpose IO I/O General-purpose IO R20, R21, R22, R23, T20, T21, T22, T23, T24, U20, V20, W20, Y21 GIO_P11 Note R24 NTS_CLK GIO_P[10:7] T5, R5, G5, F5 I/O General-purpose IO NAND_CE[3:0] D Leave open. GIO_P6 E5 I/O General-purpose IO NAND_RB3 D Leave open. GIO_P5 E6 I/O General-purpose IO NAND_RB2 D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. CAM_SCLK GIO_P4 E7 I/O General-purpose IO GIO_P[3:2] D13, C13 I/O General-purpose IO GIO_P1 H14 I/O General-purpose IO NAND_RB1 USB_WAKEUP USB_PWR_FAUL T GIO_P0 Note E14 I/O General-purpose IO VIO18 Data Sheet R19DS0008EJ0700 23 MC-10118B (16) MICROWIRE interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Type Function Handling When Not Used MWI_SK B8 Output Clock SP0_CLK D Leave open. MWI_SI C8 Input Data SP0_SI D Leave open. MWI_SO D8 Output Data SP0_SO D Leave open. MWI_CS E9 Output Chip select SP0_CS0 D Leave open. Type Handling When (17) NAND Flash interface signals (VIO3) Pin Name Pin No. I/O Function Alternate Pin Function NAND_ALE C3 Output Address latch enable URT2_SRIN Not Used D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. D Leave open. C Leave open. GIO_P108 NAND_CLE B3 Output Command latch enable URT2_SOUT GIO_P109 NAND_D[7:4] AA2, T4 I/O Data SD2_DATA[3:0] T3, T2 NAND_D3 R4 GIO_P[117:114] I/O Data SD2_CMD GIO_P113 NAND_D2 AB2 I/O Data SD2_CKO GIO_P112 NAND_D1 C4 I/O Data URT2_RTSB GIO_P111 NAND_D0 D4 I/O Data URT2_CTSB GIO_P110 NAND_OE AA1 Output Output enable SD2_CKI GIO_P93 NAND_WE C9 Output Write enable IIC2_SCL C Leave open. NAND_RB0 B9 Input Ready busy IIC2_SDA C Leave open. NAND_RB3 E5 Input Ready busy GIO_P6 D Leave open. NAND_RB2 E6 Input Ready busy GIO_P5 D Leave open. CAM_SCLK NAND_RB1 E7 Input Ready busy GIO_P4 D Leave open. NAND_CE[3:0] T5, R5, Output Chip enable GIO_P[10:7] D Leave open. G5, F5 24 Data Sheet R19DS0008EJ0700 MC-10118B (18) JTAG signals (VIO18 / VIO3) Pin Name Pin No. I/O Function Alternate Pin Type Function Note Handling When Not Used H16 Input JTAG J Leave open. JT0_TCK E16 Input JTAG C Leave open. JT0_TRSTB D17 Input JTAG C Leave open. JT0_TMS B16 Input JTAG D Leave open. JT0_TDI C16 Input JTAG D Leave open. JT0_TDO D16 Output JTAG D Leave open. JT0_RTCK C17 Output JTAG D Leave open. Alternate Pin Type DEBUG_EN VIO18 Note (19) Test signals (VIO18) Pin Name Pin No. I/O Function Function Handling When Not Used UTEST H17 Input Test pin (usually fixed to 0) E “L” level hold. TESTRSTB E17 Input Asynchronous reset for testing N Leave open. TRSTB E18 Input Test pin M Leave open. TE1 H12 Input Test pin Q Leave open. TE2 E11 Input Test pin R Leave open. (20) Power supply Pin Name Pin No. I/O Function Type Handling When Not Used V A7, A13, A20, B7, B13, B20, E1, Core power supply (1.2 V) IO power supply (1.8 V system) IO power supply (3 V system) E2, F23, F24, L21, L22, U1, U2, U3, U4, U5, U21, U22, Y11, AA11, AC5, AC18, AD5, AD18 VIO18 A21, B21, E3, E4, L23, L24, U23, U24, AA18, AB7, AB11, AB18, AC7, AC11, AD7, AD11 VIO3 A14, B14, C7, C14, D7, D14, M1, M2, M3, M4, Y1, Y2, Y3, Y4 VA1 C11, D11 PLL power supply (1.2V) VA2 A10, B10 PLL power supply (1.2V) VA3 A12, B12 PLL power supply (1.2V) VDDQ_DDR G1, G2, P3, P4, P5, W1, W2 DDR power supply (1.8V) VDD_DDR G3, G4, H21, H22, H23, H24, N21, DDR power supply (1.8V) N22, N23, N24, P1, P2, W3, W4, W21 ,W22, W23, W24 Data Sheet R19DS0008EJ0700 25 MC-10118B (21) GND Pin Name G Pin No. Function A1, A2, A3, A6, A11, A15, A19, A22, A23, A24, B1, B2, B6, B11, B15, B19, B23, B24, C1, C6, GND C15, C24, D6, D15, E15, F1, F2, F3, F4, F6, G21, G22, G23, G24, H11, H15, J8, J9, J10, J11, J12, J13, J14, J15, J16, J17,K8, K9, K10, K11, K12, K13, K14, K15, K16, L8, L9, L10, L11, L12, L13, L14, L15, L16, L17, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M21, M22, M23, M24, N1, N2, N3, N4, N5, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, T8, T9, T10, T11, T14, T15, T16, T17, U8, U9, U10, U11, U17, V1, V2, V3, V4, V5, V21, V22, V23, V24, AA6, AA10, AA15, AA19, AB1, AB6, AB10, AB15, AB19, AB24, AC1, AC2, AC6, AC10, AC15, AC19, AC23, AC24, AD1, AD2, AD3, AD6, AD10, AD15, AD19, AD22, AD23, AD24 (22) Other Pin Name Pin No. I/O Function Type Handling When Not Used IC K17, T12, T13, U12, U13, U14, U15, Internally-connected pins U16, W5, Y5, Y6, Y7, Y8, Y9, Y10, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y19, Y20, AA3, AA4, AA5, AA7, AA8, AA9, AA12, AA13, AA14, AA16, AA17, AA20, AB3, AB4, AB5, AB8, AB9, AB12, AB13, AB14, AB16, AB17, AB20, AC3, AC4, AC8, AC9, AC12, AC13, AC14, AC16, AC17, AC20, AD4, AD8, AD9, AD12, AD13, AD14, AD17, AD16, AD20 26 Data Sheet R19DS0008EJ0700 MC-10118B 1.3 I/O Circuits (1/4) Type A Description Input buffer Schmitt (VIO3) w / IO-Standby Control Other IO buffers are fixed on the time of Power OFF mode in A Y POW OFF state of appendix D by inputting the Low level to this buffer. IO-Standby go-around signal Remark In the Power-off mode, pins remain in a Hi-Z state (input) and the signals are passed through this buffer. Types B, E Normal Description C0 C1 Bidirectional buffer Schmitt (type B = VIO3, type E = VIO18) w / IOLH control Normal / Pull-up 50 k / Pull-down 50 k A OEN During power-off: Pins remain in a Hi-Z state Resistance = 50 k (typ.) Y1 Y0 50 kΩ UPC POENB Type C Normal Description C0 C1 Bidirectional buffer Schmitt (VIO3) w / IOLH control Normal / Pull-up 50 k / Pull-down 50 k A OEN During power-off: Pins remain in a Hi-Z state (masked by 0 internally) Y1 Y0 Resistance = 50 k (typ.) 50 kΩ UPC POENB Data Sheet R19DS0008EJ0700 27 MC-10118B (2/4) Type D Normal Description C0 C1 A OEN Bidirectional buffer AND (VIO3) w / IOLH control Normal / Pull-up 50 k / Pull-down 50 k During power-off: Pins remain in a Hi-Z state (masked by 0 internally) Y0 Y1 50 k Resistance = 50 k (typ.) CTL UPC POENB Types G Normal Description C0 C1 A OEN Bidirectional buffer AND (VIO18) w / IOLH control Normal / Pull-up 50 k Pull-down 50 k During power-off: Type G: Pins are pulled down (masked by 0 internally) Y0 Y1 50 k Resistance = 50 k (typ.) CTL UPC POENB Type J Normal Description C0 C1 A OEN Bidirectional buffer AND, Schmitt (VIO18) w / IOLH control Normal / Pull-up 50 k / Pull-down 50 k During power-off: Pins are pulled down (masked by 0 internally) Y0 Y1 50 k Resistance = 50 k (typ.) CTL UPC POENB 28 Data Sheet R19DS0008EJ0700 MC-10118B (3/4) Types M, N Low noise Description C0 C1 Bidirectional buffer Schmitt / LowNoise (VIO18) w / IOLH control Normal / Pull-up 50 k / Pull-down 50 k A OEN During power-off: Type M: Pins are pulled down (masked by 0 internally) Type N: Pins are pulled up (masked by 0 internally) Y1 Y0 Resistance = 50 k (typ.) 50 kΩ UPC POENB Type P Normal Description C0 Bidirectional buffer (VIO18) C1 w / IOLH control bus holder A OEN During power-off: Pins output a low level (masked by 0 internally) Y0 Resistance = 6.5 k (typ.) Y1 6.5 k BusHolder Types Q, R Description Test buffer (VIO18) Types Q and R are buffers used exclusively for testing. Leave open when used in the actual device. (Always pull A down the pins (typ. 50 k) 50 k Go-around signal Data Sheet R19DS0008EJ0700 29 MC-10118B (4/4) Type Z Description oscillator XT1 30 XT2 Data Sheet R19DS0008EJ0700 MC-10118B 2. ELECTRICAL SPECIFICATIONS 2.1 Absolute Maximum Ratings Parameter Symbol Power supply voltage Rating Unit 1.2 V system 0.5 to +1.8 V VIO18 1.8 V system (I/O) 0.5 to +2.5 V VIO3 3 V system (I/O) 0.5 to +4.6 V Power supply for memories 0.5 to +2.3 V V VDD_DDR Conditions VDDQ_DDR Input voltage Output voltage Storage temperature VI_18 1.8 V system (I/O) 0.5 to VIO18 + 0.5 V VI_33 3 V system (I/O) 0.5 to VIO3 + 0.5 V VO_18 1.8 V system (I/O) 0.5 to VIO18 + 0.5 V VO_33 3 V system (I/O) 0.5 to VIO3 + 0.5 V 40 to +125 − Tstg C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Note Instantaneous input of a voltage in the range of 0.8 to VDD12 + 0.8 V is allowed as long as capacitive coupling is implemented. 2.2 Recommended Operating Conditions Parameter Symbol Power supply voltage V Conditions MIN. TYP. MAX. Unit 1.2 V system, during normal operation 1.1 1.2 1.3 V Memory retention voltage 0.64 − − V Note 1 V_PLL 1.2 V system (PLL power supply, pin: VA) 1.1 1.2 1.3 V VIO18 1.8 V system (I/O power supply) 1.7 1.8 1.9 V VIO3 3 V system (I/O power supply) 2.7 − 3.6 V Power supply for memories 1.7 1.8 1.9 V VDD_DDR VDDQ_DDR Oscillation start voltage VOSC_S − 1.7 − − V VOSC_H − 1.7 − − V TA − 20 − +70 C Note 2 Oscillation start voltageNote 3 Operating ambient temperature Notes 1. This is the voltage that guarantees retention of data in the internal SRAM when the voltage drops during normal operation. 2. This is the voltage at which oscillation always starts after power-on. 3. This is the voltage that guarantees oscillation when the voltage drops during normal operation. Data Sheet R19DS0008EJ0700 31 MC-10118B 2.3 Capacitance (TA = +25C, f = 1 MHz, unmeasured pins returned to 0 V) Parameter Input capacitance Symbol CI Conditions 1.8 V 2.8 V Output capacitance CO 1.8 V 2.8 V I/O capacitance CIO 1.8 V 2.8 V 32 Data Sheet R19DS0008EJ0700 MIN. TYP. MAX. Unit 3 − 5 pF 2 − 4 pF 3 − 5 pF 2 − 4 pF 3 − 5 pF 2 − 4 pF MC-10118B 2.4 2.4.1 DC Characteristics VIO18 (Unless it's designated in particular by the item after this, it'll be the standard under 2.2 recommendation operating condition. ) Parameter Symbol Conditions MIN. TYP. MAX. Unit VIO18 0.1 − − V − − 0.1 V Output voltage, high VOH No DC loadNote 1 Output voltage, low VOL No DC load Input voltage, high VIH I/O pins and monitor pins 0.65 VIO18 − VIO18 + 0.5 V Input voltage, low VIL I/O pins and monitor pins 0.5 − 0.35 VIO18 V 1.7 − − mA − mA Output current, high VOH = VIO18 0.4 VNote 2 Output current, low VOL = 0.4 V Note 2 Note 1 IOUT_H1 2 mA setting Note 3 IOUT_H2 4 mA setting Note 3 3.7 − IOUT_H3 6 mA setting Note 3 5.7 − − mA IOUT_H4 8 mA settingNote 3 7.7 − − mA IOUT_H5 12 mA settingNote 3 11.0 − − mA IOUT_L1 2 mA setting Note 3 1.7 − − mA IOUT_L2 4 mA setting Note 3 3.7 − − mA IOUT_L3 6 mA setting Note 3 5.7 − − mA IOUT_L4 8 mA setting Note 3 7.7 − − mA IOUT_L5 12 mA setting 11.0 − − mA Note 3 Hysteresis voltage VH Schmitt input 0.20 VIO18 − 0.63 VIO18 V Negative trigger voltage VN Schmitt input 0.53 VIO18 0.66 − 0.35 VIO18 V Positive trigger voltage VP Schmitt input 0.68 VIO18 − 0.83 VIO18 V Input leakage current, high IL_H VI = VIO18 − − 1 A Input leakage current, low IL_L VI = GND − − 1 A Pull-up resistance RPU − 40 − 65 k Pull-down resistance RPD − 40 − 65 k Bus-holder hold resistance RBH 5 − 11 k Bus-holder series resistance Pull-up pin current IPU − − − 50 A Pull-down pin current IPD − − − 50 A Notes 1. The parameters VOH and VOL here are the values guaranteed when there is no load when applying the DC current. 2. The parameters VOH and VOL here define the output current. 3. This is the value set to the I/O buffer output current drive switch register. Data Sheet R19DS0008EJ0700 33 MC-10118B 2.4.2 VIO3 Parameter Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high VOH No DC loadNote 1 VIO3 0.1 − − V Output voltage, low VOL No DC loadNote 1 − − 0.1 V Input voltage, high VIH I/O pins and monitor pins 2.0 − VIO3 + 0.5 V Input voltage, low VIL I/O pins and monitor pins 0.5 − 0.8 V IOUT_H1 2 mA setting Note 3 1.7 − − mA IOUT_H2 4 mA setting Note 3 3.7 − − mA IOUT_H3 6 mA setting Note 3 5.7 − − mA IOUT_H4 8 mA setting Note 3 7.7 − − mA Output current, low IOUT_L1 2 mA setting Note 3 1.7 − − mA VOL = 0.4 VNote 2 IOUT_L2 4 mA settingNote 3 3.7 − − mA IOUT_L3 6 mA settingNote 3 5.7 − − mA IOUT_L4 8 mA setting 7.7 − − mA Hysteresis voltage VH Schmitt input 0.11 VIO3 − 0.41 VIO3 V Negative trigger voltage VN Schmitt input 0.17 VIO3 − 0.38 VIO3 V Schmitt input 0.54 VIO3 − 0.65 VIO3 V VI = VIO3 − − 1 A − Output current, high VOH = VIO3 0.4 VNote 2 Positive trigger voltage VP Input leakage current, high IL_H Note 3 Input leakage current, low IL_L VI = GND − 1 A Pull-up resistance RPU 50 k resistor 40 − 65 k Pull-down resistance RPD 50 k resistor 40 − 65 k Pull-up pin current IPU 50 k resistor − − 90 A Pull-down pin current IPD 50 k resistor − − 90 A Notes 1. The parameters VOH and VOL here are the values guaranteed when there is no load when applying the DC current. 2. VOL = 0.4 V, VOH = VIO3 0.4 V. The parameters VOH and VOL here define the output current. 3. This is the value set to the output current drive switch register. 2.4.3 Standby state current (Logic) (TA = 25C) Parameter Standby current Symbol MIN. TYP. MAX. Unit − 130 400 A Logic power supply L0 on, f = 0 Hz, V = 0.75 V − 100 300 A Logic power supply L0 on, f = 0 Hz, V = 1.2 V − 340 − A IDD_IO18 IO power supply f = 0 Hz, VIO18 = 1.8 V − − 10 A IDD_IO3 IO power supply f = 0 Hz, VIO3 = 2.85 V − − 10 A IDD_L0 Conditions Logic power supply L0 + L2 on, f = 0 Hz, V = 0.75 V 34 Data Sheet R19DS0008EJ0700 MC-10118B 2.4.4 Standby state current (Mobile DDR SDRAM) Parameter Standby current Symbol DDR IDD7 Conditions MIN. TYP. MAX. Unit − − 10 μA MIN. TYP. MAX. Unit -25C ≦DDR_TJ≦+85C − − 500 μA CKE≦0.2V − − 400 μA − − 300 μA CKE≦0.2V (Deep power-down mode) 2.4.5 Self refresh current Parameter PASR = “000” (Full) PASR = “001” (2BK) Symbol DDR IDD6 Conditions PASR = “010” (1BK) Data Sheet R19DS0008EJ0700 35 MC-10118B 2.5 2.5.1 AC Characteristics AC test I/O measurement points Figure 2-1. AC Test I/O Measurement Points VIO18 VIO3 0.7 VIO Input pin Input measurement points 0.3 VIO 0.7 VIO 0.3 VIO VIO18 VIO3 Input measurement points 0.8 VIO Input pin (Schmitt) 0.1 VIO 0.8 VIO 0.1 VIO VIO18 VIO3 Output pin Load condition Output measurement points 0.5 VDD DUT 0.5 VDD Output pin CL = 15 pF Remark Excluding the OSC pin. Unless specified otherwise, the load of CL is assumed to be 15 pF. Unless it's designated in particular by the item after this, it'll be the standard under 2.2 recommendation operating condition 36 Data Sheet R19DS0008EJ0700 MC-10118B 2.5.2 System control (1) Clock (input timing requirements) Parameter C32K frequency Symbol Conditions MIN. TYP. MAX. Unit fclkC32K − − 32.768 − kHz − − 1 s 32 kHz input clock duty ratio IdutyC32K − 40 50 60 % 32 kHz input clock jitter IjitterC32K − 20 − 20 ns OSC oscillation frequency range fC(OSC) Internal oscillator (OSC12M_CKI − − 13 MHz − 0.5 1 ms C32K rise/fall time trfC32K 10 to 90% or OSC12M_CKO) (with crystal resonator DSX530GA; made by Daishinku) OSC clock stabilization time tSTAB12 CI = CO = 15 pF The oscillating frequency : 12MHz (with crystal resonator DSX530GA; made by Daishinku) Figure 2-2. Clock Timing 1/fclkC32K trfC32K trfC32K twC32K(H) twC32K(L) Input clock C32K Figure 2-3. Recommended Oscillator OSC12M_CKI OSC12M_CKO Cautions 1. Keep the wiring length between the oscillator and the OSC12M_CKI and OSC12M_CKO pins as short as possible. 2. Do not cross the wiring with the other signal lines in the area enclosed by the broken lines. 3. Thoroughly evaluate matching of the resonator. Data Sheet R19DS0008EJ0700 37 MC-10118B (2) Reset (A_RESETB) Parameter Symbol A_RESETB low-level width Remark Conditions MIN. TYP. MAX. Unit − 6 − − ms tA_RESETB In the case of a hardware reset. Figure 2-4. Reset Timing tRSTIB, tA_RESETB A_RESETB (3) Power supply start-up Timing (without power supply -> Normal) IO power supply (VIO18) Time when a VIO18 power supply becomes stable. IO power supply (VIO3) Time when a VIO3 power supply becomes stable. Core power supply (V) PLL power supply (VA1/2/3) Time when V,VA1,VA2,VA3 power supply becomes stable. Min:0us C32K Min:200us DET1 Min:200us A_RESETB (inside PLL) (1) (2) (3) (4) (5) (6) Figure 2-5. Power supply start-up timing Remarks “Stable” means that each power supply becomes the specification minimum voltage. The timing figure which starts from the “Without power supply”. (1) IO power supply (VIO18) is supplied, and stands by until a power supply becomes stable. (2) IO power supply (VIO3) is supplied, and stands by until a power supply becomes stable. (3) Corepower supply (V) and PLL power supply (VA1/2/3) are supplied, and stands by until a power supply becomes stable. (4) RTC clock 32.768kHz (C32K) is input. (5) DET1 is signal is started. (6) A_RESETB signal rising (reset release), and PLL begins to oscillate. 38 Data Sheet R19DS0008EJ0700 MC-10118B (4) Power supply start-up Timing (DeepSleep<- -> Normal) IO power supply (VIO18,VIO3) Min:2ms Core power supply (V) “0.75V” setting “OFF”setting PLL power supply (VA1/2/3) C32K DET1 A_RESETB (inside PLL) Min:0ms GIO_P0 Normal (1) DeepSleep (2) Normal (3) (4) Figure 2-6. DeepSleep Normal timing (1) EM1-D512 sends the command to Power Management IC by SPI Interface. The contents of the command are as follows. Core power supply (V) voltage is changed to 0.75 from 1.2V. PLL power supply (VA1/2/3) is stopped. (2) Power Management IC changes the Core power supply (V) to 0.75V from 1.2V in at least 2 ms later and stops PLL power supply (VA1/2/3). EM1-D512 does the preparations to transfer to the DeepSleep state between (1) and (2). (3) Core power supply (V) voltage is changed to 1.2V from 0.75V. VPLL power supply (VA1/2/3) is supplied. (4) GIO_P0 signal rising and inside PLL begins to oscillate. EM1-D512 is transit of state from DeepSleep to Normal after inside PLL stable. Data Sheet R19DS0008EJ0700 39 MC-10118B (5) Power supply start-up Timing (PowerOff<- -> Normal) IO power supply (VIO18,VIO3) Core power supply(V) PLL power supply(VA1/2/3) Min:0us Min:0us C32K Min:200us Min:0us DET1 Min:200us Min:0us A_RESETB (inside PLL) GIO_P0 Normal Normal PowerOff (1) (2)(3) (4) (5) Figure 2-7. PowerOff Normal timing (1) A_RESETB signal and DET1 signal are falling, and RTC clock (C32K) is stop. Next Core power supply and PLL power supply are stopped at the same time. (2) Core power supply (V) and PLL power supply (VA1/2/3) are supplied same time, and stand by until a power supplies become stable. (3) RTC clock 32.768kHz (C32K) is input. GIO_P0 signal rising. It's to make EM1-D512 recognizes that it's different from "Without power supply". (4) DET1 is signal is started. (5) A_RESETB signal rising (reset release), and inside PLL begins to oscillate. 40 Data Sheet R19DS0008EJ0700 MC-10118B 2.5.3 Asynchronous bus (AB0) interface Parameter Asynchronous single Symbol t201 Conditions Note MIN. TYP. MAX. Unit (1 + T0 + T1 + T2) − (2 + T0 + T1 + T2) ns Tf 3 read access time Tf + 3 CSZ rise to ADVZ fall t202 Note Tf 3 − 2Tf + 3 ns ADVZ active width t203 AB0_ADVZ = Low Tf 3 − Tf + 3 ns Lower ADD for ADMUX t204 T0 Tf 3 − T0 Tf + 3 ns − hold time t205 Falling edge of AB0_RDZ T0 Tf 3 − T0 Tf + 3 ns Read signal active width t206 AB0_RDZ = Low T1 Tf 3 − T1 Tf + 3 ns Delay time from RDZ rise t207 Rising edge of AB0_RDZ T2 Tf 3 − T2 Tf + 3 ns CSInt Tf 3 − − ns − ns Delay time from ADVZ rise to read signal output to CSZ fall output CS assert interval time Asynchronous _RDATA − t208 t209 Rising edge of AB0_RDZ 15 − t210 Rising edge of AB0_RDZ 0 − − ns t211 Falling edge of AB0_RDZNote (1 + T0) Tf 8 − − ns t212 Falling edge of AB0_RDZNote (1 + T0) Tf 3 − − ns t220 Note (1 + T0 + T1W + − (2 + T0 + T1W + ns setup time Asynchronous _RDATA hold time Delay time from address determination to RDZ fall Delay time from CSZ fall to RDZ rise output Asynchronous single T2W ) Tf 3 write access time Delay time from ADVZ T2W ) Tf + 3 T0×Tf 3 − T0 Tf + 3 ns AB0_WRZ = Low T1W Tf 3 − T1W Tf + 3 ns t223 Rising edge of AB0_WRZ T2W Tf 3 − T2W Tf + 3 ns t224 Rising edge of AB0_WRZ T2W Tf 8 − − ns t225 Falling edge of AB0_WRZNote (1 + T0) Tf 8 − − ns t226 Falling edge of AB0_WRZNote (1 + T0) Tf 3 − − ns t221 Rising edge of AB0_WRZ Write signal active width t222 Delay time from WRZ rise to write signal output rise to CSZ fall output Asynchronous _WDATA output hold time Delay time from address determination to WRZ fall Delay time from CSZ fall to WRZ fall output Note The time from the CSB falling edge to the ADV falling edge (Tf) can be shortened by setting a register. Remark Tf = 1/4 of AB0_CLK. (When frequency ratio 1/4 is usually the time of the state (AB0_CLK:FLASH_CLK = 2:1). T0, T1, T2, CSInt: Values set to read the wait timing control register (AB0_CSxWAITCTRL) T1W , T2W : Values set to write the wait timing control register (AB0_CSxWAITCTRL_W) Data Sheet R19DS0008EJ0700 41 MC-10118B Figure 2-8. Asynchronous Single Read Timing t211 AB0_A[25:1] ADD t212 t201 t208 CSZ[3:0] BENZ[1:0] t202 AB0_ADV t205 t207 t206 t203 t209 AB0_RDZ t204 AB0_D[15:0] t210 ((Lower ADD) (Data) Figure 2-9. Asynchronous Single Write Timing t225 AB0_A[25:1] ADD t226 t208 t220 CSZ[3:0] BENZ[1:0] t202 AB0_ADV t221 t222 t223 AB0_WRZ t224 t204 AB0_D[15:0] 42 (Lower ADD) (Data) Data Sheet R19DS0008EJ0700 MC-10118B 2.5.4 UART interface (IO buffer drive capability: 2 mA) Parameter Symbol UARTx_SOUT output delay tDC tDR Conditions MIN. TYP. MAX. Unit Falling edge of UARTx_CTSB − − 4 RCLK Center of UARTx_SRIN stop bit − − 3 RCLK time UARTx_RTSB output delay time Remark RCLK: 1/16 of baud rate clock cycle Figure 2-10. UART Interface Timing Start UARTx_SOUT data Stop tDC UARTx_CTSB UARTx_SRIN Start data Stop tDR UARTx_RSTB Remark x = 0 to 2 (UARTx_CTSB and UARTx_RSTB for UART0 and UART2 are pins and are not provided for UART1.) Data Sheet R19DS0008EJ0700 43 MC-10118B 2.5.5 IIC interface (IO buffer drive capability: 2 mA) Parameter Symbol Conditions IIC_SCL clock frequency fC − IIC bus free time tBF Standard ModeNote 1 Interval between stop and start High-Speed ModeNote 1 Unit MIN. MAX. MIN. MAX. 0 70 0 341 kHz 4.7 1.3 s 4.0 0.6 s conditions − IIC hold timeNote 2 tH1 IIC hold time (SCL clock) tWL “Low” state 4.7 1.3 s tWH “Hi” state 4.0 0.6 s tSU1 Start condition 4.7 0.6 s 250 100Note 3 IIC setup time Restart condition ns IIC rise time tR SDA and SCL signals 300Note 4 ns IIC fall time tF SDA and SCL signals 300Note 4 ns IIC data setup time − tSU2 IIC setup time tSU3 Stop condition 4.0 0.6 s IIC data hold time tH2 Clock fall output 5.0 − s 0 3.45 0Note 5 0.9Note 6 s 400 400 pF Clock fall input Capacitance load of each Cb − IIC bus line Notes 1. Select the standard mode or high-speed mode by using the SMC0 bit of the IIC0 clock select register (IICCL0). 2. At the start condition, the first clock pulse is generated after the hold time. 3. The high-speed mode I2C bus can be used in the standard-mode I2C bus system. In this case, set the high-speed mode I2C bus so that it meets the following conditions. If the system does not extend the IIC_SCL signal’s low state hold time: tSU2 250 ns 4. Do not input noise exceeding the hysteresis width of the 1.8 V system IO Schmitt buffer during a rise or fall time. 5. The system requires a minimum of 300 ns hold time internally for the SDA signal (at VIH (MIN.) [0.7 VDD2] of IIC_SCL signal) in order to occupy the undefined area at the falling edge of IIC_SCL. 6. If the system does not extend the IIC_SCL signal low hold time (tWL), only the maximum data hold time (tH2) needs to be satisfied. 44 Data Sheet R19DS0008EJ0700 MC-10118B Figure 2-11. IIC Bus Interface Timing tWL tR tWH tF IIC_SCL tH1 IIC_SDA tBF tH2 tSU2 Stop condition Start condition IIC_SCL tSU3 tSU1 tH1 IIC_SDA Restart condition Data Sheet R19DS0008EJ0700 Stop condition 45 MC-10118B 2.5.6 Audio/Voice interface (1) Slave mode Parameter Symbol Conditions MIN. TYP. MAX. Unit tC − 100 − − ns PMx_CLK high-level width tWH − 40 − − ns PMx_CLK low-level width tWL − 40 − − ns Clock rise time tR − − − 10 ns Clock fall time tF − − − 10 ns PMx_SI, PMx_SEN setup time tSU 20 − − ns 20 − − ns 0 − 20 ns PMx_CLK cycle time Rising and falling edges of PMx_CLK PMx_SI, PMx_SEN hold time tH Rising and falling edges of PMx_CLK PMx_SO output delay time tD Rising and falling edges of PMx_CLK Remark Time from the valid edge x = 0, 1 Figure 2-12. Audio/Voice Interface Timing (Slave Mode) tC t WH tR tWL PMx_CLK (input) tSU tH PMx_SI (input) PMx_SEN (input) tD PMx_SO (output) 46 Data Sheet R19DS0008EJ0700 tF MC-10118B (2) Master mode Parameter Symbol Conditions MIN. TYP. MAX. Unit tC − 100 − − ns tWH − 40 − − ns PM0_CLK low-level width tWL − 40 − − ns Clock rise time tR − − − 10 ns Clock fall time tF − − − 10 ns PMx_SI setup time tSU − 20 − − ns PM0_SI hold time tH − 20 − − ns PM0_SO, PM0_SEN output delay time tD − 5 − 20 ns PM0_CLK cycle time PM0_CLK high-level width Remark Time from the valid edge x = 0, 1 Figure 2-13. Audio/Voice Interface Timing (Master Mode) tC tH tR tF tL PMx_CLK (output) tSU tH PMx_SI (input) tD PMx_SO (output) PMx_SEN (output) Data Sheet R19DS0008EJ0700 47 MC-10118B 2.5.7 SDIO interface Parameter Symbol Conditions SD0 (SDIA), SD1 (SDIB), SD2 (SDIC) MIN. TYP. MAX. Unit Tcyc − 24.0 − − ns Output clock high-level width Thwcko − 11.5 − − ns Output clock low-level width Tlwcko − 11.5 − − ns Tod − − − 2 ns Thwcki − 7.5 − − ns Tlwcki − 7.5 − − ns Tdcki − − − 6 ns Tiscki − 3.5 − − ns Tihcki − 0 − − ns Clock cycle Output delay Input clock high-level width Input clock low-level width Input clock delay time Setup time Hold time Figure 2-14. SDIO Interface Timing T cyc Tl wcko Thwcko SDx_CKO (output) Tod SDx_DATA[3:0] (output) SDx_CMD (output) T dcki T cyc Thwcki SDx_CKI (input) Ti scki SDx_DATA[3:0] (input) SDx_CMD (input) Remark 48 x = 0 to 2 Data Sheet R19DS0008EJ0700 T ihcki T lwcki MC-10118B 2.5.8 Camera interface Parameter Symbol Conditions MIN. TYP. MAX. Unit tC − 12.5 − − ns CAM_CLKI high-level width tWH − 4 − − ns CAM_CLKI low-level width tWL − 4 − − ns − ns CAM_CLKI input cycle CAM_YUV[7:0], CAM_HS, CAM_VS tSU0 DET = 0 5 − tH0 DET = 0 0 − − ns tSU1 DET = 1 5 − − ns tH1 DET = 1 1 − − ns setup time CAM_YUV[7:0], CAM_HS, CAM_VS hold time CAM_YUV[7:0], CAM_HS, CAM_VS setup time CAM_YUV[7:0], CAM_HS, CAM_VS hold time Figure 2-15. Camera Interface Timing tC tWH tWL CAM_CLKI (input) tSU0 tH0 DET = 0 CAM_YUV[7:0] (input) CAM_HS, CAM_VS (input) tSU1 tH1 DET = 1 CAM_YUV[7:0] (input) CAM_HS, CAM_VS (input) Data Sheet R19DS0008EJ0700 49 MC-10118B 2.5.9 LCD interface Parameter Symbol Conditions MIN. TYP. MAX. Unit tC − 30 − − ns LCD_PXCLK high-level width tWH − 12 − − ns LCD_PXCLK low-level width tWL − 12 − − ns LCD_PXCLK rise time tR LCD_PXCLK cycle LCD_PXCLK fall time tF Data delay time tD1 20 to 80% − − 5 ns 80 to 20% − − 5 ns 0 − 10 ns 0 − 10 ns LCD_R[5:0], LCD_G[5:0], LCD_B[5:0] tD2 LCD_VSYNC, CD_HSYNC, LCD_ENABLE Remark The setting of the rise and fall timing for LCD_PXCLK is based on the valid edge set by the CLKPOL value in the LCD control register (rising: CLKPOL = 0, falling: CLKPOL = 1). Figure 2-16. LCD Interface Timing tR tC tWH tWL LCD_PXCLK tD1 LCD_R[5:0] LCD_G[5:0] LCD_B[5:0] tD2 LCD_ENABLE LCD_HSYNC LCD_VSYNC 50 Data Sheet R19DS0008EJ0700 tF MC-10118B 2.5.10 USB interface Parameter Symbol USB_CLK cycle tK01 Conditions 60 MHz MIN. TYP. MAX. Unit − 16.7 − ns USB_CLK high-level width tK02 − 7 − − ns USB_CLK low-level width tK03 − 7 − − ns USB_CLK rise time tK04 − − − 2 ns USB_CLK fall time tK05 − − − 2 ns USB control input setup time tK06 − 5 − − ns USB control input hold time tK07 − 1 − − ns USB data input setup time tK08 − 5 − − ns USB data input hold time tK09 − 1 − − ns USB data output delay time tK11 − 0.5 − 7 ns USB_STP output delay time tK10 − 1 − 9 ns Figure 2-17. USB Interface Timing tK04 tK01 tK02 tK05 tK03 USB_CLK (input) tK06 tK07 tK08 tK09 USB_DIR (input) USB_NXT (input) USB_DATA[7:0] (input) tK10 USB_STP (output) tK11 USB_DATA[7:0] (output) Data Sheet R19DS0008EJ0700 51 MC-10118B 2.5.11 SPI interface (1) Master mode Parameter Symbol Conditions MIN. TYP. MAX. Unit tC − 40 − − ns SPx_CLK high-level width tWH − 16 − − ns SPx_CLK low-level width tWL − 16 − − ns SPx_CLK rise time tR 20 to 80% − 4 ns 80 to 20% − 4 ns 12 − − ns 0 − − ns 0 − 12 ns 12 − − ns 0 − − ns 0 − 12 ns 12 − − ns 0 − − ns 0 − 12 ns Common to SP0, SP1, and SP2 SPx_CLK output cycle SPx_CLK fall time tF SP0 SP0_SI setup time tSU0 Rising and falling edges of SP0_CLK SP0_SI hold time tH0 Rising and falling edges of SP0_CLK SP0_SO delay time tDO0 Rising and falling edges of SP0_CLK SP1 SP1_SI setup time tSU1 Rising and falling edges of SP1_CLK SP1_SI hold time tH1 Rising and falling edges of SP1_CLK SP1_SO delay time tDO1 Rising and falling edges of SP1_CLK SP2 SP2_SI setup time tSU2 Rising and falling edges of SP2_CLK SP2_SI hold time tH2 Rising and falling edges of SP2_CLK SP2_SO delay time tDO2 Rising and falling edges of SP2_CLK 52 Data Sheet R19DS0008EJ0700 MC-10118B Figure 2-18. SPI Interface Timing (Master Mode) tC tWH tR tF tWL SPx_CLK (output) tSU tH SPx_SI SPx_CSn (input) t DO SPx_SO (output) Remarks 1. The level of the SPx_CLK output can be inverted by setting a register. 2. SPx_CLK is not output while SPx_CLK is inactive. (Fixed to inactive.) 3. If the read latency of the connected device is long, the time can be adjusted by means such as using a function to switch the I/O phase of SI and SO (by using the rise and fall of SCLK). Data Sheet R19DS0008EJ0700 53 MC-10118B (2) Slave mode Parameter Symbol Conditions MIN. TYP. MAX. Unit tC − 50 − − ns tWH − 20 − − ns tWL − 20 − − ns tR − − − 4 ns tF − − − 4 ns tSU0 Rising and falling edges of SP0_CLK 5 − − ns 15 − − ns − 18 ns Common to SP0, SP1, SP2 SPx_CLK input cycle SPx_CLK high-level width SPx_CLK low-level width SPx_CLK rise time SPx_CLK fall time SP0 SP0_CS setup time SP0_CS hold time tH0 SP0_SO delay time Rising and falling edges of SP0_CLK tDO0 Rising and falling edges of SP0_CLK 3 tSU1 Rising and falling edges of SP1_CLK 5 − − ns 15 − − ns 20 ns SP1 SP1_CS setup time SP1_CS hold time tH1 Rising and falling edges of SP1_CLK tDO1 Rising and falling edges of SP1_CLK 3 − SP2_CS setup time tSU2 Rising and falling edges of SP2_CLK 5 − − ns SP2_CS hold time tH2 Rising and falling edges of SP2_CLK 15 − − ns SP2_SO delay time tDO2 Rising and falling edges of SP2_CLK 3 − 18 ns SP1_SO delay time SP2 Figure 2-19. SPI Interface Timing (Slave Mode) tC tWH tR tWL SPx_CLK (input) tSU tH SPx_SI SPx_CSn (input) t DO SPx_SO (output) 54 Data Sheet R19DS0008EJ0700 tF MC-10118B 2.5.12 DTV interface Parameter Symbol Conditions MIN. TYP. MAX. Unit tC − 66 − − ns DTV_BCLK high-level width tWH − 28 − − ns DTV_BCLK low-level width tWL − 28 − − ns DTV_DATA, DTV_PSYNC, DTV_VLD tSU − 12 − − ns tH − 12 − − ns DTV_BCLK input cycle setup time DTV_DATA, DTV_PSYNC, DTV_VLD hold time Figure 2-20. DTV Interface Timing tC tWH tWL DTV_BCLK (input) tSU tH DTV_DATA[7:0] (input) DTV_PSYNC (input) DTV_VLD (input) Data Sheet R19DS0008EJ0700 55 MC-10118B 2.5.13 NAND Flash interface Parameter Symbol Conditions MIN. TYP. MAX. Unit CLE setup time tCLS − tC-3 − 8 tC+3 ns CLE hold time tCLH − tC-3 − 8 tC+3 ns tALS − tC-3 − 8 tC+3 ns tALH − tC-3 − 8 tC+3 ns Write pulse width tWP − tC-3 − 16 tC+3 ns WEZ high-level hold time tWH − tC-3 − 16 tC+3 ns Write data setup time tDS1 Rising edge of NAND_WEZ tWP-3 − tWP+3 ns Write data hold time tDH1 Rising edge of NAND_WEZ tWH-3 − tWH+3 ns ALE setup time ALE hold time Remarks 1. tC = tC (AHB) in the above table 2. The AC characteristics for NAND_WEZ, REZ, CLE, and ALE are determined by a register setting, and the unit is tC (when AHB = 83 MHz with ACPU operating at 500 MHz). Figure 2-21. NAND Flash Interface Timing 1 N AND_CLE (output) tC LS tCLH N AND_ALE (output) tAL S tALH tW P tWP tWP tWH tDS1 tD H1 N AND_WE (output) tDS1 tDH1 tDS1 tD H1 N AND_DA (output) 56 Data Sheet R19DS0008EJ0700 MC-10118B Parameter Symbol Conditions MIN. TYP. MAX. Unit Read pulse width tRP − tC-3 − 16 tC+3 ns High-level hold time tREH − tC-3 − 16 tC+3 ns Read data setup time tDS2 Rising edge of NAND_OE 8 − − ns Read data hold time tDH2 Rising edge of NAND_OE 0 − − ns Remarks 1. tC in the above table = tC when AHB = 83 MHz with ACPU operating at 500 MHz, = 12 ns 2. The AC characteristics for NAND_WE, OE, CLE, and ALE are determined by a register setting, and the unit is tC. 3. The internal bus clock is used for data latching during reading via NAND_DA (input). Figure 2-22. NAND Flash Interface Timing 2 t RP tREH NAND_OE (output) t DS2 t DH2 NAND_DA (input) Data Sheet R19DS0008EJ0700 57 MC-10118B 2.5.14 ITU-R BT.656 interface Parameter Symbol Conditions MIN. TYP. MAX. Unit tC − − 37Note − ns NTSC_CLK high-level width tWH − 13 − − ns NTSC_CLK low-level width tWL − 13 − − ns NTSC_CLK rise time tR − − 5 ns NTSC_CLK fall time tF − − 5 ns NTSC_DATA output delay tD 18 ns NTSC_CLK input cycle Rising edge of NTSC_CLK 4 time Note − NTSC_CLK = 27 MHz Figure 2-23. ITU-R BT.656 Interface Timing tC tWH tR tWL NTS_BCLK（input） tD NTS_DATA[7:0]（ output） NTS_VS (output) NTS_HS（output） 58 Data Sheet R19DS0008EJ0700 tF MC-10118B 2.5.15 MICROWIRE interface Parameter Symbol Conditions MIN. TYP. MAX. Unit tC − 160 − − ns tWH − 72 − − ns tWL − 72 − − ns tR − − − 8 ns MWI_SK clock fall time tF − − − 8 ns MWI_SI setup time tSU Rising edge of MWI_SK 20 − − ns MWI_SI hold time tH Rising edge of MWI_SK 0 − − ns MWI_SO, MWI_CSn output delay tD Rising edge of MWI_SK − − 20 ns MWI_SK clock cycle MWI_SK clock high-level width MWI_SK clock low-level width MWI_SK clock rise time time Figure 2-24. MICROWIRE Interface Timing tC tR tW H tF tWL MWI_SK (output) tSU tH MWI_SI (input) tD MWI_SO (output) MWI_C S0 (output) MWI_C S1 (output) Data Sheet R19DS0008EJ0700 59 MC-10118B 3. PACKAGE DRAWING 60 Data Sheet R19DS0008EJ0700 MC-10118B Revision History Date Revision Comments February 10, 2009 1.0 − April 27, 2009 2.0 Incremental update from comments to the 1.0.. June 30, 2009 3.0 Incremental update from comments to the 2.0. The item of the power supply start-up sequence is added. (chapter 2.5.16) September 30, 2009 4.0 Incremental update from comments to the 3.0. UTEST pins : Handling When Not Used : Leave open -> “L” level hold. Power supply start-up (chapter 2.5.17) sequence is indicated on a user's manual (one chip). December 22, 2009 5.0 Incremental update from comments to the 4.0. The specification of the self refresh current is changed with name of product change (MC-10118A->, MC-10118B). February 15, 2010 6.0 Incremental update from comments to the 5.0. Change in the product name (MC-10118A/B->, MC-10118). A self-refresh electric current was returned to the value of revision 4.0. March 31, 2010 7.0 Order name change (MC-10118AF1-ENY-A -> MC-10118BF1-ENY-A). The specification of the self refresh current is changed with name of product change (MC-10118->, MC-10118B). Data Sheet R19DS0008EJ0700 61 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. 62 Data Sheet S19657EJ6V0DS The names of other companies and products are the registered trademarks or trademarks of these companies. • The information in this document is current as of March, 2010. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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