Micross AS29LV016D Superior inadvertent write protection Datasheet

COTS PEM
BOOT SECTOR FLASH
AS29LV016
16 Megabit (2M x 8-Bit / 1M x 16-Bit)
CMOS 3.0 Volt-Only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
PERFORMANCE CHARACTERISTICS
High performance
— Access times as fast as 70 ns @ Enhanced
Temp [/ET]
Commercial Off The Shelf, up-screened device
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Extended temp range available [/XT] (-55°C to
+125°C)
Manufactured on 200nm process technology
Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
Sector Protection features
— A hardware method of locking a sector to
prevent any program or erase operations within
that sector
— Sectors can be locked in-system or via
programming equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Cycling endurance: 1,000,000 cycles per sector
typical
Data retention: 20 years typical
SOFTWARE FEATURES
CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Top or bottom boot block configurations
available
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
Compatibility with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
PACKAGE OPTIONS
HARDWARE FEATURES
48-pin TSOP1
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program
or erase cycle completion
Hardware reset pin (RESET#)
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
1
COTS PEM
BOOT SECTOR FLASH
AS29LV016
GENERAL DESCRIPTION
The AS29LV016 is a 16 Mbit, 3.0 Volt-only
Flash memory organized as 2,097,152 bytes
or 1,048,576 words. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed
to be programmed in-system with the standard
system 3.0 volt VCC supply. A 12.0 V VPP or 5.0
VCC are not required for write or erase operations.
The device can also be programmed in standard
EPROM programmers.
already programmed) before executing the erase
operation. During erase, the device automatically
times the erase pulse widths and verifies proper
cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/
BY# pin, or by reading the DQ7 (Data# Polling)
and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device
is ready to read array data or accept another
command.
The device offers access times of 70 ns, 90 ns
and 100 ns allowing high speed microprocessors
to operate without wait states. To eliminate bus
contention the device has separate chip enable
(CE#), write enable (WE#) and output enable
(OE#) controls.
The sector erase architecture allows memory
sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The
device is fully erased when shipped from the
factory.
The device requires only a single 3.0 volt
power supply for both read and write functions.
Internally generated and regulated voltages are
provided for the program and erase operations.
Hardware data protection measures include
a low VCC detector that automatically inhibits
write operations during power transitions. The
hardware sector protection feature disables
both program and erase operations in any
combination of the sectors of memory. This
can be achieved in-system or via programming
equipment.
The AS29LV016 is entirely command set compatible
with the JEDEC single-power-supply Flash
standard. Commands are written to the
command register using standard microprocessor
write timings. Register contents serve as input to
an internal state-machine that controls the erase
and programming circuitry. Write cycles also
internally latch addresses and data needed for
the programming and erase operations. Reading
data out of the device is similar to reading from
other Flash or EPROM devices.
The Erase Suspend/Erase Resume feature
enables the user to put erase on hold for any
period of time to read data from, or program data
to, any sector that is not selected for erasure. True
background erase can thus be achieved.
The hardware RESET# pin terminates any
operation in progress and resets the internal state
machine to reading array data. The RESET# pin
may be tied to the system reset circuitry. A system
reset would thus also reset the device, enabling
the system microprocessor to read the boot-up
firmware from the Flash memory.
Device programming occurs by executing the
program command sequence. This initiates the
Embedded Program algorithm—an internal
algorithm that automatically times the program
pulse widths and verifies proper cell margin.
The Unlock Bypass mode facilitates faster
programming times by requiring only two write
cycles to program data instead of four.
The device offers two power-saving features.
When addresses have been stable for a specified
amount of time, the device enters the automatic
sleep mode. The system can also place the device
into the standby mode. Power consumption is
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that
automatically preprograms the array (if it is not
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
2
COTS PEM
BOOT SECTOR FLASH
AS29LV016
PRODUCT SELECTOR GUIDE
70
70
AS29LV016
90
90
100
100
70
90
100
Max OE# access time, nc (tOE)
30
Note: See AC Characteristics on page 29 for full specifications
35
40
Family Part Number
Speed Option
Voltage Range: Vcc = 2.7-3.6V
Max access time, ns (tACC)
Max CE# access time, ns (tCE)
BLOCK DIAGRAM
g
VCC
DQ0–DQ15 (A-1)
RY/BY#
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A19
AS29LV016
Rev. 2.2 01/10
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Micross Components reserves the right to change products or specifications without notice.
3
COTS PEM
BOOT SECTOR FLASH
AS29LV016
PIN CONFIGURATION
A0–A19
=
DQ0–DQ14 =
DQ15/A-1 =
BYTE#
CE#
OE#
WE#
RESET#
RY/BY#
VCC
=
=
=
=
=
=
=
VSS
NC
=
=
LOGIC SYMBOL
20 addresses
15 data inputs/outputs
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
Selects 8-bit or 16-bit mode
Chip enable
Output enable
Write enable
Hardware reset pin
Ready/Busy output
3.0 volt-only single power supply (see
Product Selector Guide for speed
options and voltage supply tolerances)
Device ground
Pin not connected internally
20
A0–A19
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
CONNECTION DIAGRAMS
44 WE#
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
AS29LV016
Rev. 2.2 01/10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Micross Components reserves the right to change products or specifications without notice.
4
COTS PEM
BOOT SECTOR FLASH
AS29LV016
ORDERING INFORMATION
AS29LV016TRG-70/ET
AS29LV016BRG-70/ET
AS29LV016TRG-90/ET
AS29LV016BRG-90/ET
AS29LV016TRG-90/XT
AS29LV016BRG-90/XT
AS29LV016TRG-100/ET
AS29LV016BRG-100/ET
AS29LV016TRG-100/XT
AS29LV016BRG-100/XT
TOP BOOT
BOTTOM BOOT
TOP BOOT
BOTTOM BOOT
TOP BOOT
BOTTOM BOOT
TOP BOOT
BOTTOM BOOT
TOP BOOT
BOTTOM BOOT
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
ENHANCED
ENHANCED
ENHANCED
ENHANCED
EXTENDED
EXTENDED
ENHANCED
ENHANCED
EXTENDED
EXTENDED
PB-FREE OPTION (WHERE AVAILABLE)
AS29LV016TRGR-70/ET TOP BOOT
AS29LV016TRGR-70/ET BOTTOM BOOT
TSOP1-48
TSOP1-48
ENHANCED
ENHANCED
TAPE / REEL OPTION (WHERE AVAILABLE)
.14-14” Reel (32mm TAPE)
.7-7” Reel (32mm TAPE)
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
5
COTS PEM
BOOT SECTOR FLASH
AS29LV016
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal
command register. The command register itself does not occupy any addressable memory location. The register
is com-posed of latches that store the commands, along with the address and data information needed to execute
the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs
dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require,
and the resulting output. The following subsections describe each of these operations in further detail.
Table 1: AS29LV016 Device Bus Operations
CE#
L
OE#
L
WE#
H
RESET#
H
Address1
AIN
Write
Standby
Output Disable
Reset
L
Vcc ± 0.3V
L
X
H
X
H
X
L
X
H
X
H
Vcc ± 0.3V
H
L
AIN
X
X
X
DIN
High-Z
High-Z
High-Z
DIN
High-Z
High-Z
High-Z
Sector Protect2
L
H
L
VID
Sector Address,
A6=L, A1=H, A0=L
DIN
X
X
Sector Unprotect2
L
H
L
VID
DIN
X
X
Temporary Sector Unprotect
X
X
X
VID
Sector Address,
A6=H, A1=H, A0=L
AIN
DIN
DIN
High-Z
Operation
Read
BYTE#
=VIH
DOUT
DQ8-DQ15
BYTE#
=VIL
DQ0DQ7
DOUT
DQ8-DQ14= High Z,
DQ15=A-1
High-Z
High-Z
High-Z
Legend:
L= Logic Low = V IL , H=Logic High=V IH , V ID =12.0±0.5V, X=Don't Care, A IN =Address In, D IN = Data In, D OUT =Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V IH ), A19:A-1 in byte mode (BYTE# = V IL )
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection /
Unprotection on page 11.
WORD / BYTE CONFIGURATION
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are
active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–
DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and
the DQ15 pin is used as an input for the LSB (A-1) address function.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
6
COTS PEM
BOOT SECTOR FLASH
AS29LV016
An erase operation can erase one sector, multiple
sectors, or the entire device. Table 2 on page 9 and
Table 3 on page 10 indicate the address space that
each sector occupies. A “sector address” consists of the
address bits required to uniquely select a sector. The
Command Definitions on page 17 has details on erasing
a sector or the entire chip, or suspending/resuming the
erase operation.
REQUIREMENTS FOR READING
ARRAY DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should
remain at VIH. The BYTE# pin determines whether the
device outputs array data in words or bytes.
After the system writes the autoselect command
sequence, the device enters the autoselect mode.
The system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to Autoselect Mode on page 11 and
Autoselect Command Sequence on page 17 for more
information.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. AC
Characteristics on page 29 contains timing specification
tables and timing diagrams for write operations.
See Reading Array Data on page 17 for more information.
Refer to the AC Read Operations on page 29 for timing
specifications and to Figure 12, on page 29 for the timing
diagram. ICC1 in the DC Characteristics table represents
the active current specification for reading array data.
PROGRAM AND ERASE
OPERATION STATUS
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to Write Operation Status
on page 22 for more information, and to AC Characteristics
on page 29 for timing diagrams.
WRITING COMMANDS / COMMAND
SEQUENCES
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. See Word Byte Configuration on page 6 for
more information.
The device features an Unlock Bypass mode to facilitate
faster programming. Once the device enters the Unlock
Bypass mode, only two write cycles are required to
program a word or byte, instead of four. Word Byte
Program Command Sequence on page 18 has details
on programming data to the device using both standard
and Unlock Bypass command sequences.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
7
COTS PEM
BOOT SECTOR FLASH
AS29LV016
STANDBY MODE
RESET#: HARDWARE RESET PIN
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of
the OE# input.
The RESET# pin provides a hardware method of
resetting the device to reading array data. When the
system drives the RESET# pin to VIL for at least a period
of tRP, the device immediately terminates any operation
in progress, tristates all data output pins, and ignores
all read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine
to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
ICC3 and ICC4 represents the standby current specification
shown in the table in DC Characteristics on page 27.
If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The system
can thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is not executing (RY/BY#
pin is 1), the reset operation is completed within a time
of tREADY (not during Embedded Algorithms). The system
can read data tRH after the RESET# pin returns to VIH.
Refer to the tables in AC Characteristics on page 29 for
RESET# parameters and to Figure 13, on page 30 for
the timing diagram.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30 ns.
The automatic sleep mode is independent of the CE#,
WE#, and OE# control signals. Standard address access
timings provide new data when addresses are changed.
While in sleep mode, output data is latched and always
available to the system. ICC4 in the DC Characteristics on
page 27 represents the automatic sleep mode current
specification.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
8
COTS PEM
BOOT SECTOR FLASH
AS29LV016
OUTPUT DISABLE MODE
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high
impedance state.
Table 2: Sector Address Tables (Top Boot Device)
Sector Size
Address Range (in hexadecimal)
Sector
A19
A18
A17
A16
A15
A14
A13
A12
(Kbytes / Kwords)
Byte Mode (x8)
Word Mode (x16)
SA0
0
0
0
0
0
X
X
X
64/32
000000-00FFFF
00000-07FFF
SA1
0
0
0
0
1
X
X
X
64/32
010000-01FFFF
08000-0FFFF
SA2
0
0
0
1
0
X
X
X
64/32
020000-02FFFF
10000-17FFF
SA3
0
0
0
1
1
X
X
X
64/32
030000-03FFFF
18000-1FFFF
SA4
0
0
1
0
0
X
X
X
64/32
040000-04FFFF
20000-27FFF
SA5
0
0
1
0
1
X
X
X
64/32
050000-05FFFF
28000-2FFFF
SA6
0
0
1
1
0
X
X
X
64/32
060000-06FFFF
30000-37FFF
SA7
0
0
1
1
1
X
X
X
64/32
070000-07FFFF
38000-3FFFF
SA8
0
1
0
0
0
X
X
X
64/32
080000-08FFFF
40000-47FFF
SA9
0
1
0
0
1
X
X
X
64/32
090000-09FFFF
48000-4FFFF
SA10
0
1
0
1
0
X
X
X
64/32
0A0000-0AFFFF
50000-57FFF
SA11
0
1
0
1
1
X
X
X
64/32
0B0000-0BFFFF
58000-5FFFF
SA12
0
1
1
0
0
X
X
X
64/32
0C0000-0CFFFF
60000-67FFF
SA13
0
1
1
0
1
X
X
X
64/32
0D0000-0DFFFF
68000-6FFFF
SA14
0
1
1
1
0
X
X
X
64/32
0E0000-0EFFFF
70000-77FFF
SA15
0
1
1
1
1
X
X
X
64/32
0F0000-0FFFFF
78000-7FFFF
SA16
1
0
0
0
0
X
X
X
64/32
100000-10FFFF
80000-87FFF
SA17
1
0
0
0
1
X
X
X
64/32
110000-11FFFF
88000-8FFFF
SA18
1
0
0
1
0
X
X
X
64/32
120000-12FFFF
90000-97FFF
SA19
1
0
0
1
1
X
X
X
64/32
130000-13FFFF
98000-9FFFF
SA20
1
0
1
0
0
X
X
X
64/32
140000-14FFFF
A0000-A7FFF
SA21
1
0
1
0
1
X
X
X
64/32
150000-15FFFF
A8000-AFFFF
SA22
1
0
1
1
0
X
X
X
64/32
160000-16FFFF
B0000-B7FFF
SA23
1
0
1
1
1
X
X
X
64/32
170000-17FFFF
B8000-BFFFF
SA24
1
1
0
0
0
X
X
X
64/32
180000-18FFFF
C0000-C7FFF
SA25
1
1
0
0
1
X
X
X
64/32
190000-19FFFF
C8000-CFFFF
SA26
1
1
0
1
0
X
X
X
64/32
1A0000-1AFFFF
D0000-D7FFF
SA27
1
1
0
1
1
X
X
X
64/32
1B0000-1BFFFF
D8000-DFFFF
SA28
1
1
1
0
0
X
X
X
64/32
1C0000-1CFFFF
E0000-E7FFF
SA29
1
1
1
0
1
X
X
X
64/32
1D0000-1DFFFF
E8000-EFFFF
SA30
1
1
1
1
0
X
X
X
64/32
1E0000-1EFFFF
F0000-F7FFF
SA31
1
1
1
1
1
0
X
X
32/16
1F0000-1F7FFF
F8000-FBFFF
SA32
1
1
1
1
1
1
0
0
8/4
1F8000-1F9FFF
FC000-FCFFF
SA33
1
1
1
1
1
1
0
1
8/4
1FA000-1FBFFF
FD000-FDFFF
SA34
1
1
1
1
1
1
1
X
16/8
1FC000-1FFFFF
FE000-FFFFF
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See Word/Byte Configuration on page 6.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
9
COTS PEM
BOOT SECTOR FLASH
AS29LV016
Table 3: Sector Address Tables (Bottom Boot Device)
Sector Size
Address Range (in hexadecimal)
Sector
A19
A18
A17
A16
A15
A14
A13
A12
(Kbytes / Kwords)
Byte Mode (x8)
Word Mode (x16)
SA0
0
0
0
0
0
0
0
X
16/8
000000-003FFF
00000-01FFF
SA1
0
0
0
0
0
0
1
0
8/4
004000-005FFF
02000-02FFF
SA2
0
0
0
0
0
0
1
1
8/4
006000-007FFF
03000-03FFF
SA3
0
0
0
0
0
1
X
X
32/16
008000-00FFFF
04000-04FFF
SA4
0
0
0
0
1
X
X
X
64/32
010000-01FFFF
08000-0FFFF
SA5
0
0
0
1
0
X
X
X
64/32
020000-02FFFF
10000-17FFF
SA6
0
0
0
1
1
X
X
X
64/32
030000-03FFFF
18000-1FFFF
SA7
0
0
1
0
0
X
X
X
64/32
040000-04FFFF
20000-27FFF
SA8
0
0
1
0
1
X
X
X
64/32
050000-05FFFF
28000-2FFFF
SA9
0
0
1
1
0
X
X
X
64/32
060000-06FFFF
30000-37FFF
SA10
0
0
1
1
1
X
X
X
64/32
070000-07FFFF
38000-3FFFF
SA11
0
1
0
0
0
X
X
X
64/32
080000-08FFFF
40000-47FFF
SA12
0
1
0
0
1
X
X
X
64/32
090000-09FFFF
48000-4FFFF
SA13
0
1
0
1
0
X
X
X
64/32
0A0000-0AFFFF
50000-57FFF
SA14
0
1
0
1
1
X
X
X
64/32
0B0000-0BFFFF
58000-5FFFF
SA15
0
1
1
0
0
X
X
X
64/32
0C0000-0CFFFF
60000-67FFF
SA16
0
1
1
0
1
X
X
X
64/32
0D0000-0DFFFF
68000-6FFFF
SA17
0
1
1
1
0
X
X
X
64/32
0E0000-0EFFFF
70000-77FFF
SA18
0
1
1
1
1
X
X
X
64/32
0F0000-0FFFFF
78000-7FFFF
SA19
1
0
0
0
0
X
X
X
64/32
100000-10FFFF
80000-87FFF
SA20
1
0
0
0
1
X
X
X
64/32
110000-11FFFF
88000-8FFFF
SA21
1
0
0
1
0
X
X
X
64/32
120000-12FFFF
90000-97FFF
SA22
1
0
0
1
1
X
X
X
64/32
130000-13FFFF
98000-9FFFF
SA23
1
0
1
0
0
X
X
X
64/32
140000-14FFFF
A0000-A7FFF
SA24
1
0
1
0
1
X
X
X
64/32
150000-15FFFF
A8000-AFFFF
SA25
1
0
1
1
0
X
X
X
64/32
160000-16FFFF
B0000-B7FFF
SA26
1
0
1
1
1
X
X
X
64/32
170000-17FFFF
B8000-BFFFF
SA27
1
1
0
0
0
X
X
X
64/32
180000-18FFFF
C0000-C7FFF
SA28
1
1
0
0
1
X
X
X
64/32
190000-19FFFF
C8000-CFFFF
SA29
1
1
0
1
0
X
X
X
64/32
1A0000-1AFFFF
D0000-D7FFF
SA30
1
1
0
1
1
X
X
X
64/32
1B0000-1BFFFF
D8000-DFFFF
SA31
1
1
1
0
0
X
X
X
64/32
1C0000-1CFFFF
E0000-E7FFF
SA32
1
1
1
0
1
X
X
X
64/32
1D0000-1DFFFF
E8000-EFFFF
SA33
1
1
1
1
0
X
X
X
64/32
1E0000-1EFFFF
F0000-F7FFF
SA34
1
1
1
1
1
X
X
X
64/32
1F0000-1FFFFF
F8000-FFFFF
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See Word/Byte Configuration on page 6.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
10
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AUTOSELECT MODE
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits (see Table 2 on page 9 and Table 3 on
page 10). Table 4, immediately below, shows the remaining
address bits that are don’t care. When all necessary bits
have been set as required, the programming equipment
may then read the corresponding identifier code on
DQ7-DQ0.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 9 on page 21. This
method does not require VID. See Command Definitions
on page 17 for details on using the autoselect mode.
Table 4: AS29LV016 Autoselect Codes (High Voltage Method)
Description
Manufacturer ID: Spansion
Device ID: S29AL016D
(Top Boot Block)
Device ID: S29AL016D
(Bottom Boot Block)
Sector Protection Verification
A19 to A11 to
A12
A10
Mode
CE#
OE#
WE#
Word
Byte
Word
Byte
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
L
H
SA
X
A9
A8 to
A7
A6
A5 to
A4
A3 to
A2
A1
A0
VID
X
L
X
L
L
L
VID
X
L
X
L
L
H
VID
X
L
X
L
L
H
VID
X
L
X
L
H
L
DQ8 to
DQ15
DQ7 to DQ0
X
22h
X
22h
X
X
X
01h
C4h
C4h
49h
49h
01h (protected)
00h (unprotected)
L= Logic Low = V IL , H=Logic High=V IH , SA = Sector Address, X=Don't Care
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9 on page 21.
SECTOR PROTECTION / UNPROTECTION
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2, on page 13 shows the
algorithms and Figure 22, on page 36 shows the timing
diagram. This method uses standard microprocessor
bus cycle timing. For sector unprotect, all unprotected
sectors must first be protected prior to the first sector
unprotect write cycle.
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See Autoselect Mode above for details.
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
Sector protection/unprotection can be implemented via
two methods.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
11
COTS PEM
BOOT SECTOR FLASH
AS29LV016
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can
be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the
previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 21, on page 35 shows
the timing diagrams, for this feature.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1.
AS29LV016
Rev. 2.2 01/10
Temporary Sector Unprotect Operation
Micross Components reserves the right to change products or specifications without notice.
12
COTS PEM
BOOT SECTOR FLASH
AS29LV016
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 μs
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 μs
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 μs
Increment
PLSCNT
No
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Reset
PLSCNT = 1
Wait 15 ms
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Yes
Yes
No
Yes
Device failed
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
PLSCNT
= 1000?
Protect another
sector?
No
No
Data = 00h?
Yes
Yes
Remove VID
from RESET#
Device failed
Last sector
verified?
Write reset
command
Sector Protect
Algorithm
Set up
next sector
address
No
Yes
Sector Unprotect
Algorithm
Sector Protect
complete
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Figure 2.
AS29LV016
Rev. 2.2 01/10
In-System Sector Protect/Unprotect Algorithms
Micross Components reserves the right to change products or specifications without notice.
13
COTS PEM
BOOT SECTOR FLASH
AS29LV016
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms
to be used for entire families of devices. Software
support can then be device-independent, JEDEC IDindependent, and forward- and backward-compatible
for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term
compatibility.
The system can also write the CFI query command when
the device is in the autoselect mode. The device enters
the CFI query mode, and the system can read CFI data
at the addresses given in Tables 5–8. The system must
write the reset command to return the device to the
autoselect mode.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h in
word mode (or address AAh in byte mode), any time the
device is ready to read array data. The system can read
CFI information at the addresses given in Tables 5–8.
In word mode, the upper address bits (A7–MSB) must
be all zeros. To terminate reading CFI data, the system
must write the reset command.
Table 5: CFI Query Identification String
Addresses
(Word Mode)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
AS29LV016
Rev. 2.2 01/10
Addresses
(Byte Mode)
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
Data
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Description
Query Unique ASCII String "QRY"
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h=none exists)
Address for Alternate OEM Extended Table (00h=none exists)
Micross Components reserves the right to change products or specifications without notice.
14
COTS PEM
BOOT SECTOR FLASH
AS29LV016
Table 6: System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
1Bh
36h
0027h
VCC Min. (write/erase) D7-D4:volt, D3-D0L 100 millivolt
1Ch
38h
0036h
VCC Max. (write/erase) D7-D4:volt, D3-D0L 100 millivolt
1Dh
3Ah
0000h
VPP Min. voltage (00h=no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h=no VPP pin present)
1Fh
3Eh
0004h
Typical timeout per single byte/word write 2N μs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N μs (00h=not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h=not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h=not supported)
Description
Table 7: Device Geometry Definition
Addresses
(Word Mode)
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
AS29LV016
Rev. 2.2 01/10
Addresses
(Byte Mode)
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
Data
0015h
0002h
0000h
0000h
0000h
0004h
0000h
0000h
0040h
0000h
0001h
0000h
0020h
0000h
0000h
0000h
0080h
0000h
001Eh
0000h
0000h
0001h
Description
Device Size = 2N Byte
Flash Device Interface description (refer to CFI publication 100)
Max. number of byte in multi-byte write = 2N (00h= not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Micross Components reserves the right to change products or specifications without notice.
15
COTS PEM
BOOT SECTOR FLASH
AS29LV016
Table 8: Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
40h
41h
42h
43h
44h
Addresses
(Byte Mode)
80h
82h
84h
86h
88h
Data
0050h
0052h
0049h
0031h
0030h
45h
8Ah
0000h
46h
8Ch
0002h
47h
8Eh
0001h
48h
90h
0001h
49h
92h
0004h
4Ah
94h
0000h
4Bh
96h
0000h
4Ch
98h
0000h
Description
Query-unique ASCII string "PRI"
Major version number, ASCII
Major version number, ASCII
Address Sensitive Unlock
0=Required, 1=Not Required
Erase Suspend
0=Not Supported, 1=To Read Only, 2=To Read and Write
Sector Protect
0=Not Supported, X=Number of Sectors Per Group
Sector Temorary Unprotect
00=Not Supported, 01=Supported
Sector Protect / Unprotect Scheme
01=29F040 mode, 02=29F016 mode,
03=29F400 mode, 04=29LV800A mode
Simultaneous Operation
00=Not Supported, 01=Supported
Burst Mode Type
00=Not Supported, 01= Supported
Page Mode Type
00=Not Supported, 01=4 Word Page, 02= 8 Word Page
HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 9 on page 21 for
command definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
LOGICAL INHIBIT
Write cycles are inhibited by holding any one of OE#
= VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device
resets. Subsequent writes are ignored until VCC is greater
than VLKO. The system must provide the proper signals
to the control pins to prevent unintentional writes when
VCC is greater than VLKO.
AS29LV016
Rev. 2.2 01/10
POWER-UP WRITE INHIBIT
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to reading array data on power-up.
Micross Components reserves the right to change products or specifications without notice.
16
COTS PEM
BOOT SECTOR FLASH
AS29LV016
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 9 on page 21 defines the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence
resets the device to reading array data.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in Erase
Suspend mode). Once programming begins, however,
the device ignores reset commands until the operation
is complete.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched
on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in AC
Characteristics on page 29.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
READING ARRAY DATA
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading
array data (also applies during Erase Suspend).
AUTOSELECT COMMAND SEQUENCE
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The system
can read array data using the standard read timings,
except that if it reads at an address within erasesuspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See Erase Suspend/Erase
Resume Commands on page 20 for more information
on this mode.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 9 on page 21 shows the address and data
requirements. This method is an alternative to that shown
in Table 4 on page 11, which is intended for PROM
programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing
two unlock cycles, followed by the autoselect command.
The device then enters the autoselect mode, and the
system may read at any address any number of times,
without initiating another command sequence.
The system must issue the reset command to re-enable
the device for reading array data if DQ5 goes high, or
while in the autoselect mode. See Reset Command,
next.
A read cycle at address XX00h retrieves the manufacturer
code. A read cycle at address XX01h returns the device
code. A read cycle containing a sector address (SA) and
the address 02h in word mode (or 04h in byte mode)
returns 01h if that sector is protected, or 00h if it is
unprotected. Refer to Table 2 on page 9 and Table 3 on
page 10 for valid sector addresses.
See also Requirements for Reading Array Data on
page 7 for more information. The Read Operations on
page 29 provides the read parameters, and Figure 12,
on page 29 shows the timing diagram.
RESET COMMAND
The system must write the reset command to exit the
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the
sequence cycles in an erase command sequence before
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
17
COTS PEM
BOOT SECTOR FLASH
AS29LV016
WORD/BYTE PROGRAM COMMAND
SEQUENCE
This mode dispenses with the initial two unlock cycles
required in the standard program command sequence,
resulting in faster total programming time. Table 9 on
page 21 shows the requirements for the command
sequence.
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Programming
is a four-bus-cycle operation. The program command
sequence is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 9 on page 21 shows
the address and data requirements for the byte program
command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid.
To exit the unlock bypass mode, the system must issue
the two-cycle unlock bypass reset command sequence.
The first cycle must contain the data 90h; the second
cycle the data 00h. Addresses are don’t care for both
cycles. The device then returns to reading array data.
Figure 3 illustrates the algorithm for the program
operation. See Erase / Program Operations on page 32
for parameters, and to Figure 16, on page 33 for timing
diagrams.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using DQ7, DQ6, or
RY/BY#. See Write Operation Status on page 22 for
information on these status bits.
START
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Byte Program command sequence should
be reinitiated once the device has reset to reading array
data, to ensure data integrity.
Write Program
Command Sequence
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
0 back to a 1. Attempting to do so may halt the operation
and set DQ5 to 1, or cause the Data# Polling algorithm
to indicate the operation was successful. However, a
succeeding read will show that the data is still 0. Only
erase operations can convert a 0 to a 1.
Verify Data?
No
Yes
UNLOCK BYPASS COMMAND SEQUENCE
Increment Address
The unlock bypass feature allows the system to program
bytes or words to the device faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that is required
to program in this mode. The first cycle in this sequence
contains the unlock bypass program command, A0h; the
second cycle contains the program address and data.
Additional data is programmed in the same manner.
AS29LV016
Rev. 2.2 01/10
Data Poll
from System
Embedded
Program
algorithm
in progress
No
Last Address?
Yes
Programming
Completed
Note: See Table 9 on page 21 for program command
sequence.
Figure 3. Program Operation
Micross Components reserves the right to change products or specifications without notice.
18
COTS PEM
BOOT SECTOR FLASH
AS29LV016
CHIP ERASE COMMAND SEQUENCE
After the command sequence is written, a sector erase
time-out of 50 μs begins. During the time-out period,
additional sector addresses and sector erase commands
may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may
be from one sector to all sectors. The time between these
additional cycles must be less than 50 μs, otherwise the
last address and command might not be accepted, and
erasure may begin. It is recommended that processor
interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be reenabled after the last Sector Erase command is written.
If the time between additional sector erase commands
can be assumed to be less than 50 μs, the system need
not monitor DQ3. Any command other than Sector
Erase or Erase Suspend during the time-out period
resets the device to reading array data. The system
must rewrite the command sequence and any additional
sector addresses and commands.
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system
to preprogram prior to erase. The Embedded Erase
algorithm automatically preprograms and verifies the
entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide
any controls or timings during these operations. Table 9
on page 21 shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates
the operation. The Chip Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See DQ3: Sector Erase Timer
on page 25.) The time-out begins from the rising edge of
the final WE# pulse in the command sequence.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
Write Operation Status on page 22 for information on
these status bits. When the Embedded Erase algorithm
is complete, the device returns to reading array data and
addresses are no longer latched.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 4, on page 20 illustrates the algorithm for the
erase operation. See Erase / Program Operations on
page 32 for parameters, and Figure 17, on page 33 for
timing diagrams.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/
BY#. (Refer to Write Operation Status on page 22 for
information on these status bits.)
SECTOR ERASE COMMAND SEQUENCE
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
addi-tional unlock write cycles are then followed by
the address of the sector to be erased, and the sector
erase command. Table 9 on page 21 shows the address
and data requirements for the sector erase command
sequence.
Figure 4 illustrates the algorithm for the erase operation.
Refer to Erase / Program Operations on page32 for
parameters, and to Figure 17, on page 33 for timing
diagrams.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase
algorithm automatically programs and verifies the sector
for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
19
COTS PEM
BOOT SECTOR FLASH
AS29LV016
ERASE SUSPEND / ERASE RESUME
COMMANDS
The system must write the Erase Resume command
(address bits are don’t care) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device
has resumed erasing.
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 μs time-out period
during the sector erase command sequence. The Erase
Suspend command is ignored if written during the chip
erase operation or Embedded Program algorithm. Writing
the Erase Suspend command during the Sector Erase
time-out immediately terminates the time-out period and
suspends the erase operation. Addresses are don’t-cares
when writing the Erase Suspend command.
START
Write Erase
Command Sequence
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 μs to suspend the erase operation. However, when
the Erase Suspend command is written during the sector
erase time-out, the device immediately terminates the
time-out period and suspends the erase operation.
Data Poll
from System
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sectors
produces status data on DQ7–DQ0. The system can
use DQ7, or DQ6 and DQ2 together, to determine if a
sector is actively erasing or is erase-suspended. See
Write Operation Status on page 22 for information on
these status bits.
No
Data = FFh?
Yes
Erasure Completed
After an erase-suspended program operation is complete,
the system can once again read array data within nonsuspended sectors. The system can determine the status
of the program operation using the DQ7 or DQ6 status
bits, just as in the standard program operation. See Write
Operation Status on page 22 for more information.
Notes:
1. See Table 9 on page 21 for erase command
sequence.
2. See DQ3: Sector Erase Timer on page 25 for more
information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes even
at addresses within erasing sectors, since the codes are
not stored in the memory array. When the device exits
the autoselect mode, the device reverts to the Erase
Suspend mode, and is ready for another valid operation.
See Autoselect Command Sequence on page 17 for
more information.
AS29LV016
Rev. 2.2 01/10
Embedded
Erase
algorithm
in progress
Figure 4. Erase Operation
Micross Components reserves the right to change products or specifications without notice.
20
COTS PEM
BOOT SECTOR FLASH
AS29LV016
Cycles
TABLE 9: COMMAND DEFINITIONS
Command Sequence1
Read6
Reset7
1
1
Autoselect8
Manufacturer ID
Device ID,
Top Boot Block
Device ID,
Bottom Boot Block
Word
Byte
Word
Byte
Word
Byte
4
4
4
555
Word
Sector Protect Verify9
Program
Unlock Bypass
Unlock Bypass Program11
Unlock Bypass Reset12
Chip Erase
Sector Erase
Erase Suspend13
Erase Resume14
Word
Byte
Word
Byte
Word
Byte
4
3
2
2
Word
Byte
Word
Byte
6
6
1
1
Bus Cycles2-5
Third
Fourth
Addr
Data
Addr
Data
2AA
555
2AA
555
2AA
555
555
AAA
555
AAA
555
AAA
55
AA
555
AAA
555
AAA
XXX
XXX
555
AAA
555
AAA
XXX
XXX
55
55
55
2AA
AAA
1
Second
Addr
Data
AA
4
Byte
CFI Query10
First
Addr
Data
RA
RD
XXX
F0
555
AA
AAA
555
AA
AAA
555
AA
AAA
90
90
90
555
55
555
90
AAA
X00
01
X01
X02
X01
X02
(SA)
X02
(SA)
X04
22C4
C4
2249
49
XX00
XX01
00
01
PA
PD
Fifth
Addr
Data
Sixth
Addr
Data
2AA
555
2AA
555
55
555
AAA
10
55
SA
30
98
AA
AA
A0
90
AA
AA
2AA
555
2AA
555
PA
XXX
2AA
555
2AA
555
55
55
555
AAA
555
AAA
A0
20
PD
F0
55
55
555
AAA
555
AAA
80
80
555
AAA
555
AAA
AA
AA
B0
30
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while
device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information.
10. Command is valid when device is ready to read array data or when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0
is also acceptable.
13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase operation.
14. The Erase Resume command is valid only during the Erase Suspend mode.
AS29LV016
Rev. 2.2 01/10
the
Micross Components reserves the right to change products or specifications without notice.
21
COTS PEM
BOOT SECTOR FLASH
AS29LV016
WRITE OPERATION STATUS
The device provides several bits to determine the status
of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/
BY#. Table 10 on page 25 and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
When the system detects DQ7 has changed from
the complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is because
DQ7 may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 18, on
page 34, illustrates this.
Table 10 on page 25 shows the outputs for Data#
Polling on DQ7. Figure 5 below shows the Data# Polling
algorithm.
DQ7: DATA# POLLING
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final WE#
pulse in the program or erase command sequence.
START
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed
to DQ7. This DQ7 status also applies to programming
during Erase Suspend. When the Embedded Program
algorithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the
program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data#
Polling on DQ7 is active for approximately 1 μs, then the
device returns to reading array data.
DQ7 = Data?
No
No
During the Embedded Erase algorithm, Data# Polling
produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a 1 on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to 1; prior
to this, the device outputs the complement, or 0. The
system must provide an address within any of the sectors
selected for erasure to read valid status information on
DQ7.
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data# Polling on
DQ7 is active for approximately 100 μs, then the device
returns to reading array data. If not all selected sectors
are protected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within
any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because
DQ7 may change simultaneously with DQ5.
Figure 5.
AS29LV016
Rev. 2.2 01/10
Yes
Data# Polling Algorithm
Micross Components reserves the right to change products or specifications without notice.
22
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BOOT SECTOR FLASH
AS29LV016
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
RY/BY#: READY/BUSY#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress
or complete. The RY/BY# status is valid after the rising
edge of the final WE# pulse in the command sequence.
Since RY/BY# is an open-drain output, several RY/
BY# pins can be tied together in parallel with a pull-up
resistor to VCC.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program
algorithm is complete.
Table 10 on page 25 shows the outputs for Toggle Bit
I on DQ6. Figure 6, on page 24 shows the toggle bit
algorithm in flowchart form, and Reading Toggle Bits
DQ6/DQ2 on page 24 explains the algorithm. Figure 19,
on page 34 shows the toggle bit timing diagrams. Figure
20, on page 5 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on DQ2:
Toggle Bit II below.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device
is ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.
Table 10 on page 25 shows the outputs for RY/BY#.
Figures: Figure 12, on page 29, Figure 13, on page 30,
Figure 16, on page 33 and Figure 17, on page 33 shows
RY/BY# for read, reset, program, and erase operations,
respectively.
DQ2: TOGGLE BIT II
The “Toggle Bit II” on DQ2, when used with DQ6,
indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II
is valid after the rising edge of the final WE# pulse in the
command sequence.
DQ6: TOGGLE BIT I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and
is valid after the rising edge of the final WE# pulse in
the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
DQ2 toggles when the system reads at addresses within
those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status
bits are required for sector and mode information. Refer
to Table 10 on page 25 to compare outputs for DQ2 and
DQ6.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for
approximately 100 μs, then returns to reading array data.
If not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
Figure 6, on page 24 shows the toggle bit algorithm
in flowchart form, and the section Reading Toggle Bits
DQ6/DQ2 on page 24 explains the algorithm. See also
the DQ6: Toggle Bit I subsection. Figure 19, on page
34 shows the toggle bit timing diagram. Figure 20, on
page 35 shows the differences between DQ2 and DQ6
in graphical form.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling on
page 22).
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
23
COTS PEM
BOOT SECTOR FLASH
AS29LV016
READING TOGGLE BITS DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after
the first read. After the second read, the system would
compare the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read
array data on DQ7–DQ0 on the following read cycle.
START
Read DQ7–DQ0
Read DQ7–DQ0
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see
the section on DQ5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as DQ5
went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete
the operation successfully, and the system must write the
reset command to return to reading array data.
Toggle Bit
= Toggle?
(Note 1)
No
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).
Toggle Bit
= Toggle?
(Notes
1,2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it
is toggling. See text.
2. Recheck toggle bit because it may stop toggling as
DQ5 changes to 1. See text.
Figure 6.
AS29LV016
Rev. 2.2 01/10
Toggle Bit Algorithm
Micross Components reserves the right to change products or specifications without notice.
24
COTS PEM
BOOT SECTOR FLASH
AS29LV016
After the sector erase command sequence is written, the
system should read the status on DQ7 (Data# Polling)
or DQ6 (Toggle Bit I) to ensure the device has accepted
the command sequence, and then read DQ3. If DQ3 is 1,
the internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is 0, the device
will accept additional sector erase commands. To ensure
the command has been accepted, the system software
should check the status of DQ3 prior to and following
each subsequent sector erase command. If DQ3 is high
on the second status check, the last command might
not have been accepted. Table 10 shows the outputs
for DQ3.
DQ5: EXCEEDED TIMING LIMITS
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a 1. This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a 1 to a location that is previously
programmed to 0. Only an erase operation can change
a 0 back to a 1. Under this condition, the device halts
the operation, and when the operation has exceeded the
timing limits, DQ5 produces a 1.
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: SECTOR ERASE TIMER
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from 0 to 1.
The system may ignore DQ3 if the system can guarantee
that the time between additional sector erase commands
will always be less than 50 μs. See also the Sector Erase
Command Sequence section on page 19.
Table 10: Write Operation Status
Operation
Standard Embedded Program Algorithm
Mode Embedded Erase Algorithm
Reading within Erase
Erase Suspended Sector
Suspend Reading within Non-Erase
Mode Suspended Sector
Erase-Suspend-Program
DQ72
DQ7#
0
DQ6
Toggle
Toggle
DQ11
0
0
DQ3
N/A
1
DQ22
RY/BY#
No Toggle
0
Toggle
0
1
No Toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Notes:
1. DQ5 switches to 1 when and Embedded Program or Embedded Erase operation has exceeded the maximum
timing limits. See DQ5: Exceeded Timing Limits for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection
for further details.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
25
COTS PEM
BOOT SECTOR FLASH
AS29LV016
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
A9, OE#, and RESET#2. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V
All other pins1 . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to VCC+0.5 V
Output Short Circuit Current3 . . . . . . . . . . . . . . . . . . . ................... . . . . . . . . . . . . . . . . . . .200 mA
Notes:
1.Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot
VSS to –2.0 V for periods of up to 20 ns. See Figure 7 below. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.
See Figure 8 below.
2.Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7 below. Maximum DC input
voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any other conditions above those indicated
in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Enhanced (/ET) Devices
Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . .. .-40°C to +105°C
Extended (/XT) Devices
Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . .. . . . . .-55°C to +125°C
VCC Supply Voltages
VCC for standard voltage range. . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
20 ns
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
+0.8 V
–0.5 V
–2.0 V
2.0 V
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
Figure 7. Maximum Negative
Overshoot Waveform
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
26
COTS PEM
BOOT SECTOR FLASH
AS29LV016
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
ILI
Input Load Current
Test Conditions
VIN=VSS to VCC, VCC=VCCmax
ILIT
A9 Input Load Current
VCC=VCCmax; A9=12.5V
ILO
Output Leakage Current
VOUT=VSS to VCC, VCC=VCCmax
VCC Active Write Current 2,3,5
2,4
ICC3
VCC Standby Current
ICC4
VCC Standby Current During Reset 2,4
ICC5
Automatic Sleep Mode 2,4,6
Input Low Voltage
VIL
VIH
VID
VOL
VOH1
VOH2
VLKO
Input High Voltage
Voltage for Autoselect and Temporary
Sector Unprotect
Output Low Voltage
Output High Voltage
Max
Unit
±1.0
35
μA
±1.0
CE#=VIL, OE#=VIH
CE#, RESET#=VCC ±0.3V
0.2
RESET#=VSS ±0.3V
VIH=VCC ±0.3V; VIL=VSS ±0.3V
0.2
VCC Active Read Current 1,2
CE#=VIL, OE#-VIH, Word Mode
ICC2
Typ
15
9
2
18
9
2
20
CE#=VIL, OE#-VIH, Byte Mode
ICC1
Min
10 MHz
5 MHz
1 MHz
10 MHz
5 MHz
1 MHz
VCC=3.3V
IOH=-100 μA, VCC=VCCmin
Low VCC Lock-Out Voltage
mA
5
μA
mA
μA
0.2
μA
-0.5
0.7 x VCC
0.8
VCC + 0.3
11.5
12.5
IOL=4.0 mA, VCC=VCCmin
IOH=-2.0 mA, VCC=VCCmin
30
16
4
35
16
4
35
0.45
V
2.4
VCC-0.4
2.3
2.5
Notes:
1.The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2.Maximum ICC specifications are tested with VCC = VCCmax.
3.ICC active while Embedded Erase or Embedded Program is in progress.
4.At extended temperature range (>+85°C), typical current is 5 μA and maximum current is 10 μA.
5.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
6.Not 100% tested.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
27
COTS PEM
BOOT SECTOR FLASH
AS29LV016
TEST CONDITIONS
3.3 V
2.7 k:
Device
Under
Test
CL
6.2 k:
Note: Diodes are IN3064 or equivalent
Figure 10.
Test Setup
Table 11: Test Specifications
Test Condition
Output Load
Output Load Capacitance, CL (including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
70
30
90
100
1 TTL gate
100
100
5
0.0 or VCC
Input timing measurement reference levels
0.5 VCC
Output timing meausrement reference levels
0.5 VCC
Unit
pF
ns
V
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
VCC
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
0.5 VCC
Measurement Level
0.5 VCC
Output
0.0 V
Figure 11.
AS29LV016
Rev. 2.2 01/10
Input Waveforms and Measurement Levels
Micross Components reserves the right to change products or specifications without notice.
28
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AC CHARACTERISTICS
Read Operations
Parameter
JEDEC
Std
tRC
tAVAV
tAVQV
Description
Read Cycle Time
Test Setup
1
tACC
Address to Output Delay
CE#=VIL,
OE#=VIL
OE#=VIL
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
tEHQZ
tDF
tGHQZ
tDF
70
Speed Options
90
100
Min
70
90
100
Max
70
90
100
Max
70
90
100
Max
30
35
40
Chip Enable to Ouput High Z
Max
25
30
35
Output Enable to Output High Z1
Max
25
30
35
tSR/W
Latency Between Read and Write Operations
Min
20
tOEH
Output Enable
Hold Time1
Read
Min
0
Toggle and Data# Polling
Min
10
tOH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First1
Min
0
tAXQX
1
Unit
ns
Notes:
1. Not 100% Tested
2. See Figure 10, on page 28 and Table 11 on page 28 for test specifications.
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tSR/W
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 12.
Read Operations Timings
S29LV016
Rev.1.0 05/06
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
29
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC Std
tREADY
tREADY
tRP
Description
RESET# Pin Low (During Embedded Algorithms)
to Read or Write 1
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write 1
RESET# Pulse Width
tRPD
RESET# High Time Before Read1
RESET# Low to Standby Mode
tRB
RY/BY# Recovery Time
tRH
Test Setup All Speed Options
Max
20
Max
500
500
Unit
μs
ns
50
Min
20
μs
0
ns
Note:
1. Not 100% Tested
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 13.
AS29LV016
Rev. 2.2 01/10
RESET# Timings
Micross Components reserves the right to change products or specifications without notice.
30
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AC CHARACTERISTICS
Word / Byte Configuration (BYTE#)
Parameter
Description
JEDEC
Std
tELFL / tELFH CE# to BYTE# Switching Low or High
tFLQZ
BYTE# Switching Low to Output HIGH Z
tFHQV
BYTE# Switching High to Output Active
Test Setup
Max
Max
Min
70
Speed Options
90
100
5
25
70
30
90
35
100
Unit
ns
OE#
BYTE#
BYTE#
Switching
from word
to byte
mode
DQ0–DQ14
tELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Figure 14.
AS29LV016
Rev. 2.2 01/10
BYTE# Timings for Read Operations
Micross Components reserves the right to change products or specifications without notice.
31
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AC CHARACTERISTICS
CE#
The falling edge of the last W
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 15.
BYTE# Timings for Write Operations
Erase / Program Operations
Speed Options
Parameter
JEDEC
tAVAV
Std
tWC
Description
tAVWL
tAS
Write Cycle Time1
Address Setup Time
tWLAX
tAH
Address Hold Time
tDVWH
tDS
Data Setup Time
tWHDX
tDH
Data Hold Time
tOES
Output Enagle Setup Time
Test Setup
70
70
90
90
0
35
45
0
tELWL
tCS
tCH
CE# Hold Time
0
tWLWH
tWP
Write Pulse Width
35
tWPH
Write Pulse Width High
30
tSR/W
Latency Between Read and Write Operations
tWHWL
tWHWH1
tWHWH1
Programming Operation2
tWHWH2
tWHWH2
Sector Erase Operation2
VCC Setup Time1
Recovery Time from RY / BY#
tVCS
tRB
tBUSY
55
0
Min
tWHEH
tGHWL
Unit
45
Read Recovery Time Before Write,
(OE# High to WE# Low)
CE# Setup Time
tGHWL
100
100
0
ns
0
20
5
Byte
Word
Typ
Min
Program / Erase Valid to RY / BY# Delay
Max
7
μs
0.7
sec
50
μs
0
90
ns
Notes:
1. Not 100% Tested.
2. See Erase and Programming Performance on page 38 for more information.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
32
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
Read Status Data (last two cycles)
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
DOUT
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 16.
Program Operation Timings
Erase Command Sequence (last two cycles)
tWC
2AAh
Addresses
Read Status Data
tAS
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on
page 31).
2. Illustration shows device in word mode.
1.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page
Figure 17. Chip/Sector Erase Operation Timings
22).
2.Illustration shows device in word mode.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
33
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and
array data read cycle.
Figure 18.
Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 19.
AS29LV016
Rev. 2.2 01/10
Toggle Bit Timings (During Embedded Algorithms)
Micross Components reserves the right to change products or specifications without notice.
34
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
WE#
Enter Erase
Suspend Program
Erase
Erase Suspend
Read
Erase
Complete
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 20.
DQ2 vs. DQ6 for Erase and Erase Suspend Operations
Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
tRSP
Description
VID Rise and Fall Time1
RESET# Setup Time for Temporary Sector Unprotect
Test Setup
Min
All Speed Options
500
Unit
ns
Min
4
μs
Note:
1. Not 100% Tested.
RESET#
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 21.
AS29LV016
Rev. 2.2 01/10
Temporary Sector Unprotect/Timing Diagram
Micross Components reserves the right to change products or specifications without notice.
35
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Protect/Unprotect
Data
60h
Valid*
Verify
60h
40h
Status
Sector Protect: 150 μs
Sector Unprotect: 15 ms
1 μs
CE#
WE#
OE#
Note:
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22.
Sector Protect/Unprotect Timing Diagram
Alternate CE# Controlled Erase / Program Operations
Parameter
JEDEC
Std
tWC
tAVAV
Description
Test Setup
70
70
Speed Options
90
100
90
100
0
tAVEL
tAS
Write Cycle Time1
Address Setup Time
tELAX
tAH
Address Hold Time
45
45
55
tDVEH
tDS
Data Setup Time
35
55
tEHDX
tDH
Data Hold Time
45
0
tOES
tWLEL
tWS
Output Enagle Setup Time
Read Recovery Time Before Write,
(OE# High to OE# Low)
WE# Setup Time
tEHWH
tWH
WE# Hold Time
tELEH
tCP
CE# Pulse Width
tEHEL
tCPH
CE# Pulse Width High
tSR/W
Latency Between Read and Write Operations
tGHEL
tWHWH1
tWHWH2
tGHEL
tWHWH1
Programming Operation2
tWHWH2
Sector Erase Operation2
Unit
0
Min
ns
0
0
0
35
35
30
40
20
Byte
Word
Typ
5
7
0.7
μs
sec
Notes:
1. Not 100% Tested.
2. See Erase and Programming Performance on page 38 for more information.
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
36
COTS PEM
BOOT SECTOR FLASH
AS29LV016
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data
written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
Figure 23.
AS29LV016
Rev. 2.2 01/10
Alternate CE# Controlled Write Operation Timings
Micross Components reserves the right to change products or specifications without notice.
37
COTS PEM
BOOT SECTOR FLASH
AS29LV016
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Chip Erase Time
Byte Programming Time
Word Programming Time
Chip Programming Time3
Byte Mode
Word Mode
Typ1
0.7
25
7
7
11
7.2
Max2
10
210
210
33
21.6
Unit
s
s
μs
μs
s
s
Comments
Excludes 00h programming
prior to erasure4
Excludes system level
overhead5
Notes:
1.Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern.
2.Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3.The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program
faster than the maximum program times listed.
4.In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 9
on page 21 for further information on command definitions.
6.The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.
TSOP, SO AND BGA PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Package
Typ
Max
Unit
CIN
Input Capacitance
VIN=0
TSOP, SO
6
7.5
pF
COUT
Output Capacitance
VOUT=0
TSOP, SO
8.5
12
pF
CIN2
Control Pin Capacitance
VIN=0
TSOP, SO
7.5
9
pF
Notes:
1. Samples, not 100% tested.
2. Test conditions T A =25 o C, f=1.0 MHz
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
38
COTS PEM
BOOT SECTOR FLASH
AS29LV016
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOP
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
2X
2
0.10
0.10
1
A2
N
SEE DETAIL B
A
REVERSE PIN OUT (TOP VIEW)
3
B
1
N
E 5
N
+1
2
N
2
D1
0.25
9
A1
4
D
2X (N/2 TIPS)
e
5
C
SEATING
PLANE
B
A
B
N
+1
2
N
2
SEE DETAIL A
0.08MM
(0.0031")
b
M
C A-B S
6
7
WITH PLATING
7
(c)
c1
b1
SECTION B-B
BASE METAL
R
(c)
e/2
GAUGE PLANE
θ°
PARALLEL TO
SEATING PLANE
0.25MM (0.0098") BSC
X
C
L
X = A OR B
DETAIL A
DETAIL B
NOTES:
Jedec
Symbol
A
A1
A2
b1
b
c1
c
D
D1
E
e
L
0
R
N
MO-142 (D) DD
MIN
MAX
1.20
0.15
0.05
1.05
0.95
1.00
0.20
0.23
0.17
0.27
0.22
0.17
0.16
0.10
0.21
0.10
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
0.50 BASIC
0.70
0.50
0.60
8˚
0˚
0.20
0.08
48
NOM
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
2
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
3
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
4
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
5
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
6
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
8
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
9
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3355 \ 16 038 10
AS29LV016
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
39
COTS PEM
BOOT SECTOR FLASH
AS29LV016
DOCUMENT TITLE
16 Megabit (2M x 8-Bit / 1M x 16-Bit), CMOS 3.0 Volt-Only Boot Sector Flash Memory
REVISION HISTORY
Rev #
2.1
2.2
AS29LV016
Rev. 2.2 01/10
History
Added Pb-Free & Tape & Reel Option
Added Micross information
Release Date
October 2008
January 2010
Status
Release
Release
Micross Components reserves the right to change products or specifications without notice.
40