LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 Low Power, Low Noise, IF and Baseband, Dual 16 bit ADC Driver With Digitally Controlled Gain Check for Samples: LMH6517 FEATURES DESCRIPTION • • • • • • • • • The LMH6517 contains two high performance, digitally controlled variable gain amplifiers (DVGA). It has been designed for use in narrowband and broadband IF sampling applications. Typically the LMH6517 drives a high performance ADC in a broad range of mixed signal and digital communication applications such as mobile radio and cellular base stations where automatic gain control (AGC) is required to increase system dynamic range. 1 2 • • Accurate, 0.5dB Gain Steps 200Ω Resistive, Differential Input Low Impedance, Differential Output Disable Function for Each Channel Parallel Gain Control SPI Compatible Serial Bus Two Wire, Pulse Mode Control On Chip Register Stores Gain Setting Low Sensitivity of Linearity and Phase to Gain Setting Single 5V Supply Voltage Small Footprint WQFN Package The LMH6517 digitally controlled attenuator provides precise 0.5dB gain steps over a 31.5dB range. On chip digital latches are provided for local storage of the gain setting. Both serial and parallel programming options are provided. A Pulse mode is also offered where simple up or down commands can change the gain one step at a time. APPLICATIONS • • • • • Cellular Base Stations IF Sampling Receivers Instrumentation Modems Imaging The output amplifier has a differential output allowing large signal swings on a single 5V supply. The low impedance output provides maximum flexibility when driving filters or analog to digital converters. KEY SPECIFICATIONS • • • • • • Each channel of LMH6517 has an independent, digitally controlled attenuator and a high linearity, differential output amplifier. Each block has been optimized for low distortion and maximum system design flexibility. Each channel can be individually disabled for power savings. OIP3: 43dBm @ 200MHz Noise figure 5.5dB Gain step size of 0.5dB Gain step accuracy: 0.05dB Frequency Range of 1200 MHz Supply current 80mA per channel The LMH6517 operates over the industrial temperature range of −40°C to +85°C. The LMH6517 is available in a 32-Pin, thermally enhanced, WQFN package. Typical Application: IF Sampling Receiver VCC RF 200 LO ½ LMH6517 ADC 6 GAIN 0-5 LATCH 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2011, Texas Instruments Incorporated LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) (3) Human Body Model 2 kV Machine Model 100V Charged Device Model 750V −0.6V to 5.5V Positive Supply Voltage (Pin 3) Differential Voltage between Any Two Grounds <200 mV −0.6V to V+ Analog Input Voltage Range −0.6V to 3.6V Digital Input Voltage Range Output Short Circuit Duration (one pin to ground) Infinite Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Soldering Information Infrared or Convection (30 sec) (1) (2) (3) 260°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Operating Ratings (1) Supply Voltage (Pin 3) 4.5V to 5.25V Differential Voltage Between Any Two Grounds <10 mV Analog Input Voltage Range, AC Coupled Temperature Range 0V to V+ (2) −40°C to +85°C Package Thermal Resistance (θJA) 32-Pin WQFN (1) (2) 2 42°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 5V Electrical Characteristics (1) The following specifications apply for single supply with V+ = 5V, Maximum Gain , RL = 100Ω, VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes. Parameter Test Conditions Min (2) Typ (3) Max (2) Units Dynamic Performance SSBW OIP3 IMD3 P1dB Frequency Range 1200 MHz Maximum Voltage Gain f = 200 MHz 22 dB Input Noise Voltage Maximum Gain, f > 1MHz, RIN= 0 Ω 1.1 nV/√Hz Output Noise Voltage Maximum Gain, f > 1MHz 22 nV/√Hz Noise Figure Maximum Gain 5.5 dB Output Third Order Intercept Point f = 150 MHz, V OUT = 4dBm per tone 43 dBm Output Third Order Intercept Point f = 200 MHz, V OUT = 4dBm per tone 43 Third Order Intermodulation Products f = 150 MHz, V OUT = 4dBm per tone −78 Third Order Intermodulation Products f = 200 MHz, V OUT = 4dBm per tone −78 1dB Compression Point f = 150 MHz, RL= 100Ω 18.3 1dB Compression Point f= 150 MHz, RL= 200Ω 15.5 Input Resistance Differential dBc dBm Analog I/O 170 Input Capacitance 200 220 2 Input Common Mode Voltage Self Biased 2.42 2.24 Input Common Mode Voltage Range Externally Driven, CMRR > 40dB 1.5 Maximum Input Voltage Swing Volts peak to peak, differential Output Common Mode Voltage Self Biased Maximum DIfferential Output Voltage Swing Differential 2.55 2.71 2.79 V 3.5 V 5.5 2.4 2.55 Ω pF V 2.7 5.9 V VPP Output Voltage Swing Single ended (each output) 1.05 1V to 4V 4.00 V VOS Output Offset Voltage All Gain Settings −25 -30 −2 25 30 mV CMRR Common Mode Rejection Ratio Maximum Gain, f=100MHz PSRR Power Supply Rejection Ratio Maximum Gain, f=100MHz 60 dB XTLK Channel to Channel Crosstalk Maximum Gain, f=100MHz −85 dBc XTLK Channel to Channel Crosstalk Maximum Gain, f=300MHz −72 dBc 60 dB Gain Parameters (1) (2) (3) Maximum Gain Gain Code 000000, DC Voltage Gain 21.7 21.65 21.85 22 22.05 dB Minimum Gain Gain Code 111111, DC Voltage Gain −9.25 −9.1 −9.5 −9.78 −9.8 dB Gain Adjust Range 31.5 dB Gain Step Size 0.5 dB dB Channel Matching Gain Error between A and B channel. ±0.05 Channel Matching Phase Shift between A and B channel. ±0.1 Gain Step Error Any two steps −0.3 ±0.05 0.3 dB Gain Step Error Maximum Gain to Maximum Gain −12dB −0.5 ±0.1 0.5 dB ° Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the electrical tables under conditions different than those tested Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 3 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com 5V Electrical Characteristics (1) (continued) The following specifications apply for single supply with V+ = 5V, Maximum Gain , RL = 100Ω, VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes. Parameter Gain Step Phase Shift Test Conditions Min (2) between any two steps Gain Step Switching Time Typ (3) Max (2) Units 0.5 ° 15 ns Power Requirements ICC Supply Current Each channel (two channels per package) 80 P Power Each Channel 400 91 mW mA ICC Disabled Supply Current Each Channel 7.5 mA All Digital Inputs Logic Compatibility TTL, 2.5V CMOS, 3.3V CMOS VIL Logic Input Low Voltage 0 0.4 VIH Logic Input High Voltage 2.0 3.6 V V IIH Logic Input High Input Current Digital Input Voltage = 3.3V −110 110 μA IIL Logic Input Low Input Current Digital Input Voltage = 0V −110 110 μA Parallel and Pulse Mode Timing tGS Setup Time 3 ns tGH Hold Time 3 ns tLP Latch Low Pulse Width 7 ns tPG Pulse Gap between Pulses 20 ns tPW Minimum Latch Pulse Width 20 ns tRW Reset Width 10 ns Serial Mode Timing and AC Characteristics SPI Compatible fSCLK Serial Clock Frequency 10.5 MHz tPH SCLK High State Duty Cycle % of SCLK Period 40 60 % tPL SCLK Low State Duty cycle % of SCLK Period 40 60 tSU Serial Data In Setup Time tH Serial Data In Hold Time tODZ Serial Data Out Driven-to- Tri-State Time Referenced to Positive edge of CS 40 50 ns tOZD Serial Data Out Tri-State-to-Driven Time Referenced to Negative edge of SCLK 15 20 ns tOD Serial Data Out Output Delay TIme Referenced to Negative edge of SCLK 15 20 ns tCSS Serial Chip Select Setup TIme Referenced to Positive edge of SCLK 10 5 tCSH Serial Chip Select Hold TIme Referenced to Positive edge of SCLK 10 5 tIAG Inter-Access Gap Minimum time Serial Chip Select pin must be asserted between accesses. 4 0.5 5 Submit Documentation Feedback 3 % ns ns Cycles of SCLK Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 CONNECTION DIAGRAM A2/CS/S1A A1/SDO/S0A IPA+ IPA- GND +5V GND A0 32 31 30 29 28 27 26 25 Top View A3/SDI/DNA 1 24 OPA+ A4/CLK/UPA 2 23 OPA- 22 ENA LMH6517 A5 3 MOD0 4 21 LATA MOD1 5 20 LATB B5 6 19 ENB B4/UPB 7 18 OPB- 17 OPB+ 9 10 11 12 13 14 15 16 B1/S0B IPB+ IPB- GND +5V GND B0 8 B2/S1B B3/DNB GND Figure 1. 32-Pin WQFN Package See Package Number RTV0032A PIN DESCRIPTIONS Pin Number Pin Name Description Analog I/O 30, 11 IPA+, IPB+ Amplifier non—inverting input. Internally biased to mid supply. Input voltage should not exceed V+ or go below GND by more than 0.5V. 29, 12 IPA−, IPB− Amplifier inverting input. Internally biased to mid supply. Input voltage should not exceed V+ or go below GND by more than 0.5V. 24, 17 OPA+, OPB+ Amplifier non—inverting output. Internally biased to mid supply. 23, 18 OPA−, OPB− Amplifier inverting output. Internally biased to mid supply. 13, 15, 26, 28, center pad GND Ground pins. Connect to low impedance ground plane. All pin voltages are specified with respect to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins. 14, 27 +5V Power supply pins. Valid power supply range is 4.5V to 5.25V. Power Common Control Pins 4, 5 MOD0, MOD1 Digital Mode control pins. These pins float to the logic hi state if left unconnected. See below for Mode settings. 22, 19 ENA, ENB Enable pins. Logic 1 = enabled state. See Application Information for operation in serial mode. Digital Inputs Parallel Mode (MOD1 = 1, MOD0 = 1) 25, 16 A0, B0 Gain bit zero = 0.5dB step. Gain steps down from maximum gain (000000 = Maximum Gain) 31, 10 A1, B1 Gain bit one = 1dB step 32, 9 A2, B2 Gain bit two = 2dB step 1, 8 A3, B3 Gain bit three = 4dB step 2, 7 A4, B4 Gain bit four = 8dB step 3, 6 A5, B5 Gain bit five = 16dB step Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 5 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com PIN DESCRIPTIONS (continued) Pin Number 21, 20 6 Pin Name LATA, LATB Description Latch pins. Logic zero = active, logic 1 = latched. Gain will not change once latch is high. Connect to ground if the latch function is not desired. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 PIN DESCRIPTIONS (continued) Pin Number Pin Name Description Digital Inputs Serial Mode (MOD1 =1 , MOD0 = 0) 2 CLK Serial Clock 1 SDI Serial Data In (SPI Compatible) See Application Information for more details. 32 CS Serial Chip Select (SPI compatible) 31 SDO Serial Data Out (SPI compatible) 3, 4, 6 — 10, 16, 20, GND 21, 25 Pins unused in Serial Mode, connect to DC ground. Digital Inputs Pulse Mode (MOD1 = 0 , MOD0 = 1) 2, 7 UPA, UPB Up pulse pin. A logic 0 pulse will increase gain one step. 1, 8 DNA, DNB Down pulse pin. A logic 0 pulse will decrease gain one step. 1 & 2 or 7 & 8 Pulsing both pins together will reset the gain to maximum gain. 31, 32 S0A, S1A Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB 10, 9 S0B, S1B Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB 3, 5, 6, 16, 25 GND Pins unused in Pulse Mode, connect to DC ground. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 7 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com Typical Performance Characteristics VCC = 5V Frequency Response 2dB Gain Steps Transformer Coupled Frequency Response 2dB Gain Steps 30 RL = 120Ö & 5 pF 25 20 15 GAIN (dB) GAIN (dB) 20 15 10 10 5 5 0 0 -5 -5 -10 -10 10 100 1000 1 10k 10 FREQUENCY (MHz) Figure 2. -40 °C 0 °C 20 °C 50 °C 80 °C 0.75 GROUP DELAY (ns) 22.4 GAIN (dB) Group Delay 1.00 22.6 22.2 22.0 21.8 21.6 21.4 0 50 100 150 200 250 FREQUENCY (MHz) 0.00 -0.25 ATT = 16 dB -0.50 150 250 350 450 550 650 750 850 FREQUENCY (MHz) Figure 4. Figure 5. Third Order Intercept Point vs Frequency Third Order Intermodulation Products vs Frequency -40 -50 ATT = 8 dB ATT = 16 dB -55 IMD3 (dBc) 40 35 POUT = 6 dBm -45 ATT = 0 dB 45 OIP3 (dBm) ATT = 31.5 dB 0.25 -1.00 50 300 55 ATT = 24 dB ATT = 24 dB -60 -65 -70 -75 ATT = 16 dB -80 30 -85 POUT = 6 dBm 100 ATT = 8 dB ATT = 0 dB 200 300 400 500 -90 0 FREQUENCY (MHz) 100 200 300 400 500 FREQUENCY (MHz) Figure 6. 8 ATT = 0 dB 0.50 -0.75 21.2 25 0 1000 Figure 3. Gain Flatness over Temperature 22.8 50 100 FREQUENCY (MHz) Figure 7. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 Typical Performance Characteristics (continued) VCC = 5V Third Order Intercept Point at Various Attenuator Settings f = 150 MHz Third Order Intercept Point at Various Attenuator Settings f = 200 MHz 46 46 44 44 ATT = 0 dB 42 42 OIP3 (dBm) OIP3 (dBm) ATT = 8 dB 40 ATT = 16 dB 38 ATT = 0 dB ATT = 8 dB 40 ATT = 16 dB 38 ATT = 24 dB 36 34 32 -2 36 RL = 100: f = 150 MHz 0 34 2 4 6 8 32 -2 10 ATT = 24dB RL = 100: f = 200 MHz 0 OUTPUT POWER (dBm/tone) 2 4 6 8 10 OUTPUT POWER (dBm/tone) Figure 8. Figure 9. Third Order Intercept Point at Various Attenuator Settings f = 250 MHz Third Order Intermodulation at Various Attenuator Settings f = 200 MHz 46 -30 ATT = 0 dB 42 ATT = 8 dB OIP3 (dBm) ATT = 16 dB 40 ATT = 24 dB 38 36 34 32 -2 RL = 100: f = 250 MHz 0 2 4 -40 Third Order IMD Products (dBc) 44 6 8 RL = 100: f = 200 MHz -50 -60 -70 -80 -90 ATT = 16 dB ATT = 0 dB -100 -2 10 ATT = 24 dB ATT = 8 dB 0 OUTPUT POWER (dBm/tone) 2 4 6 8 10 OUTPUT POWER (dBm/tone) Figure 10. Figure 11. OIP3 vs Temperature Gain Shift vs Temperature 0.3 50 POUT = 3 dBm / TONE 0.2 GAIN SHIFT (dB) OIP (dBm) 48 f = 200 MHz MAXIMUM GAIN 46 44 42 40 ATT=0 dB 0.1 ATT=31 dB ATT=16 dB 0 38 36 34 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) -0.1 -40 -10 20 50 80 105 TEMPERATURE (°C) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 9 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com Typical Performance Characteristics (continued) VCC = 5V Cumulative Gain Error vs Attenuator Setting Cumulative Gain Error over Temperature 0.4 f = 200 MHz 0.3 0.3 0.2 GAIN ERROR (dB) CUMULATIVE GAIN ERROR (dB) 0.4 0.2 CH A 0.1 CH B 0.0 0.1 TEMP = -40 0 TEMP = 25 -0.1 -0.2 -0.1 -0.3 TEMP = 85 -0.2 0 6 13 19 26 -0.4 32 5 0 25 Phase Shift vs Attenuator Setting Noise Figure vs Attenuator Setting 30 30 f = 200 MHz CH B 2 f = 350MHz 25 1 0 -1 CH A -2 -3 20 f = 150 MHz 15 f = 70 MHz 10 -4 5 0 6 13 19 26 32 0 ATTENUATION (0 = MAX GAIN) 5 10 15 20 25 30 ATTENUATOR SETTING (0 = MAX GAIN) Figure 16. Figure 17. Noise Figure vs. Temperature Noise Figure vs Frequency 9 10 8 8 350 MHz NOISE FIGURE NOISE FIGURE (dB) 20 Figure 15. -5 250 MHz 7 6 5 4 -40 6 4 2 150 MHz 0 40 80 40 MHz 0 50 120 TEMPERATURE (°C) 100 150 200 250 300 350 400 FREQUENCY (MHz) Figure 18. 10 15 Figure 14. NOISE FIGURE (dB) NORMALIZED PHASE (DEGREES) 3 10 DVGA ATTENUATOR SETTING (dB) ATTENUATION (0 = MAX GAIN) Figure 19. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 Typical Performance Characteristics (continued) VCC = 5V Second Order Harmonic Distortion at 10 MHz Third Order Harmonic Distortion at 10 MHz -40 -20 RL = 100: f = 10MHz RL = 100: f = 10MHz -50 -38 ATT = 24 dB ATT = 0 dB -60 HD3 (dBc) HD2 (dBc) ATT = 24 dB ATT = 16 dB -70 -80 ATT = 16 dB -56 -74 ATT = 0 dB -92 ATT = 16 dB ATT = 16 dB -90 -4 0 5 9 14 -110 -4 18 0 OUTPUT POWER (dBm) 9 Second Order Harmonic Distortion at 75 MHz Third Order Harmonic Distortion at 75 MHz -20 ATT = 0 dB RL = 100: f = 75 MHz -38 HD3 (dBc) -50 -60 ATT = 24 dB -70 ATT = 24 dB -56 ATT = 16 dB -74 ATT = 0 dB ATT = 16 dB -90 -4 ATT = 8 dB 0 -92 5 9 14 -110 -4 18 ATT = 16 dB 0 OUTPUT POWER (dBm) 9 14 18 OUTPUT POWER (dBm) Figure 23. Second Order Harmonic Distortion at 150 MHz Third Order Harmonic Distortion at 150 MHz -10 ATT = 0 dB RL = 100: f = 150 MHz RL = 100: f = 150 MHz -28 HD3 (dBc) -50 HD2 (dBc) 5 Figure 22. -40 -60 -70 ATT = 16 dB -80 ATT = 16 dB -46 ATT = 24 dB -64 -82 ATT = 8 dB -90 -4 18 Figure 21. RL = 100: f = 75 MHz -80 14 Figure 20. -40 HD2 (dBc) 5 OUTPUT POWER (dBm) 0 ATT = 24 dB 5 9 14 ATT = 8 dB 18 -100 -4 OUTPUT POWER (dBm) 0 5 ATT = 0 dB 9 14 18 OUTPUT POWER (dBm) Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 11 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com Typical Performance Characteristics (continued) VCC = 5V Second Order Harmonic Distortion at 200 MHz Third Order Harmonic Distortion at 200 MHz -30 -10 RL = 100: -40 f = 200 MHz RL = 100: -20 f = 200 MHz ATT = 0 dB ATT = 8 dB -30 -50 ATT = 8 dB -40 HD3 (dBc) HD2 (dBc) ATT = 16 dB -60 -70 -80 -50 ATT = 24 dB -60 ATT = 24 dB -70 ATT = 16 dB -90 -100 -4 ATT = 0 dB -80 0 5 9 14 -90 -4 18 0 OUTPUT POWER (dBm) Third Order Harmonic Distortion at 250 MHz -10 RL = 100: -20 f = 250 MHz -60 -70 -50 -70 ATT = 24 dB 0 5 ATT = 24 dB -60 ATT = 16 dB -90 ATT = 8 dB -40 HD3 (dBc) ATT = 8 dB -80 ATT = 16 dB -30 -50 HD2 (dBc) 18 Second Order Harmonic Distortion at 250 MHz RL = 100: -40 f = 250 MHz ATT = 0 dB -80 9 14 -90 -4 18 OUTPUT POWER (dBm) 0 5 9 14 18 OUTPUT POWER (dBm) Figure 28. Figure 29. Max Gain vs. Temperature Supply Current vs Temperature 180 23.00 RL = 120: 22.75 and 4.7 pF 450 MHz 75 MHz 22.00 21.75 200 MHz 21.50 150 MHz SUPPLY CURRENT (mA) 300 MHz 22.50 22.25 14 Figure 27. -30 -100 -4 9 Figure 26. ATT = 0 dB MAXIMUM GAIN (dB) 5 OUTPUT POWER (dBm) 170 160 150 140 21.25 21.00 -40 -20 0 20 40 60 130 -40 -20 80 0 20 40 60 80 TEMPERATURE (°C) 100 120 TEMPERATURE (°C) Figure 30. 12 Figure 31. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 Typical Performance Characteristics (continued) VCC = 5V Output Offset Voltage vs. Temperature Pulse Response 4 RL = 200: and 4.7 pF ATT = 0 dB 3 DIFFERENTIAL VOUT (V) 5 ATT = 8 dB 0 ATT = 24 dB -5 2 1 0 -1 -2 -3 ATT = 16 dB ATT = 31 dB -10 -40 -20 0 20 40 60 80 -4 0 100 120 TEMPERATURE (°C) 25 Enable Timing Maximum Gain ENABLE 3.0 0.3 0.2 2.5 0.2 0.1 2.0 1.5 -0.1 1.0 VOUT 0.1 VOUT (V) 0 GAIN BIT A5 (V) VOUT (V) 20 0.4 A5 0.3 VOUT 2 0 1 -0.1 0 -0.3 0 -0.4 -0.5 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) ATT = 0 dB -1 10 20 30 40 50 60 70 80 90 100 TIME (ns) Figure 34. Figure 35. Enable Timing Minimum Gain Channel To Channel Crosstalk 3.5 -30 0.3 3.0 -40 0.2 2.5 0.4 3 -0.2 0.5 -0.3 -0.4 0 15 Figure 33. Gain Change Timing -0.2 10 TIME (ns) Figure 32. 0.4 5 ENABLE (V) OUTPUT OFFSET VOLTAGE (mV) 10 2.0 0 1.5 -0.1 1.0 -0.2 0.5 0.0 -0.3 CROSSTALK (dBc) VOUT (V) VOUT 0.1 ENABLE (V) ENABLE -50 -60 CHB TO CHA -70 -80 -90 CHA to CHB ATT = 32.5 dB -0.4 0 -0.5 10 20 30 40 50 60 70 80 90 100 -100 10 TIME (ns) 100 1000 FREQUENCY (MHz) Figure 36. Figure 37. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 13 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com Typical Performance Characteristics (continued) VCC = 5V Input Impedance (S11) Output Impedance (S22) 250 50 |Z| 40 OUTPUT IMPEDANCE (:) INPUT IMPEDANCE (:) 200 150 R 100 50 jX |Z| 30 R 20 10 0 0 jX -50 10 100 1000 -10 10 FREQUENCY (MHz) 1000 FREQUENCY (MHz) Figure 38. 14 100 Figure 39. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 APPLICATION INFORMATION The LMH6517 is a fully differential amplifier optimized for signal path applications up to 400 MHz. The LMH6517 has a 200Ω input and a low impedance output. The gain is digitally controlled over a 31.5 dB range from +22dB to −9.5dB. The LMH6517 is optimized for accurate gain steps and minimal phase shift combined with low distortion products. This makes the LMH6517 ideal for voltage amplification and an ideal ADC driver where high linearity is necessary. The LMH6517 was designed for differential signal inputs only. Single ended inputs require a balun or transformer as shown on the evaluation board. VCC RF ½ LMH6517 200 LO ADC 6 GAIN 0-5 LATCH Figure 40. LMH6517 Typical Application 5 OUT + VOUT (V) 4 3 COMMON MODE = 2.5V 1.25 VP 2 1 OUT 0 0 45 90 135 180 225 270 315 360 PHASE (°) Figure 41. Output Voltage with Respect to the Output Common Mode In order to help with system design National Semiconductor offers the SP16160CH1RB High IF Receiver reference design board. This board combines the LMH6517 DVGA with the ADC16DV160 ADC and provides a ready made solution for many IF receiver applications. The SP16160CH1RB delivers an IF chain receiver sensitivity of -105 dBm, with a 9 dB carrier-to-noise ratio in a 200 kHz channel, at 192 MHz input IF. With the digitally-controlled variable gain amplifier (DVGA) set at a maximum gain of 22 dB, the sensitivity is limited primarily by the noise contribution of the DVGA. In the presence of a strong blocker, with the DVGA gain set at 12 dB and blocker level kept at 1.6 dBm input to the ADC, the SP16160CH1RB board delivers sensitivity of -86 dBm. In this blocking condition, the receiver sensitivity is determined by the ADC’s high spurious-free dynamic range (SFDR). Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 15 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com Channel A 0 to - 31.5 dB Attenuator 22 dB Attenuator 0 to - 31.5 dB 22 dB Channel B Figure 42. LMH6517 Block Diagram INPUT CHARACTERISTICS The LMH6517 input impedance is set by internal resistors to a nominal 200Ω. Process variations will result in a range of values as shown in the 5V Electrical Characteristics table. At higher frequencies parasitic reactances will start to impact the impedance. This characteristic will also depend on board layout and should be verified on the customer’s system board. At maximum gain the digital attenuator is set to 0 dB and the input signal will be much smaller than the output. At minimum gain the output is 9 dB or more smaller than the input. In this configuration the input signal will begin to clip against the ESD protection diodes before the output reaches maximum swing limits. The input signal cannot swing more than 0.5V below the negative supply voltage (normally 0V) nor should it exceed the positive supply voltage. The input signal will clip and cause severe distortion if it is too large. Because the input stage self biases to approximately mid rail the supply voltage will impose the limit for input voltage swing. At the frequencies where the LMH6517 is the most useful the input impedance is not exactly 200 Ω and it may not be purely resistive. For many AC coupled applications the impedance can be easily changed using LC circuits to transform the actual impedance to the desired impedance. SOURCE IMPEDANCE = 100: f = 200 MHz 5V C1 LMH6517 ZAMP VIN L1 ZIN C2 L1 = 160 nH 5 C1 = 16 pF C2 = 16 pF GAIN 1-5 LATCH ZAMP = (200): ZIN = (100): Figure 43. Differential 200Ω LC Conversion Circuit In Figure 43 a circuit is shown that matches the amplifier 200Ω input with source is 100Ω. This would be the case when connecting the LMH6517 directly to many common types of 50Ω test equipment. For an easy way to calculate the L and C circuit values there are several options for online tools or down-loadable programs. The following tool might be helpful. http://www.circuitsage.com/matching/matcher2.html 16 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 Excel can also be used for simple circuits; however, the “Analysis ToolPak” add-in must be installed to calculate complex numbers. OUTPUT CHARACTERISTICS The LMH6517 has a low impedance output very similar to a traditional Op-amp output. This means that nearly any load can be driven with minimal gain loss. Matching load impedance for proper termination of filters is as easy as inserting the proper value of resistor between the filter and the amplifier. This flexibility makes system design and gain calculations very easy. The LMH6517 was designed to run from a single 5V supply. In spite of this low supply voltage the LMH6517 is still able to deliver very high power gains when driving low impedance loads. The ability of the LMH6517 to drive low loads creates an opportunity to greatly increase power gain, if required. One example of using power gain to offset filter loss is shown in Figure 59. A graph showing power gain over various load conditions is shown below in Figure 44. This graph clearly shows the reduction in power gain caused by back termination. While many RF amplifiers have internal resistance and deliver maximum power into a matched load the LMH6517 has an output resistance very near to zero Ohms. The graph shows that maximum power transfer does indeed occur with a load of nearly zero Ohms. Another useful feature of the graph is the ability to determine how much gain can be recovered by dropping load resistance when it is necessary to back terminate either a transmission line or a filter. 40 NON TERMINATED POWER GAIN (dB) 35 30 25 20 BACK TERMINATED 15 10 5 1 10 100 1000 LOAD RESISTANCE (:) Figure 44. Power Gain vs Load Note 6dB power loss when adding load matching resistors. Here is an example of how to use the chart in Figure 44. In a system it is desired to have at least 20dB of maximum gain from the amplifier input to output. The system noise and harmonic distortion requirements dictate a 200 Ohm filter between the amplifier and the ADC. Using the chart we can see that a back terminated 200 Ohm filter will result in a net 16 dB of gain at the filter input. To recover this loss it is possible to use a 1:4 balun to drop the load condition of the filter to 50 Ohms at the amplifier output. This gives an additional 6dB of power gain. Since the transformer has a power loss of approximately 1dB we end up with 21dB of gain at the filter output instead of 16dB. See Figure 59 for an example where the filter performs the impedance transformation function. The LMH6517, like most high frequency amplifiers, is sensitive to loading conditions on the output. Load conditions that include small amounts of capacitance connected directly to the output can cause stability problems. In order to ensure output stability resistors should be connected directly at the amplifier output followed by a small capacitor. This circuit sets a dominant pole that will cancel out board parasitics in most applications. An example of this is shown in figure Figure 45 . In this example the amplifier and ADC are less than 0.1 wavelength apart and do not require a terminated transmission line. A more sophisticated filter may require better impedance matching. Some example filters are shown later. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 17 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com 10 f = 140 MHz 0.01P + 200: 4.7p LMH6517 220n 10 . - +IN 12p 100 100 12p VRM ADC16DV160 -IN 0.01P Figure 45. Output Configuration DIGITAL CONTROL The LMH6517 will support three modes of control, parallel mode, serial mode (SPI compatible) and pulse mode. Parallel mode is fastest and requires the most board space for logic line routing. Serial mode is compatible with existing SPI compatible systems. The pulse mode is both fast and compact, but must step through intermediate gain steps when making large gain changes. The LMH6517 has gain settings covering a range of 31.5 dB. To avoid undesirable signal transients the LMH6517 should not be powered on with large inputs signals present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs. The LMH6517 was designed to interface with 3.3V CMOS logic circuits. If operation with 5V logic is required a simple voltage divider at each logic pin will allow for this. To properly terminate 100Ω transmission lines a divider with a 66.5Ω resistor to ground and a 33.2Ω series resistor will properly terminate the line as well as give the 3.3V logic levels. Care should be taken not to exceed the 3.6V absolute maximum voltage rating of the logic pins. Some pins on the LMH6517 have different functions depending on the digital control mode. These functions will be described in the sections to follow. Control Mode MOD1 Pin Value MOD0 Pin Value Parallel 1 1 Serial 1 0 Pulse 0 1 Reserved 0 0 PARALLEL MODE (MOD1= 1, MOD0 = 1) Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space dedicated to control lines. When designing a system that requires very fast gain changes parallel mode is the best selection. 18 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 A2 A1 IPA+ IPA- GND +5V GND A0 31 30 29 28 27 26 25 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 32 www.ti.com A3 1 24 OPA+ A4 2 23 OPA- A5 3 22 ENA +3.3/NC 4 21 LATA +3.3/NC 5 20 LATB B5 6 19 ENB B4 7 18 OPB- B3 8 17 OPB+ LMH6517 13 14 GND +5V 16 12 IPB- B0 11 IPB+ 15 10 B1 GND 9 B2 GND Figure 46. Pin Functions for Parallel Mode The LMH6517 has a 6-bit gain control bus as well as a Latch pin. When the Latch pin is low, data from the gain control pins is immediately sent to the gain circuit (i.e. gain is changed immediately). When the Latch pin transitions high the current gain state is held and subsequent changes to the gain set pins are ignored. To minimize gain change glitches multiple gain control pins should not change while the latch pin is low. In order to achieve the very fast gain step switching time of 5 ns the internal gain change circuit is very fast. Gain glitches could result from timing skew between the gain set bits. This is especially the case when a small gain change requires a change in state of three or more gain control pins. If continuous gain control is desired the Latch pin can be tied to ground. This state is called transparent mode and the gain pins are always active. In this state the timing of the gain pin logic transitions should be planned carefully to avoid undesirable transients ENA and ENB pins are provided to reduce power consumption by disabling the highest power portions of the LMH6517. The gain register will preserve the last active gain setting during the disabled state. These pins will float high and can be left disconnected if they won't be used. If the pins are left disconnected a 0.01uF capacitor to ground will help prevent external noise from coupling into these pins. See Typical Performance Characteristics for disable and enable timing information. DVGA FPGA/DSP/PC/ASIC latcha ga[5:0] gb[5:0] latchb pd latcha 6 6 cmode VSS ga[5:0] gb[5:0] latchb pd Pins: 15 MSPS: 125 Low Skew Figure 47. Parallel Mode Connection for Fastest Response Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 19 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com FPGA/DSP/PC/ASIC DVGA VSS 6 ga[5:0] 6 gb[5:0] VSS latcha cmode ga[5:0] gb[5:0] Pins: 13 MSPS: 333 High Skew latchb pd pd VSS Figure 48. Parallel Mode Connection Not Using Latch Pins (Latch pins tied to logic low state) FPGA/DSP/PC/ASIC DVGA latcha ga/gb[5:0] latcha 6 cmode VSS ga[5:0] gb[5:0] latchb pd latchb pd Pins: 9 MSPS: 62.5 Low Skew Figure 49. Parallel Mode Connection Using Latch Pins to Mulitplex Digital Data SPI COMPATIBLE SERIAL INTERFACE (MOD1= 1, MOD0 = 0) Serial interface allows a great deal of flexibility in gain programming and reduced board complexity. Using only 4 wires for both channels allows for significant board space savings. The trade off for this reduced board complexity is slower response time in gain state changes. For systems where gain is changed only infrequently or where only slow gain changes are required serial mode is the best choice. 20 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 CS SDO IPA+ IPA- GND +5V GND GND 31 30 29 28 27 26 25 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 32 www.ti.com SDI 1 24 OPA+ CLK 2 23 OPA- GND 3 22 ENA GND 4 21 GND +3.3/NC 5 20 GND GND 6 19 ENB GND 7 18 OPB- GND 8 17 OPB+ LMH6517 9 10 11 12 13 14 15 16 GND GND IPB+ IPB- GND +5V GND GND GND Figure 50. Pin Functions for Serial Mode The LMH6517 has a serial interface that allows access to the control registers. The serial interface is a generic 4-wire synchronous interface that is compatible with SPI type interfaces that are used on many microcontrollers and DSP controllers. The serial mode is active when the two mode pins are set as follows: MOD1=1, MOD0=0). In this configuration the pins function as shown in the pin description table. The SPI interface uses the following signals: clock input (CLK), serial data in (SDI), serial data out, and serial chip select (CS) ENA and ENB pins are active in the serial mode. For fast disable capability these pins can be used and the serial register will hold the last active gain state. These pins will float high and can be left disconnected for serial mode. The serial control bus can also disable the DVGA channels, but at a much slower speed. The serial enable function is an AND function. For a channel to be active both the Enable pin and the serial control register must be in the enabled state. To disable a channel either method will suffice. See Typical Performance Characteristics for disable and enable timing information. LATA and LATB pins are not active during serial mode. CLK: This pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the rising edge; and to source the output data on the SDO pin on the falling edge. User may disable clock and hold it in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled or disabled. CS: This pin is the chip select pin. Each assertion starts a new register access - i.e., the SDATA field protocol is required. The user is required to deassert this signal after the 16th clock. If the SCSb is deasserted before the 16th clock, no address or data write will occur. The rising edge captures the address just shifted-in and, in the case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the deasserted pulse - which is specified in Electrical Characteristics. SDI: This pin is an input for the serial data. It must observe setup/hold requirements with respect to the SCLK. Each cycle is 16-bits long Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 21 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com SDO: This is the data output pin. Ths SDO pin is an open drain output and requires an external bias resistor. See Figure 51 for resistor sizing guidance. This output is normally at TRI-STATE and is driven only when SCSb is asserted. Upon SCSb assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges. Upon power-up, the default register address is 00h. Each serial interface access cycle is exactly 16 bits long as shown in Figure 52. Each signal's function is described below. the read timing is shown in Figure 53, while the write timing is shown in figure Figure 54. FPGA/DSP/uC/ASIC LMH6517 Clock out Chip Select out Data Out Data In CLK CS SDI (MOSI) SDO (MISO) R V+ (Logic High) SDO For SDO (MISO) pin only: VOH = V+, 25: VOL = (V+) - (R/(R+25)) * V+ Recommended: R = 300 Ohms to 2000 Ohms V+ (Logic) = 2.5V to 3.3V Figure 51. SDO Pin External Bias Resistor Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D2 D1 D0 (LSB) D2 D1 17 SCLK SCSb COMMAND FIELD SDI C7 C6 C5 C4 R/Wb 0 0 0 Reserved (3-bits) DATA FIELD C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 (MSB) D5 D4 D3 Write DATA Address (4-bits) D7 D6 (MSB) D5 D4 D3 D0 (LSB) Hi-Z Read DATA SDO Data (8-bits) Single Access Cycle Figure 52. Serial Interface Protocol (SPI compatible) 22 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 R/Wb Read / Write bit. A value of 1 indicates a read operation, while a value of 0 indicates a write operation. Reserved Not used. Must be set to 0. ADDR: Address of register to be read or written. DATA In a write operation the value of this field will be written to the addressed register when the chip select pin is deasserted. In a read operation this field is ignored. st th 1 clock th 8 clock 16 clock SCLK tCSH tCSS tCSH tCSS CSb tOZD SDO tODZ tOD D7 D1 D0 Figure 53. Read Timing Table 1. Read Timing Data Output on SDO Pin Parameter Description tCSH Chip select hold time tCSS Chip select setup time tOZD Initial output data delay tODZ High impedance delay tOD Output data delay tPL tPH 16th clock SCLK tSU SDI tH Valid Data Valid Data Figure 54. Write Timing Data Written to SDI Pin Table 2. Write Timing Data Input on SDI Pin Parameter Description tPL Minimum clock low time (clock duty dycle) tPH Minimum clock high time (clock duty cycle) tSU Input data setup time tH Input data hold time Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 23 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com Table 3. Serial Word Format for LMH6517 C7 1= read 0=write C6 0 C5 C4 0 C3 0 C2 0 C1 0 0 C0 0=Ch A 1=Ch B Table 4. Serial Word Format for LMH6517 (cont) Enable 1=On 0=Off Gb5 1=+16dB Gb4 Gb3 1=+8dB Gb2 1=+4dB Gb1 1=+2dB Gb0 1=+1dB 1=+0.5dB RES 0 PULSE MODE (MOD1= 0, MOD0 = 1) S1A S0A IPA+ IPA- GND +5V GND GND 32 31 30 29 28 27 26 25 Pulse mode is a simple yet fast way to adjust gain settings. Using only two control lines per device the LMH6517 gain can be changed by simple up and down signals. Gain steps are selectable either by hard wiring the board or using two additional logic inputs. For a system where gain changes can be stepped from one gain to the next and where board space is limited this mode may be the best choice. The ENA and ENB pins are fully active during pulse mode, and the channel gain state is preserved during the disabled state. See Typical Performance Characteristics for disable and enable timing information. DNA 1 24 OPA+ UPA 2 23 OPA- GND 3 22 ENA GND 4 21 GND +3.3/NC 5 20 GND GND 6 19 ENB UPB 7 18 OPB- DNB 8 17 OPB+ LMH6517 9 10 11 12 13 14 15 16 S1B S0B IPB+ IPB- GND +5V GND GND GND Figure 55. Pin Functions for Pulse Mode The LMH6517 supports a simple pulse up or pulse down control mode. In this mode the gain step size can be selected from a choice of 0.5, 1, 2 or 6dB steps. In operation the gain can be quickly adjusted either up of down one step at a time by a negative pulse on the UP or DN pins. This mode of operation is most suitable for applications where board space is at a premium and high speed gain changes are desired. As shown in Figure 56 each gain step pulse must have a logic high state of at least tPW= 20 ns and a logic low state of at least tPG 20 ns for the pulse to register as a gain change signal. To provide a known gain state there is a reset feature in pulse mode. To reset the gain to maximum gain both the UP and DN pins must be strobed low together as shown in Figure 56. There must be an overlap of at least tRW= 20 ns for the reset to register. 24 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 PULSE TIMING tPW tPG UP/DN RESET TIMING UP tRW DN Figure 56. Pulse Mode Timing EXPOSED PAD WQFN PACKAGE The LMH6517 is packaged in a thermally enhanced package. The exposed pad is connected to the GND pins. It is recommended, but not necessary, that the exposed pad be connected to the supply ground plane. In any case, the thermal dissipation of the device is largely dependent on the attachment of this pad. The exposed pad should be attached to as much copper on the circuit board as possible, preferably external copper. However, it is also very important to maintain good high speed layout practices when designing a system board. Please refer to the LMH6517 evaluation board for suggested layout techniques. Package information is available on the Texas Instruments web site. http://www.ti.com/packaging/ INTERFACING TO ADC The LMH6517 was designed to be used with high speed ADCs such as the ADC16DV160. As shown in Applications, AC coupling provides the best flexibility especially for IF sub-sampling applications. For DC coupled applications the use of a level shifting amplifier or a resistive biasing network may be possible. The inputs of the LMH6517 will self bias to the optimum voltage for normal operation. The internal bias voltage for the inputs is approximately mid rail which is 2.5V with the typical 5V power supply condition. In most applications the LMH6517 input will need to be AC coupled. The output common mode voltage is also self biasing to mid supply. This means that for driving most ADCs AC coupling is required. Since most often a band pass filter is desired between the amplifier and ADC the bandpass filter can be configured to block the DC voltage of the amplifier output from the ADC input. 3 pF 41 pF 27 nH ADC IN 390 nH AMP OUT 100: 200: 390 nH 100: A. Center Frequency is Designed for 200Ω Impedance 200 3 pF 140 MHz with a 20 MHz Bandwidth Figure 57. Bandpass Filter Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 25 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com ADC Noise Filter Below are filter schematics and a table of values for some common IF frequencies. The filter shown in Figure 58 offers a good compromise between bandwidth, noise rejection and cost. This filter topology is the same as is used on the ADC14V155KDRB High IF Receiver reference design board. This filter topology works best with the 12 and 14 bit sub-sampling analog to digital converters shown in the Table 6 table. Table 5. Filter Component Values Filter Component Values 75 MHz 140 MHz 170 MHz 250 MHz BW 40 MHz 20 MHz 25 MHz Narrow Band R1, R2 100Ω 200Ω 100Ω 499Ω L1, L2 390 nH 39 0nH 560 nH — C1, C2 10 pF 3 pF 1.4 pF 47 pF C3 22 pF 41 pF 32 pF 11 pF L5 220 nH 27 nH 30 nH 22 nH R3, R4 100Ω 200Ω 100Ω 499Ω R1 AMP VOUT - L1 C1 L5 C2 L2 AMP VOUT + ADC ZIN C3 AMP ZOUT R3 ADC VIN + R4 Components Fc ADC VIN - R2 ADC VCM Figure 58. Sample Filter While the filters shown above have excellent performance in most respects they have one very large drawback, and that is voltage loss. There is a 6dB loss right up front from the matching resistors (R1 and R2 in Figure 58) and there are additional losses in the filter, primarily due to the resistive losses of the inductors. One solution is to use larger inductors with higher Q ratings. An even better solution is to use the filter as an impedance transforming circuit. Designing a filter with a low impedance input and a high impedance output will result in a voltage gain that can be used to offset the voltage losses. While this solution won't work with high impedance amplifiers, the LMH6517's low impedance output stage is perfectly suited for it. In essence the additional power gained from driving a given voltage into a lower value load impedance is used to offset the power lost in the filter and matching resistors. The filter shown in Figure 59 uses both an impedance transform as well as a slight input impedance mismatch to reduce the voltage loss from the amplifier to the ADC input. This configuration makes use of the strengths of the LMH6517 output stage to deliver the best linearity possible. Due to the low impedance output stage the LMH6517 can drive a lot of current into a low impedance load and still deliver high linearity signals. 26 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 LMH6517 www.ti.com SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 AMP VOUT - 5 91n 240n 18n ADC VIN + 4.7p ADC ZIN 100 27p 5.2p 100 ADC VIN 5 AMP VOUT + 91n 240n ADC VCM Figure 59. Impedance Transforming Filter 25 Ω Input 200 Ω Output, 210 MHz Center Frequency POWER SUPPLIES The LMH6517 was designed primarily to be operated on 5V power supplies. The voltage range for VCC is 4.5V to 5.25V. A 5V supply provides the best performance while lower supplies will result in less power consumption. Power supply regulation of 2.5% or better is advised. When operated on a board with high speed digital signals it is important to provide isolation between digital signal noise and the LMH6517 inputs. The SP16160CH1RB reference board provides an example of good board layout. Of special note is that the digital circuits are powered from an internal supply voltage of 3.3V. The logic pins should not be driven above the absolute maximum value of 3.6V. See DIGITAL CONTROL for details. Table 6. Compatible High Speed Analog To Digital Converters Product Number Max Sampling Rate (MSPS) Resolution Channels ADC12L063 62 12 SINGLE ADC12DL065 65 12 DUAL ADC12L066 66 12 SINGLE ADC12DL066 66 12 DUAL CLC5957 70 12 SINGLE ADC12L080 80 12 SINGLE ADC12DL080 80 12 DUAL ADC12C080 80 12 SINGLE ADC12C105 105 12 SINGLE ADC12C170 170 12 SINGLE ADC12V170 170 12 SINGLE ADC14C080 80 14 SINGLE ADC14C105 105 14 SINGLE ADC14DS105 105 14 DUAL ADC14155 155 14 SINGLE ADC14V155 155 14 SINGLE ADC16V130 130 16 SINGLE ADC16DV160 160 16 DUAL ADC08D500 500 8 DUAL ADC08500 500 8 SINGLE ADC08D1000 1000 8 DUAL ADC081000 1000 8 SINGLE ADC08D1500 1500 8 DUAL ADC081500 1500 8 SINGLE ADC08(B)3000 3000 8 SINGLE Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 27 LMH6517 SNOSB19J – NOVEMBER 2008 – REVISED NOVEMBER 2011 www.ti.com Table 6. Compatible High Speed Analog To Digital Converters (continued) Product Number Max Sampling Rate (MSPS) Resolution Channels ADC08L060 60 8 SINGLE ADC08060 60 8 SINGLE ADC10DL065 65 10 DUAL ADC10065 65 10 SINGLE ADC10080 80 10 SINGLE ADC08100 100 8 SINGLE ADCS9888 170 8 SINGLE ADC08(B)200 200 8 SINGLE ADC11C125 125 11 SINGLE ADC11C170 170 11 SINGLE 28 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Links: LMH6517 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMH6517SQ/NOPB ACTIVE WQFN RTV 32 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L6517SQ LMH6517SQE/NOPB ACTIVE WQFN RTV 32 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L6517SQ LMH6517SQX/NOPB ACTIVE WQFN RTV 32 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L6517SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH6517SQ/NOPB WQFN RTV 32 LMH6517SQE/NOPB WQFN RTV LMH6517SQX/NOPB WQFN RTV SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6517SQ/NOPB WQFN RTV 32 1000 203.0 190.0 41.0 LMH6517SQE/NOPB WQFN RTV 32 250 203.0 190.0 41.0 LMH6517SQX/NOPB WQFN RTV 32 4500 358.0 343.0 63.0 Pack Materials-Page 2 MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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