AD ADA4937-1YCPZ-RL Ultralow distortion differential adc driver Datasheet

Ultralow Distortion
Differential ADC Driver
ADA4937-1/ADA4937-2
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
13 –VS
14 –VS
16 –VS
–FB 1
12 PD
+IN 2
11 –OUT
–IN 3
10 +OUT
9
VOCM
06591-001
+VS 8
+VS 7
+VS 6
+VS 5
+FB 4
Figure 1. ADA4937-1
19 –OUT1
20 PD1
22 –VS1
21 –VS1
24 +IN1
–IN1 1
18 +OUT1
+FB1 2
17 VOCM1
+VS1 3
16 –VS2
+VS1 4
15 –VS2
06591-002
+OUT2 12
VOCM2 11
+VS2 9
13 –OUT2
+VS2 10
14 PD2
+IN2 6
–IN2 7
–FB2 5
+FB2 8
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
23 –FB1
ADA4937-2
APPLICATIONS
Figure 2. ADA4937-2
–55
HD2,
HD3,
HD2,
HD3,
–60
GENERAL DESCRIPTION
–65
The ADA4937-1/ADA4937-2 are fabricated using Analog Devices,
Inc., proprietary silicon-germanium (SiGe), complementary
bipolar process, enabling them to achieve very low levels of
distortion with an input voltage noise of only 2.2 nV/√Hz.
The low dc offset and excellent dynamic performance of the
ADA4937-1/ADA4937-2 make them well-suited for a wide
variety of data acquisition and signal processing applications.
–75
–80
–85
–90
–95
–100
–105
–110
–115
1
10
100
FREQUENCY (MHz)
06591-003
With the ADA4937-1/ADA4937-2, differential gain configurations
are easily realized with a simple external feedback network of
four resistors that determine the closed-loop gain of the amplifier.
VS = 5.0V
VS = 5.0V
VS = 3.3V
VS = 3.3V
–70
DISTORTION (dBc)
The ADA4937-1/ADA4937-2 are low noise, ultralow distortion,
high speed differential amplifiers. They are an ideal choice for
driving high performance ADCs with resolutions up to 16 bits
from dc to 100 MHz. The adjustable level of the output common
mode allows the ADA4937-1/ADA4937-2 to match the input
of the ADC. The internal common-mode feedback loop also
provides exceptional output balance as well as suppression of
even-order harmonic distortion products.
Rev. F
15 –VS
ADA4937-1
Extremely low harmonic distortion (HD)
−112 dBc HD2 at 10 MHz
−84 dBc HD2 at 70 MHz
−77 dBc HD2 at 100 MHz
−102 dBc HD3 at 10 MHz
−91 dBc HD3 at 70 MHz
−84 dBc HD3 at 100 MHz
Low input voltage noise: 2.2 nV/√Hz
High speed
−3 dB bandwidth of 1.9 GHz, G = 1
Slew rate: 6000 V/μs, 25% to 75%
Fast overdrive recovery of 1 ns
0.5 mV typical offset voltage
Externally adjustable gain
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V
Figure 3. Harmonic Distortion vs. Frequency
The ADA4937-1/ADA4937-2 are available in a Pb-free, 3 mm ×
3 mm, 16-lead LFCSP (ADA4937-1, single) or a Pb-free, 4 mm ×
4 mm, 24-lead LFCSP (ADA4937-2, dual). The pinout has been
optimized to facilitate PCB layout and minimize distortion.
The ADA4937-1/ADA4937-2 are specified to operate over the
automotive (−40°C to +105°C) temperature range and between
3.3 V and 5 V supplies.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADA4937-1/ADA4937-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analyzing an Application Circuit ............................................ 18
Applications ....................................................................................... 1
Setting the Closed-Loop Gain .................................................. 18
General Description ......................................................................... 1
Estimating the Output Noise Voltage ...................................... 18
Functional Block Diagrams ............................................................. 1
Impact of Mismatches in the Feedback Networks ................. 19
Revision History ............................................................................... 2
Calculating the Input Impedance for an Application Circuit
....................................................................................................... 19
Specifications..................................................................................... 3
5 V Operation ............................................................................... 3
3.3 V Operation ............................................................................ 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 16
Terminology .................................................................................... 17
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 20
Setting the Output Common-Mode Voltage .......................... 20
Power-Down Operation ............................................................ 20
Layout, Grounding, and Bypassing .............................................. 22
High Performance ADC Driving ................................................. 23
3.3 V Operation .......................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
Theory of Operation ...................................................................... 18
REVISION HISTORY
6/2016—Rev. E to Rev. F
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/2015—Rev. D to Rev. E
Changes to Table 6 ............................................................................ 7
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
8/2013—Rev. C to Rev. D
Changes to Input Bias Current Parameter, Table 1 ...................... 3
Changes to Input Bias Current Parameter, Table 3 ...................... 5
Updated Outline Dimensions ....................................................... 26
3/2010—Rev. B to Rev. C
Changes to Table 2, Power Supply Parameter ............................... 4
Changes to Table 4, Power Supply Parameter ............................... 6
Changes to Figure 43 ...................................................................... 15
Added the Power-Down Operation Section ............................... 20
10/2009—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Operating Temperature Range Parameter, Table 2.. 4
Changes to Table 3 ............................................................................ 5
Changes to Figure 4 .......................................................................... 7
Changes to Figure 5 and Figure 6 ....................................................8
Added EP Row to Table 7 and EP Row to Table 8 ........................8
Added Figure 46, Figure 47, and Figure 48; Renumbered
Sequentially ..................................................................................... 15
Changes to Table 9.......................................................................... 18
Changes to Input Common-Mode Voltage Range in SingleSupply Applications Section.......................................................... 20
Changes to Ordering Guide .......................................................... 26
11/2007—Rev. 0 to Rev. A
Added the ADA4937-2 ...................................................... Universal
Changes to Features ..........................................................................1
Changes to Specifications .................................................................3
Changes to Figure 4 ...........................................................................7
Changes to Typical Performance Characteristics..........................9
Inserted Figure 44........................................................................... 15
Added the Terminating a Single-Ended Input Section ............. 19
Changes to Table 10 and Table 11 ................................................ 21
Changes to Layout, Grounding, and Bypassing Section ........... 22
Inserted Figure 59, Figure 60, and Figure 61 .............................. 22
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/2007—Revision 0: Initial Version
Rev. F | Page 2 of 28
Data Sheet
ADA4937-1/ADA4937-2
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, Gain (G) = +1, RL, dm = 1 kΩ, unless otherwise noted. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
±DIN to ±OUT Performance
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Noise Figure
Crosstalk (ADA4937-2)
INPUT CHARACTERISTICS
Offset Voltage
Test Conditions/Comments
Min
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p
VOUT, dm = 2 V p-p
VOUT, dm = 2 V p-p; 25% to 75%
VOUT, dm = 2 V p-p
VIN = 0 V to 1.5 V step; G = 3.16
See Figure 51 for distortion test circuit
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
f1 = 70 MHz; f2 = 70.1 MHz; VOUT, dm = 2 V p-p
f = 100 kHz
f = 100 kHz
G = 4; RT = 136 Ω; RF = 200 Ω; RG = 37 Ω; f = 100 MHz
f = 100 MHz
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = 2.5 V
TMIN to TMAX variation
Input Bias Current
−2.5
−50
TMIN to TMAX variation
Input Offset Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
−2
Differential
Common mode
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V
−69
Maximum ∆VOUT; single-ended output; RF = RG = 10 kΩ
Per amplifier; RL, dm = 20 Ω; f = 10 MHz
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz;
see Figure 50 for test circuit
0.9
Rev. F | Page 3 of 28
Typ
Max
Unit
1900
200
1700
6000
7
<1
MHz
MHz
MHz
V/µs
ns
ns
−112
−84
−77
−102
−91
−84
−91
2.2
4
15
−72
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
dB
±0.5
±1
−30
0.01
+0.5
6
3
1
0.3 to 3.0
−80
+2.5
−10
+2
4.1
±70
−61
mV
µV/°C
µA
µA/°C
µA
MΩ
MΩ
pF
V
dB
V
mA
dB
ADA4937-1/ADA4937-2
Data Sheet
VOCM to ±OUT Performance
Table 2.
Parameter
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
POWER-DOWN (PD)
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Bias Current per Amplifier
Enabled
Powered Down
Test Conditions/Comments
Min
1.2
8
VOS, cm = VOUT, cm; VDIN+ = VDIN− = +VS/2
Enabled
TMIN to TMAX variation
Powered down
ΔVOUT, dm/ΔVS; ΔVS = 1 V
Max
440
1150
7.5
VIN = 1.5 V to 3.5 V; 25% to 75%
f = 100 kHz
ΔVOUT, dm/ΔVOCM; ΔVOCM = ±1 V
ΔVOUT, cm/ΔVOCM; ΔVOCM = ±1 V
Typ
−70
0.97
3.0
38.0
0.02
−70
Powered down
Enabled
10
2
0.5
−75
0.98
39.5
17
0.3
−90
MHz
V/µs
nV/√Hz
3.8
12
7.1
1.00
5.25
42.0
0.5
≤1
≥2
1
200
PD = 5 V
PD = 0 V
10
−300
OPERATING TEMPERATURE RANGE
−40
Rev. F | Page 4 of 28
30
−200
Unit
V
kΩ
mV
µA
dB
V/V
V
mA
µA/°C
mA
dB
V
V
µs
ns
50
−150
µA
µA
+105
°C
Data Sheet
ADA4937-1/ADA4937-2
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, −VS = 0 V, VOCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise noted. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
±DIN to ±OUT Performance
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Noise Figure
Crosstalk (ADA4937-2)
INPUT CHARACTERISTICS
Offset Voltage
Test Conditions/Comments
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p
VOUT, dm = 2 V p-p
VOUT, dm = 2 V p-p; 25% to 75%
VOUT, dm = 2 V p-p
VIN = 0 V to 1.0 V step; G = 3.16
See Figure 51 for distortion test circuit
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
f1 = 70 MHz; f2 = 70.1 MHz; VOUT, dm = 2 V p-p
f = 100 kHz
f = 100 kHz
G = 4; RT = 136 Ω; RF = 200 Ω; RG = 37 Ω; f = 100 MHz
f = 100 MHz
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = +VS/2
TMIN to TMAX variation
Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
Min
−2.5
−50
TMIN to TMAX variation
Differential
Common mode
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V
−67
Maximum ∆VOUT; single-ended output; RF = RG = 10 kΩ
Per amplifier; RL, dm = 20 Ω; f = 10 MHz
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz;
see Figure 50 for test circuit
0.8
Rev. F | Page 5 of 28
Typ
Max
Unit
1800
200
1300
4000
7
<1
MHz
MHz
MHz
V/µs
ns
ns
−113
−85
−77
−95
−77
−71
−87
2.2
4
15
−72
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
dB
±0.5
±1
−30
0.01
6
3
1
0.3 to 1.2
−80
+2.5
−10
2.5
±47
−61
mV
µV/°C
µA
µA/°C
MΩ
MΩ
pF
V
dB
V
mA
dB
ADA4937-1/ADA4937-2
Data Sheet
VOCM to ±OUT Performance
Table 4.
Parameter
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
POWER-DOWN (PD)
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Bias Current per Amplifier
Enabled
Powered Down
Test Conditions/Comments
Min
Typ
440
900
7.5
VIN = 0.9 V to 2.4 V; 25% to 75%
f = 100 kHz
1.2
VOS, cm = VOUT, cm; VDIN+ = VDIN− = 1.67 V
∆VOUT, dm/∆VOCM; ∆VOCM = ±1 V
∆VOUT, cm/∆VOCM; ∆VOCM = ±1 V
Enabled
TMIN to TMAX variation
Powered down
∆VOUT, dm/∆VS; ∆VS = 1 V
Max
−70
0.97
3.0
36
0.02
−70
Powered down
Enabled
MHz
V/µs
nV/√Hz
2.1
10
2
0.5
−75
0.98
38
17
0.2
−90
7.1
1.00
5.25
40
0.5
≤1
≥2
1
200
PD = 3.3 V
PD = 0 V
10
−200
OPERATING TEMPERATURE RANGE
−40
Rev. F | Page 6 of 28
20
−120
Unit
V
kΩ
mV
µA
dB
V/V
V
mA
µA/°C
mA
dB
V
V
µs
ns
30
−100
µA
µA
+105
°C
Data Sheet
ADA4937-1/ADA4937-2
ABSOLUTE MAXIMUM RATINGS
Rating
5.5 V
See Figure 4
−65°C to +125°C
−40°C to +105°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD51-7.
Table 6. Thermal Resistance
Package Type
16-Lead LFCSP (Exposed Pad)
24-Lead LFCSP (Exposed Pad)
θJA
95
67
θJC
12.6
8.78
Unit
°C/W
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4937-1/
ADA4937-2 packages is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes the properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4937-1/
ADA4937-2. Exceeding a junction temperature of 150°C for
an extended period can result in changes in the silicon devices,
potentially causing failure.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through holes, ground,
and power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the ADA4937-1 single
16-lead LFCSP (95°C/W), and the ADA4937-2 dual 24-lead
LFCSP (67°C/W) on a JEDEC standard 4-layer board.
3.5
3.0
2.5
ADA4937-2
2.0
1.5
ADA4937-1
1.0
0.5
0
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90 100 110
AMBIENT TEMPERATURE (°C)
06591-004
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
MAXIMUM POWER DISSIPATION (W)
Table 5.
Figure 4. Maximum Power Dissipation vs. Temperature, 4-Layer Board
ESD CAUTION
Rev. F | Page 7 of 28
ADA4937-1/ADA4937-2
Data Sheet
19 –OUT1
21 –VS1
20 PD1
22 –VS1
24 +IN1
23 –FB1
18 +OUT1
–IN1 1
12 PD
+FB1 2
+VS1 3
+IN 2
ADA4937-1
11 –OUT
–IN 3
TOP VIEW
(Not to Scale)
10 +OUT
+VS1 4
9
–FB2 5
2
3
4
+IN
−IN
+FB
5 to 8
9
10
11
12
13 to 16
EP
+VS
VOCM
+OUT
−OUT
PD
−VS
+OUT2 12
VOCM2 11
+VS2 10
+VS2 9
13 –OUT2
Figure 6. ADA4937-2 Pin Configuration
Table 7. ADA4937-1 Pin Function Descriptions
Mnemonic
−FB
14 PD2
NOTES
1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT
ELECTRICALLY CONNECTED TO THE DEVICE. IT IS
TYPICALLY SOLDERED TO GROUND OR A POWER
PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE.
Figure 5. ADA4937-1 Pin Configuration
Pin No.
1
TOP VIEW
(Not to Scale)
–IN2 7
NOTES
1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT
ELECTRICALLY CONNECTED TO THE DEVICE. IT IS
TYPICALLY SOLDERED TO GROUND OR A POWER
PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE.
16 –VS2
15 –VS2
+IN2 6
06591-005
+VS 7
VOCM
+VS 8
+VS 5
+VS 6
+FB 4
17 VOCM1
ADA4937-2
+FB2 8
–FB 1
06591-006
13 –VS
14 –VS
16 –VS
15 –VS
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Description
Negative Output for Feedback
Component Connection.
Positive Input Summing Node.
Negative Input Summing Node.
Positive Output for Feedback
Component Connection.
Positive Supply Voltage.
Output Common-Mode Voltage.
Positive Output for Load Connection.
Negative Output for Load Connection.
Power-Down Pin.
Negative Supply Voltage.
Exposed Paddle. The exposed pad is not
electrically connected to the device. It is
typically soldered to ground or a power
plane on the PCB that is thermally
conductive.
Table 8. ADA4937-2 Pin Function Descriptions
Pin No.
1
2
3, 4
5
6
7
8
9, 10
11
12
13
14
15, 16
17
18
19
20
21, 22
23
24
EP
Rev. F | Page 8 of 28
Mnemonic
−IN1
+FB1
+VS1
−FB2
+IN2
−IN2
+FB2
+VS2
VOCM2
+OUT2
−OUT2
PD2
−VS2
VOCM1
+OUT1
−OUT1
PD1
−VS1
−FB1
+IN1
Description
Negative Input Summing Node 1.
Positive Output Feedback Pin 1.
Positive Supply Voltage 1.
Negative Output Feedback Pin 2.
Positive Input Summing Node 2.
Negative Input Summing Node 2.
Positive Output Feedback Pin 2.
Positive Supply Voltage 2.
Output Common-Mode Voltage 2.
Positive Output 2.
Negative Output 2.
Power-Down Pin 2.
Negative Supply Voltage 2.
Output Common-Mode Voltage 1.
Positive Output 1.
Negative Output 1.
Power-Down Pin 1.
Negative Supply Voltage 1.
Negative Output Feedback Pin 1.
Positive Input Summing Node 1.
Exposed Paddle. The exposed pad is
not electrically connected to the
device. It is typically soldered to
ground or a power plane on the PCB
that is thermally conductive.
Data Sheet
ADA4937-1/ADA4937-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = 0 V, VOUT, dm = 2 V p-p, VOCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise
noted. Refer to Figure 49 for the test setup circuit.
6
0
–3
–6
–9
–12
1
10
100
1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
1
10
100
1000
VS = 3.3V
VS = 5.0V
–6
–9
0
–3
–6
–9
–12
10
100
1000
FREQUENCY (MHz)
–15
06591-008
1
100
1000
Figure 11. Large Signal Frequency Response for Various Supplies
6
+105°C
+25°C
–40°C
+105°C
+25°C
–40°C
3
CLOSED-LOOP GAIN (dB)
3
10
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response for Various Supplies,
VOUT, dm = 100 mV p-p
6
1
06591-011
CLOSED-LOOP GAIN (dB)
G = +1, RF = 200Ω
G = +2, RF = 402Ω
G = +5, RF = 402Ω
3
–12
CLOSED-LOOP GAIN (dB)
–12
6
VS = 5.0V
–3
0
–3
–6
–9
0
–3
–6
–9
1
10
100
FREQUENCY (MHz)
1000
–12
06591-009
–12
–9
Figure 10. Large Signal Frequency Response for Various Gains
0
–15
–6
FREQUENCY (MHz)
VS = 3.3V
3
–3
–15
Figure 7. Small Signal Frequency Response for Various Gains,
VOUT, dm = 100 mV p-p
6
0
Figure 9. Small Signal Frequency Response for Various Temperatures,
VOUT, dm = 100 mV p-p
1
10
100
FREQUENCY (MHz)
1000
06591-012
–15
G = +1, RF = 200Ω
G = +2, RF = 402Ω
G = +5, RF = 402Ω
3
06591-076
NORMALIZED CLOSED-LOOP GAIN (dB)
3
06591-075
NORMALIZED CLOSED-LOOP GAIN (dB)
6
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. F | Page 9 of 28
ADA4937-1/ADA4937-2
6
Data Sheet
6
RL = 1kΩ
RL = 100Ω
RL = 200Ω
3
CLOSED-LOOP GAIN (dB)
0
–3
100
1000
–9
100
1000
Figure 16. Large Signal Frequency Response for Various Loads
6
3
0
–3
–6
–9
VS = 3.3V, G = +1,
VS = 3.3V, G = +2,
VS = 3.3V, G = +5,
1
10
RF = 200Ω
RF = 402Ω
RF = 402Ω
100
1000
FREQUENCY (MHz)
0
–3
–6
–9
–12
–15
06591-077
–12
3
VS = 3.3V, G = +1,
VS = 3.3V, G = +2,
VS = 3.3V, G = +5,
1
RF = 200Ω
RF = 402Ω
RF = 402Ω
10
100
1000
FREQUENCY (MHz)
06591-079
NORMALIZED CLOSED-LOOP GAIN (dB)
6
NORMALIZED CLOSED-LOOP GAIN (dB)
10
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Loads,
VOUT, dm = 100 mV p-p
Figure 17. Large Signal Frequency Response for Various Gains, VS = 3.3 V
Figure 14. Small Signal Frequency Response for Various Gains,
VS = 3.3 V, VOUT, dm = 100 mV p-p
6
NORMALIZED CLOSED-LOOP GAIN (dB)
6
3
0
–3
–6
–9
–12
G = +1, RF = 348Ω
G = +2, RF = 348Ω
G = +5, RF = 348Ω
1
10
100
1000
FREQUENCY (MHz)
Figure 15. Small Signal Frequency Response for Various Gains,
VOUT, dm = 100 mV p-p, RF = 348 Ω
3
0
–3
–6
–9
–12
–15
06591-078
NORMALIZED CLOSED-LOOP GAIN (dB)
1
06591-016
10
06591-013
1
FREQUENCY (MHz)
–15
–3
–6
–6
–15
0
G = +1, RF = 348Ω
G = +2, RF = 348Ω
G = +5, RF = 348Ω
1
10
100
FREQUENCY (MHz)
1000
06591-080
CLOSED-LOOP GAIN (dB)
3
–9
RL = 1kΩ
RL = 100Ω
RL = 200Ω
Figure 18. Large Signal Frequency Response for Various Gains, RF = 348 Ω
Rev. F | Page 10 of 28
Data Sheet
3
–50
VOCM = 1.0V
VOCM = 2.5V
VOCM = 3.9V
0
VOCM CLOSED-LOOP GAIN (dB)
ADA4937-1/ADA4937-2
HD2,
HD3,
HD2,
HD3,
–60
G
G
G
G
= +1,
= +1,
= +2,
= +2,
RF = 200Ω
RF = 200Ω
RF = 402Ω
RF = 402Ω
DISTORTION (dBc)
–70
–3
–6
–80
–90
–100
–9
1
10
100
1000
FREQUENCY (MHz)
–120
06591-019
HD2,
HD3,
HD2,
HD3,
–60
RL = 1kΩ
RL = 1kΩ
RL = 200Ω
RL = 200Ω
DISTORTION (dBc)
–70
–80
–90
–100
1
10
100
1000
–120
–55
HD2,
HD3,
HD2,
HD3,
–60
–65
1
10
06591-023
–110
06591-020
GAIN (dB)
–50
100
FREQUENCY (MHz)
Figure 20. 0.1 dB Flatness Response for Various Loads
Figure 23. Harmonic Distortion vs. Frequency and Load
–50
VS = 5.0V
VS = 5.0V
VS = 3.3V
VS = 3.3V
–60
–70
HD2,
HD3,
HD2,
HD3,
VS = 3.3V
VS = 3.3V
VS = 5.0V
VS = 5.0V
–70
–75
DISTORTION (dBc)
DISTORTION (dBc)
100
Figure 22. Harmonic Distortion vs. Frequency and Gain
RL = 1kΩ, ADA4937-1
RL = 100Ω, ADA4937-1
RL = 1kΩ, ADA4937-2
RL = 100Ω, ADA4937-2
FREQUENCY (MHz)
–80
–85
–90
–95
–80
–90
–100
–110
–100
–105
–120
1
10
100
FREQUENCY (MHz)
06591-021
–110
–115
10
FREQUENCY (MHz)
Figure 19. Small Signal Frequency Response for Various VOCM
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
1
Figure 21. Harmonic Distortion vs. Frequency and Supply Voltage
–130
–1
0
1
2
3
4
5
6
VOUT (V)
Figure 24. Harmonic Distortion vs. VOUT and Supply Voltage
Rev. F | Page 11 of 28
7
06591-024
–12
06591-022
–110
ADA4937-1/ADA4937-2
–30
HD2,
HD3,
HD2,
HD3,
–40
DISTORTION (dBc)
–50
Data Sheet
0
f = 10MHz
f = 10MHz
f = 75MHz
f = 75MHz
–20
DISTORTION (dBc)
–60
–70
–80
–90
–40
–60
–80
–100
–100
1.5
2.0
2.5
3.0
3.5
4.0
VOCM (V)
–120
69.4
06591-025
–120
1.0
HD2,
HD3,
HD2,
HD3,
–50
69.8
70.0
70.2
70.4
70.6
FREQUENCY (MHz)
Figure 25. Harmonic Distortion vs. VOCM and Frequency
–40
69.6
06591-028
–110
Figure 28. 70 MHz Intermodulation Distortion
–30
f = 30MHz
f = 30MHz
f = 75MHz
f = 75MHz
RL = 200Ω
DISTORTION (dBc)
–40
CMRR (dB)
–60
–70
–50
–80
–60
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
VOCM (V)
–70
06591-026
–100
1.1
1
10
Figure 26. Harmonic Distortion vs. VOCM and Frequency, VS = 3.3 V
–50
HD2,
HD3,
HD2,
HD3,
–60
1000
Figure 29. CMRR vs. Frequency
–10
1V p-p
1V p-p
2V p-p
2V p-p
RL = 200Ω
–20
OUTPUT BALANCE (dB)
–70
–80
–90
–100
–110
–30
–40
–50
–130
1
10
100
FREQUENCY (MHz)
Figure 27. Harmonic Distortion vs. Frequency and VOUT, VS = 3.3 V
–60
1
10
100
FREQUENCY (MHz)
Figure 30. Output Balance vs. Frequency
Rev. F | Page 12 of 28
1000
06591-068
–120
06591-027
DISTORTION (dBc)
100
FREQUENCY (MHz)
06591-029
–90
Data Sheet
–30
ADA4937-1/ADA4937-2
28
VOUT, dm PSRR, VS = 3.3V
VOUT, dm PSRR, VS = 5.0V
–40
26
G = +1
G = +2
G = +4
24
NOISE FIGURE (dB)
PSRR (dB)
–50
–60
–70
–80
22
20
18
16
14
–90
10
100
1000
FREQUENCY (MHz)
10
10
0
Figure 34. Noise Figure vs. Frequency
5
S11
S22
3
–15
2
–20
–25
VOLTAGE (V)
–30
–35
–40
–45
1
0
–1
–2
–50
–3
–55
–4
–60
10
100
1000
FREQUENCY (MHz)
–5
06591-032
1
TIME (4ns/DIV)
Figure 32. Return Loss (S11, S22) vs. Frequency
–55
Figure 35. Overdrive Recovery Time (Pulse Input)
5
SFDR, RL = 1kΩ
SFDR, RL = 200Ω
–60
06591-069
S-PARAMETERS (dB)
VIN × 3.16
VOUT, dm
4
–10
–65
100
FREQUENCY (MHz)
Figure 31. PSRR vs. Frequency, RL = 200 Ω
–5
06591-034
1
06591-031
–100
12
VIN × 3
VOUT, dm
4
–65
3
–75
SIGNAL LEVEL (V)
–80
–85
–90
–95
–100
2
1
0
–1
–2
–3
–105
–4
–115
–5
1
10
100
FREQUENCY (MHz)
Figure 33. Spurious-Free Dynamic Range vs. Frequency and Load
06591-033
–110
+VS = +2.5V
–VS = –2.5V
0
100
200
300
TIME (ns)
400
500
600
06591-070
DISTORTION (dBc)
–70
Figure 36. Overdrive Amplitude Characteristics (Triangle Wave Input)
Rev. F | Page 13 of 28
Data Sheet
60
60
55
55
50
50
45
45
SUPPLY CURRENT (mA)
40
35
+105°C
30
+25°C
25
20
+55°C
0°C
15
–40°C
10
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
15
+55°C
–40°C
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
POWER-DOWN VOLTAGE (V)
Figure 40. Supply Current vs. PD for Various Temperatures, VS = 3.3 V
3.5
+VS = +2.5V
–VS = –2.5V
VOCM = 0V
0.15
3.0
2.5
VOUT, dm = 4V p-p
VOUT, dm = 2V p-p
+VS = +2.5V
–VS = –2.5V
VOCM = 0V
2.0
0.10
1.5
0.05
VOLTAGE (V)
0
–0.05
1.0
0.5
0
–0.5
–1.0
–1.5
–0.10
–2.0
–2.5
–0.15
06591-071
–3.0
TIME (1ns/DIV)
–3.5
TIME (1ns/DIV)
Figure 41. Large Signal Pulse Response
Figure 38. Small Signal Pulse Response
4.00
2.60
VS = +5V
G=1
RL, dm = 1kΩ
2.58
06591-074
VOLTAGE (V)
0°C
20
0
1.0
0.20
VS = +5V
G=1
RL, dm = 1kΩ
3.75
3.50
2.56
OUTPUT VOLTAGE (V)
3.25
2.54
2.52
2.50
2.48
2.46
2.44
3.00
2.75
2.50
2.25
2.00
1.75
1.50
2.42
1.25
TIME (2ns/DIV)
06591-072
OUTPUT VOLTAGE (V)
+105°C
25
06591-040
1.2
06591-037
1.1
Figure 37. Supply Current vs. PD for Various Temperatures
2.40
+25°C
30
5
POWER-DOWN VOLTAGE (V)
–0.20
35
10
5
0
1.0
40
1.00
TIME (2ns/DIV)
Figure 42. Large Signal VOCM Pulse Response
Figure 39. Small Signal VOCM Pulse Response
Rev. F | Page 14 of 28
06591-073
SUPPLY CURRENT (mA)
ADA4937-1/ADA4937-2
Data Sheet
ADA4937-1/ADA4937-2
10
10
G=1
9
8
POWER-DOWN PULSE
IMPEDANCE (Ω)
AMPLITUDE (V)
7
6
5
4
1
3
OUTPUT
2
0
0.5
1.0
1.5
2.0
2.5
0.1
0.01
0.1
1
TIME (ms)
10
100
1k
FREQUENCY (MHz)
Figure 43. PD Response vs. Time
Figure 46. Closed-Loop Output Impedance
2
–40
1.0
–50
VIN
INPUT2, OUTPUT1
–60
1
0.5
–70
SETTLING ERROR
–80
0
0.1
0
–0.1
–1
–0.5
VIN (V)
CROSSTALK (dB)
06591-146
–0.5
–90
–100
INPUT1, OUTPUT2
–110
SETTLING ERROR (%)
0
–1.0
06591-043
1
–120
100
1000
FREQUENCY (MHz)
–2
–1.0
TIME (1ns/DIV)
Figure 44. Crosstalk vs. Frequency for ADA4937-2
Figure 47. 0.1% Settling Time
OPEN-LOOP GAIN (dB)
70
10
50
60
PHASE
50
GAIN
0
–50
40
30
–100
20
–150
10
–200
0
–250
–10
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
06591-045
INPUT VOLTAGE NOISE (nV/ Hz)
100
Figure 45. Voltage Spectral Noise Density, RTI
–20
1
10
100
1k
10k
100k
1M
10M 100M
1G
–300
10G
FREQUENCY (Hz)
Figure 48. Open-Loop Gain and Phase vs. Frequency
Rev. F | Page 15 of 28
OPEN-LOOP PHASE (Degrees)
10
06591-401
1
06591-044
–140
0.3
06591-147
–130
ADA4937-1/ADA4937-2
Data Sheet
TEST CIRCUITS
200Ω
5V
50Ω
200Ω
VIN
VOCM
61.9Ω
ADA4937
1kΩ
200Ω
06591-046
27.5Ω
200Ω
Figure 49. Equivalent Basic Test Circuit
200Ω
5V
50Ω
200Ω
VIN
50Ω
VOCM
61.9Ω
ADA4937
200Ω
50Ω
06591-047
27.5Ω
200Ω
Figure 50. Test Circuit for Output Balance
200Ω
5V
VIN
FILTER
61.9Ω
0.1µF
200Ω
VOCM
412Ω
FILTER
ADA4937
0.1µF
200Ω
412Ω
27.5Ω
200Ω
Figure 51. Test Circuit for Distortion Measurements
Rev. F | Page 16 of 28
06591-048
50Ω
Data Sheet
ADA4937-1/ADA4937-2
TERMINOLOGY
–FB
+IN
VOCM
–DIN
Common-Mode Voltage
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
RF
–OUT
ADA4937
RG R
F
–IN
RL, dm VOUT, dm
+OUT
+FB
VOUT, cm = (V+OUT + V−OUT)/2
06591-049
+DIN
RG
Figure 52. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Output Balance
Output balance is a measure of how close the differential signals
are to being equal in amplitude and opposite in phase. Output
balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the midpoint of the
divider with the magnitude of the differential signal (see Figure 50).
By this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
Output Balance Error 
Rev. F | Page 17 of 28
VOUT , cm
VOUT , dm
ADA4937-1/ADA4937-2
Data Sheet
THEORY OF OPERATION
The ADA4937-1/ADA4937-2 differ from conventional
operational amplifiers in that they have two outputs whose voltages
move in opposite directions. Like an operational amplifier, they
rely on open-loop gain and negative feedback to force these
outputs to the desired voltages. The ADA4937-1/ADA4937-2
behave much like standard voltage feedback operational amplifiers,
which makes it easier to perform single-ended-to-differential
conversions, common-mode level shifting, and amplifications
of differential signals. Also like an operational amplifier, the
ADA4937-1/ADA4937-2 have high input impedance and low
output impedance.
Two feedback loops control the differential and common-mode
output voltages. The differential feedback loop, set with external
resistors, controls only the differential output voltage. The
common-mode feedback loop controls only the common-mode
output voltage. This architecture makes it easy to set the output
common-mode level to any arbitrary value. It is forced, by internal
common-mode feedback, to be equal to the voltage applied to
the VOCM input without affecting the differential output voltage.
The ADA4937-1/ADA4937-2 architecture results in outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. The commonmode feedback loop forces the signal component of the output
common-mode voltage to zero. This results in nearly perfectly
balanced differential outputs that are identical in amplitude and
are exactly 180° apart in phase.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 52 can be
determined by
VOUT , dm
VIN , dm

RF
RG
This assumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
To estimate the differential output noise of the ADA4937-1/
ADA4937-2 use the noise model in Figure 53. The input-referred
noise voltage density, vnIN, is modeled as a differential input, and
the noise currents, inIN− and inIN+, appear between each input and
ground. The noise currents are assumed to be equal and produce
a voltage across the parallel combination of the gain and feedback
resistances. vn, cm is the noise voltage density at the VOCM pin. Each
of the four resistors contributes (4kTRx)1/2. Table 9 summarizes
the input noise sources, the multiplication factors, and the outputreferred noise density terms.
VnRG1
RG1
VnRF1
RF1
inIN+
+
inIN–
VnIN
ADA4937
VnOD
The ADA4937-1/ADA4937-2 use open-loop gain and negative
feedback to force their differential and common-mode output
voltages in such a way as to minimize the differential and
common-mode error voltages. The differential error voltage is
defined as the voltage between the differential inputs labeled
+IN and −IN (see Figure 52). For most purposes, this voltage
can be assumed to be zero. Similarly, the difference between the
actual output common-mode voltage and the voltage applied to
VOCM can also be assumed to be zero. Starting from these two
assumptions, any application circuit can be analyzed.
VnRG2
RG2
RF2
VnCM
VnRF2
06591-050
VOCM
ANALYZING AN APPLICATION CIRCUIT
Figure 53. ADA4937-1/ADA4937-2 Noise Model
Table 9. Output Noise Voltage Density Calculations
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor RG1
Gain Resistor RG2
Feedback Resistor RF1
Feedback Resistor RF2
Input Noise Term
vnIN
inIN−
inIN+
vn, cm
vnRG1
vnRG2
vnRF1
vnRF2
Input Noise Voltage Density
vnIN
inIN− × (RG2||RF2)
inIN+ × (RG1||RF1)
vn, cm
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
Rev. F | Page 18 of 28
Output Multiplication Factor
GN
GN
GN
GN(β1 − β2)
GN(1 − β1)
GN(1 − β2)
1
1
Output Noise Voltage
Density Term
vnO1 = GN(vnIN)
vnO2 = GN[inIN− × (RG2||RF2)]
vnO3 = GN[inIN+ × (RG1||RF1)]
vnO4 = GN(β1 − β2)(vn, cm)
vnO5 = GN(1 − β1)(4kTRG1)1/2
vnO6 = GN(1 − β2)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
Data Sheet
ADA4937-1/ADA4937-2
RF
Similar to the case of a conventional operational amplifier, the
output noise voltage densities can be estimated by multiplying
the input-referred terms at +IN and −IN by the appropriate output
factor, where:
2
GN 
is the circuit noise gain.
β1  β2 
RG1
RG2
and β2 
are the feedback factors.
β1 
RF1  RG1
RF2  RG2
Figure 54. ADA4937-1/ADA4937-2 Configured for Balanced (Differential) Inputs
When RF1/RG1 = RF2/RG2, then β1 = β2 = β, and the noise gain
becomes
For an unbalanced, single-ended input signal (see Figure 55),
the input impedance is
+VS
–DIN
+IN
VOCM
RG
VOUT, dm
–IN
RF
1
R
1 F
β
RG
R IN , cm
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms.




R


G


RF

 1 
2  RG  R F  

RF
+VS
8
2
 vnOi
RG
RS
i 1
VOCM
RT
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
ADA4937
VOUT, dm
RG
As previously mentioned in the Setting the Closed-Loop Gain
section), even if the external feedback networks (RF/RG) are
mismatched, the internal common-mode feedback loop still
forces the outputs to remain balanced. The amplitudes of the
signals at each output remain equal and 180° out of phase. The
input-to-output differential mode gain varies proportionately to
the feedback mismatch, but the output balance is unaffected.
As well as causing a noise contribution from VOCM, ratio matching
errors in the external resistors result in a degradation of the
ability of the circuit to reject input common-mode signals, much
the same as for a four-resistor difference amplifier made from a
conventional operational amplifier.
In addition, if the dc levels of the input and output commonmode voltages are different, matching errors result in a small
differential-mode output offset voltage. When G = 1, with a
ground referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worstcase input CMRR of approximately 40 dB, a worst-case
differential-mode output offset of 25 mV due to 2.5 V level
shift, and no significant degradation in output balance error.
RS
RT
06591-052
vnOD 
RG
06591-051
+DIN
RF
Figure 55. ADA4937-1/ADA4937-2 Configured for Unbalanced
(Single-Ended) Input
The input impedance of the circuit is effectively higher than it is
for a conventional operational amplifier connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the Input Gain Resistor RG.
Terminating a Single-Ended Input
This section explains how to properly terminate a single-ended
input to the ADA4937-1/ADA4937-2. Using a simple example
with an input source of 2 V and a source resistor of 50 Ω, four
simple steps must be followed.
1.
The input impedance must be calculated using the formula
R IN
RF
RIN
267Ω
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 54, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
 


 


RG
200


  267 Ω





RF
200
1

1


 

2
(
200
200
)


R
R
2
(
)



F 
G

VS
2V
200Ω
+VS
RS
RG
50Ω
200Ω
VOCM
ADA4937
RL
200Ω
–VS
RF
200Ω
Figure 56. Single-Ended Input Impedance RIN
Rev. F | Page 19 of 28
VO
RG
06591-081
GN 
ADA4937
ADA4937-1/ADA4937-2
RF
For the source termination to be 50 Ω, the termination
resistor (RT) is calculated using RT||RIN = 50 Ω, which
makes RT equal to 61.9 Ω.
+VS
RS
RF
200Ω
+VS
50Ω
RS
VS
2V
VS
2V
RTS
27.4Ω
200Ω
RT
61.9Ω
RG
RT
61.9Ω
200Ω
VOCM
VOCM
ADA4937
RL
RF
Figure 60. Complete Single-Ended-to-Differential System
06591-082
–VS
RF
200Ω
Figure 57. Adding Termination Resistor RT
RS
RTH
VTH
1.1V
27.4Ω
06591-083
RT
61.9Ω
SETTING THE OUTPUT COMMON-MODE VOLTAGE
Figure 58. Calculating Thevenin Equivalent
RTS = RTH = RS||RT = 27.4 Ω. Note that VTH is not equal to VS/2,
which is the case if the termination is not affected by the
amplifier circuit.
RF
VTH
1.1V
RTH
RG
200Ω
VOCM
ADA4937
VO
RL 0.97V
RG
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kΩ. If multiple
ADA4937-1/ADA4937-2 devices share one reference output, it is
recommended that a buffer be used.
200Ω
–VS
RF
200Ω
06591-084
RTS
27.4Ω
Figure 59. Balancing Gain Resistor RG
4.
The feedback resistor is calculated to adjust the output
voltage.
a.
The VOCM pin of the ADA4937-1/ADA4937-2 is internally biased
at a voltage approximately equal to the midsupply point, [(+VS) +
(−VS)]/2. Relying on this internal bias results in an output
common-mode voltage that is within about 100 mV of the
expected value.
In cases where more accurate control of the output commonmode level is required, it is recommended that an external source,
or resistor divider (10 kΩ or greater resistors), be used. The output
common-mode offset listed in Table 2 and Table 4 assumes that the
VOCM input is driven by a low impedance voltage source.
200Ω
+VS
27.4Ω
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The ADA4937-1/ADA4937-2 are optimized for level-shifting
ground-referenced input signals. As such, the center of the input
common-mode range is shifted approximately 1 V down from
midsupply. For 5 V single-supply operation, the input commonmode range at the summing nodes of the amplifier is 0.3 V to
3.0 V, and 0.3 V to 1.2 V with a 3.3 V supply. To avoid clipping
at the outputs, the voltage swing at the +IN and −IN terminals
must be confined to these ranges.
To compensate for the imbalance of the gain resistors,
a correction resistor (RTS) is added in series with the
inverting Input Gain Resistor RG. RTS is equal to the
Thevenin equivalent of the Source Resistance RS||RT.
VS
2V
VO
–VS
VO
200Ω
50Ω
RL
200Ω
RG
3.
ADA4937
RG
RG
50Ω
50Ω
06591-085
2.
Data Sheet
Table 10 and Table 11 list several common gain settings, associated resistor values, input impedances, and output noise density
values for both balanced and unbalanced input configurations.
To make the output voltage VOUT = 1 V, RF must be
calculated using the following formula:
POWER-DOWN OPERATION
V
 (RG  RTS )   1  (200  27.4) 

RF   OUT
  207 Ω

 
VTH
1.1



To make VO = VS = 2 V to recover the loss due to the input
termination, RF must be
The ADA4937-1/ADA4937-2 power-down pin features an
internal 25 kΩ pull-up resistor to the positive supply (+VS).
This ensures that, with the power-down pin left unconnected
(floating), the ADA4937-1/ADA4937-2 turn on. Applying a
voltage of ≤1 V turns the ADA4937-1/ADA4937-2 off.
V
 (RG  RTS )   2  (200  27.4) 

RF   OUT
  414 Ω

 
VTH
1.1



Rev. F | Page 20 of 28
Data Sheet
ADA4937-1/ADA4937-2
Table 10. Differential Ground-Referenced Input, DC-Coupled, 1 kΩ Load; See Figure 54
Nominal Gain (dB)
0
6
10
14
RF (Ω)
200
402
402
402
RG (Ω)
200
200
127
80.6
RIN, dm (Ω)
400
400
254
161
Differential Output Noise Density (nV/√Hz)
5.8
9.6
12.1
16.2
Table 11. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω, RL = 1 kΩ; See Figure 55
Nominal Gain (dB)
0
6
10
14
1
RF (Ω)
200
402
402
402
RG1 (Ω)
200
200
127
80.6
RT (Ω)
61.9
60.4
66.5
76.8
RIN, cm (Ω)
267
301
205
138
RG2 (Ω)1
226
228
155
111
RG2 = RG1 + (RS||RT)
Rev. F | Page 21 of 28
Differential Output Noise Density (nV/√Hz)
5.5
8.6
10.1
12.2
ADA4937-1/ADA4937-2
Data Sheet
LAYOUT, GROUNDING, AND BYPASSING
As high speed devices, the ADA4937-1/ADA4937-2 are sensitive
to the PCB environment in which they operate. Realizing their
superior performance requires attention to the details of high
speed PCB design. This section shows a detailed example of
how the design issues of the ADA4937-1 is addressed.
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended that two parallel bypass capacitors (1000 pF and 0.1 μF) be used for each supply with the 1000 pF
capacitor placed closer to the device; further away, provide low
frequency bypassing using 10 μF tantalum capacitors from each
supply to ground.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4937-1 as possible.
However, the area near the feedback resistors (RF), input gain
resistors (RG), and the input summing nodes (Pin 2 and Pin 3)
must be cleared of all ground and power planes (see Figure 61).
Clearing the ground and power planes minimizes any stray capacitance at these nodes and prevents peaking of the response of
the amplifier at high frequencies.
Signal routing must be short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. When
routing differential signals over a long distance, keep PCB
traces close together and twist any differential wiring to minimize loop area. Doing this reduces radiated energy and makes
the circuit less susceptible to interference.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7.
1.30
0.80
06591-086
06591-087
1.30 0.80
Figure 62. Recommended PCB Thermal Attach Pad Dimensions (mm)
Figure 61. Ground and Power Plane Voiding in Vicinity of RF and RG
1.30
TOP METAL
GROUND PLANE
0.30
PLATED
VIA HOLE
06591-088
POWER PLANE
BOTTOM METAL
Figure 63. Cross-Section of 4-layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in mm)
Rev. F | Page 22 of 28
Data Sheet
ADA4937-1/ADA4937-2
HIGH PERFORMANCE ADC DRIVING
The ADA4937-1/ADA4937-2 are ideally suited for broadband IF
applications. The circuit in Figure 64 shows a front-end connection
for an ADA4937-1 driving an AD9445, 14-bit, 105 MSPS ADC.
The AD9445 achieves optimum performance when driven
differentially. The ADA4937-1/ADA4937-2 eliminate the need for
a transformer to drive the ADC and performs a single-endedto-differential conversion and buffering of the driving signal.
The signal generator has a symmetric, ground-referenced
bipolar output. The VOCM pin of the ADA4937-1/ADA4937-2
remains unconnected allowing the internal divider to set the
output common-mode voltage at midsupply; one half of the
common-mode voltage is fed back to the summing nodes, biasing
−IN and +IN at 1.25 V. For a common-mode voltage of 2.5 V,
each ADA4937-1/ADA4937-2 output swings between 2.0 V and
3.0 V, providing a 2 V p-p differential output.
The ADA4937-1/ADA4937-2 are configured with a single 5 V
supply and unity gain for a single-ended input to differential
output. The 61.9 Ω termination resistor, in parallel with the singleended input impedance of 267 Ω, provides a 50 Ω termination
for the source. The additional 26 Ω (226 Ω total) at the inverting
input balances the parallel impedance of the 50 Ω source and the
termination resistor driving the noninverting input.
The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.
The AD9445 is configured for a 2 V p-p full-scale input by
connecting the SENSE pin to AGND, as shown in Figure 64.
5V (A) 3.3V (A) 3.3V (D)
200Ω
5V
200Ω
61.9Ω
SIGNAL
GENERATOR
VOCM
0.1µF
+
AVDD2 AVDD1 DRVDD
AD9445
VIN–
BUFFER T/H
24.3Ω
ADA4937-1
226Ω
30nH
47pF
ADC
24.3Ω
0.1µF
30nH
14
VIN+
CLOCK/
TIMING
200Ω
REF
AGND
SENSE
06591-054
50Ω
Figure 64. Driving an AD9445, 14-Bit, 105 MSPS ADC
Rev. F | Page 23 of 28
ADA4937-1/ADA4937-2
Data Sheet
The circuit in Figure 66 shows a simplified front-end connection
for an ADA4937-1 driving an AD9246, 14-bit, 125 MSPS ADC.
The AD9246 achieves optimum performance when driven
differentially. The ADA4937-1/ADA4937-2 perform the singleended-to-differential conversion, eliminating the need for a
transformer to drive the ADC.
The AD9246 is set for a 2 V p-p full-scale input by connecting
the SENSE pin to AGND. The inputs of the AD9246 are biased
at 1 V by connecting the CML output, as shown in Figure 66.
The circuit was tested with a −1 dBFS signal at various frequencies.
Figure 65 shows a plot of the second- and third-order harmonic
distortion (HD2/HD3) vs. frequency.
The ADA4937-1/ADA4937-2 are configured with a single 5 V
supply and a gain of ~2 V/V for a single-ended input to
differential output. The 76.8 Ω termination resistor, in parallel
with the single-ended input impedance of 137 Ω, provides a 50 Ω
ac termination for the source. The additional 30 Ω (120 Ω total) at
the inverting input balances the parallel ac impedance of the
50 Ω source and the termination resistor driving the
noninverting input.
–75
The signal generator has a symmetric, ground-referenced bipolar
output. The VOCM pin of the ADA4937-1/ADA4937-2 remains
unconnected; therefore, the internal pull-ups set the output
common-mode voltage to midsupply. A portion of this is fed back
to the summing nodes, biasing −IN and +IN at 0.55 V. For a
common-mode voltage of 2.5 V, each ADA4937-1/ADA4937-2
output swings between 2.0 V and 3.0 V, providing a 2 V p-p
differential output.
–80
HD3
–85
HD2
–90
–95
–100
0
20
40
60
80
FREQUENCY (MHz)
200Ω
50Ω
10µF
90Ω
90Ω
10µF
+
ADA4937-1
200Ω
10pF
200Ω
10µF
76.8Ω
33Ω
AVDD
DRVDD
VIN–
AD9246
VIN+
33Ω
D13 TO
D0
AGND SENSE CML
06591-056
VIN
1.8V
5V
76.8Ω
10µF
120
Figure 65. HD2/HD3 for Combination of ADA4937-1/ADA4937-2 and
AD9246 ADC
The output is ac-coupled to a single-pole, low-pass filter. This
reduces the noise bandwidth of the amplifier and provides some
level of isolation from the switched capacitor inputs of the ADC.
50Ω
100
06591-055
HARMONIC DISTORTION (dBc)
G = +2
200Ω
Figure 66. Driving an AD9246, 14-Bit, 125 MSPS ADC
Rev. F | Page 24 of 28
Data Sheet
ADA4937-1/ADA4937-2
ended input impedance of 306 Ω, provides a 50 Ω termination for
the source. The additional 26 Ω (226 Ω total) at the inverting input
balances the parallel impedance of the 50 Ω source and the
termination resistor that drives the noninverting input. The signal
generator has a symmetric, ground-referenced bipolar output. The
VOCM pin is connected to the CML output of the AD9230, and sets
the output common mode of the ADA4937-1/ADA4937-2 at 1.4 V.
One third of the output common-mode voltage of the amplifier is
fed back to the summing nodes, biasing −IN and +IN at ~0.5 V.
For a common-mode voltage of 1.4 V, each ADA4937-1/
ADA4937-2 output swings between 1.09 V and 1.71 V,
providing a 1.25 V p-p differential output.
3.3 V OPERATION
The ADA4937-1/ADA4937-2 provide excellent performance in
3.3 V single-supply applications. Significant power savings can
be realized when the ADA4937-1/ADA4937-2 are used in
combination with a low voltage ADC.
The circuit in Figure 67 is an example of the ADA4937-1 driving
an AD9230, 12-bit, 250 MSPS ADC that is specified to operate with
a single 1.8 V supply. The performance of the ADC is optimized
when it is driven differentially, making the best use of the signal
swing available within the 1.8 V supply. The ADA4937-1/
ADA4937-2 perform the single-ended-to-differential conversion,
common-mode level-shifting, and buffering of the driving signal.
A third-order, 125 MHz, low-pass filter between the ADA4937-1/
ADA4937-2 and the AD9230 reduces the noise bandwidth of
the amplifier and isolates the driver outputs from the ADC inputs.
The ADA4937-1/ADA4937-2 are configured with a single 3.3 V
supply and a gain of 2 V/V for a single-ended input to differential
output. The 59 Ω termination resistor, in parallel with the single453Ω
1.8V
3.3V
VIN
200Ω
59Ω
VOCM
33Ω
+
ADA4937-1
10pF
56nH
AVDD
VIN–
DRVDD
AD9230
30pF
VIN+
33Ω
226Ω
56nH
AGND
D11 TO
D0
CML
06591-057
50Ω
453Ω
Figure 67. Driving an AD9230, 12-Bit, 250 MSPS ADC
Rev. F | Page 25 of 28
ADA4937-1/ADA4937-2
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
0.30
0.23
0.18
13
0.50
BSC
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.45
1.30 SQ
1.15
4
9
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
111808-A
TOP VIEW
5
8
0.50
0.40
0.30
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters
0.30
0.25
0.20
0.50
BSC
PIN 1
INDICATOR
24
19
18
1
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
13
12
2.20
2.10 SQ
2.00
6
7
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
06-11-2012-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 69. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADA4937-1YCPZ-R2
ADA4937-1YCPZ-RL
ADA4937-1YCPZ-R7
ADA4937-2YCPZ-R2
ADA4937-2YCPZ-RL
ADA4937-2YCPZ-R7
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
Z = RoHS Compliant Part.
Rev. F | Page 26 of 28
Package Option
CP-16-21
CP-16-21
CP-16-21
CP-24-10
CP-24-10
CP-24-10
Ordering Quantity
250
5,000
1,500
250
5,000
1,500
Branding
H1S
H1S
H1S
Data Sheet
ADA4937-1/ADA4937-2
NOTES
Rev. F | Page 27 of 28
ADA4937-1/ADA4937-2
Data Sheet
NOTES
©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06591-0-6/16(F)
Rev. F | Page 28 of 28