TI DAC8574IPW Quad, 16-bit, low-power, voltage output, i2c interface digital-to-analog converter Datasheet

DAC
853
4
®
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT,
I C INTERFACE DIGITAL-TO-ANALOG CONVERTER
2
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
The DAC8574 is a low-power, quad channel, 16-bit
buffered voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail output swing to be
achieved. The DAC8574 utilizes an I2C compatible two
wire serial interface supporting high-speed interface
mode with address support of up to sixteen DAC8574’s
for a total of 64 channels on the bus.
•
•
•
•
•
Micropower Operation: 950 µA at 5 V VDD
Power-On Reset to Zero
+2.7 V to +5.5 V Analog Power Supply
16-Bit Monotonic
Settling Time: 10µs to ±0.003% FSR
I2C™ Interface Up to 3.4 Mbps
Data Transmit Capability
On-Chip Output Buffer Amplifier, Rail-to-Rail
Operation
Double-Buffered Input Register
Address Support for up to Sixteen DAC8574s
Synchronous Update Support for up to 64
Channels
Operation From -40°C to 105°C
Small 16 Lead TSSOP Package
APPLICATIONS
•
Process Control
•
•
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Data Acquisition Systems
Closed-Loop Servo Control
PC Peripherals
Portable Instrumentation
VDD
The DAC8574 requires an external reference voltage
to set the output range of the DAC. The DAC8574
incorporates a power-on-reset circuit that ensures that
the DAC output powers up at zero volts and remains
there until a valid write takes place to the device. The
DAC8574 contains a power-down feature, accessed
via the internal control register, that reduces the current
consumption of the device to 200 nA at 5 V.
The low power consumption of this part in normal
operation makes it ideally suited to portable battery
operated equipment. The power consumption is less
than 5 mW at VDD = 5 V reducing to 1 µW in
power-down mode.
The DAC8574 is available in a 16-lead TSSOP package.
IOVDD
VREFH
Data
Buffer A
DAC
Register A
DAC A
VOUTA
VOUTB
VOUTC
Data
Buffer D
DAC
Register D
Buffer
Control
Register
Control
DAC D
VOUTD
18
SCL
I2C Block
Power-Down
Control Logic
SDA
Resistor
Network
8
A0
A1
GND
A2
A3
LDAC
VREFL
I2C is a trademark of Philips Corporation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2003, Texas Instruments Incorporated
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC8574
16-TSSOP
PW
-40°C TO +105°C
D8574I
ORDERING
NUMBER
TRANSPORT MEDIA
DAC8574IPW
90 Piece Tube
DAC8574IPWR
2000 Piece Tape and Reel
PIN DESCRIPTIONS
PW PACKAGE
(TOPVIEW)
PIN
NAME
VOUTA
1
16 A3
1
VOUTA
Analog output voltage from DAC A
VOUTB
2
15 A2
2
VOUTB
Analog output voltage from DAC B
VREFH
3
3
VREFH
Positive reference voltage input
VDD
4
4
VDD
5
Negative reference voltage input
5
VREFL
VREFL
6
11 SDA
6
GND
GND
Ground reference point for all circuitry on the
part
VOUTC
7
10 SCL
7
VOUTC
Analog output voltage from DAC C
VOUTD
8
9 LDAC
8
VOUTD
Analog output voltage from DAC D
9
LDAC
H/W synchronous VOUT update
10
SCL
Serial clock input
11
SDA
Serial data input
12
IOVDD
13
A0
Device address select - I2C
14
A1
Device address select - I2C
15
A2
Device address select - Extended
16
A3
Device address select - Extended
14 A1
13 A0
DAC8574
12 IOVDD
DESCRIPTION
Analog voltage supply input
I/O voltage supply input
ABSOLUTE MAXIMUM RATINGS (1)
VDD to GND
-0.3 V to +6 V
Digital input voltage to GND
-0.3 V to VDD + 0.3 V
VOUT to GND
0.3 V to VDD + 0.3 V
Operating temperature range
40°C to +105°C
Storage temperature range
65°C to +150°C
Junction temperature range (TJ max)
Power dissipation:
Lead temperature, soldering:
(1)
2
+150°C
Thermal impedance (ΘJA)
118°C/W
Thermal impedance (ΘJC)
29°C/W
Vapor phase (60s)
215°C
Infrared (15s)
220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified.
PARAMETER
STATIC PERFORMANCE (1) (2)
TEST CONDITIONS
Resolution
MIN
TYP
UNITS
± 0.0987
% of FSR
±1
LSB
16
Bits
Relative accuracy
Differential nonlinearity
MAX
Specified monotonic by design
Zero-scale error
5
20
mV
Full-scale error
-0.15
±1.0
% of FSR
± 1.0
% of FSR
Gain error
Zero code error drift
±7
µV/°C
Gain temperature coefficient
±3
ppm of FSR/°C
0.75
mV/V
PSRR
VDD = 5 V
OUTPUT CHARACTERISTICS (3)
Output voltage range
Output voltage settling time (full scale)
0
Digital-to-analog glitch impulse
12
µs
1
V/µs
0.25
LSB
1 kHz Sine Wave
-100
RL= ∞
470
RL= 2 kΩ
1000
pF
1 LSB change around major carry
20
nV-s
0.5
nV-s
Digital feedthrough
DC output impedance
Short-circuit current
Power-up time
µs
RL = 2 kΩ; CL = 500 pF
DC crosstalk
Capacitive load stability
V
10
8
Slew rate
AC crosstalk
VREFH
RL = 2 kΩ; 0 pF < CL < 200 pF
VDD= 5 V
-96
dB
pF
1
Ω
50
mA
VDD= 3 V
20
mA
Coming out of power-down mode, VDD=
+5 V
2.5
µs
Coming out of power-down mode, VDD=
+3 V
5
µs
REFERENCE INPUT
VREFH Input range
VREFL Input range
0
VREFL < VREFH
0
Reference input impedance
Reference current
VDD
GND
VDD
35
V
V
kΩ
VREF=VDD= +5 V
135
180
VREF=VDD= +3 V
80
120
µA
LOGIC INPUTS (3)
Input current
VIN_L, Input low voltage
VIN_H, Input high voltage
VDD= 3 V
±1
µA
0.3xIOVDD
V
3
pF
5.5
V
1600
µA
0.7xIOVDD
V
Pin Capacitance
POWER REQUIREMENTS
VDD, IOVDD
IDD(normal operation)
IDD@ VDD=+3.6V to +5.5V
(1)
(2)
(3)
2.7
Excluding load current
VIH= IOVDDand VIL=GND
950
Linearity tested using a reduced code range of 485 to 64714; output unloaded.
VREFH = VDD - 0.1 V, VREFL = GND
Specified by design and characterization, not production tested.
3
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
IDD@ VDD =+2.7V to +3.6V
MIN
TYP
MAX
UNITS
VIH= IOVDDand VIL=GND
900
1500
µA
IDD@ VDD=+3.6V to +5.5V
VIH= IOVDDand IOVIL=GND
0.2
1
µA
IDD@ VDD =+2.7V to +3.6V
VIH= VDDand VIL=GND
0.05
1
µA
ILOAD= 2 mA, VDD= +5 V
93%
+105
°C
IDD (all power-down modes)
POWER EFFICIENCY
IOUT/IDD
TEMPERATURE RANGE
Specified performance
-40
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.
SYMBOL
fSCL
PARAMETER
SCL clock frequency
TEST CONDITIONS
MAX
UNITS
Standard mode
MIN
100
kHz
Fast mode
400
kHz
High-Speed Mode, CB = 100 pF
max
3.4
MHz
1.7
MHz
High-speed mode, CB = 400 pF max
tBUF
tHD; tSTA
tLOW
tHIGH
tSU; tSTA
tSU; tDAT
tHD; tDAT
tRCL
4
Bus free time between a
STOP and START condition
Hold time (repeated) START
condition
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated
START condition
Data setup time
Data hold time
Rise time of SCL signal
Standard mode
TYP
4.7
µs
Fast mode
1.3
µs
Standard mode
4.0
µs
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
4.7
µs
Fast mode
1.3
µs
High-speed mode, CB = 100 pF max
160
ns
High-speed mode, CB = 400 pF max
320
ns
Standard mode
4.0
µs
Fast mode
600
ns
High-Speed Mode, CB = 100 pF
max
60
ns
High-speed mode, CB = 400 pF max
120
ns
Standard mode
4.7
µs
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
250
ns
ns
Fast mode
100
High-speed mode
10
Standard mode
0
3.45
µs
ns
Fast mode
0
0.9
µs
High-speed mode, CB = 100 pF max
0
70
ns
High-speed mode, CB = 400 pF max
0
150
ns
Standard mode
20 × 0.1CB
1000
ns
Fast mode
20 × 0.1CB
300
ns
High-speed mode, CB = 100 pF max
10
40
ns
High-speed mode, CB = 400 pF max
20
80
ns
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
TIMING CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.
SYMBOL
tRCL1
tFCL
tRDA
tFDA
tSU; tSTO
PARAMETER
Standard mode
Rise time of SCL signal after a
Fast mode
repeated START condition
High-speed
mode,
CB = 100 pF max
and after an acknowledge BIT
High-speed mode, CB = 400 pF max
Fall time of SCL signal
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
CB
Capacitive load for SDA and
SCL
tSP
Pulse width of spike suppressed
VNH
Noise margin at the HIGH
level for each connected device (including hysteresis)
VNL
TEST CONDITIONS
Noise margin at the LOW level
for each connected device
(including hysteresis)
MIN
TYP
MAX
UNITS
20 × 0.1CB
1000
ns
20 × 0.1CB
300
ns
10
80
ns
20
160
ns
Standard mode
20 × 0.1CB
300
ns
Fast mode
20 × 0.1CB
300
ns
High-speed mode, CB = 100 pF max
10
40
ns
High-speed mode, CB = 400 pF max
20
80
ns
Standard mode
20 × 0.1CB
1000
ns
Fast mode
20 × 0.1CB
300
ns
ns
High-speed mode, CB = 100 pF max
10
80
High-speed mode, CB = 400 pF max
20
160
ns
Standard mode
20 × 0.1CB
300
ns
Fast mode
20 × 0.1CB
300
ns
High-speed mode, CB = 100 pF max
10
80
ns
High-speed mode, CB = 400 pF max
20
160
ns
Standard mode
4.0
µs
Fast mode
600
ns
High-speed mode
160
ns
400
pF
Fast mode
50
ns
High-speed mode
10
ns
Standard mode
Fast mode
0.2 VDD
V
0.1 VDD
V
High-speed mode
Standard mode
Fast mode
High-speed mode
5
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise noted.
64
48
32
16
0
- 16
- 32
- 48
- 64
Channel A
V DD = 5 V
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LE - LSB
LE - LSB
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
Channel B
0.5
0
- 0.5
0.5
0
- 0.5
-1
0000 H 2000 H 4000 H 6000 H 8000 H A000 H C000H E000 H FFFFH
-1
0000 H 2000 H 4000 H 6000 H 8000 H A000 H C000H E000 H FFFFH
Digital Input Code
Digital Input Code
Figure 1.
Figure 2.
64
48
32
16
0
- 16
- 32
- 48
- 64
Channel C
VDD = 5 V
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LE - LSB
LE - LSB
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
64
48
32
16
0
- 16
- 32
- 48
- 64
Channel D
0.5
0
- 0.5
0.5
0
- 0.5
-1
0000 H 2000 H 4000 H 6000 H 8000 H A000 H C000H E000 H FFFFH
-1
0000 H 2000 H 4000 H 6000 H 8000 H A000 H C000H E000 H FFFFH
Digital Input Code
Digital Input Code
Figure 3.
Figure 4.
64
48
32
16
0
- 16
- 32
- 48
- 64
Channel A
V DD = 2.7 V
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LE - LSB
LE - LSB
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
64
48
32
16
0
- 16
- 32
- 48
- 64
Channel B
VDD = 2.7 V
1
DLE - LSB
1
DLE - LSB
VDD = 5 V
1
DLE - LSB
DLE - LSB
1
0.5
0
- 0.5
0.5
0
- 0.5
-1
0000 H 2000 H 4000 H 6000 H 8000 H A000 H C000H E000 H FFFFH
-1
0000 H 2000 H 4000 H 6000 H 8000 H A000 H C000H E000 H FFFFH
Digital Input Code
Digital Input Code
Figure 5.
6
VDD = 5 V
1
DLE - LSB
DLE - LSB
1
64
48
32
16
0
- 16
- 32
- 48
- 64
Figure 6.
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
64
48
32
16
0
- 16
- 32
- 48
- 64
Channel C
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
VDD = 2.7 V
LE - LSB
LE - LSB
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
Channel D
VDD = 2.7 V
1
DLE - LSB
DLE - LSB
1
64
48
32
16
0
- 16
- 32
- 48
- 64
0.5
0
- 0.5
0.5
0
- 0.5
-1
0000 H 2000 H 4000 H 6000 H 8000 H A000 H C000H E000 H FFFFH
-1
0000 H 2000 H 4000 H 6000 H 8000 H A000 H C000H E000 H FFFFH
Digital Input Code
Digital Input Code
Figure 7.
Figure 8.
ZERO-SCALE ERROR
vs TEMPERATURE
ZERO-SCALE ERROR
vs TEMPERATURE
10
14
CH D
8
Zero -Scale Error - mV
Zero -Scale Error - mV
12
CH A
10
CH B
8
6
CH C
4
CH D
CH A
6
CH B
4
2
CH C
0
2
VDD = VREF = 2.7 V
VDD = VREF = 5 V
-2
0
- 40
- 10
20
50
80
- 40
110
- 10
TA - Free-Air Temperature - °C
20
50
80
TA - Free-Air Temperature - °C
Figure 9.
Figure 10.
FULL-SCALE ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
15
15
To avoid clipping of the output signal
during the test, VREF = VDD - 10 mV,
V DD = 2.7 V, VREF = 2.69 V
CH D
10
10
Full- Scale Error - mV
Full- Scale Error - mV
110
To avoid clipping of the output signal
during the test, VREF = VDD - 10 mV,
V DD = 5 V, VREF = 4.99 V
5
CH B
0
CH A
-5
CH C
- 10
CH A
0
CH B
-5
CH C
- 10
- 15
- 40
CH D
5
- 15
- 10
20
50
80
TA - Free-Air Temperature - °C
Figure 11.
110
- 40
- 10
20
50
80
110
TA - Free-Air Temperature - °C
Figure 12.
7
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
PULLDOWN CAPABILITY
vs SINK CURRENT
PULLDOWN CAPABILITY
vs SINK CURRENT
0.15
0.15
Channel B
0.125
VOUT - Output Voltage - V
VOUT - Output Voltage - V
Channel A
V DD = 2.7 V
0.1
0.075
VDD = 5 V
0.05
VREF = VDD - 10 mV
0.025
DAC Loaded With 0000
0.125
0.1
V DD = 2.7 V
0.075
VDD = 5 V
0.05
VREF = VDD - 10 mV
0.025
DAC Loaded With 0000
H
0
0
1
2
3
4
5
0
1
ISINK - Sink Current - mA
3
5
PULLDOWN CAPABILITY
vs SINK CURRENT
0.15
0.15
Channel C
Channel D
VOUT - Output Voltage - V
0.125
0.1
V DD = 2.7 V
0.075
VDD = 5 V
0.05
VREF = VDD - 10 mV
0.025
DAC Loaded With 0000
0.125
0.1
V DD = 2.7 V
0.075
VDD = 5 V
0.05
VREF = VDD - 10 mV
0.025
DAC Loaded With 0000
H
0
H
0
0
1
2
3
4
5
0
1
ISINK - Sink Current - mA
2
3
4
5
ISINK - Sink Current - mA
Figure 15.
Figure 16.
PULLUP CAPABILITY
vs SOURCE CURRENT
PULLUP CAPABILITY
vs SOURCE CURRENT
5
5
Channel B
VOUT - Output Voltage - V
Channel A
VOUT - Output Voltage - V
4
Figure 14.
PULLDOWN CAPABILITY
vs SINK CURRENT
VOUT - Output Voltage - V
2
ISINK - Sink Current - mA
Figure 13.
4.95
4.9
VREF = VDD - 10 mV
DAC Loaded With FFFF H
4.85
4.95
4.9
VREF = VDD - 10 mV
DAC Loaded With FFFF H
4.85
VDD = 5 V
VDD = 5 V
4.8
4.8
0
8
H
0
1
2
3
4
5
0
1
2
3
ISOURCE - Source Current - mA
ISOURCE - Source Current - mA
Figure 17.
Figure 18.
4
5
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
PULLUP CAPABILITY
vs SOURCE CURRENT
PULLUP CAPABILITY
vs SOURCE CURRENT
5
5
Channel D
VOUT - Output Voltage - V
VOUT - Output Voltage - V
Channel C
4.95
4.9
VREF = VDD - 10 mV
DAC Loaded With FFFF H
4.85
4.95
4.9
VREF = VDD - 10 mV
DAC Loaded With FFFF H
4.85
VDD = 5 V
VDD = 5 V
4.8
4.8
0
1
2
3
4
5
0
1
2
3
ISOURCE - Source Current - mA
ISOURCE - Source Current - mA
Figure 19.
Figure 20.
PULLUP CAPABILITY
vs SOURCE CURRENT
2.7
Channel B
VOUT - Output Voltage - V
Channel A
VOUT - Output Voltage - V
5
PULLUP CAPABILITY
vs SOURCE CURRENT
2.7
2.65
2.6
VREF = VDD - 10 mV
DAC Loaded With FFFF H
2.55
2.65
2.6
VREF = VDD - 10 mV
DAC Loaded With FFFF H
2.55
VDD = 2.7 V
VDD = 2.7 V
2.5
2.5
0
1
2
3
4
5
0
1
2
3
4
ISOURCE - Source Current - mA
ISOURCE - Source Current - mA
Figure 21.
Figure 22.
PULLUP CAPABILITY
vs SOURCE CURRENT
5
PULLUP CAPABILITY
vs SOURCE CURRENT
2.7
2.7
Channel D
VOUT - Output Voltage - V
Channel C
VOUT - Output Voltage - V
4
2.65
2.6
VREF = VDD - 10 mV
DAC Loaded With FFFF H
2.55
2.65
2.6
VREF = VDD - 10 mV
DAC Loaded With FFFF H
2.55
VDD = 2.7 V
VDD = 2.7 V
2.5
2.5
0
1
2
3
4
5
0
1
2
3
ISOURCE - Source Current - mA
ISOURCE - Source Current - mA
Figure 23.
Figure 24.
4
5
9
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs DIGITAL INPUT CODE
SUPPLY CURRENT
vs TEMPERATURE
1200
1200
VDD = V REF = 5 V
V DD = V REF = 5 V
1000
800
600
VDD = V REF = 2.7 V
400
200
0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
800
V DD = V
Reference Current Included
All Channels Powered, No Load
400
200
0
- 40
20
- 10
Digital Input Code
110
Figure 26.
SUPPLY CURRENT
vs SUPPLY VOLTAGE
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
1750
µA
1000
- Supply Current -
950
900
850
800
TA = 25C, A0 Input (All Other Inputs = GND)
Reference Current Included
1650
1550
1450
IOVDD = 5 V
1350
1250
1150
DD
750
I DD + IOI
700
650
600
1050
VDD = VREF = 2.7 V
950
850
750
2.7
3.05
3.4
3.75
4.1
4.45
4.8
VDD - Supply Voltage - V
5.15
0
5.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VLOGIC - Logic Input Voltage - V
Figure 27.
Figure 28.
HISTOGRAM OF CURRENT CONSUMPTION
HISTOGRAM OF CURRENT CONSUMPTION
1500
1500
V DD = V REF = 5 V
Reference Current Included
1000
VDD = VREF = 2.7 V
Reference Current Included
I DD - Current Consumption -
Figure 29.
µA
I
DD
- Current Consumption -
Figure 30.
µA
1060
1030
1000
970
940
910
820
790
760
1150
1120
1090
1060
1030
1000
970
940
910
880
0
850
0
820
500
790
500
730
Frequency
Frequency
1000
880
I DD - Supply Current -µ A
80
50
TA - Free - Air Temperature - oC
Figure 25.
10
= 2.7 V
REF
600
850
I DD - Supply Current
-µ A
I DD - Supply Current -µ A
1000
DAC8574
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
OUTPUT GLITCH (Mid-Scale)
2.53
VDD = VREF = 5 V
Power- Up Code = FFFFH
2.52
2.51
VOUT (V, 10 mV/div)
VOUT - Output Voltage - V
EXITING POWER-DOWN MODE
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
- 0.5
2.50
2.49
2.48
2.47
2.46
2.45
2.44
2.43
Time (4 µs/div)
Time (1µs/div)
Figure 31.
Figure 32.
OUTPUT GLITCH (Worst Case)
VOUT (V, 20 mV/div)
4.70
4.68
ABSOLUTE ERROR
20
VDD = VREF = 5 V
Code EFFFH to F000H to EFFFH
(Glitch Occurs Every N • 4096
Code Boundary)
VDD = VREF = 5 V
TA = 25°C
18
16
Output Error - mV
4.72
VDD = VREF = 5 V
Code 7FFFH to 8000H to 7FFFH
(Glitch Occurs Every N • 4096
Code Boundary)
4.66
4.64
4.62
4.60
Channel D Output
14
Channel B Output
12
10
8
6
4.58
4
4.56
2
Channel A Output
Channel C Output
0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
4.54
Time (1µs/div)
Digital Input Code
Figure 33.
Figure 34.
FULL-SCALE SETTLING TIME
(Large Signal)
ABSOLUTE ERROR
6
VDD = VREF = 2.7 V
TA = 25°C
8
Output Error - mV
6
4
Channel B Output
Channel D Output
2
0
-2
-4
-6
-8
Channel A Output
VOUT - Output Voltage - V
10
VDD = VREF = 5.5 V
Output Loaded with
2 kΩ and 200 pF
to GND
5
4
3
2
1
Channel C Output
- 10
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0
Time (12 µs/div)
Digital Input Code
Figure 35.
Figure 36.
11
DAC8574
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
HALF-SCALE SETTLING TIME
(Large Signal)
VDD = VREF = 5 V
Output Loaded with
2 kΩ and 200 pF
to GND
2.5
2.0
1.5
1.0
0.5
3.5
VDD = VREF = 2.7 V
Output Loaded with
2 kΩ and 200 pF
to GND
3.0
VOUT - Output Voltage - V
VOUT - Output Voltage - V
3.0
FULL-SCALE SETTLING TIME
(Large Signal)
2.5
2.0
1.5
1.0
0.5
0.0
0.0
Time (12 µs/div)
Time (12 µs/div)
Figure 37.
Figure 38.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
HALF-SCALE SETTLING TIME
SNR - Signal - to - Noise Ratio - dB
VOUT - Output Voltage - V
98
1.50
1.00
VDD = VREF = 2.7 V
Output Loaded with
2 kΩ and 200 pF to
GND
0.50
96
VDD = 5 V
94
92
VDD = 2.7 V
90
88
VDD = VREF
- 1 dB FSR Digital Input, F S = 52 ksps
Measurement Bandwidth = 20 kHz
86
0.00
Time (12 µs/div)
84
0
500
1k
1.5k
2k
2.5k
3k
3.5k
4k
4.5k
f - Output Frequency - Hz
Figure 39.
Figure 40.
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
0
0
VDD = VREF = 5 V
FS = 52 ksps, - 1 dB FSR Digital Input
Measurement Bandwidth = 20 kHz
- 20
- 30
- 40
THD
- 50
- 60
- 70
- 80
3rd Harmonic
- 90
2nd Harmonic
- 100
- 20
- 30
- 40
THD
- 50
- 60
- 70
- 80
- 90
2nd Harmonic
3rd Harmonic
-100
0
500
1k
1.5k
2k
2.5k
3k
f - Output Frequency - Hz
Figure 41.
12
VDD = VREF = 2.7 V
FS = 52 ksps, - 1 dB FSR Digital Input
Measurement Bandwidth = 20 kHz
- 10
THD - T otal Harmonic Distortion - dB
THD - T otal Harmonic Distortion - dB
- 10
3.5k
4k
0
500
1k
1.5k
2k
2.5k
3k
f - Output Frequency - Hz
Figure 42.
3.5k
4k
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
Small- Signal Settling Time
5mV/div
Trigger Signal
Time (2µs/div)
Figure 43.
FULL-SCALE SETTLING TIME
(Small-Signal-Negative Going Step)
Output Voltage
Output Voltage
FULL-SCALE SETTLING TIME
(Small-Signal-Positive Going Step)
Small- Signal Settling Time
5mV/div
Trigger Signal
Time (2µs/div)
Figure 44.
13
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THEORY OF OPERATION
D/A SECTION
The architecture of the DAC8574 consists of a string DAC followed by an output buffer amplifier. Figure 45
shows a generalized block diagram of the DAC architecture.
VREFH
50 k
50 k
70 k
_
Ref+
Resistor String
Ref-
DAC Register
+
VOUT
VREFL
Figure 45. R-String DAC Architecture
The input coding to the DAC8574 is unsigned binary, which gives the ideal output voltage as:
V OUT VREFL (VREFH VREFL) D
65536
(1)
Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to
65535.
RESISTOR STRING
The resistor string section is shown in Figure 46. It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
To Output
Amplifier
VREFH
VREFL
R
R
R
R
Figure 46. Typical Resistor String
Output Amplifier
The output buffer is a gain-of-2 noninverting amplifiers, capable of generating rail-to-rail voltages on its output,
which gives an output range of 0V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND.
The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs
with a half-scale settling time of 8 µs with the output unloaded.
I2C Interface
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.
14
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DAC8574
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THEORY OF OPERATION (continued)
The DAC8574 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data
transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in
this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as
HS-mode. The DAC8574 supports 7-bit addressing; 10-bit addressing, and general call address are not
supported.
F/S-Mode Protocol
•
•
•
•
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 47. All I2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 48). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 49) by pulling the SDA line low
during the entire high period of the 9th SCL cycle. Upon detecting this acknowledge, the master knows that
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 47). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
H/S-Mode Protocol
•
•
•
When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.
The master generates a start condition followed by a valid serial byte containing H/S master code
00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to
acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to
support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated
start conditions should be used to secure the bus in H/S-mode.
15
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THEORY OF OPERATION (continued)
SDA
SDA
SCL
SCL
S
P
Start
Condition
Stop
Condition
Figure 47. START and STOP Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 48. Bit Transfer on the I2C Bus
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
S
9
Clock Pulse for
Acknowledgement
START
Condition
Figure 49. Acknowledge on the I2C Bus
16
8
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Recognize STOP or
REPEATED START
Condition
Recognize START or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
MSB
Acknowledgement
Signal From Slave
Sr
Address
R/W
SCL
S
or
Sr
1
2
7
8
9
ACK
1
2
3-8
9
ACK
Sr
or
P
Clock Line Held Low While
Interrupts are Serviced
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Figure 50. Bus Protocol
DAC8574 I2C Update Sequence
The DAC8574 requires a start condition, a valid I2C address, a control byte, an MSB byte, and an LSB byte for a
single update. After the receipt of each byte, DAC8574 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I2C address selects the DAC8574. The control byte sets the operational
mode of the selected DAC8574. Once the operational mode is selected by the control byte, DAC8574 expects an
MSB byte followed by an LSB byte for data update to occur. DAC8574 performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
Control byte needs not to be resent until a change in operational mode is required. The bits of the control byte
continuously determine the type of update performed. Thus, for the first update, DAC8574 requires a start
condition, a valid I2C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,
DAC8574 needs an MSB byte and an LSB byte as long as the control command remains the same.
Using the I2C high-speed mode (fscl= 3.4 MHz), the clock running at 3.4 MHz, each 16-bit DAC update other than
the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge
signal), at 188.88 KSPS. Using the fast mode (fscl= 400 kHz), clock running at 400 kHz, maximum DAC update
rate is limited to 22.22 KSPS. Once a stop condition is received DAC8574 releases the I2C bus and awaits a new
start condition.
Address Byte
MSB
1
LSB
0
0
1
1
A1
A0
R/W
The address byte is the first byte received following the START condition from the master device. The first five
bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select
bits A1 and A0. The A1, A0 address inputs can be connected to VDD or digital GND, or can be actively driven by
TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of
the DAC8574. Up to 16 devices (DAC8574) can still be connected to the same I2C-Bus.
17
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Broadcast Address Byte
MSB
LSB
1
0
0
1
0
0
0
0
Broadcast addressing is also supported by DAC8574. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC8574 devices. DAC8574 is designed to work with other members of the
DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address,
DAC8574 responds regardless of the states of the address pins. Broadcast is supported only in write mode
(Master writes to DAC8574).
Control Byte
MSB
LSB
A3
A2
L1
L0
X
Sel1
Sel0
PD0
Table 1. Control Register Bit Descriptions
Bit Name
Extended Address Bit
A2
Extended Address Bit
L1
Load1 (Mode Select) Bit
L2
Load0 (Mode Select) Bit
The state of these bits must match the state of pins A3 and A2 in order for a
proper DAC8574 data update, except in broadcast update mode.
Are used for selecting the update mode.
00
Store I2C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the
temporary register of a selected channel. This mode does not change the DAC output of the selected
channel.
01
Update selected DAC with I2C data. Most commonly utilized mode. The contents of MS-BYTE and
LS-BYTE (or power down information) are stored in the temporary register and in the DAC register of
the selected channel. This mode changes the DAC output of the selected channel with the new data.
10
4-Channel synchronous update. The contents of MS-BYTE and LS-BYTE (or power down information)
are stored in the temporary register and in the DAC register of the selected channel. Simultaneously,
the other three channels get updated with previously stored data from the temporary register. This
mode updates all four channels together.
11
Broadcast update mode. This mode has two functions. In broadcast mode, DAC8574 responds
regardless of local address matching, and channel selection becomes irrelevant as all channels update.
This mode is intended to enable up to 64 channels simultaneous update, if used with the I2C broadcast
address (1001 0000).
Sel1
Buff Sel1 Bit
Sel0
Buff Sel0 Bit
PD0
18
Bit Number/Description
A3
If Sel1=0
All four channels are updated with the contents of their temporary register
data.
If Sel1=1
All four channels are updated with the MS-BYTE and LS-BYTE data or
powerdown.
Channel Select Bits
00
Channel A
01
Channel B
10
Channel C
11
Channel D
Power Down Flag
0
Normal operation
1
Power-down flag (MSB7 and MSB6 indicate a power-down operation, as shown in Table 2).
DAC8574
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Table 2. Control Byte
C7
A3
C6
A2
C5
C4
C3
Load1
Load0
Don’t
Care
C2
Ch Sel 1
0
0
X
0
0
0
0
C1
C0
MSB7
MSB6
MSB5...
Ch Sel 0
PD0
MSB
(PD1)
MSB-1
(PD2)
MSB-2
...LSB
0
0
0
Data
Write to temporary
register A (TRA) with
data
X
0
1
0
Data
Write to temporary
register B (TRB) with
data
0
X
1
0
0
Data
Write to temporary
register C (TRC) with
data
0
X
1
1
0
Data
Write to temporary
register D (TRD) with
data
DESCRIPTION
(Address Select)
(A3 and A2
should correspond to the
package address set via
pins A3 and
A2.)
(00, 01, 10, or 11)
0
0
X
0
1
X
0
1
X
1
0
X
1
0
X
1
see Table 8
0
(00, 01, 10, or 11)
0
Write to TRx (selected
by C2 &C1 and load
DACx w/data
Data
(00, 01, 10, or 11)
1
see Table 8
0
(00, 01, 10, or 11)
0
see Table 8
Power-down DACx
(selected by C2 and
C1)
Write to TRx (selected
by C2 &C1 w/ data and
load all DACs
Data
(00, 01, 10, or 11)
1
Write to TRx (selected
by C2 &C1
w/Powerdown Command
0
Power-down DACx
(selected by C2 and
C1) & load all DACs
Broadcast Modes (controls up to 4 devices on a single serial bus)
X
X
1
1
X
0
X
X
X
Update all DACs, all
devices with previously
stored TRx data
X
X
1
1
X
1
X
0
Data
Update all DACs, all
devices with MSB[7:0]
and LSB[7:0] data
X
X
1
1
X
1
X
1
see Table 8
0
Power-down all DACs,
all devices
Most Significant Byte
Most Significant Byte MSB[7:0] consists of eight most significant bits of 16-bit unsigned binary D/A conversion
data. C0=1, MSB[7], MSB[6] indicate a powerdown operation as shown in Table 8.
Least Significant Byte
Least Significant Byte LSB[7:0] consists of the 8 least significant bits of the 16bit unsigned binary D/A conversion
data. DAC8574 updates at the falling edge of the acknowledge signal that follows the LSB[0] bit.
Default Readback Condition
If the user initiates a readback of a specified channel without first writing data to that specified channel, the
default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase.
19
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LDAC Functionality
Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal
that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the
channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four
DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only
be used after the buffers temporary registers are properly updated through software.
DAC8574 Registers
Table 3. DAC8574 Architecture Register Descriptions
Register
Description
CTRL[7:0]
Stores 8-bit wide control byte sent by the master
MSB[7:0]
Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit
power-down data.
LSB[7:0]
Stores the 8 least significant bits of unsigned binary data sent by the master.
TRA[17:0], TRB[17:0],
TRC[17:0], TRD[17:0]
18-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 16
LSBs store data.
DRA[17:0], DRB[17:0],
DRC[17:0], DRD[17:0]
18-bit DAC registers for each channel. Two MSBs store power-down information, 16 LSBs store DAC data.
An update of this register means a DAC update with data or power-down.
DAC8574 as a Slave Receiver - Standard and Fast Mode
Figure 51 shows the standard and fast mode master transmitter addressing a DAC8574 Slave Receiver with a
7-bit address.
S SLAVE ADDRESS R/W A Ctrl-Byte A MS-Byte A LS-Byte
”0” (write)
A/A
P
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
From Master to DAC8574
DAC8574 I2C-SLAVE ADDRESS:
From DAC8574 to Master
MSB
A =
A =
S =
Sr =
P =
Acknowledge (SDA LOW)
Not Acknowledge (SDA HIGH)
START Condition
Repeated START Condition
STOP Condition
1
LSB
0
0
1
1
A1
A0
R/W
‘0’ = Write to DAC8574
‘1’ = Read from DAC8574
Factory Preset
A0 = I2C Address Pin
A1 = I2C Address Pin
Figure 51. Standard and Fast Mode: Slave Receiver
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DAC8574 as a Slave Receiver - High-Speed Mode
Figure 52 shows the high-speed mode master transmitter addressing a DAC8574 Slave Receiver with a 7-bit
address.
F/S-Mode
S
HS-Mode
HS-Master Code
A Sr Slave Address
F/S-Mode
R/W A Ctrl-Byte A MS-Byte A LS-Byte
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
”0” (write)
HS-Mode Master Code:
P
HS-Mode Continues
Sr Slave Address
MSB
0
A/A
LSB
0
0
0
1
X
X
R/X
Control Byte:
MSB
LSB
A3
A2
L1
L0
X
Sel1 Sel2 PD0
MS-Byte:
MSB
D15
LSB
D14
D13
D12
D11
D10
D9
D5
D4
D3
D2
D1
D8
LS-Byte:
MSB
D7
LSB
D6
D15 - D0 = Data Bits
D0
A3
A2
L1
L0
Sel1
Sel0
PD0
=
=
=
=
=
=
=
Extended Address Bit
Extended Address Bit
Load1 (Mode Select) Bit
Load0 (Mode Select) Bit
Buff Sel1 (Channel) Select Bit
Buff Sel0 (Channel) Select Bit
Power Down Flag
X = Don’t Care
Figure 52. High-Speed Mode: Slave Receiver
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Master Transmitter Writing to a Slave Receiver (DAC8574) in Standard/Fast Modes
All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This
control byte specifies the operation mode of DAC8574 and determines which channel of DAC8574 is being
accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the
following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC8574 expects to receive data in the following sequence HIGH-BYTE –LOW-BYTE –
HIGH-BYTE – LOW-BYTE..., until a STOP Condition or REPEATED START Condition on the I2C-Bus is
recognized (refer to the DATA INPUT MODE section of Table 4).
With (PD0-Bit = 1) the DAC8574 expects to receive 2 Bytes of power-down data (refer to the POWER DOWN
MODE section of Table 4).
Table 4. Write Sequence in F/S Mode
DATA INPUT MODE
Transmitter
MSB
6
5
4
1
0
0
1
Master
Master
A3
A2
Load 1
D15
D14
D13
LSB
1
Comment
A1
A0
R/W
Write addressing (R/W=0)
Buff Sel 0
PD0
Control byte (PD0=0)
D9
D8
Writing data word, high byte
D1
D0
Writing data word, low byte
Begin sequence
Load 0
x
Buff Sel 1
DAC8574 Acknowledges
DAC8574
Master
1
DAC8574 Acknowledges
DAC8574
Master
2
Start
DAC8574
Master
3
D12
D11
D10
DAC8574 Acknowledges
D7
D6
D5
DAC8574
D4
D3
D2
DAC8574 Acknowledges
Data or Stop or Repeated Start (1)
Master
Data or done (2)
POWER DOWN MODE
Transmitter
MSB
6
5
4
Master
Master
1
0
0
A3
A2
Load 1
DAC8574
Master
DAC8574
Master
(1)
(2)
22
1
LSB
1
1
Comment
Begin sequence
A1
A0
R/W
Write addressing (R/W=0)
Load 0
x
Buff Sel 0
PD0
Control byte (PD0 = 1)
0
0
0
Writing data word, high byte
0
0
0
Writing data word, low byte
Buff Sel 1
DAC8574 Acknowledges
PD1
PD2
0
DAC8574
Master
2
DAC8574 Acknowledges
DAC8574
Master
3
Start
0
0
DAC8574 Acknowledges
0
0
0
0
0
DAC8574 Acknowledges
Stop or Repeated Start (1)
Done
Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write.
Once DAC8574 is properly addressed and control byte is sent, HIGH–BYTE–LOW–BYTE sequences can repeat until a STOP
condition or repeated START condition is received.
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
Master Transmitter Writing to a Slave Receiver (DAC8574) in HS Mode
When writing data to the DAC8574 in HS-mode, the master begins to transmit what is called the HS-Master
Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.
The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with
R/W = 0) after which the DAC8574 acknowledges by pulling SDA low. This address byte is usually followed by
the control byte, which is also acknowledged by the DAC8574. The LSB of the control byte (PD0-Bit) determines
if the following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC8574 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE –
HIGH-BYTE – LOW-BYTE...., until a STOP condition or repeated start condition on the I2C-Bus is recognized
(refer to Table 5 HS-MODE WRITE SEQUENCE - DATA).
With (PD0-Bit = 1) the DAC8574 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE
WRITE SEQUENCE - POWER DOWN).
Table 5. Master Transmitter Writes to Slave Receiver (DAC8574) in HS-Mode
HS MODE WRITE SEQUENCE - DATA
Transmitter
MSB
6
5
4
Master
Master
0
0
0
0
NONE
0
0
1
0
0
Load 1
X
X
X
Comment
Begin sequence
1
HS Mode Master Code
No device may acknowledge HS
master code
1
A1
A0
R/W
Write addressing (R/W=0)
Load 0
0
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=0)
D9
D8
Writing data word, MSB
D1
D0
Writing data word, LSB
DAC8574 Acknowledges
D15
D14
D13
DAC8574
Master
LSB
DAC8574 Acknowledges
DAC8574
Master
1
Repeated Start
1
DAC8574
Master
2
Not Acknowledge
Master
Master
3
Start
D12
D11
D10
DAC8574 Acknowledges
D7
D6
D5
DAC8574
D4
D3
D2
DAC8574 Acknowledges
Data or Stop or Repeated Start (1)
Master
Data or done (2)
HS MODE WRITE SEQUENCE - POWER DOWN
Transmitter
MSB
6
5
4
0
0
0
0
Master
Master
0
0
0
0
Load 1
Master
(1)
(2)
X
X
Begin sequence
1
HS Mode Master Code
No device may acknowledge HS
master code
1
1
A1
A0
R/W
Write addressing (R/W = 0)
Load 2
0
Buff Sel 0
PD0
Control Byte (PD0=1)
0
0
0
Writing data word, high byte
0
0
0
Writing data word, low byte
Buff Sel 1
DAC8574 Acknowledges
PD1
PD2
0
0
0
0
DAC8574
DAC8574
X
Comment
DAC8574 Acknowledges
DAC8574
Master
LSB
Repeated Start
1
DAC8574
Master
1
Not Acknowledge
Master
Master
2
Start
NONE
Master
3
0
0
DAC8574 Acknowledges
0
0
DAC8574 Acknowledges
Stop or repeated start (1)
Done
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
Once DAC8574 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start
condition is received.
23
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
DAC8574 as a Slave Transmitter - Standard and Fast Mode
Figure 53 shows the standard and fast mode master transmitter addressing a DAC8574 Slave Transmitter with a
7-bit address.
(DAC8574)
(DAC8574)
(DAC8574)
S SLAVE ADDRESS R/W A Ctrl <7:1> PD0 A Sr Slave Address
’0’ = (Normal Mode)
Data Transferred
(2 Bytes + Acknowledge)
(DAC8574)
PD0 A Sr Slave Address
’1’ = (Power Down Flag)
(MASTER)
R/W A PDN-Byte A
(MASTER)
(MASTER)
MS-Byte A LS-Byte A P
Data Transferred
(3 Bytes + Acknowledge)
’1’ (read)
PDN-Byte:
MSB
(MASTER)
R/W A MS-Byte A LS-Byte A P
’1’ (read)
’0’ (write)
(MASTER)
LSB
PD1 PD2
1
1
1
1
1
1
PD1 = Power-Down Bit
PD2 = Power-Down Bit
Figure 53. Standard and Fast Mode: Slave Transmitter
DAC8574 as a Slave Transmitter - High-Speed Mode
Figure 54 shows an I2C-Master addressing DAC8574 in high-speed mode (with a 7-bit address), as a Slave
Transmitter.
F/S-Mode
S
HS-Master Code
A
HS-Mode
(DAC8574)
Sr
Slave Address
(DAC8574)
R/W A Ctrl <7:1> PD0 A
Sr
(DAC8574)
Slave Address
’0’ = (Normal Mode)
Data Transferred
(2 Bytes + Acknowledge)
(DAC8574)
PD0 A Sr Slave Address
’1’ = (Power -Down Flag)
(MASTER)
R/W A PDN-Byte A
’1’ (read)
(MASTER)
(MASTER)
MS-Byte A LS-Byte A P
Data Transferred
(3 Bytes + Acknowledge)
Figure 54. High-Speed Mode: Slave Transmitter
24
(MASTER)
R/W A MS-Byte A LS-Byte A P
’1’ (read)
’0’ (write)
(MASTER)
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
Master Receiver Reading From a Slave Transmitter (DAC8574) in Standard/Fast Modes
When reading data back from the DAC8574, the user begins with an address byte (with R/W = 0) after which the
DAC8574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which
is also acknowledged by the DAC8574. Following this there is a REPEATED START condition by the Master and
the address is resent with (R/W = 1). This is acknowledged by the DAC8574, indicating that it is prepared to
transmit data. Two or three bytes of data are then read back from the DAC8574, depending on the (PD0-Bit).
The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP Condition follows.
With the (PD0-Bit = 0) the DAC8574 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to
Table 2. Data Readback Mode - 2 bytes).
With the (PD0-Bit = 1) the DAC8574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 3 bytes).
Table 6. Read Sequence in F/S Mode
DATA READBACK MODE - 2 BYTES
Transmitter
MSB
6
5
4
1
0
0
1
3
Master
Master
A3
A2
Load 1
Comment
A0
R/W
Write addressing (R/W=0)
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=0)
A1
A0
R/W
Read addressing (R/W = 1)
D10
D9
D8
Reading data word, high byte
D2
D1
D0
Reading data word, low byte
Begin sequence
x
DAC8574 Acknowledges
Repeated Start
1
0
0
D15
D14
D13
DAC8574
1
1
DAC8574 Acknowledges
Master
DAC8574
A1
1
Load 0
Master
DAC8574
LSB
DAC8574 Acknowledges
DAC8574
Master
1
Start
DAC8574
Master
2
D12
D11
Master Acknowledges
D7
D6
D5
Master
D4
D3
Master Not Acknowledges
Stop or Repeated Start (1)
Master
Master signal end of read
Done
DATA READBACK MODE - 3 BYTES
Transmitter
MSB
6
5
4
3
Master
Master
1
0
0
1
A3
A2
Load 1
Load 0
DAC8574
Master
0
0
Master
(1)
1
PD1
PD2
1
1
D15
D14
D13
D12
A0
R/W
Write addressing (R/W=0)
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=1)
A1
A0
R/W
Read addressing (R/W = 1)
1
1
1
D10
D9
D8
Reading data word, high byte
D2
D1
D0
Reading data word, low byte
Begin sequence
x
1
1
Read power down byte
Master Acknowledges
Master
Master
A1
1
DAC8574 Acknowledges
Master
DAC8574
Comment
Repeated Start
1
DAC8574
DAC8574
LSB
DAC8574 Acknowledges
Master
DAC8574
1
DAC8574 Acknowledges
DAC8574
Master
2
Start
D11
Master Acknowledges
D7
D6
D5
D4
D3
Master Not Acknowledges
Stop or Repeated Start (1)
Master signal end of read
Done
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
25
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
Master Receiver Reading From a Slave Transmitter (DAC8574) in HS-Mode
When reading data to the DAC8574 in HS-MODE, the master begins to transmit, what is called the HS-Master
Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.
The Master then switches to HS-mode and issues a REPEATED START condition, followed by the address byte
(with R/W = 0) after which the DAC8574 acknowledges by pulling SDA low. This address byte is usually followed
by the control byte, which is also acknowledged by the DAC8574.
Then there is a REPEATED START condition initiated by the master and the address is resent with (R/W = 1).
This is acknowledged by the DAC8574, indicating that it is prepared to transmit data. Two or Three bytes of data
are then read back from the DAC8574, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0
determines, which channel data is read back. A STOP condition follows.
With the (PD0-Bit = 0) the DAC8574 transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to
Table 7 HS-Mode Readback Sequence).
With the (PD0-Bit = 1) the DAC8574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence).
Table 7. Master Receiver Reading Slave Transmitter (DAC8574) in HS-Mode
HS MODE READBACK SEQUENCE
Transmitter
MSB
6
5
4
0
0
0
0
3
Master
Master
0
0
1
A3
A2
Load 1
HS Mode Master Code
No device may acknowledge HS
master code
1
A1
A0
R/W
Write addressing (R/W=0)
Load 0
X
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0 = 1)
A0
R/W
Read addressing (R/W=1)
1
1
Power-down byte
D9
D8
Reading data word, high byte
D1
D0
Reading data word, low byte
Repeated Start
1
0
0
PD1
PD2
1
1
1
A1
DAC8574 Acknowledges
Master
1
1
1
Master Acknowledges
D15
D14
D13
Master
26
X
DAC8574 Acknowledges
DAC8574
DAC8574
X
DAC8574 Acknowledges
Master
DAC8574
X
Repeated Start
1
DAC8574
DAC8574
Comment
Not Acknowledge
DAC8574
Master
LSB
Begin sequence
1
Master
Master
1
Start
NONE
Master
2
D12
D11
D10
Master Acknowledges
D7
D6
D5
D4
D3
D2
Master
Master Not Acknowledges
Master signal end of read
Master
Stop or Repeated Start
Done
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
Power-On Reset
The DAC8574 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC
while it is in the process of powering up. No device pin should be brought high before supply is applied.
Power-Down Modes
The DAC8574 contains four separate power-down modes of operation. The modes are programmable via two
most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits
correspond to the mode of operation of the device.
Table 8. Power-Down Modes of Operation for the DAC8574
CTRL[0]
MSB[7]
MSB[6]
OPERATING MODE
1
0
0
High Impedance Output
1
0
1
1 kΩ to GND
1
1
0
100 kΩ to GND
1
1
1
High Impedance
When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 250 µA at 5 V per
channel. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not
only does the supply current fall but also the output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the advantage that the output impedance of the device
is known while in power-down mode. There are three different options: The output is connected internally to GND
through a 1 kΩ resistor, a 100 kΩ resistor or left open-circuit (high impedance). The output stage is illustrated in
Figure 55.
Amplifier
Resistor
String DAC
VOUT
Powerdown
Circuitry
Resistor
Network
Figure 55. Output Stage During Power Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power down is typically 2.5 µs for VDD = 5 V and 5
µs for VDD = 3 V. (See the Typical Curves section for additional information.)
The DAC8574 offers a flexible power-down interface based on channel register operation. A channel consists of
a single 16 bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR
and DR are both 18 bits wide. Two MSBs represent the power-down condition and the 16 LSBs represent data
for TR and DR. By using bits 17 and 18 of TR and DR, a power-down condition can be temporarily stored and
used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[17] and TR[16] (DR[17]
and DR[16]) when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC8574 treats power-down
conditions like data and all the operational modes are still valid for power down. It is possible to broadcast a
power-down condition to all the DAC8574s in the system, or it is possible to simultaneously power down a
channel while updating data on other channels.
27
DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
www.ti.com
CURRENT CONSUMPTION
The DAC8574 typically consumes 225 µA at VDD = 5 V and 200 µA at VDD = 3 V for each active channel,
including reference current consumption. Additional current consumption can occur at the digital inputs if VIH <<
VDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In
power-down mode, typical current consumption is 200 nA. A delay time of 10 to 20 ms after a power-down
command is issued to the DAC is typically sufficient for the power-down current to drop below 10 µA.
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC8574 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC8574 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2
kΩ can be driven by the DAC8574 while achieving very good load regulation. Load regulation error increases as
the output voltage approaches each rail. When the outputs of the DAC are driven to the positive rail under
resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this
occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within
approximately the top 20 mV of the DAC’s digital input-to-voltage output transfer characteristic. The reference
voltage applied to the DAC8574 may be reduced below the supply voltage applied to VDD in order to eliminate
this condition if good linearity is a requirement at full scale (under resistive loading conditions).
CROSSTALK AND AC PERFORMANCE
The DAC8574 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low
crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel
is typically less than 0.5 LSBs. The ac crosstalk measured (for a full-scale, 1 kHz sine wave output generated at
one channel, and measured at the remaining output channel) is typically under -100 dB. In addition, the
DAC8574 can achieve typical ac performance of 96 dB signal-to-noise ratio (SNR) and 65 dB total harmonic
distortion (THD), making the DAC8574 a solid choice for applications requiring high SNR at output frequencies at
or below 4 kHz.
OUTPUT VOLTAGE STABILITY
The DAC8574 exhibits excellent temperature stability of ±3 ppm/°C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage of each channel to stay within a ±25 µV window
for a ±1°C ambient temperature change. Good power-supply rejection ratio (PSRR) performance reduces supply
noise present on VDD from appearing at the outputs to well below 10 µV-s. Combined with good dc noise
performance and true 16-bit differential linearity, the DAC8574 becomes a perfect choice for closed-loop control
applications.
SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
Settling time to within the 16-bit accurate range of the DAC8574 is achievable within 10 µs for a full-scale code
change at the input. Worst case settling times between consecutive code changes is typically less than 2 µs. The
high-speed serial interface of the DAC8574 is designed in order to support up to 188ksps update rate. For
full-scale output swings, the output stage of each DAC8574 channel typically exhibits less than 100 mV of
overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely
low (~10 µV) given that the code-to-code transition does not cross an Nx4096 code boundary. Due to internal
segmentation of the DAC8574, code-to-code glitches occur at each crossing of an Nx4096 code boundary.
These glitches can approach 100mVs for N = 15, but settle out within ~2 µs.
28
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION
The following sections give example circuits and tips for using the DAC8574 in various applications. For more
information, contact your local TI representative, or visit the Texas Instruments website at http://www.ti.com.
BASIC CONNNECTIONS
For many applications, connecting the DAC8574 is extremely simple. A basic connection diagram for the
DAC8574 is shown in Figure 56. The 0.1 µF bypass capacitors help provide the momentary bursts of extra
current needed from the supplies.
DAC8574
I2C Pullup Resistors
1 kΩ to 10 kΩ (typical)
Microcontroller or
Microprocessor With
I2C Port
IOVDD
1 VOUTA
A3 16
2 VOUTB
A2 15
3 VREFH
A1 14
4 VDD
A0 13
5 VREFL
IOVDD 12
6 GND
SDA 11
7 VOUTC
SCL 10
8 VOUTD
LDAC 9
SCL
SDA
NOTE: DAC8574 power and input/output connections are omitted for clarity, except IC Inputs.
Figure 56. Typical DAC8574 Connections
The DAC8574 interfaces directly to standard mode, fast mode and high-speed mode I2C controllers. Any
microcontroller’s I2C peripheral, including master-only and non-multiple-master I2C peripherals, work with the
DAC8574. The DAC8574 does not perform clock-stretching (i.e., it never pulls the clock line low), so it is not
necessary to provide for this unless other devices are on the same I2C bus.
Pullup resistors are necessary on both the SDA and SCL lines because I2C bus drivers are open-drain. The size
of the these resistors depend on the bus operating speed and capacitance on the bus lines. Higher-value
resistors consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value
resistors allow higher speed at the expense of higher power consumption. Long bus lines have higher
capacitance and require smaller pullup resistors to compensate. If the pullup resistors are too small the bus
drivers may not be able to pull the bus line low.
USING GPIO PORTS FOR I2C
Most microcontrollers have programmable input/output pins that can be set in software to act as inputs or
outputs. If an I2C controller is not available, the DAC8574 can be connected to GPIO pins, and the I2C bus
protocol simulated, or bit-banged, in software. An example of this for a single DAC8574 is shown in Figure 57.
29
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
DAC8574
IOVDD
1 VOUTA
A3 16
2 VOUTB
A2 15
3 VREFH
A1 14
4 VDD
A0 13
5 VREFL
Microcontroller or
Microprocessor
IOVDD 12
6 GND
SDA 11
7 VOUTC
SCL 10
8 VOUTD
LDAC 9
GPIO-1
GPIO-2
NOTE: DAC8574 power and input/output connections are omitted for clarity, except IC Inputs.
Figure 57. Using GPIO With a Single DAC8574
Bit-banging I2C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and
output modes to apply the proper bus states. To drive the line low, the pin is set to output a zero; to let the line
go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is
pulling the line low, this reads as a zero in the port’s input register.
Note that no pullup resistor is shown on the SCL line. In this simple case the resistor is not needed. The
microcontroller can simply leave the line on output, and set it to one or zero as appropriate. It can do this
because the DAC8574 never drives its clock line low. This technique can also be used with multiple devices, and
has the advantage of lower current consumption due to the absence of a resistive pullup.
If there are any devices on the bus that may drive their clock lines low, the above method should not be used.
The SCL line should be high-Z or zero, and a pullup resistor provided as usual. Note also that this cannot be
done on the SDA line in any case, because the DAC8574 drives the SDA line low from time to time, as all I2C
devices do.
Some microcontrollers have selectable strong pullup circuits built in to their GPIO ports. In some cases, these
can be switched on and used in place of an external pullup resistor. Weak pullups are also provided on some
microcontrollers, but usually these are too weak for I2C communication. Test any circuit before committing it to
production.
30
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
USING REF02 AS A POWER SUPPLY FOR DAC8574
Due to the extremely low supply current required by the DAC8574, a possible configuration is to use a REF02 +5
V precision voltage reference to supply the required voltage to the DAC8574’s supply input as well as the
reference input, as shown in Figure 58. This is especially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC8574.
If the REF02 is used, the current it needs to supply to the DAC8574 is 950 µA typical and 1600 µA max for VDD =
5 V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total typical
current required (with a 5 kΩ load on a single DAC output) is:
950 µA + (5 V / 5 kΩ) = 1.950 mA
The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 488µV for 1.950-mA of
current drawn from it. This corresponds to a 6.4 LSB error for a 0 V to 5 V output range.
15 V
REF02
5V
950 A
I2C
Interface
SCL
SDA
VDD, Vref
DAC8574
VOUT = 0 V to 5 V
Figure 58. REF02 Power Supply
REF3040 can also be used to generate a 4.096-V reference from a 5-V supply.
31
DAC8574
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SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
GENERATING ±5 V, ±10 V, and ± 12 V OUTPUTS FOR PRECISION INDUSTRIAL CONTROL
Industrial control applications can require multiple feedback loops consisting of sensors, ADCs, MCUs, DACs,
and actuators. Loop accuracy and loop speed are the two important parameters of such control loops.
Loop Accuracy:
In a control loop, the ADC has to be accurate. Offset, gain, and the integral linearity errors of the DAC are not
factors in determining the accuracy of the loop. As long as a voltage exists in the transfer curve of a monotonic
DAC, the loop can find it and settle to it. On the other hand, DAC resolution and differential linearity do determine
the loop accuracy, because each DAC step determines the minimum incremental change the loop can generate.
A DNL error less than -1 LSB (non-monotonicity) can create loop instability. A DNL error greater than +1 LSB
implies unnecessarily large voltage steps, and missed voltage targets. With high DNL errors, the loop looses its
stability, resolution, and accuracy. Offering 16-bit assured monotonicity and ± 0.25 LSB typical DNL error, 85XX
DACs are great choices for precision control loops.
Loop Speed:
Many factors determine control loop speed. Typically, the ADC’s conversion time, and the MCU’s computation
time are the two major factors that dominate the time contstant of the loop. DAC settling time is rarely a dominant
factor because ADC conversion times usually exceed DAC conversion times. DAC offset, gain, and linearity
errors can slow the loop down only during the start-up. Once the loop reaches its steady-state operation, these
errors do not affect loop speed any further. Depending on the ringing characteristics of the loop’s transfer
function, DAC glitches can also slow the loop down. With its 188 ksps maximum data update rate, DAC8574 can
support high-speed control loops.
Generating Industrial Voltage Ranges:
For control loop applications, DAC gain and offset errors are not important parameters. This could be exploited to
lower trim and calibration costs in a high-voltage control circuit design. Using a quad op amp (OPA4130), a
voltage reference (REF3040) and a quad 12-bit DAC (DAC7574), the DAC8574 can generate the wide voltage
swings required by the control loop.
Vtail
DAC7574
R1
REF3040
R2
Vref
VREFH
DAC8574
_
Vdac
+
VOUT
OPA4130
Figure 59. Low-cost, Wide-swing Voltage Generator for Control Loop Applications
The output voltage of the configuration is given by:
Din –V
R2
V out V ref R2 1
65536 tail R1
R1
Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation. Once
R2 an R1 set the gain properly, a DAC7574 could be used to set the required offset voltages. Residual errors are
not an issue for loop accuracy because offset and gain errors could be tolerated.
For ±5-V operation: R1=10 kΩ, R2 = 15 kΩ, Vtail = 3.33 V, Vref = 4.096 V
For ±10-V operation: R1=10 kΩ, R2 = 39 kΩ, Vtail = 2.56 V, Vref = 4.096 V
For ±12-V operation: R1=10 kΩ, R2 = 49 kΩ, Vtail = 2.45 V, Vref = 4.096 V
32
www.ti.com
DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
Digital Correction of DAC Errors
For open-loop applications requiring improved accuracy, offset and gain errors of the DAC8574 can be measured
and digitally corrected. To avoid waveform clipping, it is recommended to make the offset and gain error
measurements at codes 1024 and 64512 respectively. The total error of DAC8574 is dominated by gain and
offset errors, and it can be improved by an order of magnitude using the following digital correction:
DIN = DDIN – OE – (FSE – OE) × (DDIN – 1024) ÷ 64512
where:
DIN = Digital input code to the DAC after offset and gain correction
DDIN = Digital input code to the DAC before offset and gain correction
OE = measured DAC error at code 1024 (in LSBs)
FSE = measured DAC error at code 64512 (in LSBs)
If division operation is not feasible, FSE measurement can be done at code 32768 instead of code 64512.
Division by 32768 implies a 15-bit arithmetic right shift. Improvements to the transfer curve are still significant.
DAC8574 integral linearity error is well within ±5 mV, therefore it only has a secondary effect on total DAC error.
Using piece-wise linear approximation, and non-volatile memory, integral linearity errors of DAC8574 can also be
digitally corrected. Consult TI applications engineering for details.
64 Channel Operation
DAC8574 is designed to facilitate high channel count operation. DAC8574 supports multichannel simultaneous
synchronous update up to 16 DAC8574 devices for up to 64 channels on a single I2C bus. Working with multiple
DAC8574s, single channel DAC8571s can be used on the same bus to obtain odd channel counts, or quad
channel DAC7574s can be used if some channels only need 12 bits of resolution.
Data or power down can be loaded to temporary registers of each channel serially and a single broadcast
operation can be used to update all channels of all devices simultaneously with previously stored data or
power-down condition. Another feature useful for system start-up or system shut-down is to broadcast the same
data (or power-down condition) to all channels with a single broadcast command.
All multichannel system updates are performed at the falling edge of the acknowledge signal that follows the
least significant byte.
The 64-channel operation requires 6-bit address decoding. 4-bit address decoding is used to support 16
DAC8574 devices on the same bus and 2-bit address decoding is used to select one out of four channels of a
DAC8574. 4-bit address decoding that selects one out of 16 DAC8574 devices is done as follows: To save I2C
address space, 2-bits (A0 and A1) are used for I2C address decoding, and two additional bits (A2 and A3) are
used for local address decoding. Up to 4 DAC8574 devices using the same I2C address can be connected on the
same I2C bus. These four devices with the same I2C address can be locally decoded using A2 and A3 pins. If
multiple devices use the same I2C address, multiple devices acknowledge at the same time. However, in order
for a particular device to respond to a command, the states of the first two bits of the control word C7 and C6
must match the states of A3 and A2 pins. Four devices per I2C address and four distinct I2C addresses enable
16 devices on the same bus.
The four address pins should be set at power-up, and address bits must be set to match a particular device’s
address pins. To decode up to 16 DAC8574 devices, the logic states of A3, A2, A1, A0 address pins and C7, C6,
A1, A0 address bits should be set as shown in Table 9.
33
DAC8574
www.ti.com
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
Table 9. 64 Channel Address Decoding
DEV #
A3 PIN
C7 BIT
A2 PIN
C6 BIT
A1 PIN
A1 BIT
A0 PIN
A0 BIT
1
0
0
0
0
0
0
0
0
2
0
0
0
0
0
0
1
1
3
0
0
0
0
1
1
0
0
4
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
0
0
6
0
0
1
1
0
0
1
1
7
0
0
1
1
1
1
0
0
8
0
0
1
1
1
1
1
1
9
1
1
0
0
0
0
0
0
10
1
1
0
0
0
0
1
1
11
1
1
0
0
1
1
0
0
12
1
1
0
0
1
1
1
1
13
1
1
1
1
0
0
0
0
14
1
1
1
1
0
0
1
1
15
1
1
1
1
1
1
0
0
16
1
1
1
1
1
1
1
1
Once a DAC8574 device is selected, channel select bits C2 and C1 can select a particular channel. Overall, I2C
address bits A1, A0, control bits C7, C6, C2 and C1 form the 6-bit address required to select one channel out of
64 possibilities.
Broadcast operation is supported for both I2C addressing and for extended addressing. A broadcast address
(10010000) makes all DAC8574 devices listen, regardless of the states of A0 and A1 pins. Also, a broadcast
command (C5 = C4 = 1) makes all devices listen, regardless of the states of A2 and A3 pins. The same
broadcast command (C5 = C4 = 1) also selects all channels for a given device, regardless of the states of
channel select bits. Thus, a global broadcast message that simultaneously updates up to 64 channels uses
10010000 as I2C address and has (C5 = C4 = 1) in the control word.
Examples
I2C Standard and Fast Mode Examples (A0, A1, A2, A3 and LDAC pins tied to GND):
EXAMPLE 1: WRITE 1/4 SCALE TO CHANNEL A
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0001 0000
M [7...0]
ACK
0100 0000
L [7...0]
ACK
0000 0000
Previous VoutA output voltage is valid
ACK
STOP
VoutA = 1.25 V
EXAMPLE 2: WRITE 1/2 SCALE TO CHANNEL B
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0001 0010
M [7...0]
ACK
0100 0000
L [7...0]
ACK
0000 0000
Previous VoutB output voltage is valid
ACK
STOP
VoutB = 2.50 V
EXAMPLE 3: WRITE 3/4 SCALE TO CHANNEL C
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
Previous VoutC output voltage is valid
34
0001 0100
M [7...0]
ACK
1100 0000
L [7...0]
ACK
0000 0000
ACK
STOP
VoutC = 3.75 V
DAC8574
www.ti.com
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
EXAMPLE 4: WRITE 4/4 SCALE TO CHANNEL D
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0001 0110
M [7...0]
ACK
1111 1111
L [7...0]
ACK
1111 1111
Previous VoutD output voltage is valid
ACK
STOP
VoutB = 5.0 V
EXAMPLE 5: Power-Down Channel A, With Hi-Z Output
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0001 0101
M [7...0]
ACK
0000 0000
L [7...0]
ACK
0000 0000
Previous VoutA output voltage is valid
ACK
STOP
VoutA = Hi-Z
EXAMPLE 6: Power-Down Channel B, With Hi-Z Output
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0001 0011
M [7...0]
ACK
0000 0000
L [7...0]
ACK
0000 0000
Previous VoutB output voltage is valid
ACK
STOP
VoutB = Hi-Z
EXAMPLE 7: Power-Down Channel C, With Hi-Z Output
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0001 0101
M [7...0]
ACK
0000 0000
L [7...0]
ACK
0000 0000
Previous VoutC output voltage is valid
ACK
STOP
VoutC = Hi-Z
EXAMPLE 8: Power-Down Channel D, With Hi-Z Output
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0001 0111
M [7...0]
ACK
0000 0000
L [7...0]
ACK
0000 0000
Previous VoutD output voltage is valid
ACK
STOP
VoutD = Hi-Z
EXAMPLE 9: Power-Down Channel D, With 1 kΩ Output Impedance to Ground
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0001 0111
M [7...0]
ACK
0100 0000
L [7...0]
ACK
0000 0000
Previous VoutA output voltage is valid
ACK
STOP
VoutD = 0 V
EXAMPLE 10: Power-Down Channel D, With 100 kΩ Output Impedance to Ground
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
Previous VoutD output voltage is valid
0001 0111
M [7...0]
ACK
1000 0000
L [7...0]
ACK
0000 0000
ACK
STOP
VoutD = 0 V
35
DAC8574
www.ti.com
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
EXAMPLE 11: Simultaneous Update of All Channels
Write 4/4 Scale, 4/3 Scale, 2/4 Scale, and 1/4 Scale Data to Temporary Registers of Channels A, B, C, D Serially, and Update all
DACs Simultaneously
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0000 0000
M [7...0]
L [7...0]
ACK
1111 1111
ACK
1111 1111
ACK
ACK
1100 0000
ACK
0000 0000
ACK
ACK
1000 0000
ACK
0000 0000
ACK
ACK
0100 0000
ACK
0000 0000
STOP
Previous DAC output voltages are valid for all channels
START
1001 1000
ACK
0000 0010
Previous DAC output voltages are valid for all channels
START
1001 1000
ACK
0000 0100
Previous DAC output voltages are valid for all channels
START
1001 1000
ACK
0010 0110
Previous DAC output voltages are valid for all channels
ACK
New data is valid
EXAMPLE 12: Simultaneous Update Channels A, B, C and Power-Down of Channel D at The End of The Fourth Cycle
Write 1/4 Scale, 2/4 Scale, 3/4 Scale, and Power-Down (Hi-Z) Data to Temporary Registers of Channels A, B, C, D Serially, and
Update Simultaneously
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0000 0000
M [7...0]
L [7...0]
ACK
1111 1111
ACK
1111 1111
ACK
STOP
ACK
1100 0000
ACK
0000 0000
ACK
STOP
ACK
1000 0000
ACK
0000 0000
ACK
STOP
ACK
0100 0000
ACK
0000 0000
ACK
STOP
Previous DAC output voltages are valid for all channels
START
1001 1000
ACK
0000 0010
Previous DAC output voltages are valid for all channels
START
1001 1000
ACK
0000 0100
Previous DAC output voltages are valid for all channels
START
1001 1000
ACK
0010 0110
Previous DAC output voltages are valid for all channels
New data is valid
EXAMPLE 13: Store data and wait for update command (Write codes 128, 256, 512, and 1024 to temporary registers of channels A,
B, C, D)
Write 4/4 Scale, 4/3 Scale, 2/4 Scale, and 1/4 Scale Data to Temporary Registers of Channels A, B, C, D Serially, and Update all
DACs Simultaneously
ADDRESS [7...0]
START
1001 1000
C [7...0]
ACK
0000 0000
M [7...0]
L [7...0]
ACK
0000 0000
ACK
1000 0000
ACK
STOP
ACK
0000 0001
ACK
0000 0000
ACK
STOP
ACK
0000 0010
ACK
0000 0000
ACK
STOP
ACK
0100 0100
ACK
0000 0000
ACK
STOP
Previous DAC output voltages are valid for all channels
START
1001 1000
ACK
0000 0010
Previous DAC output voltages are valid for all channels
START
1001 1000
ACK
0000 0100
Previous DAC output voltages are valid for all channels
START
1001 1000
ACK
0010 0110
Previous DAC output voltages are valid for all channels
36
DAC8574
www.ti.com
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
EXAMPLE 14: Broadcast update command. All channels of all DAC8574s update with previously stored temporary register data.
ADDRESS [7...0]
START
1001 0000
C [7...0]
ACK
M [7...0]
0011 0000
XXXX XXXX
ACK
L [7...0]
ACK
XXXX XXXX
Previous DAC output voltages are valid for all channels, all DAC8574s
ACK
STOP
New data is valid
EXAMPLE 15: Broadcast Data. All channels of all DAC8574s get set to code 7.
ADDRESS [7...0]
START
C [7...0]
1001 0000
ACK
M [7...0]
0011 0001
L [7...0]
0000 0000
ACK
ACK
0000 0111
ACK
STOP
All Vouts = 7 x 76
µV
Previous DAC output voltages are valid for all channels, all DAC8574s
EXAMPLE 16: Broadcast Power-Down. All channels of all DAC8574s get powered down with output impedance of 1 kΩ to ground.
ADDRESS [7...0]
START
C [7...0]
1001 0000
ACK
M [7...0]
0011 0001
L [7...0]
0100 0000
ACK
ACK
0000 0000
Previous DAC output voltages are valid for all channels, all DAC8574s
ACK
STOP
All Vouts = GND
I2C Read-back Examples (A0, A1, A2, A3 and LDAC pins tied to GND):
EXAMPLE 17: Read back channel A power-down bits and 16-bit channel A data. V denotes valid logic.
ADDRESS [7...0]
START
1001 1000
PWD [7...0]
MASTER
VV11 1111
ACK
C [7...0]
0001 0001
ACK
MSB [7...0]
VVVV VVVV
MASTER
ACK
ACK
REPEATED
ADDRESS
START
1001 1001
LSB [7...0]
MASTER
VVVV VVVV
NOT ACK
ACK
EXAMPLE 18: Read back channel B power-down bits and 16-bit channel B data. V denotes valid logic.
ADDRESS [7...0]
START
1001 1000
PWD [7...0]
MASTER
VV11 1111
ACK
C [7...0]
0001 0011
ACK
MSB [7...0]
VVVV VVVV
MASTER
ACK
ACK
REPEATED
ADDRESS
START
1001 1001
LSB [7...0]
MASTER
VVVV VVVV
NOT ACK
ACK
EXAMPLE 19: Read back channel C power-down bits and 16-bit channel C data. V denotes valid logic.
ADDRESS [7...0]
START
1001 1000
PWD [7...0]
MASTER
VV11 1111
ACK
C [7...0]
0001 0101
ACK
MSB [7...0]
VVVV VVVV
MASTER
ACK
ACK
REPEATED
ADDRESS
START
1001 1001
LSB [7...0]
MASTER
VVVV VVVV
NOT ACK
ACK
EXAMPLE 20: Read back channel D power-down bits and 16-bit channel D data. V denotes valid logic.
ADDRESS [7...0]
START
1001 1000
PWD [7...0]
MASTER
VV11 1111
ACK
C [7...0]
0001 0011
ACK
MSB [7...0]
VVVV VVVV
MASTER
ACK
ACK
REPEATED
ADDRESS
START
1001 1001
LSB [7...0]
MASTER
VVVV VVVV
NOT ACK
ACK
EXAMPLE 21: Read back 16-bit channel D data only. V denotes valid logic.
ADDRESS [7...0]
START
1001 1000
MSB [7...0]
MASTER
VVVV VVVV
ACK
C [7...0]
ACK
0001 0110
ACK
LSB [7...0]
MASTER
VVVV VVVV
NOT ACK
REPEATED
ADDRESS
START
1001 1001
ACK
37
DAC8574
www.ti.com
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
I2C High Speed Examples (A0, A1, A2, A3 and LDAC pins tied to GND):
EXAMPLE 22: Ramp generation on channel D (Up to Code 7 is shown)
START
HS Master Code
NOT
REPEATED
ADDRESS
0001 0000
ACK
START
10011 0000
C [7 … 0]
ACK
0001 0110
ACK
Previous VoutD voltage valid
MSB [7…0]
0000 0000
LSB [7…0]
ACK
0000 0000
Previous VoutD voltage valid
MSB [7…0]]
0000 0000
0000 0010
LSB [7…0]
ACK
0000 0001
MSB 7…0]
ACK
LSB [7…0]
ACK
0000 0100
0000 0000
LSB [7…0]
ACK
0000 0011
VoutD = 3 x 76 µV
MSB [7…0]
VoutD = 5 x 76 µV
0000 0000
LSB [7…0]
ACK
0000 0101
VoutD = 4 x 76 µV
LSB [7…0]
ACK
0000 0110
VoutD = 6 x 76 µV
ACK
VoutD = 5 x 76
µV
MSB [7…0]
ACK
ACK
VoutD = 3 x 76
µV
MSB [7…0]
ACK
ACK
VoutD = 76 µV
VoutD = 2 x 76 µV
MSB [7…0]
0000 0000
0000 0000
VoutD = 0 V
LSB [7…0]
ACK
VoutD = 76 µV
0000 0000
MSB [7…0]
ACK
0000 0000
LSB [7…0]
ACK
0000 0111
ACK
VoutD = 7 x 76
µV
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The power applied to VDD should be well-regulated and low noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, VDD should be connected to a positive power-supply plane or trace that is separate
from the connection for digital logic until they are connected at the power-entry point. In addition, a 1 µF to 10 µF
capacitor in parallel with a 0.1 µF bypass capacitor is strongly recommended. In some situations, additional
bypassing may be required, such as a 100 µF electrolytic capacitor or even a Pi filter made up of inductors and
capacitors—all designed to essentially low-pass filter the –5 V supply, removing the high-frequency noise.
38
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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