ICST ICS853031AYLF Low skew, 1-to-9 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer Datasheet

ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853031 is a low skew, high performance
1-to-9 Differential-to-2.5V/3.3V LVPECL/ECL
HiPerClockS™
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS853031 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL, LVDS,
CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
• 9 differential 2.5V/3.3V LVPECL/ECL outputs
ICS
Guaranteed output skew and part-to-part skew characteristics
make the ICS853031 ideal for high performance workstation
and server applications.
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL,
• PCLK, nPCLK supports the following input types:
LVPECL, LVDS, CML, SSTL
• Output frequency: 1.6GHz (typical)
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK or
nPCLK inputs
• Output skew: 20ps (typical)
• Part-to-part skew: 75ps (typical)
• Propagation delay: 875ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.465V
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
• Pin compatible with ICS8531-01
BLOCK DIAGRAM
PIN ASSIGNMENT
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCCO
D
CLK_EN
Q
32 31 30 29 28 27 26 25
LE
CLK
nCLK
PCLK
nPCLK
CLK_SEL
0
1
Q0
nQ0
VCC
1
24
VCCO
CLK
2
23
Q3
Q1
nQ1
nCLK
3
22
nQ3
CLK_SEL
4
21
Q4
PCLK
5
20
nQ4
nPCLK
6
19
Q5
VEE
7
18
nQ5
CLK_EN
8
17
VCCO
Q2
nQ2
Q3
nQ3
ICS853031
9 10 11 12 13 14 15 16
Vcco
Q6
nQ6
Q7
nQ7
Q8
Q5
nQ5
nQ8
Vcco
Q4
nQ4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
Q6
nQ6
Q7
nQ7
Q8
nQ8
853031AY
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1
REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VCC
Type
Description
Power
2
CLK
Input
3
nCLK
Input
4
CLK_SEL
Input
5
PCLK
Input
6
nPCLK
Input
7
VEE
Power
8
CLK_EN
Input
Core supply pin.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Clock Select input. When HIGH, selects PCLK, nPCLK inputs.
Pulldown
When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup
Pullup
Inver ting differential LVPECL clock input.
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
9, 16, 17,
24, 25, 32
10, 11
VCCO
Power
Output supply pins.
nQ8, Q8
Output
Differential output pair. LVPECL interface level.
12, 13
nQ7, Q7
Output
Differential output pair. LVPECL interface level.
14, 15
nQ6, Q6
Output
Differential output pair. LVPECL interface level.
18, 19
nQ5, Q5
Output
Differential output pair. LVPECL interface level.
20, 21
nQ4, Q4
Output
Differential output pair. LVPECL interface level.
22, 23
nQ3 Q3
Output
Differential output pair. LVPECL interface level.
26, 27
nQ2, Q2
Output
Differential output pair. LVPECL interface level.
28, 2 9
nQ1, Q1
Output
Differential output pair. LVPECL interface level.
30, 31
nQ0, Q0
Output
Differential output pair. LVPECL interface level.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
RPULLDOWN
Input Pulldown Resistor
50
KΩ
RPULLUP
Input Pullup Resistor
50
KΩ
853031AY
Test Conditions
Minimum
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2
Typical
Maximum
Units
REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
CLK_EN
CLK_SEL
Outputs
Selected Sourced
Q0:Q8
nQ0:nQ8
0
0
CLK, nCLK
Disabled; LOW
Disabled; HIGH
0
1
PCLK, nPCLK
Disabled; LOW
Disabled; HIGH
1
0
CLK, nCLK
Enabled
Enabled
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ8
Q0:Q8
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK or PCLK
Outputs
nCLK or nPCLK
Q0:Q8
nQ0:nQ8
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inver ting
1
0
HIGH
LOW
Differential to Differential
Non Inver ting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
853031AY
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3
REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Negative Supply Voltage, VEE
-4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifications only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
50mA
100mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol
Parameter
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
Test Conditions
2.375
3.3
3.465
V
VCCO
Output Supply Voltage
2.375
3.3
3.465
V
I EE
Power Supply Current
77
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol
Parameter
VIH
CLK_EN, CLK_SEL
VIL
CLK_EN, CLK_SEL
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Maximum
Units
2
Typical
3.465
V
-0.3
0.8
V
CLK_EN
VCC = VIN = 3.465V or 2.625V
10
µA
CLK _S E L
VCC = VIN = 3.465V or 2.625V
150
µA
CLK_EN
VIN = 0V, VCC = 3.465V or 2.625V
-150
µA
CLK_SEL
VIN = 0V, VCC = 3.465V or 2.625V
-50
µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS (CLK, nCLK), VCC = 2.375 TO 3.465V; VEE = 0V
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
-40°C
Min
CLK
Typ
25°C
Max
Min
Typ
150
nCLK
85°C
Max
Min
150
10
Max
150
10
10
Units
µA
µA
CLK
-50
-50
-50
µA
nCLK
-150
-150
-150
µA
VPP
0.15
1.3
0.15
1.3
0.15
Peak-to-Peak Input Voltage
Input High Voltage
VEE + 0.7
VCC - 0.85 VEE + 0.7
VCC - 0.85 VEE + 0.7
VCMR
Common Mode Range;
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
853031AY
Typ
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4
1.3
V
VCC - 0.85
V
REV. B SEPTEMBER 16, 2004
Integrated
Circuit
Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 3.3V; VEE = 0V
Symbol
-40°C
Parameter
25°C
Min
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Units
VOH
Output High Voltage; NOTE 1
2.175
2.275
2.38
2.225
2.295
2.37
2.22
2.295
2.365
V
VOL
Output Low Voltage; NOTE 1
1.405
1.545
1.68
1.425
1.52
1.615
1.44
1.535
1.63
V
VPP
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
PCLK
Input High Current
nPCLK
0.15
0.8
1.3
0.15
0.8
1.3
0.15
0.8
1.3
V
VCC
1.2
VCC
1.2
VCC
V
150
µA
VCMR
IIH
IIL
Input Low Current
PCLK
1.2
150
150
10
-50
10
-50
10
-50
µA
µA
nPCLK
-150
-150
-150
Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.165V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
µA
TABLE 4E. LVPECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 2.5V; VEE = 0V
Symbol
Parameter
VOH
-40°C
25°C
85°C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Output High Voltage; NOTE 1
1.375
1.475
1.58
1.425
1.495
1.57
1.42
1.495
1.565
V
VOL
Output Low Voltage; NOTE 1
0.605
0.745
0.88
0.625
0.72
0.815
0.64
0.735
0.83
V
VPP
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
PCLK
Input High Current
nPCLK
0.15
0.8
1.3
0.15
0.8
1.3
0.15
0.8
1.3
V
VCC
1.2
VCC
1.2
VCC
V
VCMR
IIH
IIL
Input Low Current
PCLK
1.2
-10
150
150
150
µA
10
10
10
µA
-10
-10
nPCLK
-150
-150
-150
Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.125V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
853031AY
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5
µA
µA
REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4F. ECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 0V; VEE = -2.375V TO -3.465V
-40°C
Symbol
Parameter
VOH
Typ
Max
Min
Typ
Max
-1.025
-1.075
-1.005
-0.93
-1.08
-1.005
-0.935
V
-1.895
-1.755
-1.62
-1.875
-1.78
-1.685
-1.86
-1.765
-1.67
V
0.15
0.8
1.3
0.15
0.8
1.3
0.15
0.8
1.3
V
0
VEE+1.2
0
VEE+1.2
0
V
Output High Voltage; NOTE 1
-1.125
VOL
Output Low Voltage; NOTE 1
VPP
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
PCLK
Input High Current
nPCLK
IIL
Input Low Current
PCLK
Units
Min
Typ
IIH
85°C
Max
-0.92
Min
VCMR
25°C
VEE+1.2
150
150
150
µA
10
10
10
µA
-10
-10
-10
µA
nPCLK
-150
-150
-150
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
µA
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375V TO -3.465V OR VCC = 2.375 TO 3.465V; VEE = 0V
-40°C
Symbol
Parameter
fMAX
Output Frequency
t PD
Propagation
Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
Min
Typ
25°C
Max
Min
>1.6
Typ
85°C
Max
Min
>1.6
Typ
Max
>1.6
Units
GHz
PCLK, nPCLK
75 0
825
900
785
875
965
825
925
1025
ps
CLK, nCLK
820
920
1020
860
960
1060
910
1010
1110
ps
20
55
20
55
25
55
ps
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
60
150
75
175
75
200
ps
Output
20% to 80%
100 215 400 100 225 400 100 215
350
ps
tR/tF
Rise/Fall Time
f ≤ 266MHz
48
52
48
52
48
52
%
odc
Output Duty Cycle
266MHz < f ≤ 500MHz 46
54
46
54
46
54
%
All parameters measured at ≤ 500MHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853031AY
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6
REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TYPICAL PHASE NOISE
0
155.52MHz Input/Output
-10
RMS Phase Noise Jitter
12K to 20MHz
-20
-30
-40
-50
-70
Z
(dBc
H )
PHASE NOISE
-60
-80
Output Phase Noise: 12k to 20MHz = 339fs
-90
Output Phase Noise: 12k to 20MHz = 286fs
-100
-110
-120
-130
-140
-150
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
853031AY
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REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC,
VCCO
Qx
VCC
SCOPE
nCLK, nPLK
LVPECL
V
Cross Points
PP
V
CMR
CLK, PLK
nQx
VEE
V EE
-0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
nQy
nQy
Qx
PART 2
Qy
Qy
t sk(pp)
t sk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK,
nPLK
80%
80%
CLK,
PLK
VSW I N G
Clock
Outputs
nQ0:nQ8
20%
20%
tF
tR
Q0:Q8
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0:nQ8
Q0:Q8
Pulse Width
t
odc =
PERIOD
t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
853031AY
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REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
R2
1K
0.1uF
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
853031AY
FIN
50Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
TERMINATION
FOR
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in Figure 4B can be eliminated and the
termination is shown in Figure 4C.
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
-
2,5V LVPECL
Driv er
2,5V LVPECL
Driv er
R2
62.5
R1
50
R4
62.5
R2
50
R3
18
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 5A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER
BY
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
BY
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVDS DRIVER
BY
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER WITH AC COUPLE
853031AY
BY
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11
REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 6A to 6E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the
most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination requirements.
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R1
50
CML
R4
120
R3
120
R2
50
Zo = 60 Ohm
SSTL
Zo = 50 Ohm
PCLK
PCLK
Zo = 60 Ohm
Zo = 50 Ohm
nPCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
FIGURE 6A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
HiPerClockS
PCLK/nPCLK
R2
120
FIGURE 6B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
C1
LVDS
R4
1K
R3
1K
PCLK
CLK
R5
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
C2
nPCLK
Zo = 50 Ohm
HiPerClockS
Input
R1
1K
R2
84
FIGURE 6C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
HiPerClockS
PCL K/n PC LK
R2
1K
FIGURE 6D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
84
R4
84
PCLK
nPCLK
R5
100 - 200
R6
100 - 200
R1
125
HiPerClockS
PCLK/nPCLK
R2
125
FIGURE 6E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853031AY
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REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION SCHEMATIC EXAMPLE
two terminations examples are shown in this schematic. For
more termination approaches, please refer to the LVPECL Termination Application Note.
Figure 7 shows an example of ICS853031 application schematic.
In this example, the device is operated at VCC=3.3V. The
decoupling capacitor should be located as close as possible to
the power pin. The input is driven by a 3.3V LVPECL driver. Only
VCCO = 3.3V
R3
133
R1
133
VCC = 3.3V
VCC = 3.3V
VCCO = 3.3V
Zo = 50 Ohm
+
Q0
R11
50
Zo = 50 Ohm
32
31
30
29
28
27
26
25
3.3V
CLK_SEL
LVPECL
R8
50
VCCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
VCCO
VCCO
Q3
nQ3
Q4
nQ4
Q5
nQ5
VCCO
VCC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
VEE
CLK_EN
R4
82.5
24
23
22
21
20
19
18
17
VCCO
nQ8
Q8
nQ7
Q7
nQ6
Q6
VCCO
Zo = 50 Ohm
1
2
3
4
5
6
7
8
R2
82.5
R9
50
U1
ICS853031
9
10
11
12
13
14
15
16
Zo = 50 Ohm
-
nQ0
C7
0.1uF
R10
50
Zo = 50 Ohm
Q8
+
-
Zo = 50 Ohm
nQ8
(U1-9)
VCCO
C1
0.1uF
(U1-17)
(U1-16)
C2
0.1uF
C3
0.1uF
(U1-24)
C4
0.1uF
(U1-25)
C5
0.1uF
R5
50
(U1-32)
C6
0.1uF
Optional
Y-Termination
R6
50
R7
50
FIGURE 7. ICS853031 SCHEMATIC EXAMPLE
853031AY
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13
REV. B SEPTEMBER 16, 2004
Integrated
Circuit
Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853031.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853031 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V ± 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 77mA = 266.8mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 30.94mW = 278.5mW
Total Power_MAX (3.465V, with all outputs switching) = 266.8mW + 278.5mW = 545.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.545W * 42.1°C/W = 108°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT
TERMINATION
AND
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
=V
OL_MAX
CCO_MAX
-V
OL_MAX
CCO_MAX
– 0.935V
) = 0.935V
For logic low, VOUT = V
(V
=V
CCO_MAX
– 1.67V
) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
CCO_MAX
L
-V
)=
OH_MAX
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
)=
OL_MAX
[(2V - 1.67V)/50Ω] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θ by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
200
500
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853031 is: 394
853031AY
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REV. B SEPTEMBER 16, 2004
ICS853031
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE
AND
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
DIMENSIONS - Y SUFFIX
FOR
32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
0.80 BASIC
e
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
853031AY
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REV. B SEPTEMBER 16, 2004
Integrated
Circuit
Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS853031AY
ICS853031AYT
ICS853031AYLF
Marking
ICS853031AY
ICS853031AY
ICS853031AYL
ICS853031AYLFT
ICS853031AYL
Package
32 Lead LQFP
32 Lead LQFP on Tape and Reel
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP on
Tape and Reel
Count
250 per tray
1000
250 per tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
1000
-40°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853031AY
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18
REV. B SEPTEMBER 16, 2004
Integrated
Circuit
Systems, Inc.
ICS853031
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
B
Table
T4B
Page
4
T4C
4
Differential Table - change IIL (CLK) from -10µA min. to -50µA min.
T4D
5
3.3V LVPECL Table - change VOH @ 85° to 2.22V min. and 2.295V typical from
2.295V min. and 2.33V typical.
Changed IIL (PCLK) from -10µA min. to -50µA min.
T4E
5
2.5V LVPECL Table - change VOH @ 85° to 1.42V min. and 1.495V typical from
1.495V min. and 1.53V typical.
T4F
6
ECL Table - change VOH @ 85° to -1.08V min. and -1.005V typical from
-1.005V min. and -0.97V typical.
9
Revised LVPECL Output Termination drawings.
B
B
853031AY
2
4
5
6
18
Description of Change
LVCMOS Table - changed IIL (CLK_SEL) from -10µA min. to -50µA min.
12
Revised Figure 6D.
13
Added Schematic Layout
T1
Pin Description Table - changed nCLK & nPCLK Type to Pullup (only).
T4B
LVCMOS Table - added 2.625V in Test Conditions.
T4D & E LVPECL DC Characteristics Tables - corrected Note 3.
T4F
ECL DC Characteristics Tables - corrected Note 3.
T9
Ordering Information Table - added Lead-Free par t number.
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19
Date
9/10/03
8/19/04
9/16/04
REV. B SEPTEMBER 16, 2004
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