Full/Low Speed 2.5 kV USB Digital Isolator ADuM3160 FEATURES CMOS and monolithic air core transformer technology, this isolation component provides outstanding performance characteristics and is easily integrated with low and full speed USB-compatible peripheral devices. USB 2.0 compatible Low and full speed data rate: 1.5 Mbps and 12 Mbps Bidirectional communication 4.5 V to 5.5 V VBUS operation 7 mA maximum upstream supply current at 1.5 Mbps 8 mA maximum upstream supply current at 12 Mbps 2.3 mA maximum upstream idle current Upstream short-circuit protection Class 3A contact ESD performance per ANSI/ESD STM5.1-2007 High temperature operation: 105°C High common-mode transient immunity: >25 kV/μs 16-lead SOIC wide body package RoHS compliant Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A IEC 60950-1: 600 V rms VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak Many microcontrollers implement USB so that it presents only the D+ and D− lines to external pins. This is desirable in many cases because it minimizes external components and simplifies the design; however, this presents particular challenges when isolation is required. Because the USB lines must switch between actively driving D+/D− and allowing external resistors to set the state of the bus, the ADuM3160 provides mechanisms for detecting the direction of data flow and control over the state of the output buffers. Data direction is determined on a packet-by-packet basis. The ADuM3160 uses the edge detection based iCoupler technology in conjunction with internal logic to implement a transparent, easily configured, upstream-facing port isolator. Isolating the upstream port provides several advantages in simplicity, power management, and robust operation. The isolator has a propagation delay comparable to that of a standard hub and cable. It operates with the bus voltage on either side ranging from 4.5 V to 5.5 V, allowing connection directly to VBUSx by internally regulating the voltage to the signaling level. The ADuM3160 provides isolated control of the pull-up resistor to allow the peripheral to control connection timing. The device draws low enough idle current that a suspend state is not required. A 5 kV version, the ADuM4160, is also available. APPLICATIONS USB peripheral isolation Isolated USB hub GENERAL DESCRIPTION The ADuM31601 is a USB port isolator, based on Analog Devices, Inc., iCoupler® technology. Combining high speed REG 16 VBUS2 GND1 2 15 GND2 VDD1 3 14 VDD2 PDEN 4 13 SPD SPU 5 12 PIN UD– 6 11 DD– UD+ 7 10 DD+ GND1 8 9 VBUS1 1 REG PU LOGIC PU LOGIC GND2 09125-001 FUNCTIONAL BLOCK DIAGRAM Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329. Other patents pending. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADuM3160 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................8 General Description ......................................................................... 1 Applications Information .............................................................. 10 Functional Block Diagram .............................................................. 1 Functional Description .............................................................. 10 Revision History ............................................................................... 2 Product Usage ............................................................................. 10 Specifications..................................................................................... 3 Compatibility of Upstream Applications ................................ 11 Electrical Characteristics ............................................................. 3 Power Supply Options ............................................................... 11 Package Characteristics ............................................................... 4 PC Board Layout ........................................................................ 11 Regulatory Information ............................................................... 4 DC Correctness and Magnetic Field Immunity ..................... 11 Insulation and Safety-Related Specifications ............................ 5 Insulation Lifetime ..................................................................... 12 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 5 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 Recommended Operating Conditions ...................................... 6 Absolute Maximum Ratings............................................................ 7 REVISION HISTORY 9/10—Rev. 0 to Rev. A Changes to Data Sheet Title, Features, Applications, and General Description and Added USB Logo .................................. 1 Changes to Electrical Characteristics Section and Table 1 ......... 3 Changes to Table 2 and Table 3, Endnote 1................................... 4 Changes to Table 5 ............................................................................ 5 Changes to Table 9 ............................................................................ 8 Changes to Table 10 .......................................................................... 9 Changes to Functional Description Section ............................... 10 Changes to Product Usage Section............................................... 10 Added Compatibility of Upstream Applications Section .......... 11 Changes to Power Supply Options Section and DC Correctness and Magnetic Field Immunity Section ........................................ 11 7/10—Revision 0: Initial Version Rev. A | Page 2 of 16 ADuM3160 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 4.5 V ≤ VBUS1 ≤ 5.5 V, 4.5 V ≤ VBUS2 ≤ 5.5 V; 3.1 V ≤ VDD1 ≤ 3.6 V, 3.1 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. All voltages are relative to their respective ground. Table 1. Parameter DC SPECIFICATIONS Total Supply Current2 1.5 Mbps VDD1 or VBUS1 Supply Current VDD2 or VBUS2 Supply Current 12 Mbps VDD1 or VBUS1 Supply Current VDD2 or VBUS2 Supply Current Idle Current VDD1 or VBUS1 Idle Current Input Currents Single-Ended Logic High Input Threshold Single-Ended Logic Low Input Threshold Single-Ended Input Hysteresis Differential Input Sensitivity Logic High Output Voltages Logic Low Output Voltages VDD1 and VDD2 Supply Under Voltage Lockout VBUS1 Supply Under Voltage Lockout VBUS2 Supply Under Voltage Lockout Transceiver Capacitance Capacitance Matching Full Speed Driver Impedance Impedance Matching SWITCHING SPECIFICATIONS, I/O PINS, LOW SPEED Low Speed Data Rate Propagation Delay3 Side 1 Output Rise/Fall Time (10% to 90%) Low Speed Low Speed Differential Jitter, Next Transition Low Speed Differential Jitter, Paired Transition SWITCHING SPECIFICATIONS, I/O PINS, FULL SPEED Maximum Data Rate Propagation Delay3 Output Rise/Fall Time (10% to 90%) Full Speed Full Speed Differential Jitter, Next Transition Full Speed Differential Jitter, Paired Transition Symbol Typ Max Unit Test Conditions1 IDD1 (L) IDD2 (L) 5 5 7 7 mA mA 750 kHz logic signal rate, CL = 450 pF 750 kHz logic signal rate, CL = 450 pF IDD1 (F) IDD2 (F) 6 6 8 8 mA mA 6 MHz logic signal rate, CL = 50 pF 6 MHz logic signal rate, CL = 50 pF 1.7 +0.1 2.3 +1 mA µA IDD1 (I) IDD−, IDD+, IUD+, IUD−, ISPD, IPIN, ISPU, IPDEN VIH VIL VHST VDI VOH VOL VUVLO VUVLOB1 VUVLOB2 CIN ZOUTH Min −1 2.0 0.8 0.4 0.2 2.8 0 2.4 3.5 3.5 3.6 0.3 3.1 4.35 4.4 10 10 4 UD+, UD−, DD+, DD− to ground 325 Mbps ns 300 ns ns ns CL = 50 pF CL = 50 pF, SPD = SPU = low VDD1, VDD2 = 3.3 V CL = 450 pF, SPD = SPU = low VDD1, VDD2 = 3.3 V CL = 50 pF CL = 50 pF Mbps ns ns ns ns CL = 50 pF CL = 50 pF CL = 50 pF, SPD = SPU = high CL = 50 pF CL = 50 pF 20 1.5 tRF, tFF 75 |tLJN| |tLJP| tPHL, tPLH tR, tFL |tHJN| |tHJP| 45 15 12 20 4 60 3 1 Rev. A | Page 3 of 16 |VXD+ − VXD−| RL = 15 kΩ, VL = 0 V RL = 1.5 kΩ, VL = 3.6 V pF % Ω % 10 tPHL, tPLH V V V V V V V V 0 V ≤ VDD−, VDD+, VUD+,VUD−, VSPD, VPIN, VSPU, VPDEN ≤ 3.0 70 20 ADuM3160 Parameter For All Operating Modes Common-Mode Transient Immunity at Logic High Output4 Common-Mode Transient Immunity at Logic Low Output4 Symbol Min Typ |CMH| 25 |CML| 25 Max Unit Test Conditions1 35 kV/µs 35 kV/µs VUD+, VUD−, VDD+, VDD− = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VUD+, VUD−, VDD+, VDD− = 0 V, VCM = 1000 V, transient magnitude = 800 V CL = load capacitance, RL = test load resistance, VL = test load voltage, and VCM = common-mode voltage. The supply current values for the device running at a fixed continuous data rate 50% duty cycle, alternating J and K states. Supply current values are specified with USB-compliant load present. 3 Propagation delay of the low speed DD+ to UD+ or DD− to UD− in either signal direction is measured from the 50% level of the rising or falling edge to the 50% level of the rising or falling edge of the corresponding output signal. 4 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 1 2 PACKAGE CHARACTERISTICS Table 2. Parameter Resistance (Input to Output)1 Capacitance (Input to Output)1 Input Capacitance2 IC Junction-to-Ambient Thermal Resistance Symbol RI-O CI-O CI θJA Min Typ 1012 2.2 4.0 45 Max Unit Ω pF pF °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. 1 REGULATORY INFORMATION The ADuM3160 has been approved by the organizations listed in Table 3. See Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 3. UL Recognized Under 1577 Component Recognition Program1 Single Protection 2500 V rms Isolation Voltage File E214100 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-07 and IEC 60950-1, 2nd ed., 600 V rms (849 V peak) maximum working voltage3 File 205078 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, 560 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM3160 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 10 µA). In accordance with DIN V VDE V 0884-10, each ADuM3160 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component indicates DIN V VDE V 0884-10 approval. 3 See Table 8 for recommended maximum working voltages under various operating conditions. 1 2 Rev. A | Page 4 of 16 ADuM3160 INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol Value 2500 L(I01) 8.0 min Unit V mm Minimum External Tracking (Creepage) L(I02) 7.7 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min mm >175 V IIIa Conditions 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 5. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 + Side 2 Current Insulation Resistance at TS 1 Conditions1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak 896 672 V peak V peak VTR 4000 V peak TS IS1 RS 150 550 >109 °C mA Ω VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure (see Figure 2) VIO = 500 V For information about tM, tTR, and VIO, see DIN V VDE V 0884-10. Rev. A | Page 5 of 16 600 RECOMMENDED OPERATING CONDITIONS 500 Table 6. Parameter Operating Temperature Supply Voltages1 Input Signal Rise and Fall Times 400 300 1 200 100 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 Symbol Min TA −40 VBUS1, VBUS2 3.0 Max +105 5.5 1.0 Unit °C V ms All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. 09125-002 SAFE OPERATING VDD1 CURRENT (mA) ADuM3160 Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. A | Page 6 of 16 ADuM3160 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages (VBUS1, VBUS2, VDD1, VDD2) 1, 2 Input Voltage (VUD+, VUD−, VSPU)1 Output Voltage (VDD−, VDD+, VSPD, VPIN)1 Average Output Current per Pin 3 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients 4 Rating −40°C to +150°C −40°C to +105°C −0.5 V to +6.5 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDD2 + 0.5 V ESD CAUTION −10 mA to +10 mA −10 mA to +10 mA −100 kV/µs to +100 kV/µs All voltages are relative to their respective ground. VDD1, VDD2, VBUS1, and VBUS2 refer to the supply voltages on the input and output sides of a given channel, respectively. 3 See Figure 2 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage. 1 2 Table 8. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform Basic Insulation AC Voltage, Unipolar Waveform Basic Insulation DC Voltage Basic Insulation 1 Max Unit Constraint 565 V peak 50-year minimum lifetime 849 V peak Maximum approved working voltage per IEC 60950-1 849 V peak Maximum approved working voltage per IEC 60950-1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Rev. A | Page 7 of 16 ADuM3160 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VBUS1 1 16 VBUS2 GND1* 2 15 GND2* SPU 5 UD– 6 ADuM3160 14 VDD2 13 SPD TOP VIEW 12 PIN (Not to Scale) 11 DD– UD+ 7 10 DD+ GND1* 8 9 GND2* *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. 09125-003 VDD1 3 PDEN 4 Figure 3. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic Direction Description VBUS1 Power Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage (4.5 V to 5.5 V), connect the VBUS1 pin to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect VBUS1 to VDD1 and to the external 3.3 V power supply. A bypass to GND1 is required. GND1 Return Ground 1. Ground reference for Isolator Side 1. VDD1 Power Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage (4.5 V to 5.5 V), the VDD1 pin should be used for a bypass capacitor to GND1. Signal lines that may require pull-up, such as PDEN and SPU, should be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect VBUS1 to VDD1 and to the external 3.3 V power supply. Bypass to GND1 is required. PDEN Input Pull-Down Enable. This pin is read when exiting reset. This pin must be connected to VDD1 for standard operation. When connected to GND1 while exiting from reset, the downstream pull-down resistors are disconnected, allowing buffer impedance measurements. SPU Input Speed Select Upstream Buffer. Active high logic input. Selects the full speed slew rate and timing and the logic conventions when SPU is high and low speed slew rate, timing, and logic conventions when SPU is tied low. This input must be set high via connection to VDD1 or set low via connection to GND1 and must match Pin 13. UD− I/O Upstream D−. UD+ I/O Upstream D+. GND1 Return Ground 1. Ground reference for Isolator Side 1. GND2 Return Ground 2. Ground reference for Isolator Side 2. DD+ I/O Downstream D+. DD− I/O Downstream D−. PIN Input Upstream Pull-Up Enable. SPD controls the power connection to the pull-up for the upstream port. It can be tied to VDD2 for operation on power-up or tied to an external control signal for an application requiring delayed enumeration. SPD Input Speed Select Downstream Buffer. Active high logic input. Selects the full speed slew rate and timing and the logic conventions when SPU is high and low speed slew rate, timing, and logic conventions when SPD is tied low. This input must be set high via connection to VDD2 or low via connection to GND2, and must match Pin 5. VDD2 Power Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage (4.5 V to 5.5 V), the VDD2 pin should be used for a bypass capacitor to GND2. Signal lines that may require pull-up, such as SPD, can be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect VBUS2 to VDD2 and to the external 3.3 V power supply. Bypass to GND2 is required. GND2 Return Ground 2. Ground reference for Isolator Side 2. VBUS2 Power Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage (4.5 V to 5.5 V), connect VBUS2 to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect VBUS2 to VDD2 and to the external 3.0 V to 3.3 V power supply. A bypass to GND2 is required. Rev. A | Page 8 of 16 ADuM3160 Table 10. Truth Table, Control Signals, and Power (Positive Logic) VSPU Input1 VUD+, VUD− State1 VBUS1, VDD1 State VBUS2, VDD2 State H Active Powered Powered VDD+, VDD− VPIN State1 Input1 H Active L Active Powered Powered Active H L L Active Powered Powered Active H H H Active Powered Powered Active H L X Z Powered Powered Z L X Upstream Side 1 presents a disconnected state to the USB cable. X X Unpowered Powered Z X X When power is not present on VDD1, the downstream data output drivers revert to high-Z within 32 bit times. The downstream side initializes in the high-Z state. X Z Powered Unpowered X X X When power is not present on the VDD2, the upstream side disconnects the pull-up and disables the upstream drivers within 32 bit times. 1 VSPD Input1 H Description Input and output logic set for full speed logic convention and timing. Input and output logic set for low speed logic convention and timing. Not allowed. VSPU and VSPD must be set to the same value. The USB host detects communications error. Not allowed. VSPU and VSPD must be set to the same value. The USB host detects communications error. H represents logic high input or output, L represents logic low input or output, X represents the don’t care logic input or output, and Z represents the high impedance output state. Rev. A | Page 9 of 16 ADuM3160 APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION PRODUCT USAGE USB isolation in the D+/D− lines is challenging for several reasons. First, access to the output enable signals is normally required to control the transceiver. Some level of intelligence must be built into the isolator to interpret the data stream and determine when to enable and disable its upstream and downstream output buffers. Second, the signal must be faithfully reconstructed on the output side of the coupler while retaining precise timing and not passing transient states such as invalid SE0 and SE1 states. In addition, the part must meet the low power requirements of the suspend mode. The ADuM3160 is designed to be integrated into a USB peripheral with an upstream-facing USB port as shown in Figure 4. The key design points are as follows: During the data transfers, the input side of the coupler holds its output buffers disabled. The output side enables its output buffers and disables edge detection from the input buffers. This allows the data to flow in one direction without wrapping back through the coupler causing the iCoupler to latch. Timing is based on the differential input signal transition. Logic is included to eliminate any artifacts due to different input thresholds of the differential and single-ended buffers. The input state is transferred across the isolation barrier as one of three valid states, J, K, or SE0. The signal is reconstructed at the output side with a fixed time delay from the input side differential input. The iCoupler does not have a special suspend mode, nor does it need one because its power supply current is below the suspend current limit of 2.5 mA when the USB bus is idle. The ADuM3160 is designed to interface with an upstreamfacing low/full speed USB port by isolating the D+/D− lines. An upstream-facing port supports only one speed of operation; therefore, the speed-related parameters, J/K logic level, and D+/D− slew rate are set to match the speed of the upstreamfacing peripheral port (see Table 10). A control line on the downstream side of the ADuM3160 activates the idle state pull-up resistor. This allows the downstream port to control when the upstream port attaches to the USB bus. The pin can be tied to the peripheral pull-up, a control line, or the peripheral power supply depending on when the initial bus connect is performed. The USB host provides power for the upstream side of the ADuM3160 through the cable. The peripheral supply provides power to the downstream side of the ADuM3160. The DD+/DD− lines of the isolator interface with the peripheral controller, and the UD+/UD− lines of the isolator connect to the cable or host. Peripheral devices have a fixed data rate that is set at design time. The ADuM3160 has configuration pins, SPU and SPD, that are set by the user to match this speed on the upstream and downstream sides of the coupler. USB enumeration begins when either the D+ or D−line is pulled high at the peripheral end of the USB cable. Control of the timing of this event is provided by the PIN input on the downstream side of the coupler. Pull-up and pull-down resistors are implemented inside the coupler. Only external series resistors and bypass capacitors are required for operation. • • • • • PERIPHERAL 3.3V VBUS USB HOST D+ D– ADuM3160 D+ D– µCPU POWER SUPPLY GNDBUS 09125-004 The iCoupler technology is based on edge detection and, therefore, lends itself well to the USB application. The flow of data through the device is accomplished by monitoring the inputs for activity and setting the direction for data transfer based on a transition from the idle state. After data directionality is established, data is transferred until either an end of packet (EOP) or a sufficiently long idle state is encountered. At this point, the coupler disables its output buffers and monitors its inputs for the next activity. • Figure 4. Typical ADuM3160 Application Other than the delayed application of pull-up resistors, the ADuM3160 is transparent to USB traffic, and no modifications to the peripheral design are required to provide isolation. The isolator adds propagation delay to the signals comparable to a hub and cable. Isolated peripherals must be treated as if there were a built-in hub when determining the maximum number of hubs in a data chain. Hubs can be isolated like any other peripheral. Isolated hubs can be created by placing an ADuM3160 on the upstream port of a hub chip. This configuration can be made compliant if counted as two hub delays. The hub chip allows the ADuM3160 to operate at full speed yet maintains compatibility with low speed devices. Rev. A | Page 10 of 16 ADuM3160 COMPATIBILITY OF UPSTREAM APPLICATIONS PC BOARD LAYOUT The ADuM3160 is designed specifically for isolating a USB peripheral. However, the chip does have two USB interfaces that meet the electrical requirements for driving USB cables. This opens the possibility of implementing isolation in downstream USB ports such as isolated cables, which have generic connections to both upstream and downstream devices, as well as isolating host ports. The ADuM3160 digital isolator requires no external interface circuitry for the logic interfaces. For full speed operation, the D+ and D− lines on each side of the device requires a 24 Ω ± 1% series termination resistor. These resistors are not required for low speed applications. Power supply bypassing is required at the input and output supply pins (see Figure 5). Install bypass capacitors between VBUSx and VDDx on each side of the chip. The capacitor value should have a minimum value of 0.1 µF and low ESR. The total lead length between both ends of the capacitor and the power supply pin should not exceed 10 mm. The practical result of using the ADuM3160 in a host port is that the port works at a single speed. This behavior is acceptable in embedded host applications; however, this type of interface is not fully compliant as a general-purpose USB port. Bypassing between Pin 2 and Pin 8 and between Pin 9 and Pin 15 should also be considered unless the ground pair on each package side is connected close to the package. All logic level signals are 3.3 V and should be referenced to the local VDDx pin or 3.3 V logic signals from an external source. PDEN SPU UD– UD+ GND1 POWER SUPPLY OPTIONS Two power pins are present on each side, VBUSx and VDDx. If 5 V is supplied to VBUSx, an internal regulator creates 3.3 V to power the xD+ and xD− drivers. VDDx provides external access to the 3.3 V supply to allow external bypass as well as bias for external pull-ups. If only 3.3 V is available, it can be supplied to both VBUSx and VDDx. This disables the regulator and powers the coupler directly from the 3.3 V supply. Figure 5 shows how to configure a typical application when the upstream side of the coupler receives power directly from the USB bus and the downstream side is receiving 3.3 V from the peripheral power supply. The downstream side can run from a 5V VBUS2 power supply as well. It can be connected in the same manner as VBUS1, as shown in Figure 5, if needed. VBUS2 GND2 VDD2 VBUS1 GND1 VDD1 Isolated cable applications have a similar issue. The cable operates at the preset speed only; therefore, treat cable assemblies as custom applications, not general-purpose isolated cables. In most USB transceivers, 3.3 V is derived from the 5 V USB bus through an LDO regulator. The ADuM3160 includes internal LDO regulators on both the upstream and downstream sides. The output of the LDO is available on the VDD1 and VDD2 pins. In some cases, especially on the peripheral side of the isolation, there may not be a 5 V power supply available. The ADuM3160 has the ability to bypass the regulator and run on a 3.3 V supply directly. VBUS2 = 3.3V INPUT VDD2 = 3.3V INPUT VBUS1 = 5.0V INPUT VDD1 = 3.3V OUTPUT ADuM3160 SPD PIN DD– DD+ GND2 09125-005 In a fully compliant application, a downstream facing port must be able to detect whether a peripheral is low speed or full speed based on the application of the upstream pull-up. The buffers and logic conventions must adjust to match the requested speed. Because the ADuM3160 sets its speed by hardwiring pins, the part cannot adjust to different peripherals on the fly. Figure 5. Suggested Printed Circuit Board Layout Example In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins to exceed the device Absolute Maximum Ratings, thereby leading to latch-up or permanent damage. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. The limitation on the magnetic field immunity of the ADuM3160 is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM3160 is examined because it represents the most susceptible mode of operation. Rev. A | Page 11 of 16 ADuM3160 where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM3160 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 6. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 7. Maximum Allowable Current for Various Current-to-ADuM3160 Spacings 100 Note that, at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces may induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. 10 1 INSULATION LIFETIME 0.1 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 09125-006 0.01 0.001 1k DISTANCE = 1m 100 09125-007 V = (−dβ/dt)∑∏rn2; n = 1, 2, … , N 1000 MAXIMUM ALLOWABLE CURRENT (kA) The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by Figure 6. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM3160 transformers. Figure 7 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM3160 is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, a 0.5 kA current must be placed 5 mm away from the ADuM3160 to affect component operation. All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM3160. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 8 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM3160 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 8, Figure 9, and Figure 10 illustrate these different isolation voltage waveforms. Rev. A | Page 12 of 16 ADuM3160 varying between 0 and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. Note that the voltage shown in Figure 8 and Figure 9 is presented as sinusoidal for illustration purposes only. The sinusoidal depiction is meant to represent any voltage waveform Rev. A | Page 13 of 16 09125-008 RATED PEAK VOLTAGE 0V Figure 8. Bipolar AC Waveform RATED PEAK VOLTAGE 09125-009 In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 8 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage case. Any crossinsulation voltage waveform that does not conform to Figure 9 or Figure 10 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 8. 0V Figure 9. Unipolar AC Waveform RATED PEAK VOLTAGE 09125-010 Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage. 0V Figure 10. DC Waveform ADuM3160 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 45° 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 032707-B 1 Figure 11. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimension shown in millimeters and (inches) ORDERING GUIDE Model1 ADuM3160BRWZ ADuM3160BRWZ-RL EVAL-ADUM4160EBZ 1 Number of Inputs, VDD1 Side 2 2 Number of Inputs, VDD2 Side 2 2 Maximum Full Speed Data Rate (Mbps) 12 12 Maximum Full Speed Propagation Delay, 5 V (ns) 70 70 Maximum Full Speed Jitter (ns) 3 3 Z = RoHS Compliant Part. Rev. A | Page 14 of 16 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 16-Lead SOIC_W 16-Lead SOIC_W Evaluation Board Package Option RW-16 RW-16 ADuM3160 NOTES Rev. A | Page 15 of 16 ADuM3160 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09125-0-9/10(A) Rev. A | Page 16 of 16