Cypress CY8C21645-12PVXE Automotive psocâ® programmable system-on-chipâ ¢ Datasheet

CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
®
Automotive PSoC
Programmable System-on-Chip™
Features
❐
■
Automotive Electronics Council (AEC) Q100 qualified
Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Automotive A-grade: 3.0 V to 5.25 V operation at –40 °C to
+85 °C temperature range
❐ Automotive E-grade: 4.75 V to 5.25 V operation at –40 °C to
+125 °C temperature range
®
■ Advanced peripherals (PSoC blocks)
❐ Six analog Type ‘E’ PSoC blocks provide:
• Up to four comparators with digital-to-analog converters
(DAC) references
• Up to 10-bit single or dual analog-to-digital converters
(ADCs)
❐ Up to eight digital PSoC blocks provide:
• 8 to 32-bit timers, counters, and pulse width modulators
(PWMs)
• One-shot, multi-shot mode in timers and PWMs
• PWM with deadband in one digital block
• Shift register, cyclical redundancy check (CRC), and
pseudo random sequence (PRS) modules
• Full- or half-duplex UARTs
• SPI masters or slaves, 8- to 16-bit variable data length
• Connectable to all general-purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
❐ Powerful synchronization support, analog module operations
can be synchronized by digital blocks or external signals.
■ High-speed 10-bit successive approximation register (SAR)
ADC with sample and hold optimized for embedded control
®
®
■ CY8C22345H devices integrate Immersion TouchSense
haptics technology for ERM drive control
■ Precision, programmable clocking
❐ Internal oscillator up to 24 MHz
❐ High accuracy 24 MHz with optional 32-kHz crystal and
phase locked loop (PLL)
❐ Optional external oscillator, up to 24 MHz
❐ Internal low speed, low-power oscillator for watchdog and
sleep functionality
■ Flexible on-chip memory
❐ Up to 16 KB flash program storage, 1000 erase/write cycles
❐ Up to 1 KB SRAM data storage
❐ In-System Serial Programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
®
■ Optimized CapSense resource
❐ Supports two CapSense channels with simultaneous
scanning
❐ Two current DACs provide programmable sensor tuning in
firmware
■
Cypress Semiconductor Corporation
Document Number: 001-55397 Rev. *I
•
Two dedicated clock resources for CapSense
Two dedicated 16-bit timers/counters for CapSense
scanning
Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
Programmable pin configurations
❐ 25 mA sink, 10 mA drive on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIOs
❐ Analog input on all GPIOs
❐ Configurable interrupt on all GPIOs
Additional system resources:
2
❐ I C master, slave, or multi-master
• Operation up to 400 kHz
• Hardware address detection feature
❐ Watchdog and sleep timers
❐ User-configurable low voltage detection
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
❐ Hardware real time clock (RTC) block
❐
■
■
■
198 Champion Court
Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
PSoC CORE
System Bus
Global Digital
Interconnect
SRAM
1KB/512B
Global Analog Interconnect
SROM
Flash 16K/8K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
10-bit SAR
ADC
Digital Block
Array
Multiply
Accum.
Analog
Ref
Analog
Input
Muxing
CapSense Digital
Resources
Digital
Clocks
ANALOG SYSTEM
Analog
Block
Array
POR and LVD
I2C
RTC
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 18, 2011
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CY8C22345, CY8C22345H, CY8C22645
Contents
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
Digital System ............................................................. 3
Analog System ............................................................ 4
Haptics TS2000 Controller .......................................... 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 6
PSoC Designer Software Subsystems ........................ 6
Designing with PSoC Designer ....................................... 7
Select User Modules ................................................... 7
Configure User Modules .............................................. 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pinouts .............................................................................. 8
28-Pin Part Pinout ....................................................... 8
48-Pin Part Pinout ....................................................... 9
Registers ......................................................................... 11
Register Conventions ................................................ 11
Register Mapping Tables .......................................... 11
Document Number: 001-55397 Rev. *I
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ....................................... 15
Operating Temperature ............................................ 15
DC Electrical Characteristics ..................................... 16
AC Electrical Characteristics ..................................... 21
Packaging Information ................................................... 26
Package Dimensions ................................................. 26
Thermal Impedances ................................................ 27
Capacitance on Crystal Pins .................................... 27
Solder Reflow Peak Temperature ............................. 27
Tape and Reel Information ........................................ 28
Development Tool Selection ......................................... 30
Software .................................................................... 30
Development Kits ...................................................... 30
Evaluation Tools ........................................................ 30
Device Programmers ................................................. 31
Accessories (Emulation and Programming) .............. 31
Ordering Information ...................................................... 32
Ordering Code Definitions ........................................ 33
Document Conventions ................................................. 34
Acronyms Used ......................................................... 34
Units of Measure ....................................................... 34
Numeric Naming ........................................................ 34
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 36
Worldwide Sales and Design Support ....................... 36
Products .................................................................... 36
PSoC Solutions ......................................................... 36
Page 2 of 36
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PSoC Functional Overview
The PSoC programmable system-on-chip series of products
consists of many devices. These devices are designed to
replace multiple traditional MCU-based system components with
one low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, as well as
programmable interconnects. This architecture enables the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
Digital System
The digital system is composed of eight digital PSoC blocks.
Each block is an 8-bit resource that may be used alone or
combined with other blocks to form 8-, 16-, 24-, and 32-bit
peripherals, which are called user modules.
Figure 1. Digital System Block Diagram[1]
Port 3
Port 2
Port 0
To System Bus
Digital Clocks
From Core
The PSoC architecture, shown in the Block Diagram on page 1,
consists of four main areas: PSoC core, digital system, analog
system, and system resources. Configurable global busing
allows the combining of all the device resources into a complete
custom system. The PSoC family can have up to five I/O ports
connecting to the global digital and analog interconnects,
providing access to eight digital blocks[1] and six analog blocks.
To Analog
System
DIGITAL SYSTEM
Row 0
DBC00
DBC01
DCC02
4
DCC03
4
Row Output
Configuration
Row Input
Configuration
Digital PSoC Block Array
8
8
PSoC Core
8
Row Input
Configuration
8
The M8C CPU core is a powerful processor with speeds up to
24 MHz (up to 12 MHz for E-grade devices), providing four MIPS
(two MIPS for E-grade devices) 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller to simplify the
programming of real time embedded events.
Row 1
DBC00
GIE[7:0]
GIO[7:0]
Program execution is timed and protected using the included
Sleep Timer and Watch Dog Timer (WDT).
DBC01
DCC02
DCC03
Global Digital
Interconnect
Row Output
Configuration
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO.
Memory encompasses 16 KB of flash (8 KB for CY8C21x45
devices) for program storage, 1 KB of SRAM (512 bytes for
CY8C21x45 devices) for data storage, and EEPROM emulation
using the flash. Program flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
Port 1
Port 4
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■
PWMs (8- to 32-bit)
■
PWMs with deadband (8- to 32-bit)
The PSoC device incorporates flexible internal clock generators,
including a 24-MHz internal main oscillator (IMO). For A-grade
devices the 24-MHz IMO can also be doubled to 48 MHz for use
by the digital system. A low-power 32-kHz internal low-speed
oscillator (ILO) is provided for the Sleep Timer and WDT. If
crystal accuracy is required, the 32.768 kHz external crystal
oscillator (ECO) is available for use as a RTC, and can optionally
generate a crystal-accurate 24-MHz system clock using a PLL.
The clocks, together with programmable clock dividers (as a
system resource), provide the flexibility to integrate almost any
timing requirement into the PSoC device.
■
Counters (8- to 32-bit)
■
Timers (8- to 32-bit)
■
One-shot and multi-shot modules
■
Full or half-duplex 8-bit UART with selectable parity (up to two
full-duplex or four half-duplex)
■
SPI master and slave (up to four total) with programmable data
length from 8 to 16 bits.
■
Shift register (1- to 32-bit)
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Each pin can also generate a system interrupt.
■
I2C master, slave, or multi-master (one available)
■
CRC/generator (16-bit)
■
IrDA (up to two)
■
PRS generators (8- to 32-bit)
Note
1. CY8C22x45 devices have 2 digital rows with 8 digital blocks. CY8C21x45 devices only have 1 digital row with 4 digital blocks.
Document Number: 001-55397 Rev. *I
Page 3 of 36
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The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Figure 2. Analog System Block Diagram
Array Input Configuration
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides a choice of
system resources for your application. Family resources are
shown in Table 1 on page 5.
ACI0[1:0]
ACI1[1:0]
ACI1[1:0]
ACI1[1:0]
ACE00
ACE01
ACE10
ACE11
ASE10
ASE11
Analog System
The Analog System of CY8C21x45 and CY8C22x45 PSoC
devices consists of a 10-bit SAR ADC and six configurable
analog blocks.
The programmable 10-bit SAR ADC is an optimized ADC with a
fast maximum sample rate. External filters are required on ADC
input channels for antialiasing. This ensures that any out-of-band
content is not folded into the input signal band.
AmuxL
AmuxR
P0[0:7]
Reconfigurable analog resources allow creating complex analog
signal flows. Analog peripherals are very flexible and may be
customized to support specific application requirements. Some
of the more common PSoC analog functions (most available as
user modules) are:
■
Analog-to-digital converters (single or dual, with up to 10-bit
resolution)
■
Pin-to-pin comparator
■
Single-ended comparators (up to four) with absolute (1.3 V)
reference or DAC reference
■
Block Array
ACI2[3:0]
10 bit SAR ADC
Analog Reference
Interface to
Digital System
AGND
Reference
Generators
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Precision voltage reference (1.3 V nominal)
CY8C21x45 and CY8C22x45 devices have six limited-functionality Type 'E' analog blocks. These analog blocks are arranged
in four columns. Each column contains one continuous time (CT)
Type E block. The first two columns also have a switched
capacitor (SC) type E block. Refer to the PSoC Technical
Reference Manual for CY8C21x45 and CY8C22x45 devices for
detailed information on the Type E analog blocks.
Document Number: 001-55397 Rev. *I
Haptics TS2000 Controller
The CY8C22x45H family of devices features an easy-to-use
Haptics controller resource with up to 14 different effects. These
effects are available for use with three different, selectable ERM
modules.
Page 4 of 36
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■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Table 1. PSoC Device Characteristics
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
■
Additional digital resources and clocks dedicated to and
optimized for CapSense.
CY8C29x66[2]
up to
64
4
16
up to
12
4
4
■
RTC hardware block.
CY8C28xxx
up to
44
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
CY8C27x43
up to
44
2
8
up to
12
4
4
12
256 16 KB
Bytes
CY8C24x94[2]
up to
56
1
4
up to
48
2
2
6
1 KB
16 KB
The I2C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multi-master modes are all
supported.
CY8C24x23A[2]
up to
24
1
4
up to
12
2
2
6
256
Bytes
4 KB
CY8C23x33
up to
25
1
4
up to
12
2
2
4
256
Bytes
8 KB
CY8C22x45[2]
up to
38
2
8
up to
38
0
4
6[3]
1 KB
16 KB
CY8C21x45[2]
up to
38
1
4
up to
38
0
4
6[3]
512
Bytes
8 KB
CY8C21x34[2]
up to
28
1
4
up to
28
0
2
4[3]
512
Bytes
8 KB
CY8C21x23
up to
16
1
4
up to
8
0
2
4[3]
256
Bytes
4 KB
CY8C20x34[2]
up to
28
0
0
up to
28
0
0
3[3, 4]
512
Bytes
8 KB
■
■
■
Low voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced power
on reset (POR) circuit eliminates the need for a system
supervisor.
An internal voltage reference provides an absolute reference
for the analog system, including ADCs and DACs.
PSoC Part
Number
Flash
Size
Depending on your PSoC device characteristics, the digital and
analog systems can have varying numbers of digital and analog
blocks. The following table lists the resources available for
specific PSoC device groups. The PSoC families covered by this
datasheet are highlighted in the table.
SRAM
Size
PSoC Device Characteristics
System Resources, some of which are listed in the previous
sections, provide additional capability useful for complete
systems. Additional resources include a MAC, low voltage
detection, and power on reset. The merits of each system
resource are:
Analog
Blocks
Additional System Resources
Digital
I/O
CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
12
2 KB
32 KB
1 KB
16 KB
up to up to up to up to up to up to
3
12
44
4
6
16
Notes
2. Automotive qualified devices available in this group.
3. Limited analog functionality.
4. Two analog blocks and one CapSense® block.
Document Number: 001-55397 Rev. *I
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Getting Started
Development Tools
For in depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
PSoC Designer™ is the revolutionary Integrated Design
Environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
Training
■
Integrated source-code editor (C and assembly)
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
CYPros Consultants
■
Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC
consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
makes it possible to change configurations at run time. In
essence, this allows you to use more than 100 percent of PSoC's
resources for a given application.
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
Document Number: 001-55397 Rev. *I
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C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality In-Circuit Emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24-MHz) operation.
Designing with PSoC Designer
The development process for the PSoC® device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in four steps:
1. Select User Modules.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a pulse
width modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by
selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the user module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows you to
develop and customize your applications in either C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Document Number: 001-55397 Rev. *I
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Pinouts
The automotive CY8C21x45 and CY8C22x45 PSoC devices are available in a variety of packages which are listed and illustrated in
the following tables. Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog mux bus.
However, VSS, VDD, and XRES are not capable of digital I/O.
28-Pin Part Pinout
Table 2. 28-Pin Part Pinout (SSOP)
Type
Pin
No.
Digital
Analog
1
I/O
I, MR
P0[7]
Analog column mux input, CMOD
capacitor pin
2
I/O
I, ML
P0[5]
Analog column mux input, CMOD
capacitor pin
Pin Name
Description
Figure 3. CY8C21345, CY8C22345, and CY8C22345H
28-Pin PSoC Device
AI, MR, P0[7]
AI, ML, P0[5]
AI, ML, P0[3]
3
I/O
I, ML
P0[3]
Analog column mux input
AI, ML, P0[1]
4
I/O
I, ML
P0[1]
Analog column mux input
AI, ML, P2[7]
5
I/O
I, ML
P2[7]
Direct input to analog block
6
I/O
ML
P2[5]
Optional SAR ADC external reference
(EXTREF)
7
8
I/O
I/O
9
10
ML
ML
Power
I/O
ML
P2[1]
Ground connection
P1[7]
I2C Serial Clock (SCL)
ML
P1[5]
I/O
ML
P1[3]
13
I/O
ML
P1[1]
Crystal Input (XTALin), I2C SCL,
ISSP-SCLK[5]
VSS
Ground Connection
Crystal Output (XTALout), I2C SDA,
ISSP-SDATA[5]
MR
P1[0]
16
I/O
MR
P1[2]
17
I/O
MR
P1[4]
18
I/O
MR
P1[6]
19
Input
XRES
P0[6], MR, AI
P0[4], MR, AI
P0[2], MR, AI
P0[0], MR, AI
P2[6], MR, AI
P2[4], MR
P2[2], MR
P2[0], MR
XRES
P1[6], MR
P1[4], MR, EXTCLK
P1[2], MR
P1[0], MR, I2C SDA, XTALout
Optional external clock input (EXTCLK)
Active high external reset with internal
pull-down
I/O
MR
P2[0]
21
I/O
MR
P2[2]
22
I/O
MR
P2[4]
23
I/O
I, MR
P2[6]
Direct input to analog block
24
I/O
I, MR
P0[0]
Analog column mux input
25
I/O
I, MR
P0[2]
Analog column mux input
26
I/O
I, MR
P0[4]
Analog column mux input
27
I/O
I, MR
P0[6]
Analog column mux input
VDD
Supply voltage
Power
VSS
VDD
I C Serial Data (SDA)
20
28
XTALin, I2C SCL, ML, P1[1]
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
I/O
I/O
VSS
ML, P1[3]
VSS
15
ML, P2[1]
I2C SDA, ML, P1[5]
11
Power
ML, P2[3]
I2C SCL, ML, P1[7]
P2[3]
12
14
EXTREF, ML, P2[5]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LEGEND: A = Analog, I = Input, O = Output, MR= Right analog mux bus input, ML= Left analog mux bus input.
Note
5. These are the ISSP pins, which are not High Z after exiting a reset state. See the PSoC Technical Reference Manual for CY8C21x45 and CY8C22x45 devices for details.
Document Number: 001-55397 Rev. *I
Page 8 of 36
[+] Feedback
CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
48-Pin Part Pinout
Table 3. 48-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Type
Pin Name
Description
Digital Analog
I/O
I, MR
P0[7]
Analog column mux input, CMOD
capacitor pin
I/O
I, ML
P0[5]
Analog column mux input, CMOD
capacitor pin
I/O
I, ML
P0[3]
Analog column mux input
I/O
I, ML
P0[1]
Analog column mux input
I/O
I, ML
P2[7]
Direct input to analog block
I/O
ML
P2[5]
Optional SAR ADC external reference
I/O
ML
P2[3]
I/O
ML
P2[1]
Power
VDD
Supply voltage
I/O
ML
P4[5]
I/O
ML
P4[3]
I/O
ML
P4[1]
Power
VSS
Ground connection
I/O
ML
P3[7]
I/O
ML
P3[5]
I/O
ML
P3[3]
I/O
ML
P3[1]
NC
Not connected
NC
Not connected
I/O
ML
P1[7]
I2C Serial Clock
I/O
ML
P1[5]
I2C Serial Data
I/O
ML
P1[3]
I/O
ML
P1[1]
Crystal Input (XTALin), I2C SCL,
ISSP-SCLK[6]
Power
VSS
I/O
MR
P1[0]
Crystal Output (XTALout), I2C SDA,
ISSP-SDATA[6]
I/O
MR
P1[2]
I/O
MR
P1[4]
Optional external clock input
I/O
MR
P1[6]
NC
Not connected
NC
Not connected
I/O
MR
P3[0]
I/O
MR
P3[2]
I/O
MR
P3[4]
I/O
MR
P3[6]
Input
XRES
Active high external reset with internal
pull-down
I/O
MR
P4[0]
I/O
MR
P4[2]
I/O
MR
P4[4]
Power
VSS
Ground Connection
I/O
MR
P2[0]
Figure 4. CY8C21645 and CY8C22645
48-Pin PSoC Device
AI, MR, P0[7]
AI, ML, P0[5]
AI, ML, P0[3]
AI, ML, P0[1]
AI, ML, P2[7]
EXTREF, ML, P2[5]
ML, P2[3]
ML, P2[1]
VDD
ML, P4[5]
ML, P4[3]
ML, P4[1]
VSS
ML, P3[7]
ML, P3[5]
ML, P3[3]
ML, P3[1]
NC
NC
I2C SCL, ML, P1[7]
I2C SDA, ML, P1[5]
ML, P1[3]
XTALin, I2C SCL, ML, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
P0[6], MR, AI
P0[4], MR, AI
P0[2], MR, AI
P0[0], MR, AI
P2[6], MR, AI
P2[4], MR
P2[2], MR
P2[0], MR
VSS
P4[4], MR
P4[2], MR
P4[0], MR
XRES
P3[6], MR
P3[4], MR
P3[2], MR
P3[0], MR
NC
NC
P1[6], MR
P1[4], MR, EXTCLK
P1[2], MR
P1[0], MR, I2C SDA, XTALout
Note
6. These are the ISSP pins, which are not High Z after exiting a reset state. See the PSoC Technical Reference Manual for CY8C21x45 and CY8C22x45 devices for
details.
Document Number: 001-55397 Rev. *I
Page 9 of 36
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Table 3. 48-Pin Part Pinout (SSOP) (continued)
Pin
No.
41
42
43
44
45
46
47
48
Type
Pin Name
Digital Analog
I/O
MR
P2[2]
I/O
MR
P2[4]
I/O
I, MR
P2[6]
I/O
I, MR
P0[0]
I/O
I, MR
P0[2]
I/O
I, MR
P0[4]
I/O
I, MR
P0[6]
Power
VDD
Description
Direct input to analog block
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Supply voltage
LEGEND: A = Analog, I = Input, O = Output, MR= Right analog mux bus input, ML= Left analog mux bus input
Document Number: 001-55397 Rev. *I
Page 10 of 36
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Registers
This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer to the PSoC
Technical Reference Manual for CY8C21x45 and CY8C22x45 devices.
Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
Table 4. Abbreviations
Convention
Description
RW
Read and write register or bit(s)
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-55397 Rev. *I
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Page 11 of 36
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Table 5. Register Map Bank 0 Table: User Space
Addr
(0,Hex)
00
Access
PRT0DR
RW
Addr
(0,Hex)
40
PRT0IE
01
RW
41
81
PRT0GS
02
RW
42
82
C2
PRT0DM2
03
RW
43
83
C3
PRT1DR
04
RW
44
PRT1IE
05
RW
45
85
PRT1GS
06
RW
46
86
C6
PRT1DM2
07
RW
47
87
C7
PRT2DR
08
RW
48
88
PWMVREF0
C8
#
PRT2IE
09
RW
49
89
PWMVREF1
C9
#
RW
Name
Name
Access
Name
ASE10CR0
ASE11CR0
Addr
(0,Hex)
80
84
Access
Name
RW
Addr
(0,Hex)
C0
Access
C1
RW
C4
C5
PRT2GS
0A
RW
4A
8A
IDAC_MODE
CA
PRT2DM2
0B
RW
4B
8B
PWM_SRC
CB
#
PRT3DR
0C
RW
4C
8C
TS_CR0
CC
RW
PRT3IE
0D
RW
4D
8D
TS_CMPH
CD
RW
PRT3GS
0E
RW
4E
8E
TS_CMPL
CE
RW
PRT3DM2
0F
RW
4F
8F
TS_CR1
CF
RW
PRT4DR
10
RW
CSD0_DR0_L
90
CUR PP
D0
RW
PRT4IE
11
RW
STK_PP
D1
RW
PRT4GS
12
RW
PRT4DM2
13
RW
50
R
CSD0_DR1_L
51
W
91
CSD0_CNT_L
52
R
92
D2
CSD0_CR0
53
#
93
IDX_PP
D3
14
CSD0_DR0_H
54
R
94
MVR_PP
D4
RW
RW
15
CSD0_DR1_H
55
W
95
MVW_PP
D5
RW
RW
16
CSD0_CNT_H
56
R
96
I2C0_CFG
D6
17
CSD0_CR1
57
RW
97
I2C0_SCR
D7
#
18
CSD1_DR0_L
58
R
98
I2C0_DR
D8
RW
19
CSD1_DR1_L
59
W
99
#
CSD1_CNT_L
5A
R
9A
I2C0_MSCR
INT_CLR0
D9
1A
DA
RW
1B
CSD1_CR0
5B
#
9B
INT_CLR1
DB
RW
1C
CSD1_DR0_H
5C
R
9C
INT_CLR2
DC
RW
1D
CSD1_DR1_H
5D
W
9D
DD
RW
1E
CSD1_CNT_H
5E
R
9E
INT_CLR3
INT_MSK3
DE
RW
RW
CSD1_CR1
5F
RW
9F
20
#
AMX_IN
60
RW
A0
INT_MSK2
INT_MSK0
DF
DBC00DR0
1F
E0
RW
DBC00DR1
21
W
AMUX_CFG
61
RW
A1
INT_MSK1
E1
RW
DBC00DR2
22
RW
PWM_CR
62
RW
A2
INT_VC
E2
RC
DBC00CR0
23
#
ARF_CR
63
RW
A3
RES_WDT
E3
W
DBC01DR0
24
#
CMP_CR0
64
#
A4
DBC01DR1
25
W
ASY_CR
65
#
A5
DBC01DR2
26
RW
CMP_CR1
66
RW
DBC01CR0
27
#
DCC02DR0
28
#
ADC0_CR
68
DCC02DR1
29
W
ADC1_CR
69
DCC02DR2
2A
RW
SADC_DH
6A
DCC02CR0
2B
#
SADC_DL
DCC03DR0
2C
#
DCC03DR1
2D
DCC03DR2
2E
DCC03CR0
2F
#
DBC10DR0
30
#
A6
DEC _CR0
E6
RW
A7
DEC_CR1
E7
RW
#
A8
MUL0_X
E8
W
#
A9
MUL0_Y
E9
W
RW
AA
MUL0_DH
EA
R
6B
RW
AB
EB
R
TMP_DR0
6C
RW
AC
MUL0_DL
ACC0_DR1
EC
RW
W
TMP_DR1
6D
RW
AD
ACC0_DR0
ED
RW
RW
TMP_DR2
6E
RW
AE
ACC0_DR3
EE
RW
TMP_DR3
6F
RW
ACC0_DR2
EF
RW
67
70
DBC10DR1
31
W
DBC10DR2
32
RW
ACE00CR1
ACE00CR2
DBC10CR0
33
#
DBC11DR0
34
#
AF
RDI0RI
71
72
RW
73
RW
74
75
B0
RW
RDI0SYN
B1
RW
F1
RDI0IS
B2
RW
F2
RDI0LT0
B3
RW
F3
RDI0LT1
B4
RW
F4
F5
DBC11DR1
35
W
RDI0RO0
B5
RW
DBC11DR2
36
RW
ACE01CR1
76
RW
RDI0RO1
B6
RW
DBC11CR0
37
#
ACE01CR2
77
RW
RDI0DSM
B7
RW
DCC12DR0
38
#
RDI1RI
B8
RW
78
F0
F6
CPU_F
F7
RL
F8
DCC12DR1
39
W
79
RDI1SYN
B9
RW
F9
DCC12DR2
3A
RW
7A
RDI1IS
BA
RW
FA
DCC12CR0
3B
#
7B
RDI1LT0
BB
RW
DCC13DR0
3C
#
7C
RDI1LT1
BC
RW
IDACR_D
FC
RW
DCC13DR1
3D
W
7D
RDI1RO0
BD
RW
IDACL_D
FD
RW
DCC13DR2
3E
RW
7E
RDI1RO1
BE
RW
CPU_SCR1
FE
#
7F
RDI1DSM
# Access is bit specific.
BF
RW
CPU_SCR0
FF
#
DCC13CR0
3F
#
Blank fields are Reserved and must not be accessed.
Document Number: 001-55397 Rev. *I
FB
Page 12 of 36
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr
(1,Hex)
00
Access
Name
RW
Addr
(1,Hex)
40
Access
Name
ASE10CR0
Addr
(1,Hex)
80
Access
Name
RW
Addr
(1,Hex)
C0
PRT0DM1
01
RW
41
81
C1
PRT0IC0
02
RW
42
82
C2
PRT0IC1
03
RW
43
83
PRT1DM0
04
RW
44
ASE11CR0
84
Access
C3
RW
C4
PRT1DM1
05
RW
45
85
C5
PRT1IC0
06
RW
46
86
C6
PRT1IC1
07
RW
47
87
C7
PRT2DM0
08
RW
48
88
C8
PRT2DM1
09
RW
49
89
C9
PRT2IC0
0A
RW
4A
8A
CA
PRT2IC1
0B
RW
4B
8B
CB
PRT3DM0
0C
RW
4C
8C
CC
PRT3DM1
0D
RW
4D
8D
CD
PRT3IC0
0E
RW
4E
8E
CE
PRT3IC1
0F
RW
4F
8F
PRT4DM0
10
RW
CMP0CR1
50
RW
90
GDI_O_IN
D0
RW
PRT4DM1
11
RW
CMP0CR2
51
RW
91
GDI_E_IN
D1
RW
PRT4IC0
12
RW
92
GDI_O_OU
D2
RW
PRT4IC1
13
RW
GDI_E_OU
D3
RW
52
CF
VDAC50CR0
53
RW
93
14
CMP1CR1
54
RW
94
D4
15
CMP1CR2
55
RW
95
D5
16
56
17
VDAC51CR0
57
RW
96
D6
97
D7
18
CSCMPCR0
58
#
98
MUX_CR0
D8
RW
19
CSCMPGOEN
59
RW
99
MUX_CR1
D9
RW
1A
CSLUTCR0
5A
RW
9A
MUX_CR2
DA
RW
1B
CMPCOLMUX
5B
RW
9B
MUX_CR3
DB
RW
1C
CMPPWMCR
5C
RW
9C
DAC_CR1#
DC
RW
1D
CMPFLTCR
5D
RW
9D
OSC_GO_EN
DD
RW
1E
CMPCLK1
5E
RW
9E
OSC_CR4
DE
RW
CMPCLK0
5F
RW
DBC00FN
1F
20
RW
CLK_CR0
60
RW
GDI_O_IN_CR
A0
9F
OSC_CR3
DF
RW
OSC_CR0
E0
RW
DBC00IN
21
RW
CLK_CR1
61
RW
GDI_E_IN_CR
A1
DBC00OU
22
RW
ABF_CR0
62
RW
GDI_O_OU_CR
A2
RW
OSC_CR1
E1
RW
RW
OSC_CR2
E2
DBC00CR1
23
RW
AMD_CR0
63
RW
GDI_E_OU_CR
A3
RW
RW
VLT_CR
E3
RW
RW
DBC01FN
24
RW
CMP_GO_EN
64
RW
RTC_H
A4
RW
VLT_CMP
E4
R
DBC01IN
25
RW
CMP_GO_EN1
65
RW
RTC_M
A5
RW
ADC0_TR
E5
RW
DBC01OU
26
RW
AMD_CR1
66
RW
RTC_S
A6
RW
ADC1_TR
E6
RW
DBC01CR1
27
RW
ALT_CR0
67
RW
RTC_CR
A7
RW
V2BG_TR
E7
RW
DCC02FN
28
RW
ALT_CR1
68
RW
SADC_CR0
A8
RW
IMO_TR
E8
W
DCC02IN
29
RW
CLK_CR2
69
RW
SADC_CR1
A9
RW
ILO_TR
E9
W
DCC02OU
2A
RW
AMUX_CFG1
6A
RW
SADC_CR2
AA
RW
BDG_TR
EA
RW
DBC02CR1
2B
RW
CLK_CR3
6B
RW
SADC_CR3TRIM
AB
RW
ECO_TR
EB
W
DCC03FN
2C
RW
TMP_DR0
6C
RW
SADC_CR4
AC
RW
MUX_CR4
EC
RW
DCC03IN
2D
RW
TMP_DR1
6D
RW
I2C0_AD
AD
RW
DCC03OU
2E
RW
TMP_DR2
6E
RW
AE
DBC03CR1
2F
RW
TMP_DR3
6F
RW
AF
DBC10FN
30
RW
70
RDI0RI
B0
RW
F0
DBC10IN
31
RW
71
RDI0SYN
B1
RW
F1
ED
EE
EF
DBC10OU
32
RW
ACE00CR1
72
RW
RDI0IS
B2
RW
F2
DBC10CR1
33
RW
ACE00CR2
73
RW
RDI0LT0
B3
RW
F3
DBC11FN
34
RW
74
RDI0LT1
B4
RW
F4
DBC11IN
35
RW
75
RDI0RO0
B5
RW
F5
DBC11OU
36
RW
ACE01CR1
76
RW
RDI0RO1
B6
RW
DBC11CR1
37
RW
ACE01CR2
77
RW
RDI0DSM
B7
RW
DCC12FN
38
RW
RDI1RI
B8
RW
78
DCC12IN
39
RW
79
RDI1SYN
B9
RW
DCC12OU
3A
RW
7A
RDI1IS
BA
RW
DBC12CR1
3B
RW
7B
RDI1LT0
BB
RW
F6
CPU_F
F7
RL
F8
F9
FLS_PR1
FA
RW
FB
DCC13FN
3C
RW
7C
RDI1LT1
BC
RW
DCC13IN
3D
RW
7D
RDI1RO0
BD
RW
DAC_CR0#
FD
RW
DCC13OU
3E
RW
7E
RDI1RO1
BE
RW
CPU_SCR1
FE
#
7F
RDI1DSM
# Access is bit specific.
BF
RW
CPU_SCR0
FF
#
DBC13CR1
3F
RW
Blank fields are Reserved and must not be accessed.
Document Number: 001-55397 Rev. *I
FC
Page 13 of 36
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Electrical Specifications
This section presents the DC and AC electrical specifications for automotive CY8C21x45 and CY8C22x45 PSoC devices. For the
latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com.
Specifications are valid for A-grade devices at –40 °C  TA  85 °C, TJ  100 °C, and for E-grade devices at –40 °C  TA  125 °C,
TJ  150 °C, unless noted otherwise.
Figure 5. Voltage vs. CPU Frequency for A-grade Devices
Figure 6. Voltage vs. CPU Frequency for E-grade Devices
5.25
O Va
p
R era lid
eg t
i o i ng
n
5.25
4.75
Vdd Voltage (V)
Vdd Voltage (V)
4.75
lid g
Va atin
er n
Op egio
R
3.0
0
0
12 MHz
93 kHz
12 MHz
93 kHz
24 MHz
24 MHz
CPU Frequency
(nominal setting)
CPU Frequency
(nominal setting)
Figure 7. IMO Frequency Trim Options (A-grade Devices Only)
5.25
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
Vdd Voltage (V)
4.75
3.6
3.0
0
6 MHz
12 MHz
24 MHz
IMO Frequency
Document Number: 001-55397 Rev. *I
Page 14 of 36
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Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 7. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
TBAKETEMP Bake temperature
Min
–55
Typ
25
Max
+150
Units
°C
–
125
C
See
package
label
–
See
package
label
72
Hours
–40
–40
–0.5
–
–
–
+85
+125
+6.0
°C
°C
V
TBAKETIME
Bake time
TA
VDD
Ambient temperature with power applied
A-grade devices
E-grade devices
Supply voltage on VDD relative to VSS
VIO
DC input voltage
VSS – 0.5
–
VDD + 0.5
V
VIOz
DC voltage applied to tristate
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any port pin
–25
–
+50
mA
ESD
Electrostatic discharge voltage
2000
–
–
V
LU
Latch up current
–
–
200
mA
Min
Typ
Max
Units
–40
–40
–
–
+85
+125
°C
°C
–40
–40
–
–
+100
+135
°C
°C
Notes
Recommended storage
temperature is 25 °C ±
25 °C. Higher storage
temperatures reduce
data retention time.
Human body model ESD
Operating Temperature
Table 8. Operating Temperature
Symbol
Description
TA
Ambient temperature
A-grade devices
E-grade devices
TJ
Junction temperature
A-grade devices
E-grade devices
Document Number: 001-55397 Rev. *I
Notes
The temperature rise
from ambient to junction
is package specific. See
Table 24 on page 27. The
user must limit the power
consumption to comply
with this requirement.
Page 15 of 36
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DC Electrical Characteristics
DC Chip Level Specifications
Table 9 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 9. DC Chip Level Specifications
Symbol
VDD
IDD
ISB
ISBXTL
VREF
Description
Supply voltage
A-grade devices
E-grade devices
Supply current
A-grade devices, 3.0 V  VDD  3.6 V
A-grade devices, 4.75 V  VDD  5.25 V
E-grade devices
Sleep (mode) current
A-grade devices, 3.0 V  VDD  3.6 V
A-grade devices, 4.75 V  VDD  5.25 V
E-grade devices
Sleep (mode) current with ECO
A-grade devices, 3.0 V  VDD  3.6 V
A-grade devices, 4.75 V  VDD  5.25 V
E-grade devices
Reference voltage (Bandgap)
Document Number: 001-55397 Rev. *I
Min
Typ
Max
Units
3.0
4.75
–
–
5.25
5.25
V
V
–
–
–
4
7
8
7
12
15
mA
mA
mA
–
–
–
3
4
4
12
25
25
A
A
A
–
–
–
1.275
4
5
5
1.30
13
26
26
1.325
A
A
A
V
Notes
See Table 14 on page 19
CPU = 3 MHz, 48 MHz disabled.
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 93.75 kHz, Analog blocks
disabled
Everything disabled except ILO,
POR, LVD, Sleep Timer, and
WDT circuits
Everything disabled except ECO,
POR, LVD, Sleep Timer, and
WDT circuits
Trimmed for appropriate VDD
setting.
Page 16 of 36
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DC General Purpose I/O Specifications
Table 10 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 10. DC GPIO Specifications
Symbol
RPU
RPD
VOH
Description
Pull-up resistor
Pull-down resistor
High output level
Min
Typ
4
5.6
4
5.6
VDD – 1.0
–
Max
8
8
–
VOL
Low output level
–
–
0.75
IOH
High-level source current
10
–
–
IOL
Low-level sink current
25
–
–
VIL
VIH
VH
IIL
CIN
Input low level
Input high level
Input hysteresis
Input leakage (absolute value)
Capacitive load on pins as input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
COUT
Capacitive load on pins as output
–
3.5
10
–
–
10
Units
Notes
k
k
V
IOH = 10 mA, VDD = 4.75 to 5.25 V
(80 mA maximum combined IOH
budget)
V
IOL = 25 mA, VDD = 4.75 to 5.25 V
(100 mA maximum combined IOL
budget)
mA VOH  VDD – 1.0 V, see the limitations
of the total current in the note for
VOH.
mA VOL  0.75 V, see the limitations
of the total current in the note for
VOL.
V
V
mV
nA Gross tested to 1 A
pF Package and pin dependent.
Temp = 25 °C
pF Package and pin dependent.
Temp = 25 °C
DC Operational Amplifier Specifications
The following table lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless
otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V
and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade
devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V
at 25°C, unless specified otherwise, and are for design guidance only.
Table 11. DC Operational Amplifier Specifications
Symbol
VOSOA
ISOA
Description
Input offset voltage (absolute value)
Supply current (absolute value)
A-grade devices
E-grade devices
TCVOSOA Average input offset voltage drift
Input leakage current (Port 0 analog pins)
IEBOA[7]
Input capacitance (Port 0 analog pins)
CINOA
Min
–
Typ
2.5
–
–
–
–
–
–
–
10
200
4.5
Common mode voltage range
0.5
–
VCMOA
Max
15
Units
mV
Notes
A
µA
V/°C
pA Gross tested to 1 A
pF Package and pin dependent.
Temp = 25 °C
VDD – 1
V
30
35
–
–
9.5
Note
7. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25 °C; 50 nA over temperature. Use Port 0 Pins 1 – 7 for the lowest leakage of 200 nA.
Document Number: 001-55397 Rev. *I
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DC SAR10 ADC Specifications
Table 12 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 12. DC SAR10 ADC Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VADCREF
Reference voltage at pin P2[5] when configured
as ADC reference voltage
3.0
–
5.25
V
When VREF is buffered inside
ADC, the voltage level at P2[5]
(when configured as ADC
reference voltage) must be
always maintained to be at least
300 mV less than the chip supply
voltage level on VDD pin.
(VADCREF < VDD)
IADCREF
Current into P2[5] when configured as ADC VREF
–
–
100
µA
Disables the internal voltage
reference buffer
INLADC
Integral nonlinearity
A-grade devices
E-grade devices
–3.0
–5.0
–
–
3.0
5.0
LSbit
LSbit
DNLADC
Differential nonlinearity
A-grade devices
E-grade devices
–1.5
–4.0
–
–
1.5
4.0
LSbit
LSbit
10-bit resolution
10-bit resolution
DC Analog Mux Bus Specifications
Table 13 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 13. DC Analog Mux Bus Specifications
Min
Typ
Max
Units
RSW
Symbol
Switch resistance to common analog bus
Description
–
–
400

RGND
Resistance of initialization switch to GND
–
–
800

Document Number: 001-55397 Rev. *I
Notes
Page 18 of 36
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DC POR and LVD Specifications
Table 14 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 14. DC POR and LVD Specifications
Symbol
Description
VPPOR1
VPPOR2
VDD value for PPOR trip
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD value for LVD trip
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Document Number: 001-55397 Rev. *I
Min
Typ
Max
Units
–
–
2.82
4.55
2.95
4.73
V
V
2.95
3.06
4.37
4.50
4.62
4.71
3.02
3.13
4.48
4.64
4.73
4.81
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
Notes
VDD must be greater than or
equal to 3.0 V during startup,
reset from the XRES pin, or
reset from Watchdog. VPPOR1 is
only applicable to A-grade
devices.
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DC Programming Specifications
Table 15 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 15. DC Programming Specifications
Symbol
Description
VDDIWRITE Supply voltage for flash write operations
Min
3.0
Typ
–
Max
–
Units
V
IDDP
Supply current during programming or verify
–
5
25
mA
VILP
Input low voltage during programming or verify
–
–
0.8
V
VIHP
Input high voltage during programming or verify
2.2
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
0.75
V
VDD – 1.0
–
VDD
V
1,000
100
–
–
–
–
–
–
128,000
256,000
12,800
25,600
–
–
–
–
–
–
–
–
–
–
–
–
10
10
–
–
–
–
Years
Years
IILP
Input current when applying VILP to P1[0] or
P1[1] during programming or verify
IIHP
Input current when applying VIHP to P1[0] or
P1[1] during programming or verify
VOLV
Output low voltage during programming or
verify
VOHV
Output high voltage during programming or
verify
FlashENPB Flash endurance (per block)[8, 9]
A-grade devices
E-grade devices
FlashENT Flash endurance (total)[9, 10]
CY8C21x45 A-grade devices
CY8C22x45 A-grade devices
CY8C21x45 E-grade devices
CY8C22x45 E-grade devices
FlashDR
Flash data retention[9]
A-grade devices
E-grade devices
Notes
Driving internal pull-down
resistor
Driving internal pull-down
resistor
Erase/write cycles per block
Erase/write cycles
Notes
8. The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to
5.25 V.
9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor and feed the result to the temperature
argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
10. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device.
Document Number: 001-55397 Rev. *I
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AC Electrical Characteristics
AC Chip Level Specifications
The following tables list the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless
otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V
and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade
devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V
at 25 °C, unless specified otherwise, and are for design guidance only.
Table 16. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
FIMO24
Internal main oscillator frequency for 24 MHz
A-grade devices, 4.75 V  VDD  5.25 V
A-grade devices, 3.0 V  VDD  3.6 V
E-grade devices
22.8
22.5
22.3
24
24
24
25.2[11]
25.5[11]
25.7[11]
MHz
MHz
MHz
FIMO6
Internal main oscillator frequency for 6 MHz
A-grade devices
E-grade devices
5.5
5.5
6
6
6.5[11]
6.5[11]
MHz
MHz
FCPU1
CPU frequency (5 V VDD operation)
A-grade devices
E-grade devices
0.089
0.089
–
–
25.2[11]
12.6[11]
MHz
MHz
FCPU2
CPU frequency (3.3 V VDD operation)
0.089
–
12.6[11]
MHz
FBLK5
Digital PSoC block
operation)
A-grade devices
E-grade devices
frequency0(5
V VDD
Notes
Trimmed for 5 V or 3.3 V operation
using factory trim values. See
Figure 7 on page 14.
Trimmed for 5 V or 3.3 V operation
using factory trim values. See
Figure 7 on page 14.
A-grade devices only
Refer to Table 19 on page 23.
0
0
48
24
50.4[11, 12]
25.2[11, 12]
MHz
MHz
FBLK33
Digital PSoC block frequency (3.3 V VDD
operation)
0
24
24.6[11]
MHz
A-grade devices only
F32K1
ILO frequency
15
32
75
kHz
This specification applies when
the ILO has been trimmed.
F32KU
ILO untrimmed frequency
5
–
–
kHz
After a reset and before the M8C
processor starts to execute, the ILO
is not trimmed.
Jitter32k
32 kHz RMS period jitter
–
100
–
ns
TXRST
External reset pulse width
10
–
–
µs
DC24M
24 MHz duty cycle
40
50
60
%
DCILO
ILO duty cycle
20
50
80
%
Fout48M
48 MHz output frequency
45.6
48.0
50.4[11]
MHz
Jitter24M1
24 MHz period jitter (IMO)
–
300
600
ps
FMAX
Maximum frequency of signal on row input or
row output
–
–
12.6
MHz
SRPOWERUP Power supply slew rate
–
–
250
V/ms
TPOWERUP
–
16
100
ms
Time between end of POR state and CPU code
execution
VDD slew rate during power-up.
Power-up from 0 V.
Figure 8. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Notes
11. Accuracy derived from IMO with appropriate trim for VDD range
12. Refer to the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 001-55397 Rev. *I
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Figure 9. 32 kHz Period Jitter (ILO) Timing Diagram
Jitter32k
F 32K1
AC General Purpose I/O Specifications
Table 17 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 17. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO operating frequency
Rise time, normal strong mode, Cload = 50 pF
A-grade devices
E-grade devices
Fall time, normal strong mode, Cload = 50 pF
A-grade devices
E-grade devices
Rise time, slow strong mode, Cload = 50 pF
A-grade devices
E-grade devices
Fall time, slow strong mode, Cload = 50 pF
A-grade devices
E-grade devices
Min
0
Typ
–
Max
12.6
3
3
–
–
18
24
2
2
–
–
18
28
7
7
27
32
–
–
7
7
22
28
–
–
Units
Notes
MHz Normal strong mode
Refer to Figure 10
ns
ns
Refer to Figure 10
ns
ns
Refer to Figure 10
ns
ns
Refer to Figure 10
ns
ns
Figure 10. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
T RiseS
T FallF
TFallS
AC Operational Amplifier Specifications
Table 18 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 18. AC Operational Amplifier Specifications
Symbol
TCOMP
Description
Comparator mode response time, 50 mV
Document Number: 001-55397 Rev. *I
Min
–
Typ
–
Max
100
Units
ns
Notes
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AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless
otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V
and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade
devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V
at 25 °C, unless specified otherwise, and are for design guidance only.
Table 19. AC Digital Block Specifications
Function
All
Functions
Description
Maximum block clocking frequency ( 4.75 V)
Maximum block clocking frequency (< 4.75 V)
Timer
Capture pulse width
Maximum frequency, no capture
Maximum frequency, with or without capture
Enable pulse width
Maximum frequency, no enable input
Maximum frequency, enable input
Kill pulse width:
Asynchronous restart mode
Synchronous restart mode
Disable mode
Maximum frequency
Maximum input clock frequency
Counter
Dead Band
CRCPRS
(PRS Mode)
CRCPRS
Maximum input clock frequency
(CRC Mode)
SPIM
Maximum input clock frequency
SPIS
Min
–
–
Typ
–
–
Max
50.4
25.2
50[13]
–
–
50[13]
–
–
–
–
–
–
–
–
–
50.4
25.2
–
50.4
25.2
Units
Notes
MHz Note [14]
MHz VDD < 4.75 V and/or temperature
> 85 °C
ns
MHz Note [14]
MHz
ns
MHz Note [14]
MHz
20
50[13]
50[13]
–
–
–
–
–
–
–
–
–
–
50.4
50.4
ns
ns
ns
MHz Note [14]
MHz Note [14]
–
–
25.2
MHz
–
–
8.4
–
50[13]
–
–
–
–
4.2
–
25.2
MHz Maximum nominal data rate is
4 Mbps due to 2 x overclocking
MHz
ns
MHz Maximum nominal baud rate is
3 Mbaud due to 8 × overclocking
MHz Maximum nominal baud rate is
6 Mbaud due to 8 × overclocking
MHz Maximum nominal baud rate is
3 Mbaud due to 8 × overclocking
MHz Maximum nominal baud rate is
6 Mbaud due to 8 × overclocking
Transmitter
Maximum input clock frequency
Width of SS_ negated between transmissions
Maximum input clock frequency
–
–
50.4
Receiver
Maximum input clock frequency with
VDD 4.75 V, 2 stop bits
Maximum input clock frequency
–
–
25.2
Maximum input clock frequency with
VDD 4.75 V, 2 stop bits
–
–
50.4
Notes
13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
14. 4.75 V  VDD  5.25 V at –40 °C to 85 °C
Document Number: 001-55397 Rev. *I
Page 23 of 36
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AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless
otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V
and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade
devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V
at 25 °C, unless specified otherwise, and are for design guidance only.
Table 20. AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High period
20.0
–
5300
ns
–
Low period
20.0
–
–
ns
–
Power-up IMO to switch
150
–
–
s
Notes
AC SAR10 ADC Specifications
Table 21 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 21. AC SAR10 ADC Specifications
Symbol
FINADC
Description
SAR ADC input clock frequency
Min
Typ
Max
–
–
2
Units
Notes
MHz The sample rate of the SAR10
ADC is equal to FINADC divided
by 13.
AC Programming Specifications
Table 22 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 22. AC Programming Specifications
Symbol
TRSCLK
Description
Rise time of SCLK
Min
1
Typ
–
Max
20
Units
ns
Notes
TFSCLK
Fall time of SCLK
1
–
20
ns
TSSCLK
Data setup time to falling edge of SCLK
40
–
–
ns
THSCLK
Data hold time from falling edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
FSCLK3
Frequency of SCLK
0
–
6
MHz VDD  3.6 V
ms
TERASEB
Flash erase time (block)
–
10
40[15]
TWRITE
Flash block write time
–
40
160[15]
ms
TDSCLK
Data out delay from falling edge of SCLK
–
–
55
ns
TDSCLK3
Data out delay from falling edge of SCLK
–
–
65
ns
3.0 V VDD 3.6 V, 30 pF load
–
–
100[15]
ms
TJ  0 °C
–
–
200[15]
ms
TJ 0 °C
TPRGH
TPRGC
Total flash block program time
(TERASEB + TWRITE), Hot
Total flash block program time
(TERASEB + TWRITE), Cold
VDD > 3.6 V, 30 pF load
Note
15. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
Document Number: 001-55397 Rev. *I
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AC I2C Specifications
Table 23 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise
noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C
to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices
for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C,
unless specified otherwise, and are for design guidance only.
Table 23. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Description
Standard Mode
Min
Max
0
100[16]
Fast Mode
Min
Max
0
400[16]
Units
FSCLI2C
SCL clock frequency
THDSTAI2C
4.0
–
0.6
–
s
TLOWI2C
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
LOW period of the SCL clock
kHz
4.7
–
1.3
–
s
THIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
s
TSUSTAI2C
Setup time for a repeated START condition
4.7
–
0.6
–
s
THDDATI2C
Data hold time
0
–
0
–
s
TSUDATI2C
Data setup time
250
–
100[17]
–
ns
TSUSTOI2C
Setup time for STOP condition
4.0
–
0.6
–
s
TBUFI2C
Bus-free time between a STOP and START
condition
Pulse width of spikes are suppressed by the
input filter
4.7
–
1.3
–
s
–
–
0
50
ns
TSPI2C
Figure 11. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSPI2C
T SUDATI2C
T HDSTAI2C
TBUFI2C
SCL
S T HDSTAI2C T HDDATI2C T HIGHI2C
T SUSTAI2C
Sr
T SUSTOI2C
P
S
Notes
16. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the
FSCLI2C specification adjusts accordingly.
17. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C  250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released.
Document Number: 001-55397 Rev. *I
Page 25 of 36
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Packaging Information
This section provides the packaging specifications for the automotive CY8C21x45 and CY8C22x45 PSoC devices. The thermal
impedances for each package and the typical package capacitance on crystal pins are given.
Package Dimensions
Figure 12. 28-Pin (210-Mil) SSOP
51-85079 *D
Document Number: 001-55397 Rev. *I
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Figure 13. 48-Pin (300-Mil) SSOP
.020
24
1
0.395
0.420
0.292
0.299
25
DIMENSIONS IN INCHES MIN.
MAX.
48
0.620
0.630
0.088
0.092
0.095
0.110
SEATING PLANE
0.005
0.010
.010
GAUGE PLANE
0.004
0.025
BSC
0°-8°
0.008
0.016
0.008
0.0135
Thermal Impedances
0.024
0.040
51-85061 *D
Capacitance on Crystal Pins
Table 24. Thermal Impedances per Package
Typical JA
Package
Table 25. Typical Package Capacitance on Crystal Pins
[18]
Package
Package Capacitance
28-pin SSOP
97.6 °C/W
28-pin SSOP
2.8 pF
48-pin SSOP
69 °C/W
48-pin SSOP
3.3 pF
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 26. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[19] Maximum Peak Temperature
28-pin SSOP
240 °C
260 °C
48-pin SSOP
240 °C
260 °C
Notes
18. TJ = TA + POWER x JA
19. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 001-55397 Rev. *I
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Tape and Reel Information
Figure 14. 28-Pin SSOP Carrier Tape Drawing
51-51100 *B
Document Number: 001-55397 Rev. *I
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Figure 15. 48-Pin SSOP Carrier Tape Drawing
51-51104 *D
Table 27. Tape and Reel Specifications
Package
Cover Tape
Width (mm)
Hub Size
(inches)
Minimum Leading
Empty Pockets
28-Pin SSOP
48-Pin SSOP
13.3
25.5
7
4
42
32
Document Number: 001-55397 Rev. *I
Minimum
Trailing Empty
Pockets
25
19
Standard Full Reel
Quantity
1000
1000
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Development Tool Selection
This section presents the development tools available for the automotive CY8C21x45 and CY8C22x45 families.
Software
PSoC Designer
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for years. PSoC
Designer is available free of charge at http://www.cypress.com.
PSoC Designer comes with a free C compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com.
Development Kits
All development kits can be purchased from the Cypress Online
Store. The online store also has the most up to date information
on kit contents, descriptions, and availability.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the contents of specific memory locations. Advanced
emulation features are also supported through PSoC Designer.
The kit includes:
■
ICE-Cube unit
■
28-pin PDIP emulation pod for CY8C29466-24PXI
■
28-pin CY8C29466-24PXI PDIP PSoC device samples (two)
■
PSoC Designer software CD
■
ISSP cable
■
MiniEval socket programming and evaluation board
■
Backward compatibility cable (for connecting to legacy pods)
■
Universal 110/220 power supply (12 V)
■
European plug adapter
■
USB 2.0 cable
■
Getting Started guide
■
Development kit registration form
Document Number: 001-55397 Rev. *I
CY3280-22X45 Universal CapSense Controller Board
The CY3280-22X45 controller board is an additional controller
board for the CY3280-BK1 Universal CapSense Controller Kit.
The Universal CapSense Controller kit is designed for easy
prototyping and debug of CapSense designs with pre-defined
control circuitry and plug-in hardware. The CY3280-22X45 kit
contains no plug-in hardware. Therefore, it is only usable if
plug-in hardware is purchased as part of the CY3280-BK1 kit or
other separate kits. The kit includes:
■
CY3280-22X45 universal CapSense controller board
■
CY3280-22X45 universal CapSense controller board CD
■
DC power supply
■
Printed documentation
CY3280-CPM1 CapSensePlus Module
The CY3280-CPM1 CapSensePlus Module is a plug-in module
board for the CY3280-22X45 CapSense controller board kit. This
plug-in module has no capacitive sensors on it. Instead, it has
other general circuitry (such as a seven-segment display,
potentiometer, LEDs, buttons, thermistor) that can be used to
develop applications that require capacitive sensing along with
other additional functionality. To use this kit, a CY3280-22X45 kit
is required.
Evaluation Tools
All evaluation tools can be purchased from the Cypress online
store. The online store also has the most up-to-date information
on kit contents, descriptions, and availability.
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, an RS-232 port, and
plenty of breadboarding space to meet all of your evaluation
needs. The kit includes:
■
Evaluation board with LCD module
■
MiniProg programming unit
■
28-pin CY8C29466-24PXI PDIP PSoC device sample (two)
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
Page 30 of 36
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Device Programmers
CY3207ISSP In-System Serial Programmer
All device programmers can be purchased from the Cypress
Online Store.
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows the user to program PSoC
devices through the MiniProg1 programming unit. The MiniProg
is a small, compact prototyping programmer that connects to the
PC through a provided USB 2.0 cable. The kit includes:
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. This software is free and can be
downloaded from http://www.cypress.com. The kit includes:
■
CY3207 programmer unit
■
MiniProg programming unit
■
PSoC ISSP software CD
■
MiniEval socket programming and evaluation board
■
110 ~ 240-V power supply, Euro-Plug adapter
■
28-pin CY8C29466-24PXI PDIP PSoC device sample
■
USB 2.0 cable
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
Accessories (Emulation and Programming)
Table 28. Emulation and Programming Accessories
Part Number
Pin Package
Pod Kit[20]
Foot Kit[21]
Prototyping
Module
Adapter[22]
CY8C21345-24PVXA
CY8C21345-12PVXE
CY8C22345-24PVXA
CY8C22345H-24PVXA
CY8C22345-12PVXE
28-pin SSOP
CY3250-22345
CY3250-28SSOP-FK
–
AS-28-28-02SS-6ENP-GANG
CY8C21645-24PVXA
CY8C21645-12PVXE
CY8C22645-24PVXA
CY8C22645-12PVXE
48-pin SSOP
–
–
–
AS-48-48-01SS-6-GANG
Notes
20. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
21. Foot kit includes surface mount feet that can be soldered to the target PCB.
22. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-55397 Rev. *I
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Ordering Information
The following table lists the key package features and ordering codes of the automotive CY8C21x45 and CY8C22x45 device families.
SRAM (Bytes)
Temperature
Range
Digital Blocks
Analog Blocks
Digital I/O Pins
Analog Inputs
Analog Outputs
XRES Pin
CY8C21345-24PVXA
8K
512
–40 °C to +85 °C
4
6
24
24
0
Yes
28-pin (210-Mil) SSOP
(Tape and Reel)
28-pin (210-Mil) SSOP
CY8C21345-24PVXAT
8K
512
–40 °C to +85 °C
4
6
24
24
0
Yes
CY8C21345-12PVXE
8K
512
–40 °C to +125 °C
4
6
24
24
0
Yes
28-pin (210-Mil) SSOP
(Tape and Reel)
28-pin (210-Mil) SSOP
CY8C21345-12PVXET
8K
512
–40 °C to +125 °C
4
6
24
24
0
Yes
CY8C22345-24PVXA
16 K
1K
–40 °C to +85 °C
8
6
24
24
0
Yes
28-pin (210-Mil) SSOP
(Tape and Reel)
28-pin (210-Mil) SSOP
CY8C22345-24PVXAT
16 K
1K
–40 °C to +85 °C
8
6
24
24
0
Yes
CY8C22345H-24PVXA
16 K
1K
–40 °C to +85 °C
8
6
24
24
0
Yes
28-pin (210-Mil) SSOP
(Tape and Reel)
28-pin (210-Mil) SSOP
CY8C22345H-24PVXAT
16 K
1K
–40 °C to +85 °C
8
6
24
24
0
Yes
CY8C22345-12PVXE
16 K
1K
–40 °C to +125 °C
8
6
24
24
0
Yes
28-pin (210-Mil) SSOP
(Tape and Reel)
48-pin (300-Mil) SSOP
CY8C22345-12PVXET
16 K
1K
–40 °C to +125 °C
8
6
24
24
0
Yes
CY8C21645-24PVXA
8K
512
–40 °C to +85 °C
4
6
38
38
0
Yes
48-pin (300-Mil) SSOP
(Tape and Reel)
48-pin (300-Mil) SSOP
CY8C21645-24PVXAT
8K
512
–40 °C to +85 °C
4
6
38
38
0
Yes
CY8C21645-12PVXE
8K
512
–40 °C to +125 °C
4
6
38
38
0
Yes
48-pin (300-Mil) SSOP
(Tape and Reel)
48-pin (300-Mil) SSOP
CY8C21645-12PVXET
8K
512
–40 °C to +125 °C
4
6
38
38
0
Yes
CY8C22645-24PVXA
16 K
1K
–40 °C to +85 °C
8
6
38
38
0
Yes
48-pin (300-Mil) SSOP
(Tape and Reel)
48-pin (300-Mil) SSOP
CY8C22645-24PVXAT
16 K
1K
–40 °C to +85 °C
8
6
38
38
0
Yes
CY8C22645-12PVXE
16 K
1K
–40 °C to +125 °C
8
6
38
38
0
Yes
48-pin (300-Mil) SSOP
(Tape and Reel)
CY8C22645-12PVXET
16 K
1K
–40 °C to +125 °C
8
6
38
38
0
Yes
Ordering Code
28-pin (210-Mil) SSOP
Package
Flash (Bytes)
Table 29. PSoC Device Family Key Features and Ordering Information
Document Number: 001-55397 Rev. *I
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Ordering Code Definitions
CY 8 C 2x xxx x-SPxx
Package type:
PX = PDIP Pb-free
SX = SOIC Pb-free
PVX = SSOP Pb-free
LFX/LTX = QFN Pb-free
AX = TQFP Pb-free
Thermal rating:
A = Automotive –40 °C to +85 °C
C = Commercial
E = Automotive Extended –40 °C to +125 °C
I = Industrial
CPU Speed: 12/24 MHz
Optional part number modifier: H = Integrated Immersion® TouchSense® technology
Part number
Family code (21, 22)
Technology code: C = CMOS
Marketing code: 8 = PSoC
Company ID: CY = Cypress Semiconductor
Document Number: 001-55397 Rev. *I
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Document Conventions
Acronyms Used
Units of Measure
Table 30. Acronyms
Table 31. Units of Measure
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
AEC
Automotive Electronics Council
API
application programming interface
CPU
central processing unit
CRC
cyclic redundancy check
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
ERM
eccentric rotating motor
FSR
full scale range
GPIO
general purpose I/O
ICE
in-circuit emulator
IDE
integrated development environment
I/O
input/output
ILO
internal low-speed oscillator
IMO
internal main oscillator
IPOR
imprecise power on reset
LSbit
least significant bit
LVD
low voltage detect
MSbit
most significant bit
PC
program counter
PCB
printed circuit board
POR
power on reset
PPOR
precision power on reset
PRS
pseudo-random sequence
PSoC
Programmable System-on-Chip
PWM
pulse width modulator
RAM
random access memory
ROM
read only memory
SC
switched capacitor
SMP
switch mode pump
SPI
serial peripheral interface
UART
universal asynchronous receiver/transmitter
Document Number: 001-55397 Rev. *I
Symbol
°C
dB
fF
Hz
KB
Kbit
kHz
k
LSbit
Mbaud
Mbps
MHz
M
A
F
H
s
V
Vrms
W
mA
ms
mV
nA
ns
nV

pA
pF
pp
ppm
ps
sps

V
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
least significant bit
megabaud
megabits per second
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
microwatts
milliampere
millisecond
millivolts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, ‘01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘0x’, or ‘b’ are
decimal.
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Document History Page
Document Title: CY8C21345, CY8C21645, CY8C22345, CY8C22345H, CY8C22645 Automotive PSoC®
Programmable System-on-Chip™
Document Number: 001-55397
Revision
ECN
Orig. of
Change
Submission
Date
**
2759868
VIVG
09/04/09
New Datasheet
*A
2788690
VIVG
10/20/09
Added 48 SSOP to the marketing part numbers.
Corrected the ISOA spec in table 13/14.
Changed the ThetaJA values based on PE inputs.
*B
2792800
VIVG
10/26/09
Corrected typo in ordering information table (Digital I/O for 48-SSOP devices)
*C
2822630
BTK
12/07/09
Added CY8C22345H devices and updated Features section and PSoC
Functional Overview section to include haptics device information. Updated
Features section. Added Contents section. Updated PSoC Functional Overview
section. Updated Block Diagram of device. Updated PSoC Device Characteristics table. Updated Pinouts section. Fixed issues with the Register Map tables.
Added a figure for SLIMO configuration. Updated footnotes for the DC
Programming Specifications table. Corrected VDDIWRITE and FlashENT electrical
specifications. Updated Ordering Information section. Added Development Tool
Selection section. Combined 5 V DC Operational Amplifier Specifications table
with 3.3 V DC Operational Amplifier Specifications table. Updated all AC specifications to conform to 5% IMO accuracy and 8.33% SLIMO accuracy. Split up
electrical specifications for A-grade and E-grade devices in the Absolute
Maximum Ratings, Operating Temperature, DC Chip Level Specifications, DC
Programming Specifications, and AC Chip-Level Specifications tables. Added
Solder Reflow Peak Temperature table. Added TPRGH, TPRGC, IOL, IOH, F32KU,
DCILO, and TPOWERUP electrical specifications. Added maximum values and
updated typical values for TERASEB and TWRITE electrical specifications.
Replaced TRAMP electrical specification with SRPOWERUP electrical specification.
This revision fixes CDT 62018.
*D
2905459
NJF
04/06/10
Updated Cypress website links
Added TBAKETEMP, TBAKETIME, and Fout48M electrical specifications
Removed sections ‘Third Party Tools’ ‘Build a PSoC Emulator into your Board’
Updated package diagrams
Updated Ordering Information table
Updated Solder Reflow Peak Temperature specifications.
Updated the Getting Started and Designing with PSoC Designer sections.
Converted data sheet from Preliminary to Final
Fixes from CDT 72358: Deleted 5% oscillator accuracy reference in the Features
section. Deleted reference to a specific SAR10 ADC sample rate in the Analog
System section. Updated the following Electrical Specifications: IDD, ISB, ISBXTL,
VREF, VCMOA, IADCREF, INLADC, DNLADC, VPPOR2, FlashDR, FIMO24, TRiseF,
TFallF, TRiseS, TFallS. Deleted the SPSADC electrical specification, the DC Low
Power Comparator Specifications, the AC Low Power Comparator Specifications, and the AC Analog Mux Bus Specifications.
*E
2915673
VIVG
04/16/10
Post to external web
*F
2991841
BTK
07/23/10
Added a clarifying note to the VPPOR1 electrical specification.
Added CY8C22345-12PVXE(T) devices.
Moved Document Conventions to the end of the document.
This revision fixes the following CDTs: 72476, 75127, 78329.
*G
3037161
BTK
09/23/10
Added CY8C21345-12PVXE(T) devices to the Ordering Information section.
*H
3085024
BTK
11/12/10
Added CY8C21645-12PVXE(T), CY8C21645-24PVXA(T),
CY8C22645-12PVXE(T), and CY8C22645-24PVXA(T) devices to the Ordering
Information section. Refer to CDT 87793.
*I
3200275
BTK
03/18/11
Added tape and reel packaging information (CDT 96026).
Document Number: 001-55397 Rev. *I
Description of Change
Page 35 of 36
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-55397 Rev. *I
Revised March 18, 2011
Page 36 of 36
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective
corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their
respective holders.
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