TI1 OPA837IDBVT Opa837 low-power, precision, 105-mhz, voltage-feedback op amp Datasheet

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OPA837
SBOS673 – SEPTEMBER 2017
OPA837 Low-Power, Precision, 105-MHz, Voltage-Feedback Op Amp
1 Features
3 Description
•
•
•
•
•
•
•
The OPA837 device is a unity-gain stable, voltagefeedback op amp that provides among the highest
MHz per mW of bandwidth versus power among
precision op amps. Using only 600 µA on a single 5-V
supply, this 3.0-mW device delivers 105-MHz
bandwidth at a gain of 1 V/V. The very low trimmed
offset voltage of ±130 µV (maximum) comes with a
typical (±1σ) drift of ±0.4 µV/°C.
1
•
•
•
•
•
Bandwidth: 105 MHz (AV = 1 V/V)
Very Low (Trimmed) Supply Current: 600 µA
Gain Bandwidth Product: 50 MHz
Slew Rate: 105 V/µs
Negative Rail Input, Rail-to-Rail Output
25°C Input Offset: ±130 µV (Max)
Input Offset Voltage Drift (DCK Package):
< ±1.6 µV/°C (Maximum)
Input Voltage Noise: 4.7 nV/√Hz (> 100 Hz)
HD2: –120 dBc at 2 VPP, 100 kHz
HD3: –145 dBc at 2 VPP, 100 kHz
Settling Time: 35 ns, 0.5-V Step to 0.1%
5-µA Shutdown Current With Fast Recovery From
Shutdown for Power Scaling Applications
Ideally
suited
to
single-ended,
successiveapproximation register (SAR) analog-to-digitalconverter (ADC) driving applications, the OPA837
provides one of the lowest input spot noise levels at
4.7 nV/√Hz for the 3-mW quiescent power. The very
high 50-MHz gain bandwidth product provides the low
output impedance to high frequencies required to
supply the fast charging currents in SAR ADC driver
applications. This low dynamic output impedance is
also suitable for reference buffer applications with
precision ADCs. The single-channel OPA837 is
available in a 6-pin SOT-23 package (that includes a
power shutdown feature) and a 5-pin SC70 package.
2 Applications
•
•
•
•
•
•
•
12-Bit to 16-Bit, Low-Power SAR Drivers
Precision ADC Reference Buffers
Very-Low-Power Active Filters
Low-Power Transimpedance Amplifiers
Sensor Signal Conditioning
Wearable Devices
Low-Side Current Sensing
The OPA837 is characterized for operation over the a
wide temperature range of –40°C to +125°C.
Device Information(1)
PART NUMBER
PACKAGE
OPA837
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Low-Power, Low-Noise, Precision, Single-Ended SAR ADC Driver With
True Ground Input and Output Range
5.0 V
REF5040
4.096 V
GND
3.3 V
+VCC
0V
3.8 V
0V
4.0 V
PD
+
OPA837
±
Gain = 1.05 V/V
±VCC
22 Ÿ
2.2 nF
499 Ÿ
ADS8860
16-Bit SAR
1 SPS
22 Ÿ
10.0 kŸ
GND
GND
GND
±0.23 V
LM7705
3.3 V
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA837
SBOS673 – SEPTEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
7.3 Feature Description................................................. 20
7.4 Device Functional Modes........................................ 23
1
1
1
2
3
4
8
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 36
9 Power Supply Recommendations...................... 40
10 Layout................................................................... 40
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: VS = 5 V........................... 5
Electrical Characteristics: VS = 3 V........................... 7
Typical Characteristics: VS = 5.0 V ........................... 9
Typical Characteristics: VS = 3.0 V ......................... 12
Typical Characteristics: ±2.5-V to ±1.5-V Split
Supply ...................................................................... 15
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 41
11 Device and Documentation Support ................. 42
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 19
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
42
12 Mechanical, Packaging, and Orderable
Information ........................................................... 42
7.1 Overview ................................................................. 19
7.2 Functional Block Diagrams ..................................... 19
4 Revision History
2
DATE
REVISION
NOTES
September 2017
*
Initial release.
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SBOS673 – SEPTEMBER 2017
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
DCK Package
5-Pin SC70
Top View
VOUT
1
6
VS+
VS-
2
5
PD
+IN 3
4
VIN-
OUT
1
V-
2
+IN
3
5
V+
4
-IN
Pin Functions
PIN
NAME
FUNCTION
DESCRIPTION
SOT-23
SC-70
PD
5
—
I/O
Amplifier power down.
Low = disabled, high = normal operation (pin must be driven).
VIN–
4
4
I/O
Inverting input pin
VIN+
3
3
I/O
Noninverting input pin
VOUT
1
1
I/O
Output pin
VS–
2
2
Power
Negative power-supply pin
VS+
6
5
Power
Positive power-supply input
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SBOS673 – SEPTEMBER 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS– to VS+
Supply voltage
Supply turn-on/off maximum dV/dT
(2)
MAX
UNIT
5.5
V
1
V/µs
VS+ + 0.5
V
Differential input voltage
±1
V
II
Continuous input current
±10
mA
IO
Continuous output current (3)
±20
mA
VI
Input voltage
VID
VS– – 0.5
Continuous power dissipation
See Thermal Information
TJ
Maximum junction temperature
150
°C
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Staying below this ± supply turn-on edge rate prevents the edge-triggered ESD absorption device across the supply pins from turning
on.
Long-term continuous output current for electromigration limits.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VS+
Single-supply voltage
2.7
5
5.4
V
TA
Ambient temperature
–40
25
125
°C
6.4 Thermal Information
OPA837
THERMAL METRIC
(1)
DBV
(SOT23-6)
DCK
(SC70)
UNIT
6 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
194
203
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
129
152
°C/W
RθJB
Junction-to-board thermal resistance
39
76
°C/W
ψJT
Junction-to-top characterization parameter
26
58
°C/W
ψJB
Junction-to-board characterization parameter
39
76
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS673 – SEPTEMBER 2017
6.5 Electrical Characteristics: VS = 5 V
at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
90
105
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
VOUT = 20 mVPP, G = 1
SSBW
Small-signal bandwidth
VOUT = 20 mVPP, G = 2
45
VOUT = 20 mVPP, G = 10
5
45
C
MHz
C
C
GBP
Gain-bandwidth product
VOUT = 20 mVPP, G = 10
50
MHz
LSBW
Large-signal bandwidth
VOUT = 2 VPP, G = 2
C
26
MHz
Bandwidth for 0.1-dB flatness
VOUT = 200 mVPP, G = 2
C
6
MHz
SR
Slew rate
From LSBW (2)
C
105
V/µs
tR, tF
Rise, fall time
VOUT = 0.5-V step, G = 2, input tR = 10ns
C
ns
Overshoot
VOUT = 2-V step, G = 2, input tR = 40 ns
7.0%
C
Settling time to 0.1%
VOUT = 2.0-V step, G = 1, input tR = 4 ns
25
ns
C
Settling time to 0.01%
VOUT = 2.0-V step, G = 1, input tR = 4 ns
40
ns
C
HD2
Second-order harmonic distortion
f = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73)
–120
dBc
C
HD3
Third-order harmonic distortion
f = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73)
–145
dBc
C
Input voltage noise
f = 500 Hz
nV/√Hz
C
10
11
C
4.7
Voltage noise 1/f corner frequency See Figure 39
35
Hz
C
Input current noise
0.4
pA/√Hz
C
5
kHz
C
75
ns
C
0.14
Ω
C
dB
A
f = 20 kHz
Current noise 1/f corner frequency See Figure 39
Overdrive recovery time
G = 2, 2x output overdrive (see Figure 30)
Closed-loop output impedance
f = 1 MHz, G = 1 (see Figure 38)
DC PERFORMANCE
AOL
Open-loop voltage gain
120
135
TA ≈ 25°C
–130
±30
130
TA = 0°C to +70°C (DCK package)
–170
±30
200
TA = –40°C to +85°C (DCK package)
–234
±30
226
TA = –40°C to +125°C (DCK package)
–234
±30
290
Input offset voltage drift (3)
DCK package, TA = –40°C to +125°C
–1.6
±0.4
1.6
µV/°C
B
Input offset voltage drift (3)
DBV package, TA = –40°C to +125°C
–2.0
±0.4
2.0
µV/°C
B
TA ≈ 25°C
150
340
520
TA = 0°C to +70°C
50
340
664
TA = –40°C to +85°C
50
340
718
TA = –40°C to +125°C
50
340
850
TA = –40°C to +125°C
0.8
1.5
3.3
TA ≈ 25°C
–40
±6
40
TA = 0°C to +70°C
–46
±6
52
TA = –40°C to +85°C
–56
±6
55
TA = –40°C to +125°C
–56
±6
65
TA = –40°C to +125°C
–250
±40
250
Input-referred offset voltage
Input bias current (4)
Input bias current drift (3)
Input offset current
Input offset current drift (3)
(1)
(2)
(3)
(4)
VO = ±2 V, RL = 2 kΩ
A
µV
B
B
B
A
nA
B
B
B
nA/°C
B
A
nA
B
B
B
pA/°C
B
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
For a complete selection of TI high speed amplifiers, visit www.ti.com.
Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range. Typical drift specifications are ±1σ. Maximum drift specifications
are set by the min, max sample packaged test data using a wafer-level screened drift. Min, max drift is not specified by final automated
test equipment (ATE) nor by QA sample testing.
Current is considered positive out of the pin.
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Electrical Characteristics: VS = 5 V (continued)
at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–0.2
0
UNIT
TEST
LEVEL (1)
INPUT
TA ≈ 25°C, < 3-dB degradation in CMRR limit
Common-mode input range, low
TA = –40°C to +125°C, < 3-dB degradation in
CMRR limit
TA ≈ 25°C, < 3-dB degradation in CMRR limit
Common-mode input range, high
CMRR
TA = –40°C to +125°C, < 3-dB degradation in
CMRR limit
Common-mode rejection ratio
–0.2
3.7
3.7
95
0
A
V
3.8
B
A
V
3.8
110
B
dB
A
Input impedance common-mode
250 || 1.5
kΩ || pF
C
Input impedance differential mode
180 || 0.5
kΩ || pF
C
OUTPUT
VOL
Output voltage, low
VOH
TA ≈ 25°C, G = 2
0.05
0.1
TA = –40°C to +125°C, G = 5
0.05
0.1
V
A
B
TA ≈ 25°C, G = 2
4.9
4.95
TA = –40°C to +125°C, G = 5
4.8
4.9
Maximum current into a resistive
load
TA ≈ 25°C, ±1.6 V into 27 Ω, VIO < 2 mV
±58
±70
mA
A
Linear current into a resistive load
TA ≈ 25°C, ±1.7 V into 37.4 Ω, AOL > 80 dB
±45
±50
mA
A
Linear current into a resistive load
overtemperature
TA = –40°C to +125°C, ±1.31 V into 37.4 Ω,
AOL > 80 dB
±35
±45
mA
C
Closed-loop output impedance
Gain of 1 V/V, ±30-mA DC
mΩ
C
V
B
Output voltage, high
V
0.6
.
A
B
POWER SUPPLY
Specified operating voltage
Quiescent operating current per
amplifier (5-V supply)
Supply current temperature
coefficient
2.7
5.4
TA ≈ 25°C (5)
564
592
625
TA = –40°C to +125°C
408
592
865
TA = –40°C to +125°C (see Figure 57)
1.1
1.9
2.4
µA
A
B
µA/°C
B
+PSRR
Positive power-supply rejection
ratio
95
110
dB
A
–PSRR
Negative power-supply rejection
ratio
92
108
dB
A
V
A
V
A
50
nA
A
10
µA
A
10
µA
B
POWER DOWN (Pin Must be Driven)
(5)
6
Enable voltage threshold
Specified on above VS– + 1.5 V
Disable voltage threshold
Specified off below VS– + 0.55 V
0.55
1.5
Power-down pin bias current
PD = 0 V to VS+
–50
Power-down quiescent current
PD ≤ 0.55 V
Power-down quiescent current
over temperature
PD ≤ 0.55 V, TA = –40°C to +125°C
Turnon time delay
Time from PD = high to VOUT = 90% of final
value
300
ns
C
Turnoff time delay
Time from PD = low to VOUT = 10% of original
value
100
ns
C
4
5
The typical specification is at 25°C TJ. The min, max limits are expanded for the automated test equipment (ATE) to account for an
ambient range from 22°C to 32°C with a 2-µA/°C temperature coefficient on the supply current.
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SBOS673 – SEPTEMBER 2017
6.6 Electrical Characteristics: VS = 3 V
at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
85
105
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
VOUT = 20 mVPP, G = 1
SSBW
Small-signal bandwidth
VOUT = 20 mVPP, G = 2
45
VOUT = 20 mVPP, G = 10
5
GBP
Gain-bandwidth product
VOUT = 20 mVPP, G = 10
LSBW
Large-signal bandwidth
VOUT = 1 VPP, G = 2
Bandwidth for 0.1-dB flatness
VOUT = 200 mVPP, G = 2
SR
Slew rate
tR, tF
40
C
MHz
C
C
50
MHz
C
30
MHz
C
6
MHz
C
From LSBW (2)
65
V/µs
C
Rise, fall time
VOUT = 0.5-V step, G = 2, input tR = 10 ns
10
ns
C
Overshoot
VOUT = 2-V step, G = 2, input tR = 40 ns
7%
Settling time to 0.1%
VOUT = 0.5-V step, G = 1, input tR = 4 ns
35
ns
C
Settling time to 0.01%
VOUT = 0.5-V step, G = 1, input tR = 4 ns
50
ns
C
HD2
Second-order harmonic distortion
f = 100 kHz, VO = 1 VPP, G = 1 (see Figure 73)
–125
dBc
C
HD3
Third-order harmonic distortion
f = 100 kHz, VO = 1 VPP, G = 1 (see Figure 73)
–138
dBc
C
Input voltage noise
f = 500 Hz
nV/√Hz
C
11
C
4.9
Voltage noise 1/f corner frequency See Figure 39
35
Hz
C
Input current noise
0.4
pA/√Hz
C
5
kHz
C
f = 10 kHz
Current noise 1/f corner frequency See Figure 39
Overdrive recovery time
G = 2, 2x output overdrive (see Figure 29)
65
ns
C
Closed-loop output impedance
f = 1 MHz, G = 1 (see Figure 38)
.14
Ω
C
dB
A
DC PERFORMANCE
AOL
Open-loop voltage gain
120
133
TA ≈ 25°C
–130
±30
130
TA = 0°C to +70°C
–170
±30
200
TA = –40°C to +85°C
–234
±30
226
TA = –40°C to +125°C
–234
±30
290
Input offset voltage drift (3)
DCK package, TA = –40°C to +125°C
–1.6
±0.4
1.6
µV/°C
B
Input offset voltage drift
DBV package, TA = –40°C to +125°C
–2.0
±0.4
2.0
µV/°C
B
TA ≈ 25°C
145
320
510
TA = 0°C to +70°C
50
320
659
TA = –40°C to +85°C
50
320
708
TA = –40°C to +125°C
50
320
840
TA = –40°C to +125°C
0.8
1.5
3.3
TA ≈ 25°C
–40
±6
40
TA = 0°C to +70°C
–46
±6
52
TA = –40°C to +85°C
–56
±6
55
TA = –40°C to +125°C
–56
±6
65
TA = –40°C to +125°C
–250
±40
250
Input-referred offset voltage
Input bias current (4)
Input bias current drift (3)
Input offset current
Input offset current drift (3)
(1)
(2)
(3)
(4)
VO = ±1 V, RL = 2 kΩ
A
µV
B
B
B
A
nA
B
B
B
nA/°C
B
A
nA
B
B
B
pA/°C
B
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
For a complete selection of TI high speed amplifiers, visit www.ti.com.
Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range. Typical drift specifications are ±1σ. Maximum drift specifications
are set by the min, max sample packaged test data using a wafer-level screened drift. Min, max drift is not specified by final automated
test equipment (ATE) nor by QA sample testing.
Current is considered positive out of the pin.
Submit Documentation Feedback
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SBOS673 – SEPTEMBER 2017
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Electrical Characteristics: VS = 3 V (continued)
at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–0.2
0
UNIT
TEST
LEVEL (1)
INPUT
TA ≈ 25°C, < 3-dB degradation in CMRR limit
Common-mode input range, low
TA = –40°C to +125°C, < 3-dB degradation in
CMRR limit
TA ≈ 25°C, < 3-dB degradation in CMRR limit
Common-mode input range, high
CMRR
TA = –40°C to +125°C, < 3-dB degradation in
CMRR limit
Common-mode rejection ratio
–0.2
3.8
3.8
90
0
A
V
3.9
B
A
V
3.9
105
B
dB
A
Input impedance common-mode
250 || 1.5
kΩ || pF
C
Input impedance differential mode
180 || 0.5
kΩ || pF
C
OUTPUT
VOL
Output voltage, low
VOH
TA ≈ 25°C, G = 2
0.05
0.1
TA = –40°C to +125°C, G = 2
0.10
0.2
TA ≈ 25°C, G = 2
V
A
B
4.9
4.95
TA = –40°C to +125°C, G = 2
4.80
4.9
Maximum current into a resistive
load
TA ≈ 25°C, ±0.8 V into 17.5 Ω, VIO < 2 mV
±45
±55
mA
A
Linear current into a resistive load
TA ≈ 25°C, ±0.9 V into 21.5 Ω, AOL > 80 dB
±40
±45
mA
A
Linear current into a resistive load
overtemperature
TA = –40°C to +125°C, ±0.7 V into 21.5 Ω, AOL
> 80 dB
±32
±40
B
Ω
C
5.4
V
B
TA ≈ 25°C (5)
547
570
607
TA = –40°C to +125°C
404
570
817
TA = –40°C to +125°C (see Figure 57)
0.8
1.7
2.2
Output voltage, high
V
A
B
POWER SUPPLY
Specified operating voltage
Quiescent operating current per
amplifier (3-V supply)
Supply current temperature
coefficient
2.7
µA
A
B
µA/°C
B
+PSRR
Positive power-supply rejection
ratio
90
110
dB
A
–PSRR
Negative power-supply rejection
ratio
88
105
dB
A
V
A
V
A
50
nA
A
8
µA
A
8
µA
B
POWER DOWN (Pin Must be Driven)
(5)
8
Enable voltage threshold
Specified on above VS– + 1.5 V
Disable voltage threshold
Specified off below VS– + 0.55 V
0.55
1.5
Power-down pin bias current
PD = 0 V to VS+
–50
Power-down quiescent current
PD ≤ 0.55 V
Power-down quiescent current
over temperature
PD ≤ 0.55 V, TA = –40°C to +125°C
Turnon time delay
Time from PD = high to VOUT = 90% of final
value
300
ns
C
Turnoff time delay
Time from PD = low to VOUT = 10% of original
value
100
ns
C
1
3
The typical specification is at 25°C TJ. The min, max limits are expanded for the automated test equipment (ATE) to account for an
ambient range from 22°C to 32°C with a 4-µA/°C temperature coefficient on the supply current.
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6.7 Typical Characteristics: VS = 5.0 V
3
3
0
0
Normalized Gain (dB)
Normalized Gain (dB)
at VS+ = 5.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
-3
-6
-9
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
-12
-15
0.1
-6
-9
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
-12
1
10
Frequency (MHz)
-15
0.1
100
1
D002
Figure 2. Inverting Small-Signal Frequency Response
vs Gain
3
6
0
3
-3
Gain (dB)
9
0
100
See Figure 74 and Table 3, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 1. Noninverting Small-Signal Frequency Response
vs Gain
-3
-6
-9
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO 2 VPP
-6
-9
0.1
1
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
-12
10
Frequency (MHz)
-15
0.1
100
1
0.8
0.8
0.6
0.6
Normalized Gain (dB)
1
0.4
0.2
0
-0.2
-0.4
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
-1
0.1
1
0.4
0.2
0
-0.2
-0.4
Gain = -1 V/V
Gain = -2 V/V
Gain = -5 V/V
Gain = -10 V/V
-0.6
-0.8
10
Frequency (MHz)
D004
Figure 4. Inverting Large-Signal Bandwidth vs VOPP
1
-0.8
100
Gain = –1 V/V, RLOAD = 2 kΩ
Figure 3. Noninverting Large-Signal Bandwidth vs VOPP
-0.6
10
Frequency (MHz)
D003
Gain = 2 V/V, RLOAD = 2 kΩ
Normalized Gain (dB)
10
Frequency (MHz)
D001
See Figure 73 and Table 2, VO = 20 mVPP, RLOAD = 2 kΩ
Gain (dB)
-3
-1
0.1
100
1
D005
See Figure 73 and Table 2, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 5. Noninverting Response Flatness vs Gain
10
Frequency (MHz)
100
D006
See Figure 74 and Table 3, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 6. Inverting Response Flatness vs Gain
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Typical Characteristics: VS = 5.0 V (continued)
1.2
1
1
0.8
0.8
0.6
0.6
0.4
Output Voltage (V)
Output Voltage (V)
at VS+ = 5.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
0.4
0.2
0
-0.2
-0.4
-0.6
VO = ±0.125 V
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
-0.8
-1
0.2
0
-0.2
-0.4
-0.6
VO = ±0.125 V
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
-0.8
-1
-1.2
-1.2
0
100
200
300
400 500 600
Time (ns)
700
800
900 1000
0
See Figure 73, gain = 2 V/V,
input edge rate set to stay below slew limiting
0.08
0.08
0.06
0.06
0.04
0.04
0.02
0
-0.02
-0.04
AV = 1, 500-mV Step, TR = 10 ns
AV = 1, 2-V Step, TR = 40 ns
AV = 2, 500-mV Step, TR = 10 ns
AV = 2, 2-V Step, TR = 40 ns
700
800
900 1000
D008
AV = -1 , 500-mV Step, TR = 10 ns
AV = -1 , 2-V Step, TR = 40 ns
AV = -2 , 500-mV Step, TR = 10 ns
AV = -2, 2-V Step, TR = 40 ns
0.02
0
-0.02
-0.04
-0.08
-0.1
0
25
50
75
100 125 150
Time (ns)
175
200
225
250
0
25
50
75
D009
See Figure 73 and Table 2
100 125 150
Time (ns)
175
200
225
250
D010
See Figure 74 and Table 3
Figure 9. Simulated Noninverting Settling Time
Figure 10. Simulated Inverting Settling Time
5
5
VIN x 2 gain
VOUT (AV = 2)
3
2
1
0
-1
-2
-3
3
2
1
0
-1
-2
-3
-4
-4
-5
50
-5
50
250
450
650
850
Time (ns)
1050
1250
VOUT (AV = 2)
VIN x 2 gain
4
Input and Output Voltage (V)
4
Input and Output (V)
400 500 600
Time (ns)
-0.06
-0.1
1450
D011
See Figure 73 and Table 2, gain = 2 V/V
Figure 11. Noninverting Overdrive Recovery
10
300
Figure 8. Inverting Step Response vs Time and VOPP
0.1
Settling Value (%)
Settling Value (%)
Figure 7. Noninverting Step Response vs Time and VOPP
-0.08
200
See Figure 74, gain = –1 V/V,
input edge rate set to stay below slew limiting
0.1
-0.06
100
D007
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250
450
650
850
Time (ns)
1050
1250
1450
D012
See Figure 73 and Table 3, gain –1 V/V
Figure 12. Inverting Overdrive Recovery
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Typical Characteristics: VS = 5.0 V (continued)
at VS+ = 5.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
-80
-100
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
-100
-105
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-90
-110
-120
-130
-140
-110
-115
-120
-125
-130
-135
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
-140
-145
-150
10k
100k
Frequency (Hz)
-150
100
1M
1k
RLOAD (:)
D013
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP
D014
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP,
f = 100 kHz
Figure 14. Harmonic Distortion vs RLOAD
Figure 13. Harmonic Distortion vs Frequency
-100
-110
-105
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-115
-120
-125
-130
HD2, Gain = 2 V/V
HD3, Gain = 2 V/V
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
-135
-140
0.4
-120
-125
-130
-135
HD2, +Gain
HD3, +Gain
HD2, Gain
HD3, Gain
-140
-150
0.8
1.2
1.6
2
2.4
2.8
Output Voltage (V)
3.2
3.6
4
1
1M
Figure 16. Harmonic Distortion vs Gain Magnitude
-80
-85
-90
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
10k
HD2 (PGA 1)
HD3 (PGA 1)
HD2 (PGA 2)
HD3 (PGA 2)
100k
Frequency (Hz)
D017
See Figure 86, VO = 2 VPP, f = 100 kHz
D016
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP,
f = 100 kHz
Harmonic Distortion (dBc)
HD2
HD3
100k
Frequency (Hz)
10
Gain Magnitude (V/V)
D015
Figure 15. Harmonic Distortion vs Output Voltage
Harmonic Distortion (dBc)
-115
-145
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP,
f = 100 kHz
-80
-85
-90
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
10k
-110
1M
D018
See Figure 86, gain of 1 V/V or 2 V/V, VO = 2 VPP,
f = 100 kHz
Figure 17. Harmonic Distortion as Active Mux
Figure 18. Harmonic Distortion as 1-Bit PGA
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6.8 Typical Characteristics: VS = 3.0 V
3
3
0
0
-3
-3
Normalized Gain (dB)
Normalized Gain (dB)
at VS+ = 3.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
-6
-9
-12
-15
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
-18
-21
0.1
1
-6
-9
-12
-15
-18
10
Frequency (MHz)
-21
0.1
100
1
100
D020
Figure 20. Inverting Small-Signal Response vs Gain
3
0
0
-3
-3
-6
-6
Gain (dB)
3
-9
-12
-15
-9
-12
-15
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
-18
-21
0.1
1
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
-18
10
Frequency (MHz)
-21
0.1
100
1
10
Frequency (MHz)
D021
See Figure 73, gain = 2 V/V
100
D022
See Figure 74, gain = –1 V/V
Figure 21. Noninverting Large-Signal Bandwidth vs VOPP
Figure 22. Inverting Large-Signal Bandwidth vs VOPP
1.2
1
1
0.8
0.8
Normalized Gain (dB)
0.6
Normalized Gain (dB)
10
Frequency (MHz)
See Figure 74 and Table 3, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 19. Noninverting Small-Signal Response vs Gain
0.4
0.2
0
-0.2
-0.4
Gain = 1 V/V
Gain = 2 V/V
Gain = 5 V/V
Gain = 10 V/V
-0.6
-0.8
-1
0.1
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
Gain =
Gain =
Gain =
Gain =
-0.8
-1
1
10
Frequency (MHz)
100
D023
See Figure 73 and Table 2, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 23. Noninverting Response Flatness vs Gain
12
1 V/V
2 V/V
5 V/V
10 V/V
D019
See Figure 73 and Table 2, VO = 20 mVPP, RLOAD = 2 kΩ
Gain (dB)
Gain =
Gain =
Gain =
Gain =
-1.2
0.1
1 V/V
2 V/V
5 V/V
10 V/V
1
10
100
Frequency (MHz)
D024
See Figure 74 and Table 3, VO = 20 mVPP, RLOAD = 2 kΩ
Figure 24. Inverting Response Flatness vs Gain
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Typical Characteristics: VS = 3.0 V (continued)
at VS+ = 3.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
0.6
1.2
0.4
0.8
1
Output Voltage (V)
Output Voltage (V)
0.6
0.2
0
-0.2
0.4
0.2
0
-0.2
-0.4
-0.6
VO = ±0.125 V
VO = ±0.25 V
VO = ±0.5 V
-0.4
VO = ±0.125 V
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
-0.8
-1
-0.6
-1.2
0
100
200
300
400 500 600
Time (ns)
700
800
900 1000
0
See Figure 73 and Table 2, gain = 2 V/V,
input edge rate set to stay below slew limiting
0.08
0.08
0.06
0.06
0.04
0.04
0.02
0
-0.02
-0.04
400 500 600
Time (ns)
700
800
900 1000
D026
AV =
AV =
AV =
AV =
1, 500-mV Step, TR = 10 ns
1 , 2-V Step, TR = 40 ns
2 , 500-mV Step, TR = 10 ns
2 , 1-V Step, TR = 40 ns
0.02
0
-0.02
-0.04
-0.06
AV = 1, 500-mV Step, TR = 10 ns
AV = 2 , 1-V Step, TR = 20 ns
AV = 2 , 500-mV Step, TR = 10 ns
-0.08
-0.1
-0.1
0
25
50
75
100
125
Time (ns)
150
175
200
0
25
75
100 125 150 175 200 225 250 275
Time (ns)
D028
See Figure 74 and Table 3
Figure 27. Simulated Noninverting Settling Time
Figure 28. Simulated Inverting Settling Time
3
3
VIN x 2 gain
VOUT (AV = 2)
Input and Output Voltage (V)
2
1
0
-1
-2
-3
50
50
D027
See Figure 73 and Table 2
Input and Output Voltage (V)
300
Figure 26. Inverting Step Response vs VOPP
0.1
Settling Value (%)
Settling Value (%)
Figure 25. Noninverting Step Response vs VOPP
-0.08
200
See Figure 74 and Table 3, gain = –1 V/V,
input edge rate set to stay below slew limiting
0.1
-0.06
100
D025
250
450
650
850
Time (ns)
1050
1250
1450
VOUT (AV = 1)
VIN
2
1
0
-1
-2
-3
50
250
D029
See Figure 73 and Table 2, gain = 2 V/V
450
650
850
Time (ns)
1050
1250
1450
D030
See Figure 74 and Table 3, gain = –1 V/V
Figure 29. Noninverting Overdrive Recovery
Figure 30. Inverting Overdrive Recovery
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Typical Characteristics: VS = 3.0 V (continued)
at VS+ = 3.0 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈
25°C (unless otherwise noted)
-80
-100
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
Harmonic Distortion (dBc)
-90
-110
Distortion (dBc)
-100
-105
-110
-120
-130
-115
-120
-125
-130
-140
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
-135
-150
10k
100k
Frequency (Hz)
-140
100
1M
1k
Load (:)
D031
See Figure 73, Figure 74, Table 2, and Table 3, VO = 1 VPP,
RLOAD = 2 kΩ
Figure 32. Harmonic Distortion vs RLOAD
-100
-118
-105
-120
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
Figure 31. Harmonic Distortion vs Frequency
-116
HD2, Gain = 2 V/V
HD3, Gain = 2 V/V
HD2, Gain = 1 V/V
HD3, Gain = 1 V/V
-122
-124
-126
-128
-130
-132
HD2, +Gain
HD3, +Gain
HD2, Gain
HD3, Gain
-110
-115
-120
-125
-130
-135
-134
-136
0.4
-140
0.5
0.6
0.7
0.8
VOPP (V)
0.9
1
1.1
1
Figure 33. Harmonic Distortion vs Output Swing
Figure 34. Harmonic Distortion vs Gain Magnitude
-80
HD2
HD3
HD2 (PGA 1)
HD3 (PGA 1)
HD2 (PGA 2)
HD3 (PGA 2)
-90
Harmonic Distortion (dBc)
-100
D034
See Figure 73, Figure 74, Table 2, and Table 3, RLOAD = 2 kΩ,
f = 100 kHz, VOUT = 2 VPP
-90
-95
10
Gain Magnitude (V/V)
D033
See Figure 73, Figure 74, Table 2, and Table 3, RLOAD = 2 kΩ,
f = 100 kHz
Harmonic Distortion (dBc)
D032
See Figure 73, Figure 74, Table 2, and Table 3, VO = 2 VPP,
f = 100 kHz, RLOAD = 2 kΩ
-105
-110
-115
-120
-125
-130
-135
-140
-100
-110
-120
-130
-140
-145
-150
10k
100k
Frequency (Hz)
1M
100k
Frequency (Hz)
D035
See Figure 86, gain = 1 V/V, VOUT = 1 VPP, RLOAD = 2 kΩ
Figure 35. Harmonic Distortion as Active Mux
14
-150
10k
1M
D036
See Figure 87, gain of 1 V/V and 2 V/V, VOUT = 1 VPP,
RLOAD = 2 kΩ
Figure 36. Harmonic Distortion as 1-Bit PGA
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6.9 Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
with PD = VCC and TA ≈ 25°C (unless otherwise noted)
90
-90
70
-120
50
-150
30
-180
10
-210
-10
Output Impedance (ohms)
110
130
Open-Loop Gain (dB)
20
10
0
5-V AOL (dB)
3-V AOL (dB)
-30
5-V AOL phase (q)
3-V AOL phase (q) -60
Open-Loop Phase (q)
150
-240
1
10
100
1k
10k 100k
Frequency (Hz)
1M
G = 1, 3-V supply
G = 1, 5-V supply
G = 2, 3-V supply
G = 2, 5-V supply
G = 5, 3-V supply
G = 5, 5-V supply
1
0.1
0.01
0.001
10k
10M 100M
100k
No load simulation
10M
D038
Figure 73 and Table 2 (simulation)
Figure 37. Open-Loop Gain and Phase vs Frequency
Figure 38. Closed-Loop Output Impedance vs Frequency
10
250
5-V supply
3-V supply
200
Input Voltage Noise (nV)
Input Spot Voltage (nV/—Hz) and
Spot Current (pA/—Hz) noise
1M
Frequency (Hz)
D037
+5-V En
+5-V In
+3-V En
+3-V In
1
150
100
50
0
-50
-100
-150
0.1
10
-200
100
1k
10k
100k
Frequency (Hz)
1M
10M
0
1
D039
Measured then fit to ideal 1/f model
Figure 39. Input Spot Noise Density vs Frequency
-75
Off-Channel Isolation (dBm)
110
Rejection Ratio (dB)
100
90
80
70
40
30
20
100
CMRR 5 V
CMRR 3 V
PSRR VCC 5 V
PSRR VEE 5 V
PSRR VCC 3 V
PSRR VEE 3 V
1k
5
6
Time (s)
7
8
9
10
D040
-80
-85
-90
-95
-100
-105
-110
-115
10k
100k
Frequency (Hz)
4
Figure 40. Low-Frequency Voltage Noise vs Time
-70
50
3
Input-referred voltage noise RS = 0 Ω
120
60
2
1M
10M
-120
100k
D041
5-V 200-mVPP (Output)
5-V 2-VPP (Output)
3-V 200-mVPP (Output)
3-V 2-VPP (Output)
1M
Frequency (Hz)
10M
D042
Simulated curves
Figure 41. CMRR and PSRR vs Frequency
Figure 42. Disabled Isolation Noninverting Input to Output
vs Frequency
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Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (continued)
with PD = VCC and TA ≈ 25°C (unless otherwise noted)
250
500
5-V Supply
3-V Supply
5-V Supply
3-V Supply
450
200
No. of Units in Each Bin
No. of Units in Each Bin
225
175
150
125
100
75
400
350
300
250
200
150
50
100
25
50
0
0
-130-110 -90 -70 -50 -30 -10 10 30 50 70 90 110 130
Input Offset Voltage (PV)
D043
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40
Input Offset Current (nA)
D044
830 units at each supply voltage
830 units at each supply voltage
Figure 43. Input Offset Voltage Distribution
Figure 44. Input Offset Current Distribution
30
200
25
20
Input Offset Current (nA)
Input Offset Voltage (PV)
150
100
50
0
-50
-100
10
5
0
-5
-10
-15
-20
-150
-200
-40
15
-25
-20
0
20
40
60
80
Ambient Temperature (qC)
100
-30
-40
120
-20
D045
50 units at 5-V and 3-V supply
120
D046
Figure 46. Input Offset Current vs Ambient Temperature
5-V Supply
3-V Supply
5-V Supply
3-V Supply
No. of Units in 25-pA/qC Bins
55
50
45
40
35
30
25
20
15
10
5
0
-2
5
-2 0
2
-2 5
0
-1 0
7
-1 5
5
-1 0
2
-1 5
00
-7
5
-5
0
-2
5
0
25
50
75
10
0
12
5
15
0
17
5
20
0
22
5
25
0
-1 2
.
-1 8
.
-1 6
.
-1 4
.2
-0 1
.
-0 8
.
-0 6
.
-0 4
.2
0
0.
2
0.
4
0.
6
0.
8
1
1.
2
1.
4
1.
6
1.
8
2
No. of Units in 0.2-PV/qC Bins
100
60
D047
Input Offset Voltage Drift (PV/qC)
–40°C to +125°C fit, 82 units, DBV package
Figure 47. Input Offset Voltage Drift Distribution
16
20
40
60
80
Ambient Temperature (qC)
50 units at 5-V and 3-V supply
Figure 45. Input Offset Voltage vs Ambient Temperature
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
Input Offset Current Drift (pA/qC)
D048
–40°C to +125°C fit, 82 units, DBV package
Figure 48. Input Offset Current Drift Distribution
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Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (continued)
with PD = VCC and TA ≈ 25°C (unless otherwise noted)
21
AV = 1 V/V
AV = 2 V/V
AV = 5 V/V
AV = 10 V/V
Small Signal Frequency Response (dB)
ROUT (:)
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
Gain 1, 100 pF
Gain 1, 1000 pF
Gain 2, 100 pF
Gain 2, 1000 pF
Gain 5, 100 pF
Gain 5, 1000 pF
Gain 10, 100 pF
Gain 10, 1000 pF
18
15
12
9
6
3
0
-3
-6
1
10
100
CLOAD (pF)
1k
1M
10k
10M
100M
Frequency (Hz)
1G
D050
D049
See Figure 65 and Table 2, small signal,
targeting 30° phase margin
Figure 50. Small-Signal Frequency Response vs CLOAD
With Recommended ROUT
Figure 49. Output Resistor vs CLOAD
3
Control and Output Voltages (V)
2
1
0
-1
Power-Down Voltage (5 V)
Output Voltage (5 V)
Power-Down Voltage (3 V)
Output Voltage (3 V)
-2
-3
1
1.1
1.2
1.3
Time (Ps}
1.4
2
1
0
-1
-2
-3
0.8
1.5
Figure 51. Turn-On Time to Sinusoidal Input
3
5.5
0.005
5
0.004
4.5
0.003
0.002
0.001
2.5
0
2
-0.001
1.5
-0.002
Disable and VOUT (V)
Disable and VOUT (V)
4
3.5
1
1.1
Time (Ps)
1.2
1.3
D052
Figure 52. Turn-Off Time to Sinusoidal Input
0.006
Error to Final Value
5-V Disable
5-V VOUT
5-V %Err
3-V Disable
3-V VOUT
3-V %Err
4.5
0.9
D051
5.5
5
Power-Down Voltage (5 V)
Output Voltage (5 V)
Power-Down Voltage (3 V)
Output Voltage (3 V)
0.006
5-V Disable
5-V VOUT
5-V %Err
3-V Disable
3-V VOUT
3-V %Err
4
3.5
3
0.005
0.004
0.003
0.002
0.001
2.5
0
2
-0.001
1.5
-0.002
1
-0.003
1
-0.003
0.5
-0.004
0.5
-0.004
-0.005
0.4
0
0
0
0.1
0.2
0.3
Time From Turn-On (Ps)
0
D053
Figure 53. Gain of 1 Turn-On Time to Final DC Value at
Midscale (Simulated)
0.1
0.2
0.3
Time from Turn-On (Ps)
0.4
Error to Final Value
Control and Output Voltages (V)
3
-0.005
0.5
D054
Figure 54. Gain of 2 Turn-On Time to Final DC Value at
Midscale (Simulated)
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Typical Characteristics: ±2.5-V to ±1.5-V Split Supply (continued)
with PD = VCC and TA ≈ 25°C (unless otherwise noted)
3
3
2.5
2
2
Output Voltage (V)
Output Voltage (V)
1.5
1
VOUT +5 V
VOUT +3 V
VOUT 5 V
VOUT 3 V
0.5
0
-0.5
-1
1
VOUT +5 V
VOUT +3 V
VOUT 5 V
VOUT 3 V
0
-1
-1.5
-2
-2
-2.5
-3
100
-3
100m
0.1
1k
RLOAD (:)
Figure 55. Output Voltage Swing vs Load Resistor
10
D056
Figure 56. Output Saturation Voltage vs Load Current
840
800
800
700
Supply Current (PA)
760
Supply Current (PA)
1
IOUT (mA)
D055
720
680
640
600
560
IQ 5 V
IQ 3 V
600
500
400
300
200
520
100
480
440
-40
0
0.5
-20
0
20
40
60
80
Ambient Temperature (qC)
100
0.6
0.7
0.8
120
0.9
1
1.1
PD-VS (V)
1.2
1.3
1.4
1.5
D058
D057
50 units at 5-V and 3-V supply
Figure 58. Supply Current vs Power-Down Voltage
(Turn-On Higher Than Turn-Off)
800
150
700
60
30
0
-30
-60
-90
-120
-150
-0.4
18
20
5-V IB
5-V IB+
5-V IOS
90
Input Bias Current (nA)
Input Offset Voltage (PV)
120
0.1
0.6
1.1
1.6
2.1
2.6
3.1
3.6
Input Common-Mode Voltage (Single Supply, V)
4.1
3-V IB
3-V IB+
3-V IOS
15
600
10
500
5
400
0
300
-5
200
-10
100
-15
0
-0.5
0
D059
0.5
1
1.5
2
2.5
3
3.5
Input Common-Mode Voltage (V)
4
-20
4.5
D060
12 units, 5-V and 3-V supplies
Measured single device, 5-V and 3-V supplies
Figure 59. Input Offset Voltage vs
Input Common-Mode Voltage
Figure 60. Input Bias and Offset Current vs VICM
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Input Offset Current (nA)
Figure 57. Supply Current vs Ambient Temperature
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7 Detailed Description
7.1 Overview
The OPA837 is a power efficient, unity-gain stable, voltage-feedback amplifier (VFA). Combining a negative rail
input stage and a rail-to-rail output (RRO) stage, the OPA837 provides a flexible solution where exceptional
precision and wide bandwidth at low power are required. This 50-MHz gain bandwidth product (GBP) amplifier
requires less than 0.65 mA of supply current over a 2.7-V to 5.4-V total supply operating range. A shutdown
feature on the 6-pin package version provides power savings where the system requires less than 10 µA when
shut down. Offering a unity-gain bandwidth greater than 100 MHz, the OPA837 provides less than –118-dBc
THD at 100 kHz and a 2-VPP output.
7.2 Functional Block Diagrams
The OPA837 is a standard voltage-feedback op amp with two high-impedance inputs and a low-impedance
output. Figure 61 and Figure 62 show the supported standard applications circuits. These application circuits are
shown with a DC VREF on the inputs that set the DC operating points for single-supply designs. The VREF is often
ground, especially for split-supply applications.
VSIG
VS+
VREF
VIN
VOUT
OPA837
RG
GVSIG
VREF
VREF
VSRF
Copyright © 2017, Texas Instruments Incorporated
Figure 61. Noninverting Amplifier
VREF
VSIG
VS+
VREF
RG
OPA837
VOUT
GVSIG
V IN
VREF
VSRF
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Figure 62. Inverting Amplifier
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7.3 Feature Description
7.3.1 OPA837 Comparison
Table 1 lists several members of the device family that includes the OPA837.
Table 1. Device Family Comparison (1)
(1)
PART NUMBER
Av = +1
BANDWIDTH (MHz)
5-V IQ
(mA, Max 25°C)
INPUT NOISE
VOLTAGE
(nV/√Hz)
2-VPP THD
(dBc, 100 kHz)
RAIL-TO-RAIL
INPUT/OUTPUT
DUALS
OPA837
105
0.63
4.7
–118
VS–, output
—
LMV118
45
0.9
40
—
VS–, output
—
LMH6647
55
1.6
17
–75
Input, output
LMH6646
OPA835
56
0.35
9.4
–104
VS–, output
OPA2835
OPA625
120
2.2
2.5
–120
VS–, output
OPA2625
OPA836
205
1.0
4.6
–118
VS–, output
OPA2836
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7.3.2 Input Common-Mode Voltage Range
When the primary design goal is a linear amplifier with high CMRR, the design must remain within the input
common-mode voltage range (VICR) of an op amp. These ranges are referenced off of each supply as an input
headroom requirement. Ensured operation at 25°C is maintained to the negative supply voltage and to within
1.3 V of the positive supply voltage. The common-mode input range specifications in the Electrical
Characteristics table use CMRR to set the limit. The limits are selected to ensure CMRR does not degrade more
than 3 dB below the minimum CMRR value if the input voltage is within the specified range.
Assuming the op amp is in linear operation, the voltage difference between the input pins is small (ideally 0 V);
and the input common-mode voltage is analyzed at either input pin with the other input pin assumed to be at the
same potential. The voltage at VIN+ is simple to evaluate. In the noninverting configuration of Figure 61, the input
signal, VIN, must not violate the VICR. In the inverting configuration of Figure 62, the reference voltage, VREF, must
be within the VICR.
The input voltage limits have fixed headroom to the power rails and track the power-supply voltages. For one 5-V
supply, the typical linear input voltage ranges from –0.2 V to 3.8 V and –0.2 V to 1.5 V for a 2.7-V supply. The
delta headroom from each power-supply rail is the same in either case: –0.2 V and 1.2 V, respectively.
7.3.3 Output Voltage Range
The OPA837 is a rail-to-rail output op amp. Rail-to-rail output typically means that the output voltage swings to
within 100 mV of the supply rails. There are two different ways to specify this feature: one is with the output still
in linear operation and another is with the output saturated. Saturated output voltages are closer to the powersupply rails than the linear outputs, but the signal is not a linear representation of the input. Saturation and linear
operation limits are affected by the output current, where higher currents lead to more voltage loss in the output
transistors; see Figure 55.
The Electrical Characteristics tables list saturated output voltage specifications with a 2-kΩ load. Figure 55
illustrates the saturated voltage-swing limits versus output load resistance, and Figure 56 illustrates the output
saturation voltage versus load current. Given a light load, the output voltage limits have nearly constant
headroom to the power rails and track the power-supply voltages. For example, with a 2-kΩ load and a single
5-V supply, the linear output voltage ranges from 0.10 V to 4.9 V and ranges from 0.1 V to 2.6 V for a 2.7-V
supply. The delta from each power-supply rail is the same in either case: 0.1 V.
With devices like the OPA837 where the input range is lower than the output range, typically the input limits the
available signal swing only in a noninverting gain of 1 V/V. Signal swing in noninverting configurations in gains
greater than +1 V/V and inverting configurations in any gain are typically limited by the output voltage limits of the
op amp.
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7.3.4 Power-Down Operation
The OPA837 includes a power-down mode in the 6-pin SOT23-6 package. Under logic control, the amplifier can
switch from normal operation to a standby current of less than 10 µA. When the PD pin is connected high, the
amplifier is active. Connecting the PD pin low disables the amplifier and places the output in a high-impedance
state. When the amplifier is configured as a unity-gain buffer, the output stage is in a high DC-impedance state.
A new feature in the OPA837 is a switch from the external inverting input pin to the internal active transistors.
This switch operates with the disable pin function to open up the connection to the internal devices when
powered down. Operating in unity gain provides a high-impedance voltage into both the output and inverting
input pins. This feature allows direct active multiplexer operation to be implemented; see Figure 86. When
disabled, the internal input devices on the inverting input approximately follow the noninverting input on the other
side of the open switch through the back-to-back protection diodes across the inputs. When powered up, these
diodes (two in each direction) act to limit overdrive currents into the active transistors.
The PD pin must be actively driven high or low and must not be left floating. If the power-down mode is not used,
PD must be tied to the positive supply rail.
PD logic states are referenced relatively low to the negative supply rail, VS–. When the op amp is powered from a
single-supply and ground, and the disable line is driven from logic devices with similar VDD voltages to the op
amp, the disable operation does not require any special consideration. The OPA837 is specified to be off with PD
driven to within 0.55 V of the negative supply and specified to be on when driven more than 1.5 V above the
negative supply. Slight hysteresis is provided around a nominal 1-V switch point; see Figure 58. When the op
amp is powered from a split supply with VS– below ground, a level shift logic swing below ground is required to
operate the disable function.
7.3.5 Low-Power Applications and the Effects of Resistor Values on Bandwidth
The OPA837 can use a direct short in the feedback for a gain of 1 V/V. Table 2 gives a list of recommended
values over gain for an increasing noninverting gain target. This table was produced by increasing the R values
until they added 50% of the total output noise power. Higher values can be used to reduce power at the cost of
higher noise. Lower values can be used to reduce the total output noise at the cost of more load power in the
feedback network. Stability is also impaired going to very high values because of the pole introduced into the
feedback path with the inverting input capacitance (1.5-pF common-mode). In low-power applications, reducing
the current in the feedback path is preferable by increasing the resistor values. Using larger value resistors has
two primary side effects (other than lower power) because of the interactions with the inverting input parasitic
capacitance. Using large value resistors lowers the bandwidth and lowers the phase margin. When the phase
margin is lowered, peaking in the frequency response and overshoot and ringing in the pulse response results.
Figure 63 shows the gain = 2 V/V (6 dB) small-signal frequency response with RF and RG equal to 1 kΩ, 2 kΩ,
5 kΩ, 10 kΩ, and 20 kΩ. This test was done with RL = 2 kΩ. Lower RL values can reduce the peaking because of
RL loading effects, but higher values do not have a significant effect.
18
15
Gain (dB)
12
Rf = 1 kOhm
Rf = 2 kOhm
Rf = 5 kOhm
Rf = 10 kOhm
Rf = 20 kOhm
Rf = 20 kOhm || 1.5 pF
9
6
3
0
10k
100k
1M
Frequency (Hz)
10M
100M
D063
Figure 63. Frequency Response With Various RF = RG Resistor Values
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As expected, larger value resistors cause lower bandwidth and peaking in the response (peaking in frequency
response is synonymous with overshoot and ringing in pulse response). Adding a 1.5-pF capacitor in parallel with
RF (equal to the input common-mode capacitance) helps compensate the phase margin loss and restores flat
frequency response. Figure 64 shows the test circuit.
VIN
RG
VOUT
OPA837
2 kW
RF
Optional CF
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Figure 64. G = 2 Test Circuit for Various Gain-Setting Resistor Values
7.3.6 Driving Capacitive Loads
The OPA837 can drive a parasitic load capacitance up through 4 pF on the output with no special
considerations. When driving capacitive loads greater than 4 pF, TI recommends using a small resistor (RO) in
series with the output as close to the device as possible. Without RO, output capacitance interacts with the output
impedance of the amplifier causing phase shift in the loop gain of the amplifier that reduces the phase margin.
This reduction causes peaking in the frequency response and overshoot and ringing in the pulse response.
Inserting RO isolates the phase shift from the loop-gain path and restores the phase margin; however RO can
also limit bandwidth to the capacitive load.
Figure 65 shows the test and Figure 49 illustrates the recommended values of RO versus capacitive loads, CL
using a 30° phase margin target for the op amp. See Figure 50 for the frequency responses with various values
of CL and ROUT parametric on gain.
RO
VIN
VOUT
OPA837
CL
2 kΩ
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Figure 65. ROUT versus CL Test Circuit
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7.4 Device Functional Modes
7.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
To facilitate testing with common lab equipment, the OPA837EVM (see the OPA837DBV and OPA836DBV EVM
User's Guide) allows split-supply operation. This configuration eases lab testing because the mid-point between
the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum analyzers, and
other lab equipment have inputs and outputs that prefer a ground reference for DC-coupled testing.
Figure 66 shows a simple noninverting configuration analogous to Figure 61 with a ±2.5-V supply and VREF equal
to ground. The input and output swing symmetrically around ground. For ease of use, split supplies are preferred
in systems where signals swing around ground. In this example, an optional bias current cancellation resistor is
used in series with the noninverting input. For DC-coupled applications, set this resistor to be equal to the
parallel combination of RF and RG. This resistor increases the noise contribution at the input because of that
resistor noise (see the Output Noise Calculations section).
+2.5 V
RF // RG
RG
VSIG
VOUT
OPA837
Load
-2.5 V
RF
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Figure 66. Split-Supply Operation
Figure 67 shows the step response for this gain of 2-V/V circuit with a ±1-V input to a ±2-V output. For a 4-V
output step, the input edge rate is set to 40 ns to avoid slew limiting.
2.5
Input and Output Voltage (V)
2
1.5
1
0.5
0
-0.5
-1
-1.5
Input
Output
-2
-2.5
0
200
400
600
Time (ns)
800
1000
1200
D064
Figure 67. VIN and VOUT vs Time
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Device Functional Modes (continued)
7.4.2 Single-Supply Operation (2.7 V to 5.4 V)
Most newer systems use a single power supply to improve efficiency and to simplify power-supply design. The
OPA837 can be used with single-supply power (ground for the negative supply) with no change in performance
from split supply, as long as the input and output pins are biased within the linear operating region of the device.
The outputs nominally swing rail-to-rail with approximately a 100-mV headroom required for linear operation. The
inputs can typically swing 0.2 V below the negative rail (typically ground) and to within 1.2 V of the positive
supply. For DC-coupled single-supply operation, the input swing is below the available output swing range for
noninverting gains greater than 1.30 V/V. Typically, the 1.2-V input headroom required to the positive supply only
limits output swing range for a unity-gain buffer.
To change the circuit from split supply to single-supply, level shift all voltages by half the difference between the
power-supply rails. For example, Figure 68 depicts changing from a ±2.5-V split supply to a 5-V single-supply.
The load is shown as mid-supply referenced but can be grounded as well.
5V
RG
VSIG
VOUT
OPA837
Load
RF
2.5 V
Copyright © 2017, Texas Instruments Incorporated
Figure 68. Single-Supply Concept
A practical circuit has an amplifier or other circuit providing the bias voltage for the input, and the output of this
amplifier stage provides the bias for the next stage.
Figure 69 shows a typical noninverting amplifier circuit. With 5-V single-supply, a mid-supply reference generator
is needed to bias the negative side through RG. To cancel the voltage offset that is otherwise caused by the input
bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of 2 V/V is required and
RF = 2 kΩ, select RG = 2 kΩ to set the gain, and R1 = 1 kΩ for bias current cancellation which reduces the output
DC error to IOS × RF. The value for C is dependent on the reference, and TI recommends a value of at least
0.1 µF to limit noise. The frequency response flatness is impacted by the AC impedance, including the reference
and capacitor added to the RG element.
Signal and bias
from previous stage
VSIG
2.5 V
5V
R1
RO
VOUT
OPA837
5V
GVSIG
RG
2.5 V
REF
2.5 V
C
RF
Signal and bias to
next stage
Copyright © 2017, Texas Instruments Incorporated
Figure 69. Noninverting Single-Supply Operation With Reference
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Device Functional Modes (continued)
Figure 70 shows a similar noninverting single-supply scenario with the reference generator replaced by the
Thevenin equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5-V
supply and are used to bias the negative side with the parallel sum equal to the equivalent RG to set the gain. To
cancel the voltage offset that is otherwise caused by the input bias currents, R1 is selected to be equal to RF in
parallel with RG’ in parallel with RG” (R1= RF || RG’ || RG”). For example, if a gain of 2 V/V is required and RF =
2 kΩ, selecting RG’ = RG” = 4 kΩ gives an quivalent parallel sum of 2 kΩ, sets the gain to 2, and references the
input to mid-supply (2.5 V). R1 is set to 1 kΩ for bias current cancellation. The resistor divider costs less than the
2.5-V reference in Figure 69 but increases the current from the 5-V supply. Any noise or variation on the 5-V
supply now also comes into the circuit as an input through the biasing path.
Signal and bias
from previous stage
VSIG
2.5 V
5V
R1
RO
RG’
VOUT
OPA837
GVSIG
5V
2.5 V
RG”
Signal and bias to
next stage
RF
Copyright © 2017, Texas Instruments Incorporated
Figure 70. Noninverting Single-Supply Operation With Resistor Mid-Supply Biasing
Figure 71 shows a typical inverting amplifier circuit. With a 5-V single supply, a mid-supply reference generator is
needed to bias the positive side through R1. To cancel the voltage offset that is otherwise caused by the input
bias currents, R1 is selected to be equal to RF in parallel with RG. For example, if a gain of –2 V/V is required and
RF = 2 kΩ, select RG = 1 kΩ to set the gain and R1 = 667 Ω for bias current cancellation. The value for C is
dependent on the reference, but TI recommends a value of at least 0.1 µF to limit noise into the op amp.
5V
R1
5V
2.5 V
REF
RO
V OUT
OPA837
C
GVSIG
2.5 V
RG
RF
VSIG
Signal and bias to
next stage
2.5 V
Signal and bias
from previous stage
Copyright © 2017, Texas Instruments Incorporated
Figure 71. Inverting Single-Supply Operation With Reference
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Device Functional Modes (continued)
Figure 72 shows a similar inverting single-supply scenario with the reference generator replaced by the Thevenin
equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5-V supply and are
used to bias the positive side. To cancel the voltage offset that is otherwise caused by the input bias currents,
set the parallel value of R1 and R2 equal to the parallel value of RF and RG. C must be added to limit coupling of
noise into the positive input. For example, if gain of –2 V/V is required and RF = 2 kΩ, select RG = 1 kΩ to set the
gain. R1 = R2 = 2 × 667 Ω = 1.33 kΩ for the mid-supply voltage bias and for op-amp input-bias current
cancellation. A good value for C is 0.1 µF. The resistor divider costs less than the 2.5-V reference in Figure 71
but increases the current from the 5-V supply. Any noise or variation in the 5-V supply also comes into the circuit
through this bias setup but be band-limited by the pole formed with R1 || R2 and C.
5V
5V
R1
RO
R2
C
VOUT
OPA837
GVSIG
2.5 V
RG
RF
VSIG
Signal and bias to
next stage
2.5 V
Signal and bias
from previous stage
Copyright © 2017, Texas Instruments Incorporated
Figure 72. Inverting Single-Supply Operation With Resistor Midsupply Biasing
These examples are only a few of the ways to implement a single-supply design. Many other designs exist that
can often be simpler if AC-coupled inputs are allowed. A good compilation of options can be found in the SingleSupply Op Amp Design Techniques application report.
26
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Noninverting Amplifier
The OPA837 can be used as a noninverting amplifier with a signal input to the noninverting input, VIN+. A basic
block diagram of the circuit is illustrated in Figure 61. VREF is often ground when split supplies are used.
Calculate the amplifier output according to Equation 1 if VIN = VREF + VSIG.
æ
RF ö
V
= VSIG ç 1 +
÷ + VREF
OUT
RG ø
è
(1)
The signal gain of the circuit is set by Equation 2, and VREF provides a reference around which the input and
output signals swing. Output signals are in-phase with the input signals within the flat portion of the frequency
response. For a high-speed, low-noise device such as the OPA837, the values selected for RF (and RG for the
desired gain) can strongly influence the operation of the circuit. For the characteristic curves, the noninverting
circuit of Figure 73 shows the test configuration set for a gain of 2 V/V. Table 2 lists the recommended resistor
values over gain.
RF
G= 1 +
RG
(2)
RF 2 NŸ
50-Ÿ
source
Network
Analyzer
RT 50 Ÿ
RS 50 Ÿ
U1 OPA837
±
50-Ÿ
Cable
+
+
R3 1.96 NŸ
2-kŸ load
PD
50-Ÿ
Cable
Network
Analyzer
RLOAD 50 Ÿ
VEE
R6 51.1 Ÿ
RG 2 NŸ
V
VM1
VCC
VCC
+
VEE
+
V1 2.5
V2 2.5
Copyright © 2017, Texas Instruments Incorporated
Figure 73. Characterization Test Circuit for Network, Spectrum Analyzer
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Application Information (continued)
Table 2 lists the recommended resistor values from target gains of 1 V/V to 10 V/V where standard E96 values
are shown. This table controls the RF and RG values to set the resistor noise contribution at approximately 50%
of the total output noise power. These values increase the spot noise at the output over what the op amp voltage
noise produces by 41%. Lower values reduce the output noise of any design at the cost of more power in the
feedback circuit. Using the TINA model and simulation tool shows the impact of different resistor value choices
on response shape and noise.
Table 2. Noninverting Recommended Resistor Values
TARGET GAIN (V/V)
RF (Ω)
RG (Ω)
ACTUAL GAIN (V/V)
GAIN (dB)
1
0
Open
1.00
0.00
1.5
1190
2370
1.50
3.53
2
2000
2000
2.00
6.02
3
2260
1130
3.00
9.54
4
2370
787
4.01
12.07
5
2490
619
5.02
14.02
6
2550
511
5.99
15.55
7
2610
432
7.04
16.95
8
2670
383
7.97
18.03
9
2670
332
9.04
19.13
10
2670
294
10.08
20.07
8.1.2 Inverting Amplifier
The OPA837 can be used as an inverting amplifier with a signal input to the inverting input, VIN–, through the
gain-setting resistor RG. A basic block diagram of the circuit is illustrated in Figure 62.
The output of the amplifier can be calculated according to Equation 3 if VIN = VREF + VSIG and the noninverting
input is biased to VREF.
æ -R
VOUT = VSIG ç F
è RG
28
ö
÷ + VREF
ø
(3)
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The signal gain of the circuit is set by Equation 4 and VREF provides a reference point around which the input and
output signals swing. For bipolar-supply operation, VREF is often ground. The output signal is 180˚ out-of-phase
with the input signal in the pass band of the application. Figure 74 shows the 50-Ω input matched configuration
used for the inverting characterization plots set up for a gain of –1 V/V. In this case, an added termination
resistor, RT, is placed in parallel with the input RG resistor to provide an impedance match to 50-Ω test
equipment. The output network appears as a 2-kΩ load but with a 50-Ω source to the network analyzer. This
output interface network does add a 37.9-dB insertion loss that is normalized out in the characterization curves.
Table 3 lists the suggested values for RF, RG, and RT for inverting gains from –0.5 V/V to –10 V/V. If a 50-Ω input
match is not required, eliminate the RT element.
-RF
G=
RG
(4)
+
VCC
RF 2 NŸ
±
+
VEE
Å 50-Ÿ source
VEE
+
PD
2-kŸ load Æ
+
+
2.5 V
2.5 V
50-Ÿ
Cable
R1 1.96 NŸ
Network
Analyzer
RLOAD 50 Ÿ
RG 2 NŸ
RT 51.1 Ÿ
RS 50 Ÿ
Gain of -1 V/V
50-Ÿ
Cable
R2 51.1 Ÿ
Network
Analyzer
V
VCC
Copyright © 2017, Texas Instruments Incorporated
Figure 74. Inverting Characterization Circuit for Network Analyzer
Table 3. Inverting Recommended Resistor Values
INVERTING GAIN
(V/V)
RF (Ω)
RG (Ω)
STANDARD RT
(Ω)
INPUT ZI (Ω)
ACTUAL (V/V)
GAIN (dB)
–0.5
1190
2370
51.1
50.02
–0.50
–5.98
–1
2000
2000
51.1
49.83
–1.00
0.00
–2
2260
1130
52.3
49.99
–2.00
6.02
–3
2370
787
53.6
50.18
–3.01
9.58
–4
2490
619
54.9
50.43
–4.02
12.09
–5
2550
511
54.9
49.57
–4.99
13.96
–6
2610
432
56.2
49.73
–6.04
15.62
–7
2670
383
57.6
50.07
–6.97
16.87
–8
2670
332
59
50.10
–8.04
18.11
–9
2670
294
60.4
50.11
–9.08
19.16
–10
2670
267
61.9
50.25
–10.00
20.00
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8.1.3 Output DC Error Calculations
The OPA837 can provide excellent DC signal accuracy because of its high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full
advantage of this low input offset voltage, pay careful attention to input bias current cancellation. The low-noise
input stage for the OPA837 has a relatively high input bias current (0.34 µA typical out the pins) but with a close
match between the two input currents. The OPA837 is a negative rail input device using PNP input devices
where the base current flows out of the device pins. A large resistor to ground on the V+ input shifts the pin
voltage positively because of the input bias current. The mismatch between the two input bias currents is very
low, typically only ±10 nA of input offset current. Match the DC source impedances out of the two inputs to
reduce the total output offset voltage. Figure 66 illustrates an example of resistor matching for bias current
cancellation. Analyzing the simple circuit of Figure 66 (using a gain of 2-V/V target with RF = RG = 2 kΩ)
illustrates that the noise gain for the input offset voltage drift is 1 + 2 kΩ / 2 kΩ = 2 V/V. This value results in an
output drift term of ±1.6 µV/°C × 2 = ±3.2 µV/°C (DCK package). Because the two impedances out of the inputs
are matched, the residual error from the maximum ±250 pA/°C offset current drift is this maximum IOS drift times
the 2-kΩ feedback resistor value, or ±50 µV/°C. The total output DC error drift band is ±53.2 µV/°C. If the output
DC drift is more important than reduced feedback currents, lower the resistor values to reduce the dominant drift
term resulting from the IOS term.
8.1.4 Output Noise Calculations
The unity-gain stable, voltage-feedback OPA837 op amp offers among the lowest input voltage and current noise
terms for any device with a supply current less than 0.7 mA. Figure 75 shows the op amp noise analysis model
that includes all noise terms. In this model, all noise terms are shown as noise voltage or current density terms in
nV/√Hz or pA/√Hz.
ENI
+
OPA837
RS
EO
IBN
ERS
RF
4kTRS
RG
4kTRF
IBI
4kT
RG
4kT = 1.6E ± 20J
at 290° K
Copyright © 2017, Texas Instruments Incorporated
Figure 75. Op Amp Noise Analysis Model
The total output spot noise voltage is computed as the square root of the squared contributing terms to the
output noise voltage. This computation is adding all the contributing noise powers at the output by superposition,
then taking the square root to return to a spot noise voltage. The last term includes the noise for both the RG and
RF resistors. Equation 5 shows the general form for this output noise voltage using the terms presented in
Figure 75.
EO
2
ªENI
¬
IBNRS
4kTRS º NG2
¼
IBIRF
2
4kTRFNG
(5)
Dividing this expression by the noise gain (NG = 1 + RF / RG), as shown in Equation 6, gives the equivalent input
referred spot noise voltage at the noninverting input.
EN
30
2
ENI
IBNRS
2
4kTRS
§ IBIRF ·
¨ NG ¸
©
¹
2
4kTRF
NG
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Using the resistor values listed in Table 2 with RS = 0 Ω results in a constant input-referred voltage noise of
< 7 nV/√Hz. Reducing the resistor values can reduce this noise value towards the 4.7 nV/√Hz intrinsic to the
OPA837. As shown in Equation 5, adding the RS for bias current cancellation in noninverting mode adds the
noise from the RS to the total output noise. In inverting mode, bypass the RS bias current cancellation resistor
with a capacitor for the best noise performance. For more details on op amp noise analysis, see the Noise
Analysis for High-Speed Op Amps application report.
8.1.5 Instrumentation Amplifier
Figure 76 is an instrumentation amplifier that combines the high input impedance of the differential-to-differential
amplifier circuit and the common-mode rejection of the differential-to-single-ended amplifier circuit. This circuit is
often used in applications where high input impedance is required (such as taps from a differential line) or in
cases where the signal source is a high impedance.
The output of the amplifier can be calculated according to Equation 7 if VIN+ = VCM + VSIG+ and VIN– = VCM +
VSIG–.
VOUT =
(VIN+ - VIN- )
æ
2RF1 ö æ RF2 ö
´ ç1 +
÷ ç
÷ + VREF
RG1 ø è RG2 ø
è
(7)
Equation 8 shows the signal gain of the circuit. The input VCM is rejected, and VREF provides a reference voltage
or level shift around which the output signal swings. The single-ended output signal is in-phase to the lower input
signal polarity.
æ
2R F1 ö æ R F2 ö
G = ç1 +
÷ ç
÷
R G 1 ø è R G2 ø
è
(8)
VIN½OPA837
VSIG-
RF2
VCM
RG2
RF1
RG1
RG2
VSIG+
½OPA837
VIN+
G[(VSIG+)-(VSIG-)]
RF2
VCM
VOUT
OPA837
RF1
VREF
VREF
Copyright © 2017, Texas Instruments Incorporated
Figure 76. Instrumentation Amplifier (INA)
Integrated INA solutions are available, but the OPA837 device provides a high-frequency solution at relatively
low power (< 1.8 mA for the three op-amp solution). For best CMRR performance, resistors must be matched. A
good rule of thumb is CMRR ≈ the resistor tolerance; so a 0.1% tolerance provides approximately 60-dB CMRR.
For higher gain INA implementations with higher bandwidths, apply the OPA838 to the circuit of Figure 76.
8.1.6 Attenuators
The noninverting circuit of Figure 61 has a minimum gain of 1. To implement attenuation, a resistor divider can
be placed in series with the positive input, and the amplifier set for a gain of 1 V/V by shorting VOUT to VIN– and
removing RG. Because the op amp input is high impedance, the resistor divider sets the attenuation.
The inverting circuit of Figure 62 is used as an attenuator by making RG larger than RF. The attenuation is the
resistor ratio. For example, a 10:1 attenuator can be implemented with RF = 2 kΩ and RG = 20 kΩ.
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8.1.7 Differential to Single-Ended Amplifier
Figure 77 shows a differential amplifier that converts differential signals to single-ended in a single stage and
provides gain (or attenuation) and level shifting. This circuit can be used in applications such as a line receiver
for converting a differential signal from a Cat5 cable to a single-ended output signal.
The output of the amplifier can be calculated according to Equation 9 if VIN+ = VCM + VSIG+ and VIN– = VCM +
VSIG–.
æR ö
VOUT = (VIN+ - VIN - ) ´ ç F ÷ + VREF
è RG ø
(9)
The signal gain of the circuit is shown in Equation 10, VCM is rejected, and VREF provides a level shift or
reference voltage around which the output signal swings. The single-ended output signal is in-phase with the
noninverting input signal. VREF is often ground when split supplies are used on the op amp.
RF
G=
RG
(10)
VSIG-
RF
VCM
RG
VINRG
VIN+
VOUT
OPA837
G[(VSIG+)-(VSIG-)]
VSIG+
VCM
RF
VREF
VREF
Copyright © 2017, Texas Instruments Incorporated
Figure 77. Differential to Single-Ended Amplifier
Line termination can be accomplished by adding a shunt resistor across the VIN+ and VIN– inputs. The differential
impedance is the shunt resistance in parallel with the input impedance of the amplifier circuit, which is usually
much higher. For low gain and low line impedance, the resistor value to add is approximately the impedance of
the line. For example, if a 100-Ω Cat5 cable is used with a gain of 1 V/V amplifier and RF = RG = 2 kΩ, adding a
100-Ω shunt across the input gives a differential impedance of 99 Ω, which is an adequate match for most
applications.
For best CMRR performance, resistors must be matched. Assuming CMRR ≈ the resistor tolerance, a 0.1%
tolerance provides approximately 60-dB CMRR.
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8.1.8 Differential-to-Differential Amplifier
Figure 78 shows a differential amplifier that is used to amplify differential signals to a differential output. This
circuit has high input impedance and is used in differential line driver applications where the signal source is a
high-impedance driver (for example, a differential DAC) that must drive a line.
The output of the amplifier can be calculated according to Equation 11 if VIN± is set to VCM + VSIG±.
æ
2RF ö
V
= VIN ± ´ ç 1 +
÷ + VCM
OUT ±
RG ø
è
(11)
The signal gain of the circuit is shown in Equation 12, and VCM passes with unity gain. The amplifier combines
two noninverting amplifiers into one differential amplifier that shares the RG resistor, which makes RG effectively
half its value when calculating the gain. The output signals are in-phase with the input signals.
2RF
G= 1 +
RG
(12)
VIN½ OPA837
VOUT-
VSIGGVSIG-
VCM
VCM
RF
RG
RF
VSIG+
GVSIG+
VCM
VCM
½ OPA837
VOUT+
VIN+
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Figure 78. Differential-to-Differential Amplifier
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8.1.9 Pulse Application With Single-Supply Circuit
For pulsed applications where the signal is at ground and pulses to a positive or negative voltage, the circuit
bias-voltage considerations differ from those in an application with a signal that swings symmetrically around a
reference point. Figure 79 shows a circuit where the signal is at ground (0 V) and pulses to a positive value. The
waveforms are shown slightly above ground because the output stage requires approximately 100 mV headroom
to the supplies. To operate with the I/O swing truly to ground on a single-supply setup, consider using the fixed
–0.23-V output LM7705.
Signal and bias
from previous stage
VSIG
0V
5V
R1
RO
VOUT
OPA837
GVSIG
RG
0V
RF
Signal and bias to
next stage
Copyright © 2017, Texas Instruments Incorporated
Figure 79. Noninverting Single-Supply Circuit With Pulse
As shown in Figure 80, an inverting amplifier is more appropriate if the input signal pulses negative from ground.
A key consideration in noninverting and inverting cases is that the input and output voltages are kept within the
limits of the amplifier. Because the VICR of the OPA837 includes the negative supply rail, the OPA837 op amp is
well-suited for this application.
5V
R1
RO
VOUT
OPA837
GVSIG
RG
Signal and bias
from previous stage
0V
0V
RF
Signal and bias to
next stage
VSIG
Copyright © 2017, Texas Instruments Incorporated
Figure 80. Inverting Single-Supply Circuit With Pulse
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8.1.10 ADC Driver Performance
The OPA837 provides excellent performance when driving high-performance delta-sigma (ΔΣ) or successiveapproximation-register (SAR) ADCs in low-power audio and industrial applications.
Figure 81 repeats the front page diagram. Many designs prefer to work with a true 0-V input range to 0-V output
at the ADC. The 100-mV output headroom requirement for the OPA837 then requires a small negative supply to
hold the output linearity to ground. This supply is provided in this example using the low-cost LM7705 fixed
negative, –0.23-V output regulator. On a 5-V supply, the input headroom requires at least a 1.2-V headroom to
that supply. As shown in Figure 81, this requirement limits the maximum input to 3.8 V. The SAR operates with a
precision 4.096-V reference provided by the REF5040, where the gain of 1.05 V/V takes the 3.8-V maximum
input to a 4.0-V maximum output. The RC values have been set to limit the overshoot at the OPA837 output pin
to reduce clipping on fast (50 ns) transitions.
5.0 V
REF5040
4.096 V
GND
3.3 V
+VCC
0V
3.8 V
0V
4.0 V
PD
+
OPA837
±
Gain = 1.05 V/V
±VCC
22 Ÿ
2.2 nF
499 Ÿ
ADS8860
16-Bit SAR
1 SPS
22 Ÿ
10.0 kŸ
GND
GND
GND
±0.23 V
LM7705
3.3 V
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Figure 81. OPA837 and ADS8860 Example Circuit
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8.2 Typical Applications
8.2.1 Active Filters
The OPA837 is a good choices for active filters. Figure 83 and Figure 82 show MFB and Sallen-Key circuits
designed implementing second-order low-pass Butterworth filter circuits. Figure 84 shows the frequency
response.
The main difference is that the MFB active filter provides an inverting amplifier in the pass band and the SallenKey active filter is noninverting. The primary advantage for each active filter is that the Sallen-Key filter in unity
gain has no resistor gain error term or feedback resistor noise contribution. The MFB active filter has better
attenuation properties beyond the bandwidth of the op amp. The example circuits are assuming a split-supply
operation but single-supply operation is possible with midscale biasing.
1.4 kW
430 pF
1.4 kW
1.91 kW
OPA837
2.2 nF
Copyright © 2017, Texas Instruments Incorporated
Figure 82. MFB Active Filter, 100-kHz, Second-Order, Low-Pass Butterworth Filter Circuit
12 nF
147 W
255 W
5.6 nF
OPA837
Copyright © 2017, Texas Instruments Incorporated
Figure 83. Sallen-Key Active Filter, 100-kHz, Second-Order, Low-Pass Butterworth Filter Circuit
8.2.1.1 Design Requirements
For both designs, target the following filter shape characteristic:
• Gain of 1 V/V
• 100-kHz Butterworth response
• Q = 0.707 gives a flat Butterworth design
Scale the resistors down to reduce their noise contribution. In the MFB design, the input resistor is the in-band
load to the prior stage. Use values slightly below the gain of –1 V/V in Table 3. The Sallen-Key filter shows a
high impedance input in-band, so scale those resistors down further to improve noise.
The output DC error and drift can be improved by adding bias current cancellation resistors. For the MFB filter
that is a resistor (and a noise filter capacitor) on the noninverting input to ground equal to the resistor inside the
loop times the noise gain. For the Sallen-Key design, add a feedback resistor equal to the sum of the two input
resistors.
8.2.1.2 Detailed Design Procedure
The filter designs shown in this section used an improved design flow that reduces the resistor noise and noise
gain peaking. For the MFB filter, the design was based on the information in the Design Methodology for MFB
Filters in ADC Interface Applications application note.
For the Sallen-Key design, the solution is based on the information in the Component Pre-Distortion for Sallen
Key Filters application note.
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Typical Applications (continued)
8.2.1.3 Application Curves
Figure 84 shows the comparative response curves for each of the filter design examples. Both filters hit the
desired response shape exactly. However, notice the loss of stop-band rejection in the Sallen-Key design. This
loss results from the op amp output impedance increasing at higher frequencies and allowing the signal to feed
through the feedback capacitor to the output.
Figure 84 shows a comparison of the output spot noise for the two designs. The Sallen-Key is much lower due to
the lower resistor values used. Also, the MFB shows a noise gain of 2V/V vs the Sallen-Key gain of 1V/V. This
immediately increases the MFB output noise by at least 2X the input voltage noise from the op amp. Then the
higher resistor values also increase the total output noise for the MFB.
3
20
MFB
SKF
-3
16
Output Noise (nV/—Hz)
Gain Magnitude (dB)
-9
-15
-21
-27
-33
-39
14
12
10
8
6
4
-45
-51
1k
MFB
SKF
18
2
10k
100k
Frequency (Hz)
1M
10M
0
100
D083
Figure 84. MFB and Sallen-Key Active Filters, SecondOrder, Low-Pass Butterworth Filter Response
1k
10k
Frequency (Hz)
100k
1M
D084
Figure 85. Output Spot Noise Comparison
8.2.2 Implementing a 2:1 Active Multiplexer
The OPA837 includes a unique feature that enables a much improved wired-or mux operation. When disabled,
an internal switch opens from the inverting input to the active transistors isolating those nonlinear loads from the
signal being driven back into the inverting input through the active channel. Figure 86 illustrates a simple
example of this multiplexer. In this figure, one of two signals are selected to be passed on to a shared output.
The logic control turns both amplifiers off (logic low) prior to turning one of them on. This control eliminates both
outputs being active at the same time. If both amplifiers must be on, as in the simple switch illustrated in
Figure 86, adding 100-Ω isolating resistors inside the loop at the outputs limits the current flow when both
amplifiers are turned on. This solution offers a very high input impedance to both inputs, very low buffered output
drive, and nearly perfect channel-to-channel isolation. The example of Figure 86 also includes a –0.23-V supply
generator to allow true swing to ground on the output pins. This negative supply generator is optional if the
outputs are more than 0.1 V above ground or intended to be AC-coupled. Testing with a single channel active
and an off channel attached to the output showed no degradation in harmonic distortion; see Figure 17 and
Figure 35. This approach can be expanded to more than two channels or to operate with gain in the channels.
Adding more than two select channels in parallel should add 100-Ω feedback resistors to isolate the inverting
input capacitance from the active output channel.
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+VS
Typical Applications (continued)
PD
R6 100 k
+VS
Å
U1 OPA837
+
This line is
actually
a logic
line
+
+
VIN 1
R3 2 k
VOUT
Å9S
+VS
+
+VS
+
Å9S
2X1 Active
Mux
LM7705 ± 230 mV
VS1 5
PD
+VS
Å
U2 OPA837
+
R7 100 k
+
VIN 2
Å9S
+
Copyright © 2017, Texas Instruments Incorporated
Figure 86. 2:1 Active Multiplexer
8.2.2.1 Design Requirements
To implement a 2:1 active mux, connect the outputs of two OPA837 devices together with separate input signals.
If termination is required for the input signals, add this termination as a resistor to ground on the noninverting
inputs. The inputs accept an input range from 0 V to 3.8 V by using a negative 0.23-V supply generator, such as
the LM7705.
8.2.2.2 Detailed Design Procedure
Aside from simply connecting the two outputs together as shown in Figure 86, there are several other
considerations as well:
• If the source impedance is not 0 Ω, consider adding a resistor in the feedback networks equal to that source
impedance to reduce the output DC error resulting from bias currents
• If the logic control can place both channels on at the same time, place 100-Ω resistors inside the feedback
loop to limit supply currents when both outputs are active
• If a matched gain is desired for the two inputs, configure the op amps for that gain instead of gain of 1 V/V
• If the load is capacitive, add the required ROUT before the summing point on each op amp output
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Typical Applications (continued)
8.2.3 1-Bit PGA Operation
Using the internal inverting input switch that operates along with the power disable function can also allow a
simple gain selection on a single input signal. Figure 87 shows an example gain select of either 1 V/V or 2 V/V
from a single input to a single output. The logic disables both channels before turning one of them on to avoid
high currents in both outputs to be active at the same time. If this approach is not possible, as in the simple
switch shown in Figure 87, insert 100-Ω resistors inside the loop of each op amp output. A bipolar supply is
shown in Figure 87, but any of the single-supply options are also possible. Any combination of gains can be
implemented, but wide gain ranges show a larger change in signal bandwidth. This approach can be expanded
to more than two gain settings. Testing with the circuit of Figure 87 showed no change in harmonic distortion;
see Figure 18 and Figure 36.
R5 2 k
R4 2 k
Gain of 2 or
Gain of 1
Å9S
1-Bit PGA
OPA837
VIN
++
VOUT
PD
R1 100 k
+VS
R3 1 k
+VS
Å9S
This line is
actually
a logic
line
OPA837
Å9S
+VS
++
R2 100 k
+VS
Å9S
+
+
PD
VS1 2.5
VS1 Å2.5
+VS
Copyright © 2017, Texas Instruments Incorporated
Figure 87. 1-Bit PGA
8.2.3.1 Design Requirements
Configure two OPA837 device outputs in different gains when driving the noninverting input with the same input
signal. Select one the two channels using the disable control. Set one channel to a gain of 1 V/V and the second
channel to a gain of 2 V/V using the recommended 2-kΩ values from Table 2.
8.2.3.2 Detailed Design Procedure
The simple design of Figure 87 has several options and details to consider, which include:
• For split-supply operation, the disable control line must operate to within 0.55 V of the negative supply to
disable a channel. A logic level shift is required.
• Any combination of gains can be implemented. However, the signal bandwidths may vary widely through the
gain bandwidth product effect between the two channels if the gains are widely separated. If a more constant
bandwidth between gains is desired, consider adding a fixed RC filter after the combined outputs at a lower
cutoff frequency than the slowest gain setting.
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9 Power Supply Recommendations
The OPA837 is intended to work in a nominal supply range of 3.0 V to 5 V. Supply-voltage tolerances are
supported with the specified operating range of 2.7 V (–10% on a 3-V supply) and 5.4 V (+8% on a 5-V supply).
Good power-supply bypassing is required. Minimize the distance (< 0.1 inch) from the power-supply pins to highfrequency, 0.1-µF decoupling capacitors. A larger capacitor (2.2 µF is typical) is used along with a highfrequency, 0.1-µF supply-decoupling capacitor at the device supply pins. For single-supply operation, only the
positive supply has these capacitors. When a split supply is used, use these capacitors for each supply to
ground. If necessary, place the larger capacitors further from the device and share these capacitors among
several devices in the same area of the printed circuit board (PCB). Avoid narrow power and ground traces to
minimize inductance between the pins and the decoupling capacitors. An optional supply decoupling capacitor
across the two power supplies (for bipolar operation) reduces second harmonic distortion.
The OPA837 has a positive supply current temperature coefficient; see Figure 57. This coefficient helps improve
the input offset voltage drift. Supply current requirements in the system design must account for this effect using
the maximum intended ambient and Figure 57 to size the supply required. The very low power dissipation for the
OPA837 typically does not require any special thermal design considerations. For the extreme case of 125°C
operating ambient, use the approximate maximum 200°C/W for the two packages, and a maximum internal
power of 5.4-V supply × 0.8-mA 125°C supply current from Figure 57 gives a maximum internal power of
4.3 mW. This power only gives a 0.86°C rise from ambient to junction temperature, which is well below the
maximum 150°C junction temperature. Load power adds to this value, but also increases the junction
temperature only slightly over ambient temperature.
10 Layout
10.1 Layout Guidelines
The OPA837EVM can be used as a reference when designing the circuit board. TI recommends following the
EVM layout of the external components near to the amplifier, ground plane construction, and power routing as
closely as possible. General guidelines are listed below:
1. Signal routing must be direct and as short as possible into an out of the op amp.
2. The feedback path must be short and direct avoiding vias if possible, especially with G = 1 V/V.
3. Ground or power planes must be removed from directly under the negative input and output pins of the
amplifier.
4. TI recommends placing a series output resistor as close to the output pin as possible. See Figure 49 for
recommended values for the expected capacitive load. These values are derived targeting a 30° phase
margin to the output of the op amp.
5. A 2.2-µF power-supply decoupling capacitor must be placed within two inches of the device and can be
shared with other op amps. For split supply, a capacitor is required for both supplies.
6. A 0.1-µF power-supply decoupling capacitor must be placed as close to the supply pins as possible,
preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
7. The PD pin uses low logic swing levels. If the pin is not used, PD must be tied to the positive supply to
enable the amplifier. If the pin is used, PD must be actively driven. A bypass capacitor is not necessary, but
can be used for robustness in noisy environments.
40
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10.2 Layout Example
Ground and power plane exist on
inner layers
Non-inverting input
terminated in 50 Ÿ
1
6
Place bypass capacitors
close to power pins
2
3
±
Place bypass capacitors
close to power pins
Ground and power plane removed
from inner layers
+
Place output resistors close
to output pins to minimize
parasitic capacitance
5
Power control (disable) pin
Must be driven
4
Place input resistor close to pin 4
to minimize stray capacitance
Place feedback resistor on the bottom
of PCB between pins 4 and 6
Remove GND and Power plane
under pins 1 and 4 to minimize
stray PCB capacitance
Figure 88. EVM Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• ADS8860 16-Bit, 1-MSPS, Serial Interface, microPower, Miniature, Single-Ended Input, SAR Analog-to-Digital
Converter
• LM7705 Low-Noise Negative Bias Generator
• OPA838 1-mA, 300-MHz Gain Bandwidth, Voltage-Feedback Op Amp
• REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference
• OPA837DBV, OPA836DBV EVM
• Single-Supply Op Amp Design Techniques
• Noise Analysis for High-Speed Op Amps
• Design Methodology for MFB Filters in ADC Interface Applications
• Component Pre-Distortion for Sallen Key Filters
• TINA model and simulation tool
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
42
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA837IDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19FF
OPA837IDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19FF
OPA837IDCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16K
OPA837IDCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16K
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Sep-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
OPA837IDBVR
SOT-23
3000
178.0
9.0
DBV
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
OPA837IDBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
OPA837IDCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
OPA837IDCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Sep-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA837IDBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
OPA837IDBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
OPA837IDCKR
SC70
DCK
5
3000
180.0
180.0
18.0
OPA837IDCKT
SC70
DCK
5
250
180.0
180.0
18.0
Pack Materials-Page 2
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