EL1883 ® Data Sheet July 26, 2004 FN7010.1 Sync Separator with Horizontal Output Features The EL1883 video sync separator is manufactured using Elantec’s high performance analog CMOS process. This device extracts sync timing information from both standard and non-standard video input and also in the presence of Macrovision pulses. It provides composite sync, vertical sync, burst/back porch timing, and horizontal outputs. Fixed 70mV sync tip slicing provides sync edge detection when the video input level is between 0.5VP-P and 2VP-P (sync tip amplitude 143mV to 572mV). A single external resistor sets all internal timing to adjust for various video standards. The composite sync output follows video in sync pulses and a vertical sync pulse is output on the rising edge of the first vertical serration following the vertical preequalizing string. For non-standard vertical inputs, a default vertical pulse is output when the vertical signal stays low for longer than the vertical sync default delay time. The horizontal output gives horizontal timing with pre/post equalizing pulses. • NTSC, PAL, SECAM, non-standard video sync separation The EL1883 is available in an 8-pin SO package and is specified for operation over the full -40°C to +85°C temperature range. • Low supply current - 1.5mA typ. • Single 3V to 5V supply • Composite sync output • Vertical output • Horizontal output • Burst/back porch output • Macrovision compatible • Available in 8-pin SO package • Pb-free available Applications • Video amplifiers • PCMCIA applications • A/D drivers • Line drivers Ordering Information PART NUMBER • Fixed 70mV slicing of video input levels from 0.5VP-P to 2VP-P • Portable computers • High speed communications PACKAGE TAPE & REEL PKG. DWG. # EL1883IS 8-Pin SO - MDP0027 • RGB applications EL1883IS-T7 8-Pin SO 7” MDP0027 • Broadcast equipment EL1883IS-T13 8-Pin SO 13” MDP0027 • Active filtering EL1883ISZ (See Note) 8-Pin SO (Pb-free) - MDP0027 EL1883ISZ-T7 (See Note) 8-Pin SO (Pb-free) 7” MDP0027 EL1883ISZT13 (See Note) 8-Pin SO (Pb-free) 13” MDP0027 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. Demo Board • A dedicated demo board is available Pinout EL1883 (8-PIN SO) TOP VIEW COMPOSITE SYNC OUT 1 COMPOSITE VIDEO IN 2 7 HORIZONTAL OUTPUT VERTICAL SYNC OUT 3 6 RSET GND 4 1 8 VDD 5 BURST/BACK PORCH OUTPUT CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL1883 Absolute Maximum Ratings (TA = 25°C) VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications VDD = 3.3V, TA = 25°C, RSET = 681kΩ, Unless Otherwise Specified. PARAMETER DESCRIPTION MIN TYP MAX UNIT IDD, Quiescent VDD = 5V 0.75 1.5 3 mA Clamp Voltage Pin 2, ILOAD = -100µA 1.35 1.5 1.65 V Clamp Discharge Current Pin 2 = 2V 6 12 16 µA Clamp Charge Current Pin 2 = 1V -0.85 -0.65 -0.45 mA RSET Pin Reference Voltage Pin 6 1.1 1.22 1.35 V VOL Output Low Voltage IOL = 1.6mA 0.24 0.5 V VOH Output High Voltage IOH = -40µA 3 3.2 V IOH = -1.6mA 2.5 3.0 V MIN TYP MAX UNIT 35 75 ns 40 80 ns 3.8 5.2 6.2 µs Dynamic Characteristics PARAMETER DESCRIPTION Comp Sync Prop Delay, tCS See Figure 13 Horizontal Sync Delay, tHS Horizontal Sync Width Vertical Sync Width, tVS Normal or Default Trigger, 50%-50% 190 230 300 µs Vertical Sync Default Delay, tVSD See Figure 14 35 62 85 µs Burst/Back Porch Delay, tBD See Figure 13 120 200 300 ns Burst/Back Porch Width, tB See Figure 13 2.5 3.5 4.5 µs Input Dynamic Range Video Input Amplitude to Maintain Slice Level Spec, VDD = 5V 0.5 2 VP-P Slice Level VSLICE above VCLAMP 50 90 mV 2 70 EL1883 Pin Descriptions PIN NUMBER PIN NAME PIN FUNCTION 1 Composite Sync Out Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge 2 Composite Video In AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase) 3 Vertical Sync Out 4 GND 5 Burst/Back Porch Output 6 RSET (Note) 7 Horizontal Output 8 VDD 5V Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period Supply ground Burst/back porch output; low during burst portion of composite video An external resistor to ground sets all internal timing; a 681k 1% resistor will provide correct timing for NTSC signals Horizontal output; falling edge active Positive supply (5V) NOTE: RSET must be a 1% resistor Typical Performance Curves VDD = 3V, VDD = 5V, TA = 25°C TA = 25°C BURST BACK PORCH DELAY (ns) 900 800 RSET (kΩ) 700 600 500 400 300 200 100 0 10 20 30 40 50 60 70 300 250 200 VDD=5V 150 100 VDD=3V 50 200 0 100 200 300 FREQUENCY (kHz) 700 800 TA = 25°C BURST BACK PORCH WIDTH (ns) HORIZONTAL SYNC WIDTH (µs) 600 FIGURE 2. BURST/BACK PORCH DELAY vs RSET TA = 25°C 7 6 VDD=3V 5 4 VDD=5V 3 2 1 200 500 RSET (kΩ) FIGURE 1. RSET vs HORIZONTAL FREQUENCY 0 100 400 300 400 500 600 700 800 RSET (kΩ) FIGURE 3. HORIZONTAL SYNC WIDTH vs RSET 3 4.5 4 VDD=5V VDD=3V 3.5 3 2.5 2 1.5 1 0.5 0 100 300 500 700 900 RSET (kΩ) FIGURE 4. BURST/BACK PORCH WIDTH vs RSET EL1883 Typical Performance Curves (Continued) VERTICAL SYNC WIDTH (µs) VDD=3V 250 200 VDD=5V 150 100 50 0 100 200 300 400 500 600 700 800 BURST/BACK PORCH DELAY TIME (ns) TA = 25°C 300 RSET = 681kΩ 300 250 VDD=5V 200 150 VDD=3V 100 50 0 -50 -30 -10 RSET (kΩ) RSET = 681kΩ BURST/BACK PORCH WIDTH (µs) VERTICAL SYNC WIDTH (µs) VDD=3V 5.15 5.1 5 4.95 VDD=5V 4.9 10 30 50 70 90 3.6 VDD=3V 3.58 3.56 VDD=5V 3.54 3.52 3.5 3.48 3.46 -50 -30 -10 1.6 POWER DISSIPATION (W) VERTICAL SYNC PLUS WIDTH (µs) 1.8 229 228 227 VDD=3V 225 224 223 VDD=5V 221 -10 50 70 90 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 230 -30 30 FIGURE 8. BURST/BACK PORCH WIDTH vs TEMPERATURE RSET = 681kΩ 220 -50 10 TEMPERATURE (°C) FIGURE 7. HORIZONTAL SYNC WIDTH vs TEMPERATURE 222 90 3.62 TEMPERATURE (°C) 226 70 RSET = 681kΩ 5.2 -10 50 FIGURE 6. BURST/BACK PORCH DELAY vs TEMPERATURE 5.25 -30 30 TEMPERATURE (°C) FIGURE 5. VERTICAL SYNC WIDTH vs RSET 4.85 -50 10 10 30 50 70 90 TEMPERATURE (°C) FIGURE 9. VERTICAL SYNC PULSE WIDTH vs TEMPERATURE 4 1.4 1.2 1.136W 1 θJ 0.8 0.6 SO 8 10 °C /W A =1 0.4 0.2 0 0 25 50 75 85 100 125 150 TEMPERATURE (°C) FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE EL1883 Typical Performance Curves (Continued) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 1.2 1 781mW 0.8 θJ 0.6 SO 8 60 °C /W A =1 0.4 0.2 0 0 25 50 75 85 100 125 150 TEMPERATURE (°C) FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1 SIGNAL 1c. VERTICAL SYNC OUTPUT, PIN 3 tVS SIGNAL 1d. BACK PORCH OUTPUT, PIN 5 SIGNAL 1e. HORIZONTAL SYNC OUTPUT, PIN 7 SEE FIG. 12, 13 SEE FIG. 15 FIGURE 12. TIMING DIAGRAM NOTES: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). e. Horizontal sync output produces the true “H” pulses of nominal width of 5µs. It has the same delay as the composite sync. 5 EL1883 FIGURE 13. STANDARD VERTICAL TIMING FIGURE 14. NON-STANDARD VERTICAL TIMING 6 EL1883 VSLICE 70mV HORIZONTAL SYNC, PIN 7 No pulses in next 75% of line time tB BACK PORCH OUTPUT, PIN 5 tBD FIGURE 15. NON-STANDARD VERTICAL TIMING I/P SIGNAL I/P SIGNAL COMPOSITE SYNC OUT (PIN 1) COMPOSITE SYNC OUT (PIN 1) HORIZONTAL OUT (PIN 7) HORIZONTAL OUT (PIN 7) VERTICAL OUT (PIN 3) VERTICAL OUT (PIN 3) FIGURE 16. EXAMPLE OF EL1883 WITH NTSC SIGNAL THAT INCLUDES MACROVISION COPY PROTECTION (RSET=681kΩ) 7 FIGURE 17. EXAMPLE OF EL1883 WITH 480p SIGNAL THAT INCLUDES MACROVISION COPY PROTECTION (RSET=310kΩ) EL1883 Applications Information Video In A simplified block diagram is shown following page. An AC coupled video signal is input to Video In pin 2 via C1, nominally 0.1µF. Clamp charge current will prevent the signal on pin 2 from going any more negative than Sync Tip Ref, about 1.5V. This charge current is nominally about 1mA. A clamp discharge current of about 10µA is always attempting to discharge C1 to Sync Tip Ref, thus charge is lost between sync pulses that must be replaced during sync pulses. The droop voltage that will occur can be calculated from IT = CV, where V is the droop voltage, I is the discharge current, T is the time between sync pulses (sync period sync tip width), and C is C1. An NTSC video signal has a horizontal frequency of 15.73kHz, and a sync tip width of 4.7µs. This gives a period of 63.6µs and a time T = 58.9µs. The droop voltage will then be V = 5.9mV. This is less than 2% of a nominal sync tip amplitude of 286mV. The charge represented by this droop is replaced in a time given by T = CV/I, where I = clamp charge current = 1mA. Here T = 590ns, about 12% of the sync pulse width of 4.7µs. It is important to choose C1 large enough so that the droop voltage does not approach the switching threshold of the internal comparator. Composite Sync The Composite Sync output is simply a reproduction of the input signal with the active video removed. The sync tip of the Composite video signal is clamped to 1.5V at pin 2 and then slices at 70mV above the sync tip reference. The output signal is buffered out to pin 1. When loss of sync, the Composite Sync output is held low. Burst A low-going burst pulse follows each rising edge of sync, and lasts approximately 3.5µs for an RSET of 681kΩ. When loss of sync, the Back Porch output is held high. Vertical Sync A low-going Vertical Sync pulse is output during the start of the vertical cycle of the incoming video signal. The vertical cycle starts with a pre-equalizing phase of pulses with a duty cycle of about 93%, followed by a vertical serration phase that has a duty cycle of about 15%. Vertical Sync is clocked out of the EL1883 on the first rising edge during the vertical serration phase. In the absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 60µS after the last falling edge of the vertical equalizing phase for RSET = 681kΩ. When loss of sync, the vertical output is held low. Horizontal Sync The Horizontal circuit senses the composite sync edges and produces the true horizontal pulses of nominal width 5.2µs with RSET = 681kΩ. The leading edge is triggered from the 8 leading edge of the input H sync, with the same propagation delay as composite sync. The half line pulses present in the input signal during vertical blanking are removed with an internal 2H line eliminator circuit. This is a circuit that inhibits horizontal output pulses until 75% of the line time is reached, then the horizontal output operation is enabled again. Any signals present on the I/P signal after the true H sync will be ignored, thus the horizontal output will not be affected by MacroVision copy protection. When loss of sync, the Horizontal Sync output is held high. RSET An external RSET resistor, connected from RSET pin 6 to ground, produces a reference current that is used internally as the timing reference for vertical sync width, vertical sync default delay, burst gate delay and burst width. Decreasing the value of RSET increases the reference current, which in turn decreases reference times and pulse widths. A higher frequency video input necessitates a lower RSET value. Chroma Filter A chroma filter is suggested to increase the S/N ratio of the incoming video signal. Use of the optional chroma filter is shown in the figure below. It can be implemented very simply and inexpensively with a series resistor of 620Ω and a parallel capacitor of 500pF, which gives a single pole roll-off frequency of about 500kHz. This sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet passes the approximately 15kHz sync signals without appreciable attenuation. A chroma filter will increase the propagation delay from the composite input to the outputs. EL1883 Simplified Block Diagram CLAMP SYNC TIP REF 1.5V C1 RF 620Ω CF 510pF VDD 8 VDD 5V C2 0.1µF COMPOSITE VIDEO IN 2 SLICE 1.57V 0.1µF COMP. + 1 COMPOSITE SYNC GND 4 RSET C3 0.1µF RSET* 6 REF GEN SYNC TIP 70mV SLICE BURST 5 BURST/BACK PORCH OUT V SYNC 3 VERTICAL SYNC OUT H SYNC 7 HORIZONTAL SYNC OUT NOTE: RSET must be at 1% resistor. 2H ELIMINATOR All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9