ON NVMFS5C423NLT1G Single nâ channel power mosfet Datasheet

NVMFS5C423NL
Power MOSFET
40 V, 2.0 mW, 150 A, Single N−Channel
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS5C423NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
ID MAX
2.0 mW @ 10 V
40 V
150 A
3.0 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RqJC (Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
Pulsed Drain Current
Value
Unit
VDSS
40
V
VGS
±20
V
ID
150
A
TC = 100°C
TC = 25°C
110
PD
TC = 100°C
TA = 25°C
Power Dissipation
RqJA (Notes 1 & 2)
Symbol
Steady
State
TA = 100°C
TA = 25°C
A
31
PD
1.8
900
A
TJ, Tstg
−55 to
+ 175
°C
IS
81
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 14 A)
EAS
280
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Source Current (Body Diode)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
N−CHANNEL MOSFET
MARKING
DIAGRAM
W
3.7
IDM
Operating Junction and Storage Temperature
S (1,2,3)
22
TA = 100°C
TA = 25°C, tp = 10 ms
G (4)
W
83
42
ID
D (5,6)
Symbol
Value
Unit
Junction−to−Case − Steady State
RqJC
1.8
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
41
1
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
D
S
S
S
G
D
XXXXXX
AYWZZ
D
D
XXXXXX = 5C423L
XXXXXX = (NVMFS5C423NL) or
XXXXXX = 423LWF
XXXXXX = (NVMFS5C423NLWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 0
1
Publication Order Number:
NVMFS5C423NL/D
NVMFS5C423NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
17
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25 °C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
100
nA
2.0
V
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.2
−5.3
mV/°C
VGS = 4.5 V
ID = 50 A
2.4
3.0
VGS = 10 V
ID = 50 A
1.6
2.0
gFS
VDS =15 V, ID = 50 A
140
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
3100
VGS = 0 V, f = 1 MHz, VDS = 20 V
CRSS
1300
pF
60
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 20 V; ID = 50 A
23
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 20 V; ID = 50 A
50
Threshold Gate Charge
QG(TH)
5.0
Gate−to−Source Charge
QGS
9.8
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
3.1
td(ON)
12
VGS = 4.5 V, VDS = 20 V; ID = 50 A
nC
nC
6.7
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 4.5 V, VDS = 20 V,
ID = 50 A, RG = 1.0 W
tf
72
ns
28
8.4
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.85
TJ = 125°C
0.73
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 50 A
1.2
V
41
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 50 A
QRR
23
ns
23
40
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS5C423NL
TYPICAL CHARACTERISTICS
3.4 V
160
140
3.2 V
120
100
3.0 V
80
60
2.8 V
40
2.6 V
20
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
200 VDS = 3 V
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
140
120
100
80
TJ = 25°C
60
40
TJ = 125°C
0
1.5
2
TJ = −55°C
2.5
3
3.5
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
VGS, GATE VOLTAGE (V)
4
5.0
TJ = 25°C
4.5
4.0
3.5
3.0
VGS = 4.5 V
2.5
2.0
VGS = 10 V
1.5
1.0
0.5
0
20
40
60
80
100
120
140
160 180 200
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.9
100,000
VGS = 10 V
ID = 50 A
IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
1
VGS, GATE−TO−SOURCE VOLTAGE (V)
4.5
1.7
0.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ = 25°C
ID = 50 A
2.0
160
0
5.0
0.0
180
20
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
ID, DRAIN CURRENT (A)
180
220
3.6 V
10 V to
3.8 V
200
ID, DRAIN CURRENT (A)
220
1.5
1.3
1.1
TJ = 150°C
10,000
TJ = 125°C
1000
TJ = 85°C
100
0.9
0.7
−50 −25
0
25
50
75
100
125
150
175
10
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVMFS5C423NL
10000
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
C, CAPACITANCE (pF)
CISS
COSS
1000
CRSS
100
10
VGS = 0 V
TJ = 25°C
f = 1 MHz
0
10
20
30
40
4
15
QGD
QGS
2
0
10
VDS = 20 V
TJ = 25°C
ID = 50 A
0
4
12 16 20 24 28
8
5
0
32 36 40 44 48
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
100.0
IS, SOURCE CURRENT (A)
100
t, TIME (ns)
20
6
QG, TOTAL GATE CHARGE (nC)
td(off)
tf
tr
td(on)
10
VGS = 4.5 V
VDD = 20 V
ID = 50 A
1
10
TJ = 125°C
TJ = 25°C
10.0
TJ = −55°C
1.0
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1.0
100
1000
TC = 25°C
VGS ≤ 10 V
0.01 ms
IDS (A)
IPEAK (A)
0.1 ms
100
1 ms
dc
10
1
25
8
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
1
30
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
TJ(initial) = 25°C
10
TJ(initial) = 100°C
10 ms
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
1
100
1E−04
1E−03
VDS (V)
TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
1E−02
NVMFS5C423NL
TYPICAL CHARACTERISTICS
100
RqJA(t) (°C/W)
50% Duty Cycle
10
20%
10%
5%
1
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
Marking
Package
Shipping†
NVMFS5C423NLT1G
5C423L
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C423NLWFT1G
423LWF
DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
NVMFS5C423NLT3G
5C423L
DFN5
(Pb−Free)
5000 / Tape & Reel
NVMFS5C423NLWFT3G
423LWF
DFN5
(Pb−Free, Wettable Flanks)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS5C423NL
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2X
0.20 C
D
2
A
B
D1
2X
0.20 C
3
q
E
2
2
c
A1
4
TOP VIEW
C
A
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 C
SIDE VIEW
8X b
C A B
0.05
c
SEATING
PLANE
DETAIL A
0.10 C
0.10
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
4X
E1
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
2X
DETAIL A
0.495
4.560
2X
1.530
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
e/2
e
L
1
3.200
4
4.530
K
PIN 5
(EXPOSED PAD)
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.30
5.15
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
E2
L1
M
1.330
2X
0.905
1
0.965
G
4X
D2
1.000
4X 0.750
BOTTOM VIEW
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
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NVMFS5C423NL/D