STMicroelectronics M48Z2M1Y 5 v or 3.3 v, 16 mbit (2 mb x 8) zeropowerâ® sram Datasheet

M48Z2M1Y
M48Z2M1V
5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
■
Integrated, ultra low power SRAM, power-fail
control circuit, and batteries
■
Conventional SRAM operation; unlimited
WRITE cycles
■
10 years of data retention in the absence of
power
■
Automatic power-fail chip deselect and WRITE
protection
■
WRITE protect voltages
(VPFD = power-fail deselect voltage):
– M48Z2M1Y: VCC = 4.5 to 5.5 V;
4.2 V ≤ VPFD ≤ 4.5 V
– M48Z2M1V: VCC = 3.0 to 3.6 V;
2.8 V ≤ VPFD ≤ 3.0 V
■
Batteries are internally isolated until power is
applied
■
Pin and function compatible with JEDEC
standard 2 Mb x 8 SRAMs
■
RoHS compliant
– Lead-free second level interconnect
June 2011
36
1
PLDIP36 module
Doc ID 5135 Rev 6
This is information on a product still in production but not recommended for new designs.
1/20
www.st.com
1
Contents
M48Z2M1Y, M48Z2M1V
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
Doc ID 5135 Rev 6
M48Z2M1Y, M48Z2M1V
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PLDIP36 – 36-pin plastic DIP long module, package mechanical data . . . . . . . . . . . . . . . 16
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 5135 Rev 6
3/20
List of figures
M48Z2M1Y, M48Z2M1V
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
4/20
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PLDIP36 – 36-pin plastic DIP long module, package outline . . . . . . . . . . . . . . . . . . . . . . . 16
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Doc ID 5135 Rev 6
M48Z2M1Y, M48Z2M1V
1
Description
Description
The M48Z2M1Y/V ZEROPOWER® RAM is a non-volatile 16,777,216-bit, static RAM
organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries,
CMOS SRAMs and a control circuit in a plastic 36-pin DIP, long module.
The ZEROPOWER RAM replaces industry standard SRAMs. It provides the non-volatility of
PROMs without any requirement for special WRITE timing or limitations on the number of
WRITEs that can be performed.
Figure 1.
Logic diagram
VCC
21
8
A0-A20
W
DQ0-DQ7
M48Z2M1Y
M48Z2M1V
E
G
VSS
Table 1.
AI02048
Signal names
A0-A20
DQ0-DQ7
Address inputs
Data inputs / outputs
E
Chip enable
G
Output enable
W
WRITE enable
VCC
Supply voltage
VSS
Ground
NC
Not connected internally
Doc ID 5135 Rev 6
5/20
Description
M48Z2M1Y, M48Z2M1V
Figure 2.
DIP connections
NC
A20
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
36
2
35
34
3
33
4
5
32
6
31
30
7
29
8
M48Z2M1Y
9 M48Z2M1V 28
27
10
26
11
25
12
24
13
14
23
15
22
16
21
20
17
19
18
VCC
A19
NC
A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02049
Figure 3.
Block diagram
VCC
A0-A20
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
2048K x 8
SRAM ARRAY
DQ0-DQ7
E
W
G
INTERNAL
BATTERIES
VSS
6/20
Doc ID 5135 Rev 6
AI02050
M48Z2M1Y, M48Z2M1V
2
Operation modes
Operation modes
The M48Z2M1Y/V has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operations brought on by low VCC. As VCC falls below
approximately 3 V, the control circuitry connects the batteries which sustain data until valid
power returns.
Table 2.
Operating modes
Mode
VCC
Deselect
3.0 to 3.6 V
or
4.5 to 5.5 V
WRITE
READ
READ
Deselect
VSO to VPFD
≤ VSO
Deselect
(min)(1)
(1)
E
G
W
DQ0DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS standby
X
X
X
High Z
Battery backup mode
1. See Table 10 on page 15 for details.
Note:
X = VIH or VIL; VSO = battery backup switchover voltage.
2.1
READ mode
The M48Z2M1Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,777,216 locations in the static storage array. Thus, the unique address specified by the
21 address inputs defines which one of the 2,097,152 bytes of data is to be accessed. Valid
data will be available at the data I/O pins within address access time (tAVQV) after the last
address input signal is stable, providing that the E (chip enable) and G (output enable)
access times are also satisfied. If the E and G access times are not met, valid data will be
available after the later of chip enable access time (tELQV) or output enable access time
(tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the
outputs are activated before tAVQV, the data lines will be driven to an indeterminate state
until tAVQV. If the address inputs are changed while E and G remain low, output data will
remain valid for output data hold time (tAXQX) but will go indeterminate until the next address
access.
Figure 4.
Address controlled, READ mode AC waveforms
A0-A20
tAVAV
tAVQV
DQ0-DQ7
tAXQX
DATA VALID
AI02051
Note:
Chip enable (E) and output enable (G) = low, WRITE enable (W) = high.
Doc ID 5135 Rev 6
7/20
Operation modes
M48Z2M1Y, M48Z2M1V
Figure 5.
Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
VALID
A0-A20
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI02052
Note:
WRITE enable (W) = high.
Table 3.
Symbol
READ mode AC characteristics
M48Z2M1Y
M48Z2M1V
–70
–85
Parameter(1)
Min
tAVAV
READ cycle time
70
tAVQV(2)
Address valid to output valid
tAXQX(2)
Address transition to output transition
tEHQZ
(3)
tELQV(2)
tELQX(3)
tGHQZ(3)
tGLQV(2)
tGLQX(3)
Max
Min
Unit
Max
85
70
5
ns
85
5
ns
ns
Chip enable high to output Hi-Z
30
35
ns
Chip enable low to output valid
70
85
ns
Chip enable low to output transition
5
5
ns
Output enable high to output Hi-Z
25
35
ns
Output enable low to output valid
35
45
ns
Output enable low to output transition
5
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 100 pF or 50 pF (see Figure 9 on page 13).
3. CL = 5 pF (see Figure 9 on page 13).
8/20
Doc ID 5135 Rev 6
M48Z2M1Y, M48Z2M1V
2.2
Operation modes
WRITE mode
The M48Z2M1Y/V is in the WRITE mode whenever W and E are active. The start of a
WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated
by the earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for
minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE
cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for
tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus
contention; although, if the output bus has been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
Figure 6.
WRITE enable controlled, WRITE mode AC waveforms
tAVAV
VALID
A0-A20
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02053
Note:
Output enable (G) = high.
Figure 7.
Chip enable controlled, WRITE mode AC waveforms
tAVAV
A0-A20
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI02054
Note:
Output enable (G) = high.
Doc ID 5135 Rev 6
9/20
Operation modes
Table 4.
Symbol
M48Z2M1Y, M48Z2M1V
WRITE mode AC characteristics
M48Z2M1Y
M48Z2M1V
–70
–85
Parameter(1)
Min
Max
Min
Unit
Max
tAVAV
WRITE cycle time
70
85
ns
tAVEH
Address valid to chip enable high
65
75
ns
tAVEL
Address valid to chip enable low
0
0
ns
tAVWH
Address valid to WRITE enable high
65
75
ns
tAVWL
Address valid to WRITE enable low
0
0
ns
tDVEH
Input valid to chip enable high
30
35
ns
tDVWH
Input valid to WRITE enable high
30
35
ns
tEHAX
Chip enable high to address transition
15
15
ns
tEHDX
Chip enable high to input transition
10
15
ns
tELEH
Chip enable low to chip enable high
55
75
ns
tWHAX
WRITE enable high to address transition
5
5
ns
tWHDX
WRITE enable high to input transition
0
0
ns
WRITE enable high to output transition
5
5
ns
tWHQX(2)(3)
tWLQZ(2)(3)
tWLWH
WRITE enable low to output Hi-Z
WRITE enable pulse width
25
55
30
65
ns
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6V (except where
noted).
2. CL = 5 pF (see Figure 9 on page 13).
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z2M1Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all
inputs are treated as “Don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time tWP, write protection takes
place. When VCC drops below VSO, the control circuit switches power to the internal energy
source which preserves data.
The internal coin cells will maintain data in the M48Z2M1Y/V after the initial application of
VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system
power returns and VCC rises above VSO, the batteries are disconnected, and the power
supply is switched to external VCC. Write protection continues for tER after VCC reaches
VPFD to allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
10/20
Doc ID 5135 Rev 6
M48Z2M1Y, M48Z2M1V
2.4
Operation modes
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 8) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 8.
Supply voltage protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
Doc ID 5135 Rev 6
11/20
Maximum ratings
3
M48Z2M1Y, M48Z2M1V
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Absolute maximum ratings
Symbol
TA
TSTG
TBIAS
TSLD(1)
Parameter
Ambient operating temperature
Storage temperature (VCC off)
Temperature under bias
Lead solder temperature for 10 seconds
Value
Unit
0 to 70
–40 to 85
–40 to 85
260
°C
°C
°C
°C
VIO
Input or output voltages
M48Z2M1Y
M48Z2M1V
–0.3 to 7
–0.3 to 4.6
V
V
VCC
Supply voltage
M48Z2M1Y
M48Z2M1V
–0.3 to 7
–0.3 to 4.6
V
V
20
1
mA
W
IO
PD
Output current
Power dissipation
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices
shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST
recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
Caution:
12/20
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Doc ID 5135 Rev 6
M48Z2M1Y, M48Z2M1V
4
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 6.
Operating and AC measurement conditions
Parameter
Supply voltage (VCC)
M48Z2M1Y
M48Z2M1V
Unit
4.5 to 5.5
3.0 to 3.6
V
0 to 70
0 to 70
°C
Load capacitance (CL)
Ambient operating temperature (TA)
100
50
pF
Input rise and fall times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Input pulse voltages
Input and output timing ref. voltages
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 9.
AC testing load circuit
5V
1.9kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL = 100pF or 5pF (Y)
50pF or 5pF (V)
CL includes JIG capacitance
Doc ID 5135 Rev 6
AI07816
13/20
DC and AC parameters
Table 7.
Capacitance
Parameter(1)(2)
Symbol
CIN
CIO
(3)
M48Z2M1Y, M48Z2M1V
Min
Max
Unit
Input capacitance
-
40
pF
Input / output capacitance
-
40
pF
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. Outputs deselected.
3. At 25 °C.
Table 8.
Sym
DC characteristics
Parameter
Test condition(1)
M48Z2M1Y
Unit
Min
ILI(2)
ILO
(2)
Input leakage current
Output leakage current
M48Z2M1V
Max
Min
Max
0 V ≤ VIN ≤ VCC
±4
±4
µA
0 V ≤ VOUT ≤ VCC
±4
±4
µA
E = VIL,
Outputs open
140
70
mA
E = VIH
10
2
mA
E ≥ VCC – 0.2 V
8
1
mA
ICC
Supply current
ICC1
Supply current (standby) TTL
ICC2
Supply current (standby) CMOS
VIL
Input low voltage
–0.3
0.8
–0.3
0.6
V
VIH
Input high voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output low voltage
IOL = 2.1 mA
0.4
V
VOH
Output high voltage
IOH = –1 mA
0.4
2.4
2.2
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. Outputs deselected.
14/20
Doc ID 5135 Rev 6
V
M48Z2M1Y, M48Z2M1V
DC and AC parameters
Figure 10. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tDR
tF
tR
tFB
tRB
tWP
E
tER
DON'T CARE
RECOGNIZED
RECOGNIZED
HIGH-Z
VALID
OUTPUTS
VALID
(PER CONTROL INPUT)
Table 9.
(PER CONTROL INPUT)
AI01031
Power down/up AC characteristics
Parameter(1)
Symbol
Min
Max
Unit
120
ms
tER
E recovery time
40
tF(2)
VPFD (max) to VPFD (min) VCC fall time
300
µs
tFB(3)
VPFD (min) to VSO VCC fall time
M48Z2M1Y
10
µs
M48Z2M1V
150
µs
10
µs
tR
tWP
VPFD (min) to VPFD (max) VCC rise time
Write protect time from VCC = VPFD
M48Z2M1Y
40
150
µs
M48Z2M1V
40
250
µs
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
VPFD
VSO
tDR
(3)
Power-fail deselect voltage
Battery backup switchover voltage
Min
Typ
Max
Unit
M48Z2M1Y
4.2
4.3
4.5
V
M48Z2M1V
2.8
2.9
3.0
V
M48Z2M1Y
3.0
V
M48Z2M1V
2.45
V
Expected data retention time
10
YEARS
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
3. At 25 °C; VCC = 0 V.
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Package mechanical data
5
M48Z2M1Y, M48Z2M1V
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 11. PLDIP36 – 36-pin plastic DIP long module, package outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
Note:
Drawing is not to scale.
Table 11.
PLDIP36 – 36-pin plastic DIP long module, package mechanical data
mm
inches
Symb
Typ
Min
Max
A
9.27
A1
0.38
B
Min
Max
9.52
0.3650
0.3748
0.43
0.59
0.0169
0.0232
C
0.20
0.33
0.0079
0.0130
D
52.58
53.34
2.0701
2.1000
E
18.03
18.80
0.7098
0.7402
e1
2.30
2.81
0.0906
0.1106
0.5902
0.6299
e3
eA
16/20
Typ
0.0150
43.18
1.7
14.99
16.00
L
3.05
3.81
0.1201
0.1500
S
4.45
5.33
0.1752
0.2098
N
36
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Part numbering
Part numbering
Table 12.
Ordering information scheme
Example:
M48Z
2M1Y
–70
PL
1
Device type
M48Z
Supply voltage and write protect voltage
2M1Y(1) = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V
2M1V(1) = VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V
Speed
–70 = 70 ns (Y)
–85 = 85 ns (V)
Package
PL = PLDIP36
Temperature range
1 = 0 to 70°C
9 = extended temperature
Shipping method
blank = ECOPACK® package, tubes
1. Not recommended for new design. Contact ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
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Environmental information
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M48Z2M1Y, M48Z2M1V
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
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8
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
Changes
Jul-1999
1
31-Aug-2000
2
From preliminary data to datasheet
20-Mar-2002
3
Reformatted; temperature information added to tables (Table 7, 8, 3, 4,
9, 10)
29-May-2002
3.1
Modified “VCC noise and negative going transients” text
28-Mar-2003
3.2
Remove 5 V/5%, add 3 V part (Figure 1, 2, 9; Table 5, 6, 8, 2, 3, 4, 9,
10, 12)
First issue
02-Jul-2003
3.3
18-Feb-2005
4
Reformatted; IR reflow update (Table 5)
Changed characteristic (Table 8)
02-Aug-2010
5
Updated Features, Section 3, Table 12; added ECOPACK® text to
Section 5; added Section 7: Environmental information.
24-Jun-2011
6
Devices are not recommended for new design (updated cover page,
Table 12); updated footnote of Table 5: Absolute maximum ratings;
updated Section 7: Environmental information.
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M48Z2M1Y, M48Z2M1V
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