NCV8501 Series Micropower 150 mA LDO Linear Regulators with ENABLE, DELAY, RESET, and Monitor FLAG http://onsemi.com The NCV8501 is a family of precision micropower voltage regulators. Their output current capability is 150 mA. The family has output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V. The output voltage is accurate within ±2.0% with a maximum dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature drawing only 90 A with a 100 A load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active RESET (with DELAY), and a FLAG monitor which can be used to provide an early warning signal to the microprocessor of a potential impending RESET signal. The use of the FLAG monitor allows the microprocessor to finish any signal processing before the RESET shuts the microprocessor down. The active RESET circuit operates correctly at an output voltage as low as 1.0 V. The RESET function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions. SO−8 D SUFFIX CASE 751 8 1 16 1 SOIC 16 LEAD WIDE BODY EXPOSED PAD PDW SUFFIX CASE 751R MARKING DIAGRAMS SO−8 SOW−16 E PAD 8 16 8501x ALYW 8501x AWLYYWW 1 1 Features • • • • • • • • • • • Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V ±2.0% Output Low 90 A Quiescent Current Fixed or Adjustable Output Voltage Active RESET ENABLE 150 mA Output Current Capability Fault Protection ♦ +60 V Peak Transient Voltage ♦ −15 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload Early Warning through FLAG/MON Leads NCV Prefix for Automotive and Other Applications Requiring Site and Change Control Pb−Free Packages are Available Semiconductor Components Industries, LLC, 2004 September, 2004 − Rev. 19 1 x = Voltage Ratings as Indicated Below: A = Adjustable 2 = 2.5 V 3 = 3.3 V 5 = 5.0 V 8 = 8.0 V 1 = 10 V A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. Publication Order Number: NCV8501/D NCV8501 Series PIN CONNECTIONS, ADJUSTABLE OUTPUT SO−8 1 VIN 8 VOUT VADJ VOUT NC NC NC NC VIN MON VADJ FLAG MON ENABLE NC GND SOW−16 E PAD 1 16 FLAG NC NC GND NC NC NC ENABLE PIN CONNECTIONS, FIXED OUTPUT SO−8 1 VIN 8 MON ENABLE FLAG VOUT NC NC NC NC VIN MON FLAG RESET DELAY GND VIN SOW−16 E PAD 1 16 RESET NC NC GND NC NC DELAY ENABLE VOUT VDD 10 F 10 F NCV8501 DELAY RFLG 10 k Microprocessor VBAT VOUT RRST 10 k MON CDELAY ENABLE VADJ (Adjustable Output Only) RESET FLAG I/O GND Figure 1. Application Diagram http://onsemi.com 2 I/O NCV8501 Series MAXIMUM RATINGS* Rating Value Unit −15 to 45 V Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) 60 V Operating Voltage 45 V VOUT (dc) 16 V Voltage Range (RESET, FLAG) −0.3 to 10 V Input Voltage Range (MON) −0.3 to 10 V −0.3 to 10** V 2.0 kV Junction Temperature, TJ −40 to +150 °C Storage Temperature, TS −55 to 150 °C 45 165 °C/W °C/W 15 56 35 °C/W °C/W °C/W 240 peak 260 Peak (Pb−Free) (Note 3) °C VIN (dc) Input Voltage Range (ENABLE) ESD Susceptibility (Human Body Model) Package Thermal Resistance, SO−8: Junction−to−Case, RJC Junction−to−Ambient, RJA Package Thermal Resistance, SOW−16 E PAD: Junction−to−Case, RJC Junction−to−Ambient, RJA Junction−to−Pin, RJP (Note 1) Lead Temperature Soldering: Reflow: (SMD styles only) (Note 2) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. *During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely. **Reference Figure 14 for switched−battery ENABLE application. 1. Measured to pin 16. 2. 150 second maximum above 183°C, Pb−Free − 150 second maximum above 217°C. 3. −5°C / +0°C allowable conditions, applies to both Pb and Pb−Free devices. http://onsemi.com 3 NCV8501 Series ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 125°C; VIN dependent on voltage option (Note 4); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Output Stage Output Voltage for 2.5 V Option 6.5 V < VIN < 16 V, 100 A ≤ IOUT ≤ 150 mA 5.5 V < VIN < 26 V, 100 A ≤ IOUT ≤ 150 mA 2.450 2.425 2.5 2.5 2.550 2.575 V V Output Voltage for 3.3 V Option 7.3 V < VIN < 16 V, 100 A ≤ IOUT ≤ 150 mA 5.5 V < VIN < 26 V, 100 A ≤ IOUT ≤ 150 mA 3.234 3.201 3.3 3.3 3.366 3.399 V V Output Voltage for 5.0 V Option 9.0 V < VIN < 16 V, 100 A ≤ IOUT ≤ 150 mA 6.0 V < VIN < 26 V, 100 A ≤ IOUT ≤ 150 mA 4.90 4.85 5.0 5.0 5.10 5.15 V V Output Voltage for 8.0 V Option 9.0 V < VIN < 26 V, 100 A ≤ IOUT ≤ 150 mA 7.76 8.0 8.24 V Output Voltage for 10 V Option 11 V < VIN < 26 V, 100 A ≤ IOUT ≤ 150 mA 9.7 10 10.3 V Output Voltage for Adjustable Option VOUT = VADJ (Unity Gain) 6.5 V < VIN < 16 V, 100 A < IOUT < 150 mA 5.5 V < VIN < 26 V, 100 A < IOUT < 150 mA 1.254 1.242 1.280 1.280 1.306 1.318 V V − − 400 100 600 150 mV mV −30 5.0 30 mV − 15 60 mV − − − − − − 90 90 90 100 100 50 125 125 125 150 150 75 A A A A A A Dropout Voltage (VIN − VOUT) (5.0 V, 8.0 V, 10 V, and Adj. > 5.0 V Options Only) IOUT = 150 mA IOUT = 1.0 mA Load Regulation VIN = 14 V, 5.0 mA ≤ IOUT ≤ 150 mA Line Regulation [VOUT(Typ) + 1.0] < VIN < 26 V, IOUT = 1.0 mA Quiescent Current, Low Load 2.5 V Option 3.3 V Option 5.0 V Option 8.0 V Option 10 V Option Adjustable Option IOUT = 100 A, VIN = 12 V, MON = VOUT Quiescent Current, Medium Load All Options IOUT = 75 mA, VIN = 14 V, MON = VOUT − 4.0 6.0 mA Quiescent Current, High Load All Options IOUT = 150 mA, VIN = 14 V, MON = VOUT − 12 19 mA Quiescent Current, (IQ) Sleep Mode ENABLE = 0 V, VIN = 12 V − 12 30 A Current Limit 151 300 − mA Short Circuit Output Current VOUT = 0 V − 40 190 − mA Thermal Shutdown (Guaranteed by Design) 150 180 − °C RESET Threshold for 2.5 V Option HIGH (VRH) LOW (VRL) 5.5 V ≤ VIN ≤ 26 V (Note 5) VOUT Increasing VOUT Decreasing 2.28 2.25 2.350 2.300 0.98 × VOUT 0.97 × VOUT V V RESET Threshold for 3.3 V Option HIGH (VRH) LOW (VRL) 5.5 V ≤ VIN ≤ 26 V (Note 5) VOUT Increasing VOUT Decreasing 3.00 2.97 3.102 3.036 0.98 × VOUT 0.97 × VOUT V V RESET Threshold for 5.0 V Option HIGH (VRH) LOW (VRL) VOUT Increasing VOUT Decreasing 4.55 4.50 4.70 4.60 0.98 × VOUT 0.97 × VOUT V V Reset Function (RESET) 4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type. 5. For VIN ≤ 5.5 V, a RESET = Low may occur with the output in regulation. http://onsemi.com 4 NCV8501 Series ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 125°C; VIN dependent on voltage option (Note 4); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Reset Function (RESET) RESET Threshold for 8.0 V Option HIGH (VRH) LOW (VRL) VOUT Increasing VOUT Decreasing 6.86 6.80 7.52 7.36 0.98 × VOUT 0.97 × VOUT V V RESET Threshold for 10 V Option HIGH (VRH) LOW (VRL) VOUT Increasing VOUT Decreasing 8.60 8.50 9.40 9.20 0.98 × VOUT 0.97 × VOUT V V Output Voltage Low (VRLO) 1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k − 0.1 0.4 V 1.4 1.8 2.2 V DELAY Switching Threshold (VDT) − DELAY Low Voltage VOUT < RESET Threshold Low(min) − − 0.1 V DELAY Charge Current DELAY = 1.0 V, VOUT > VRH 1.5 2.5 3.5 A DELAY Discharge Current DELAY = 1.0 V, VOUT = 1.5 V 5.0 − − mA Increasing and Decreasing 1.10 1.20 1.31 V FLAG/Monitor Monitor Threshold Hysteresis − 20 50 100 mV −0.5 0.1 0.5 A − 0.1 0.4 V VADJ = 1.28 V −0.5 − 0.5 A Input Threshold Low High − 3.0 − − 0.5 − V V Input Current ENABLE = 5.0 V − 1.0 5.0 A Input Current MON = 2.0 V Output Saturation Voltage MON = 0 V, IFLAG = 1.0 mA Voltage Adjust (Adjustable Output only) Input Current ENABLE 4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type. 5. For VIN ≤ 5.5 V, a RESET = Low may occur with the output in regulation. http://onsemi.com 5 NCV8501 Series PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT Package Pin Number SO−8 SOW−16 E PAD Pin Symbol 1 7 VIN 2 8 MON 3 9 ENABLE 4 3−6, 10−12, 14, 15 NC 5 13 GND Ground. All GND leads must be connected to Ground. 6 16 FLAG Open collector output from early warning comparator. 7 1 VADJ Voltage Adjust. A resistor divider from VOUT to this lead sets the output voltage. 8 2 VOUT ±2.0%, 150 mA output. Function Input Voltage. Monitor. Input for early warning comparator. If not needed connect to VOUT. ENABLE control for the IC. A high powers the device up. No connection. PACKAGE PIN DESCRIPTION, FIXED OUTPUT Package Pin Number SO−8 SOW−16 E PAD Pin Symbol 1 7 VIN 2 8 MON 3 9 ENABLE 4 10 DELAY 5 13 GND 6 16 RESET 7 1 FLAG Open collector output from early warning comparator. 8 2 VOUT ±2.0%, 150 mA output. − 3−6, 11, 12, 14, 15 NC Function Input Voltage. Monitor. Input for early warning comparator. If not needed connect to VOUT. ENABLE control for the IC. A high powers the device up. Timing capacitor for RESET function. Ground. All GND leads must be connected to Ground. Active reset (accurate to VOUT ≥ 1.0 V) No connection. http://onsemi.com 6 NCV8501 Series TYPICAL PERFORMANCE CHARACTERISTICS 3.35 5.01 VOUT = 5.0 V VIN = 14 V IOUT = 5.0 mA VOUT = 3.3 V VIN = 14 V IOUT = 5.0 mA 3.34 3.33 VOUT (V) VOUT (V) 5.00 4.99 3.32 3.31 3.30 3.29 3.28 4.98 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 3.27 −40 −25 −10 Figure 2. Output Voltage vs. Temperature 5 20 35 50 65 Temperature (°C) 80 Figure 3. Output Voltage vs. Temperature 1.2 14 VIN = 12 V VIN = 12 V 12 1.0 +125°C 10 +25°C 0.6 IQ (mA) IQ (mA) 0.8 −40°C +125°C 8 +25°C 6 −40°C 0.4 4 0.2 0 2 0 5 10 15 IOUT (mA) 20 0 25 0 Figure 4. Quiescent Current vs. Output Current 15 30 45 60 75 90 IOUT (mA) 105 120 135 140 Figure 5. Quiescent Current vs. Output Current 120 7 T = 25°C T = 25°C 6 100 80 4 IQ (A) IQ (mA) IOUT = 100 A IOUT = 100 mA 5 3 60 49 IOUT = 50 mA 2 20 1 0 95 110 125 IOUT = 10 mA 6 8 10 12 14 16 18 VIN (V) 20 22 24 0 26 6 Figure 6. Quiescent Current vs. Input Voltage 8 10 12 14 16 18 VIN (V) 20 22 24 Figure 7. Quiescent Current vs. Input Voltage http://onsemi.com 7 26 NCV8501 Series 450 16 400 14 VIN = 12 V 350 Quiescent Current (A) Dropout Voltage (mV) TYPICAL PERFORMANCE CHARACTERISTICS 300 +125°C +25°C 250 −40°C 200 150 100 VOUT = 5.0 V, 8.0 V, or 10 V 50 0 0 25 50 75 IOUT (mA) 100 125 12 10 8 6 4 2 0 −40 −25 −10 150 Figure 8. Dropout Voltage vs. Output Current 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 9. Sleep Mode IQ vs. Temperature 1000 1000 Unstable Region Unstable Region CVout = 10 F 100 100 CVout = 0.1 F 10 V 8V 10 2.5 V 3.3 V ESR () ESR () 5 5V 1.0 10 1.0 Stable Region Stable Region 0.1 0.1 CVOUT = 10 F 0.01 0.01 0 10 20 30 40 50 60 70 80 90 100 0 OUTPUT CURRENT (mA) Figure 10. Output Stability with Output Voltage Change 10 20 30 40 50 60 70 80 OUTPUT CURRENT (mA) 90 100 110 Figure 11. Output Stability with Output Capacitor Change http://onsemi.com 8 NCV8501 Series VOUT VIN Current Source (Circuit Bias) ENABLE IBIAS Current Limit Sense + + − IBIAS + − VBG Error Amplifier RESET VBG + − 1.8 V Fixed Voltage only Thermal Protection 3.0 A Delay IBIAS Bandgap Reference VBG VADJ VBG − Figure 12. Block Diagram http://onsemi.com 9 GND IBIAS + MON 20 k Adjustable Version only FLAG NCV8501 Series CIRCUIT DESCRIPTION The DELAY lead provides source current (typically 2.5 A) to the external DELAY capacitor during the following proceedings: 1. During Power Up (once the regulation threshold has been verified). 2. After a reset event has occurred and the device is back in regulation. The DELAY capacitor is discharged when the regulation (RESET threshold) has been violated. This is a latched incident. The capacitor will fully discharge and wait for the device to regulate before going through the delay time event again. REGULATOR CONTROL FUNCTIONS The NCV8501 contains the microprocessor compatible control function RESET (Figure 13). VIN RESET Threshold VOUT DELAY DELAY Threshold (VDT) RESET Td FLAG/Monitor Function Td An on−chip comparator is provided to perform an early warning to the microprocessor of a possible reset signal. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with the microprocessor. The signal received from the FLAG pin will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the bandgap reference. The actual trip point can be programmed externally using a resistor divider to the input monitor (MON) (Figure 15). The typical threshold is 1.20 V on the MON pin. Figure 13. Reset and Delay Circuit Wave Forms RESET Function A RESET signal (low voltage) is generated as the IC powers up until VOUT is within 6.0% of the regulated output voltage, or when VOUT drops out of regulation,and is lower than 8.0% below the regulated output voltage. Hysteresis is included in the function to minimize oscillations. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V. VBAT VOUT VIN ENABLE Function VCC NCV8501 The part stays in a low IQ sleep mode when the ENABLE pin is held low. The part has an internal pull down if the pin is left floating. This is intended for failure modes only. An external connection (active pulldown, resistor, or switch) for normal operation is recommended. The integrity of the ENABLE pin allows it to be tied directly to the battery line through an external resistor. It will withstand load dump potentials in this configuration. I/O FLAG MON P COUT RADJ RESET RESET DELAY GND Figure 15. FLAG/Monitor Function Voltage Adjust VBAT Figure 16 shows the device setup for a user configurable output voltage. The feedback to the VADJ pin is taken from a voltage divider referenced to the output voltage. The loop is balanced around the Unity Gain threshold (1.28 V typical). VOUT VIN NCV8501 10 k ENABLE GND ≈5.0 V VOUT NCV8501 Figure 14. ENABLE Function VADJ DELAY Function 15 k COUT 1.28 V 5.1 k The reset delay circuit provides a programmable (by external capacitor) delay on the RESET output lead. Figure 16. Adjustable Output Voltage http://onsemi.com 10 NCV8501 Series APPLICATION NOTES VIN CIN* 0.1 F NCV8501 VIN MJD31C VOUT VBAT C2 0.1 F R1 294 k NCV8501 RRST COUT** 10 F RESET 5.0 V >1 Amp VADJ VOUT C1 47 F *CIN required if regulator is located far from the power supply filter **COUT required for stability. Capacitor must operate at minimum temperature expected R2 100 k Figure 19. Test and Application Circuit Showing Output Compensation Figure 17. Additional Output Current SETTING THE DELAY TIME The delay time is controlled by the Reset Delay Low Voltage, Delay Switching Threshold, and the Delay Charge Current. The delay follows the equation: Adding Capability Figure 17 shows how the adjustable version of parts can be used with an external pass transistor for additional current capability. The setup as shown will provide greater than 1 Amp of output current. tDELAY FLAG MONITOR Figure 18 shows the FLAG Monitor waveforms as a result of the circuit depicted in Figure 15. As the output voltage falls (VOUT), the Monitor threshold is crossed. This causes the voltage on the FLAG output to go low sending a warning signal to the microprocessor that a RESET signal may occur in a short period of time. TWARNING is the time the microprocessor has to complete the function it is currently working on and get ready for the RESET shutdown signal. [CDELAY(Vdt Reset Delay Low Voltage)] Delay Charge Current Example: Using CDELAY = 33 nF. Assume reset Delay Low Voltage = 0. Use the typical value for Vdt = 1.8 V. Use the typical value for Delay Charge Current = 2.5 A. tDELAY [33 nF(1.8 0)] 23.8 ms 2.5 A STABILITY CONSIDERATIONS The output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 19 should work for most applications, however it is not necessarily the optimized solution. VOUT MON FLAG Monitor Ref. Voltage RESET FLAG TWARNING Figure 18. FLAG Monitor Circuit Waveform http://onsemi.com 11 NCV8501 Series CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 20) is: VIN(max)IQ Thermal Resistance, Junction to Ambient, RJA, (°C/W) PD(max) [VIN(max) VOUT(min)] IOUT(max) 100 (eq. 1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RJA can be calculated: T RJA 150°C A PD SMART REGULATOR 70 60 50 0 200 400 600 Copper Area (mm2) 800 Figure 21. 16 Lead SOW (Exposed Pad), JA as a Function of the Pad Copper Area (2 oz. Cu Thickness), Board Material = 0.0625 G−10/R−4 (eq. 2) HEATSINKS A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RJA: IOUT IIN 80 40 The value of RJA can then be compared with those in the package section of the data sheet. Those packages with RJA’s less than the calculated value in Equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. VIN 90 VOUT RJA RJC RCS RSA (eq. 3) where: RJC = the junction−to−case thermal resistance, RCS = the case−to−heatsink thermal resistance, and RSA = the heatsink−to−ambient thermal resistance. RJC appears in the package section of the data sheet. Like RJA, it too is a function of package type. RCS and RSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers. } Control Features IQ Figure 20. Single Output Regulator with Key Performance Parameters Labeled http://onsemi.com 12 NCV8501 Series ORDERING INFORMATION Device NCV8501DADJ NCV8501DADJG NCV8501DADJR2 NCV8501DADJR2G Output Voltage Package Shipping† Adjustable SO−8 98 Units/Rail Adjustable SO−8 (Pb−Free) 98 Units/Rail Adjustable SO−8 2500 Tape & Reel Adjustable SO−8 (Pb−Free) 2500 Tape & Reel Adjustable SOW−16 Exposed Pad 2.5 V SO−8 98 Units/Rail 2.5 V SO−8 (Pb−Free) 98 Units/Rail 2.5 V SO−8 2500 Tape & Reel 2.5 V SO−8 (Pb−Free) 2500 Tape & Reel 25V 2.5 SOW−16 Exposed Pad 3.3 V SO−8 98 Units/Rail 3.3 V SO−8 (Pb−Free) 98 Units/Rail 3.3 V SO−8 2500 Tape & Reel 3.3 V SO−8 (Pb−Free) 2500 Tape & Reel 33V 3.3 SOW−16 Exposed Pad 5.0 V SO−8 98 Units/Rail 5.0 V SO−8 (Pb−Free) 98 Units/Rail 5.0 V SO−8 2500 Tape & Reel 5.0 V SO−8 (Pb−Free) 2500 Tape & Reel 50V 5.0 SOW−16 Exposed Pad 8.0 V SO−8 98 Units/Rail 8.0 V SO−8 (Pb−Free) 98 Units/Rail 8.0 V SO−8 2500 Tape & Reel 8.0 V SO−8 (Pb−Free) 2500 Tape & Reel 80V 8.0 SOW−16 Exposed Pad 10 V SO−8 98 Units/Rail 10 V SO−8 (Pb−free) 98 Units/Rail 10 V SO−8 2500 Tape & Reel 10 V SO−8 (Pb−Free) 2500 Tape & Reel 10 V SOW−16 Exposed Pad NCV8501PDWADJ NCV8501PDWADJR2 NCV8501D25 NCV8501D25G NCV8501D25R2 NCV8501D25R2G 47 Units/Rail NCV8501PDW25 NCV8501PDW25R2 NCV8501D33 NCV8501D33G NCV8501D33R2 NCV8501D33R2G 47 Units/Rail NCV8501PDW33 NCV8501PDW33R2 NCV8501D50 NCV8501D50G NCV8501D50R2 NCV8501D50R2G NCV8501D80 NCV8501D80G NCV8501D80R2 NCV8501D80R2G NCV8501D100 NCV8501D100G NCV8501D100R2 NCV8501D100R2G 1000 Tape & Reel 47 Units/Rail NCV8501PDW100 NCV8501PDW100R2 1000 Tape & Reel 47 Units/Rail NCV8501PDW80 NCV8501PDW80R2 1000 Tape & Reel 47 Units/Rail NCV8501PDW50 NCV8501PDW50R2 1000 Tape & Reel 1000 Tape & Reel 47 Units/Rail 1000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 13 NCV8501 Series PACKAGE DIMENSIONS SO−8 NB D SUFFIX CASE 751−07 ISSUE AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 NCV8501 Series PACKAGE DIMENSIONS SOIC 16 LEAD WIDE BODY EXPOSED PAD PDW SUFFIX CASE 751R−02 ISSUE A −U− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751R−01 OBSOLETE, NEW STANDARD 751R−02. A M 16 9 P 0.25 (0.010) M W M B 1 R x 45 8 −W− G PIN 1 I.D. 14 PL DETAIL E TOP SIDE C F −T− 0.10 (0.004) T K D 16 PL 0.25 (0.010) T U M SEATING PLANE W S S J DETAIL E H EXPOSED PAD 1 8 L 16 9 BACK SIDE http://onsemi.com 15 DIM A B C D F G H J K L M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 3.76 3.86 0.25 0.32 0.10 0.25 4.58 4.78 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.148 0.152 0.010 0.012 0.004 0.009 0.180 0.188 0 7 0.395 0.415 0.010 0.029 NCV8501 Series SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 16 For additional information, please contact your local Sales Representative. NCV8501/D