MX29LA129M H/L 128M-BIT SINGLE VOLTAGE 3V ONLY UNIFORM SECTOR FLASH MEMORY FEATURES GENERAL FEATURES • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Configuration - 16,777,216 x 8 / 8,388,608 x 16 switchable • Sector structure - 64KB(32KW) x 256 • Latch-up protected to 250mA from -1V to VCC + 1V • Low VCC write inhibit is equal to or less than 1.5V • Compatible with JEDEC standard - Pin-out and software compatible to single power supply Flash • Status Reply - Data# polling & Toggle bits provide detection of program and erase operation completion HARDWARE FEATURES • Ready/Busy (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode • WP#/ACC input - Write protect (WP#) function allows protection of all sectors, regardless of sector protection settings - ACC (high voltage) accelerates programming time for higher throughput during system PERFORMANCE • High Performance - Fast access time: 90R/100ns - Page read time: 25ns - Sector erase time: 0.5s (typ.) - 4 word/8 byte page read buffer - 16 word/ 32 byte write buffer: reduces programming time for multiple-word/byte updates • Low Power Consumption - Active read current: 18mA(typ.) - Active write current: 20mA(typ.) - Standby current: 20uA(typ.) • Minimum 100,000 erase/program cycle • 20-years data retention SECURITY • Sector Protection/Chip Unprotect - Provides sector group protect function to prevent program or erase operation in the protected sector group - Provides chip unprotect function to allow code changes - Provides temporary sector group unprotect function for code changes in previously protected sector groups • Sector Permanent Lock - A unique lock bit feature allows the content to be permanently locked (Please contact Macronix sales for specific information regarding this permanent lock feature) • Secured Silicon Sector - Provides a 128-word OTP area for permanent, secure identification - Can be programmed and locked at factory or by customer SOFTWARE FEATURES • Support Common Flash Interface (CFI) - Flash device parameters stored on the device and provide the host system to access. • Program Suspend/Program Resume - Suspend program operation to read other sectors • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data/program other sectors PACKAGE • 56-pin TSOP GENERAL DESCRIPTION The MX29LA129M H/L is a 128-mega bit Flash memory organized as 16M bytes of 8 bits or 8M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LA129M H/L is packaged in 56-pin TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LA129M H/L offers access time as fast as 90ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LA129M H/L has separate chip enable (CEx) and output enable (OE#) controls. MXIC's Flash memories augment EPROM functionality P/N:PM1171 REV. 1.0, FEB. 27, 2006 1 MX29LA129M H/L with in-circuit electrical erasure and programming. The MX29LA129M H/L uses a command register to manage this functionality. AUTOMATIC SECTOR ERASE The MX29LA129M H/L is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29LA129M H/L uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V. AUTOMATIC PROGRAMMING The MX29LA129M H/L is byte/word/page programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# . AUTOMATIC PROGRAMMING ALGORITHM MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29LA129M H/L electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA# polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 50 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. P/N:PM1171 REV. 1.0, FEB. 27, 2006 2 MX29LA129M H/L PIN CONFIGURATION PIN DESCRIPTION 56 TSOP A22 CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 WP#/ACC RESET# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NC WE# OE# RY/BY# Q15 Q7 Q14 Q6 GND Q13 Q5 Q12 Q4 VI/O GND Q11 Q3 Q10 Q2 VCC Q9 Q1 Q8 Q0 A0 BYTE# A23 CE2 SYMBOL PIN NAME A0 Byte-Select Address A1~A23 Address Input Q0~Q15 Data Inputs/Outputs CE0~CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input RESET# Hardware Reset Pin, Active Low WP#/ACC Hardware Write Protect/Programming Acceleration input RY/BY# Read/Busy Output BYTE# Selects 8 bit or 16 bit mode VCC +3.0V single power supply VI/O Output Buffer Power (2.7V~3.6V this input should be tied directly to VCC ) LOGIC SYMBOL Device Ground NC Pin Not Connected Internally Chip Enable Truth Table 24 A0-A23 GND 16 or 8 Q0-Q15 CE2 CE1 CE0 DEVICE VIL VIL VIL Enabled VIL VIL VIH Disabled VIL VIH VIL Disabled VIL VIH VIH Disabled CEx VIH VIL VIL Enabled OE# VIH VIL VIH Enabled WE# VIH VIH VIL Enabled VIH VIH VIH Disabled RESET# RY/BY# WP#/ACC Note: For Single-chip applications, CE2 and CE1 can be strapped to GND. BYTE# VI/O P/N:PM1171 REV. 1.0, FEB. 27, 2006 3 MX29LA129M H/L BLOCK DIAGRAM CEx OE# WE# WP# BYTE# RESET# WRITE CONTROL LOGIC STATE HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER STATE FLASH REGISTER ARRAY ARRAY Y-DECODER AND X-DECODER ADDRESS A0-A23 PROGRAM/ERASE INPUT Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15 I/O BUFFER P/N:PM1171 REV. 1.0, FEB. 27, 2006 4 MX29LA129M H/L MX29LA129M H/L SECTOR ADDRESS TABLE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address A23-A16 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001110 00001111 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 00100000 00100001 00100010 00100011 00100100 00100101 00100110 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF 200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF 260000-26FFFF P/N:PM1171 (x16) Address Range 000000-007FFF 008000-00FFFF 010000-017FFF 018000-01FFFF 020000-027FFF 028000-02FFFF 030000-037FFF 038000-03FFFF 040000-047FFF 048000-04FFFF 050000-057FFF 058000-05FFFF 060000-067FFF 068000-06FFFF 070000-077FFF 078000-07FFFF 080000-087FFF 088000-08FFFF 090000-097FFF 098000-09FFFF 0A0000-0A7FFF 0A8000-0AFFFF 0B0000-0B7FFF 0B8000-0BFFFF 0C0000-0C7FFF 0C8000-0CFFFF 0D0000-0D7FFF 0D8000-0DFFFF 0E0000-0E7FFF 0E8000-0EFFFF 0F0000-0F7FFF 0F8000-0FFFFF 100000-107FFF 108000-10FFFF 110000-117FFF 118000-11FFFF 120000-127FFF 128000-12FFFF 130000-137FFF REV. 1.0, FEB. 27, 2006 5 MX29LA129M H/L Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 Sector Address A23-A16 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 01000000 01000001 01000010 01000011 01000100 01000101 01000110 01000111 01001000 01001001 01001010 01001011 01001100 01001101 01001110 01001111 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 270000-27FFFF 280000-28FFFF 290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3FFFFF 400000-40FFFF 410000-41FFFF 420000-42FFFF 430000-43FFFF 440000-44FFFF 450000-45FFFF 460000-46FFFF 470000-47FFFF 480000-48FFFF 490000-49FFFF 4A0000-4AFFFF 4B0000-4BFFFF 4C0000-4CFFFF 4D0000-4DFFFF 4E0000-4EFFFF 4F0000-4FFFFF P/N:PM1171 (x16) Address Range 138000-13FFFF 140000-147FFF 148000-14FFFF 150000-157FFF 158000-15FFFF 160000-167FFF 168000-16FFFF 170000-177FFF 178000-17FFFF 180000-187FFF 188000-18FFFF 190000-197FFF 198000-19FFFF 1A0000-1A7FFF 1A8000-1AFFFF 1B0000-1B7FFF 1B8000-1BFFFF 1C0000-1C7FFF 1C8000-1CFFFF 1D0000-1D7FFF 1D8000-1DFFFF 1E0000-1E7FFF 1E8000-1EFFFF 1F0000-1F7FFF 1F8000-1FFFFF 200000-207FFF 208000-20FFFF 210000-217FFF 218000-21FFFF 220000-227FFF 228000-22FFFF 230000-237FFF 238000-23FFFF 240000-247FFF 248000-24FFFF 250000-257FFF 258000-25FFFF 260000-267FFF 268000-26FFFF 270000-277FFF 278000-27FFFF REV. 1.0, FEB. 27, 2006 6 MX29LA129M H/L Sector SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 Sector Address A23-A16 01010000 01010001 01010010 01010011 01010100 01010101 01010110 01010111 01011000 01011001 01011010 01011011 01011100 01011101 01011110 01011111 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 01101100 01101101 01101110 01101111 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 500000-50FFFF 510000-51FFFF 520000-52FFFF 530000-53FFFF 540000-54FFFF 550000-55FFFF 560000-56FFFF 570000-57FFFF 580000-58FFFF 590000-59FFFF 5A0000-5AFFFF 5B0000-5BFFFF 5C0000-5CFFFF 5D0000-5DFFFF 5E0000-5EFFFF 5F0000-5FFFFF 600000-60FFFF 610000-61FFFF 620000-62FFFF 630000-63FFFF 640000-64FFFF 650000-65FFFF 660000-66FFFF 670000-67FFFF 680000-68FFFF 690000-69FFFF 6A0000-6AFFFF 6B0000-6BFFFF 6C0000-6CFFFF 6D0000-6DFFFF 6E0000-6EFFFF 6F0000-6FFFFF 700000-70FFFF 710000-71FFFF 720000-72FFFF 730000-73FFFF 740000-74FFFF 750000-75FFFF 760000-76FFFF 770000-77FFFF 780000-78FFFF P/N:PM1171 (x16) Address Range 280000-287FFF 288000-28FFFF 290000-297FFF 298000-29FFFF 2A0000-2A7FFF 2A8000-2AFFFF 2B0000-2B7FFF 2B8000-2BFFFF 2C0000-2C7FFF 2C8000-2CFFFF 2D0000-2D7FFF 2D8000-2DFFFF 2E0000-2E7FFF 2E8000-2EFFFF 2F0000-2F7FFF 2F8000-2FFFFF 300000-307FFF 308000-30FFFF 310000-317FFF 318000-31FFFF 320000-327FFF 328000-32FFFF 330000-337FFF 338000-33FFFF 340000-347FFF 348000-34FFFF 350000-357FFF 358000-35FFFF 360000-367FFF 368000-36FFFF 370000-377FFF 378000-37FFFF 380000-387FFF 388000-38FFFF 390000-397FFF 398000-39FFFF 3A0000-3A7FFF 3A8000-3AFFFF 3B0000-3B7FFF 3B8000-3BFFFF 3C0000-3C7FFF REV. 1.0, FEB. 27, 2006 7 MX29LA129M H/L Sector SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 Sector Address A23-A16 01111001 01111010 01111011 01111100 01111101 01111110 01111111 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111 10010000 10010001 10010010 10010011 10010100 10010101 10010110 10010111 10011000 10011001 10011010 10011011 10011100 10011101 10011110 10011111 10100000 10100001 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 790000-79FFFF 7A0000-7AFFFF 7B0000-7BFFFF 7C0000-7CFFFF 7D0000-7DFFFF 7E0000-7EFFFF 7F0000-7FFFFF 800000-80FFFF 810000-81FFFF 820000-82FFFF 830000-83FFFF 840000-84FFFF 850000-85FFFF 860000-86FFFF 870000-87FFFF 880000-88FFFF 890000-89FFFF 8A0000-8AFFFF 8B0000-8BFFFF 8C0000-8CFFFF 8D0000-8DFFFF 8E0000-8EFFFF 8F0000-8FFFFF 900000-90FFFF 910000-91FFFF 920000-92FFFF 930000-93FFFF 940000-94FFFF 950000-95FFFF 960000-96FFFF 970000-97FFFF 980000-98FFFF 990000-99FFFF 9A0000-9AFFFF 9B0000-9BFFFF 9C0000-9CFFFF 9D0000-9DFFFF 9E0000-9EFFFF 9F0000-9FFFFF A00000-A0FFFF A10000-A1FFFF P/N:PM1171 (x16) Address Range 3C8000-3CFFFF 3D0000-3D7FFF 3D8000-3DFFFF 3E0000-3E7FFF 3E8000-3EFFFF 3F0000-3F7FFF 3F8000-3FFFFF 400000-407FFF 408000-40FFFF 410000-417FFF 418000-41FFFF 420000-427FFF 428000-42FFFF 430000-437FFF 438000-43FFFF 440000-447FFF 448000-44FFFF 450000-457FFF 458000-45FFFF 460000-467FFF 468000-46FFFF 470000-477FFF 478000-47FFFF 480000-487FFF 488000-48FFFF 490000-497FFF 498000-49FFFF 4A0000-4A7FFF 4A8000-4AFFFF 4B0000-4B7FFF 4B8000-4BFFFF 4C0000-4C7FFF 4C8000-4CFFFF 4D0000-4D7FFF 4D8000-4DFFFF 4E0000-4E7FFF 4E8000-4EFFFF 4F0000-4F7FFF 4F8000-4FFFFF 500000-507FFF 508000-50FFFF REV. 1.0, FEB. 27, 2006 8 MX29LA129M H/L Sector SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 Sector Address A23-A16 10100010 10100011 10100100 10100101 10100110 10100111 10101000 10101001 10101010 10101011 10101100 10101101 10101110 10101111 10110000 10110001 10110010 10110011 10110100 10110101 10110110 10110111 10111000 10111001 10111010 10111011 10111100 10111101 10111110 10111111 11000000 11000001 11000010 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range A20000-A2FFFF A30000-A3FFFF A40000-A4FFFF A50000-A5FFFF A60000-A6FFFF A70000-A7FFFF A80000-A8FFFF A90000-A9FFFF AA0000-AAFFFF AB0000-ABFFFF AC0000-ACFFFF AD0000-ADFFFF AE0000-AEFFFF AF0000-AFFFFF B00000-B0FFFF B10000-B1FFFF B20000-B2FFFF B30000-B3FFFF B40000-B4FFFF B50000-B5FFFF B60000-B6FFFF B70000-B7FFFF B80000-B8FFFF B90000-B9FFFF BA0000-BAFFFF BB0000-BBFFFF BC0000-BCFFFF BD0000-BDFFFF BE0000-BEFFFF BF0000-BFFFFF C00000-C0FFFF C10000-C1FFFF C20000-C2FFFF C30000-C3FFFF C40000-C4FFFF C50000-C5FFFF C60000-C6FFFF C70000-C7FFFF C80000-C8FFFF C90000-C9FFFF CA0000-CAFFFF P/N:PM1171 (x16) Address Range 510000-517FFF 518000-51FFFF 520000-527FFF 528000-52FFFF 530000-537FFF 538000-53FFFF 540000-547FFF 548000-54FFFF 550000-557FFF 558000-55FFFF 560000-567FFF 568000-56FFFF 570000-577FFF 578000-57FFFF 580000-587FFF 588000-58FFFF 590000-597FFF 598000-59FFFF 5A0000-5A7FFF 5A8000-5AFFFF 5B0000-5B7FFF 5B8000-5BFFFF 5C0000-5C7FFF 5C8000-5CFFFF 5D0000-5D7FFF 5D8000-5DFFFF 5E0000-5E7FFF 5E8000-5EFFFF 5F0000-5F7FFF 5F8000-5FFFFF 600000-607FFF 608000-60FFFF 610000-617FFF 618000-61FFFF 620000-627FFF 628000-62FFFF 630000-637FFF 638000-63FFFF 640000-647FFF 648000-64FFFF 650000-657FFF REV. 1.0, FEB. 27, 2006 9 MX29LA129M H/L Sector SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 Sector Address A23-A16 11001011 11001100 11001101 11001110 11001111 11010000 11010001 11010010 11010011 11010100 11010101 11010110 11010111 11011000 11011001 11011010 11011011 11011100 11011101 11011110 11011111 11100000 11100001 11100010 11100011 11100100 11100101 11100110 11100111 11101000 11101001 11101010 11101011 11101100 11101101 11101110 11101111 11110000 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 P/N:PM1171 (x8) Address Range CB0000-CBFFFF CC0000-CCFFFF CD0000-CDFFFF CE0000-CEFFFF CF0000-CFFFFF D00000-D0FFFF D10000-D1FFFF D20000-D2FFFF D30000-D3FFFF D40000-D4FFFF D50000-D5FFFF D60000-D6FFFF D70000-D7FFFF D80000-D8FFFF D90000-D9FFFF DA0000-DAFFFF DB0000-DBFFFF DC0000-DCFFFF DD0000-DDFFFF DE0000-DEFFFF DF0000-DFFFFF E00000-E0FFFF E10000-E1FFFF E20000-E2FFFF E30000-E3FFFF E40000-E4FFFF E50000-E5FFFF E60000-E6FFFF E70000-E7FFFF E80000-E8FFFF E90000-E9FFFF EA0000-EAFFFF EB0000-EBFFFF EC0000-ECFFFF ED0000-EDFFFF EE0000-EEFFFF EF0000-EFFFFF F00000-F0FFFF (x16) Address Range 658000-65FFFF 660000-667FFF 668000-66FFFF 670000-677FFF 678000-67FFFF 680000-687FFF 688000-68FFFF 690000-697FFF 698000-69FFFF 6A0000-6A7FFF 6A8000-6AFFFF 6B0000-6B7FFF 6B8000-6BFFFF 6C0000-6C7FFF 6C8000-6CFFFF 6D0000-6D7FFF 6D8000-6DFFFF 6E0000-6E7FFF 6E8000-6EFFFF 6F0000-6F7FFF 6F8000-6FFFFF 700000-707FFF 708000-70FFFF 710000-717FFF 718000-71FFFF 720000-727FFF 728000-72FFFF 730000-737FFF 738000-73FFFF 740000-747FFF 748000-74FFFF 750000-757FFF 758000-75FFFF 760000-767FFF 768000-76FFFF 770000-777FFF 778000-77FFFF 780000-787FFF REV. 1.0, FEB. 27, 2006 10 MX29LA129M H/L Sector SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 Sector Address A23-A16 11110001 11110010 11110011 11110100 11110101 11110110 11110111 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 P/N:PM1171 (x8) Address Range F10000-F1FFFF F20000-F2FFFF F30000-F3FFFF F40000-F4FFFF F50000-F5FFFF F60000-F6FFFF F70000-F7FFFF F80000-F8FFFF F90000-F9FFFF FA0000-FAFFFF FB0000-FBFFFF FC0000-FCFFFF FD0000-FDFFFF FE0000-FEFFFF FF0000-FFFFFF (x16) Address Range 788000-78FFFF 790000-797FFF 798000-79FFFF 7A0000-7A7FFF 7A8000-7AFFFF 7B0000-7B7FFF 7B8000-7BFFFF 7C0000-7C7FFF 7C8000-7CFFFF 7D0000-7D7FFF 7D8000-7DFFFF 7E0000-7E7FFF 7E8000-7EFFFF 7F0000-7F7FFF 7F8000-7FFFFF REV. 1.0, FEB. 27, 2006 11 MX29LA129M H/L MX29LA129M H/L Sector Group Protection Address Table Sector Group SA0 SA1 SA2 SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA63 SA64-SA67 SA68-SA71 SA72-SA75 SA76-SA79 SA80-SA83 SA84-SA87 SA88-SA91 SA92-SA95 SA96-SA99 SA100-SA103 SA104-SA107 SA108-SA111 SA112-SA115 SA116-SA119 SA120-SA123 SA124-SA127 Sector Group SA128-SA131 SA132-SA135 SA136-SA139 SA140-SA143 SA144-SA147 SA148-SA151 SA152-SA155 SA156-SA159 SA160-SA163 SA164-SA167 SA168-SA171 SA172-SA175 SA176-SA179 SA180-SA183 SA184-SA187 SA188-SA191 SA192-SA195 SA196-SA199 SA200-SA203 SA204-SA207 SA208-SA211 SA202-SA215 SA206-SA219 SA220-SA223 SA224-SA227 SA228-SA231 SA232-SA235 SA236-SA239 SA240-SA243 SA244-SA247 SA248-SA251 SA252 SA253 SA254 SA255 A23-A16 00000000 00000001 00000010 00000011 000001xx 000010xx 000011xx 000100xx 000101xx 000110xx 000111xx 001000xx 001001xx 001010xx 001011xx 001100xx 001101xx 001110xx 001111xx 010000xx 010001xx 010010xx 010011xx 010100xx 010101xx 010110xx 010111xx 011000xx 011001xx 011010xx 011011xx 011100xx 011101xx 011110xx 011111xx P/N:PM1171 A23-A16 100000xx 100001xx 100010xx 100011xx 100100xx 100101xx 100110xx 100111xx 101000xx 101001xx 101010xx 101011xx 101100xx 101101xx 101110xx 101111xx 110000xx 110001xx 110010xx 110011xx 110100xx 110101xx 110110xx 110111xx 111000xx 111001xx 111010xx 111011xx 111100xx 111101xx 111110xx 11111100 11111101 11111110 11111111 REV. 1.0, FEB. 27, 2006 12 MX29LA129M H/L Table 1. BUS OPERATION (1) Q8~Q15 Operation CEx OE# WE# RE- WP# ACC Address Q0~Q7 SET# Read enable L H H X X AIN DOUT Word Byte Mode Mode DOUT Q8-Q15= High Z Write enable H L H (Note 3) X AIN (Note 4) (Note 4 (Program/Erase) Accelerated High Z enable H L H (Note 3) VHH AIN (Note 4) (Note 4) Q8-Q15= Program Standby Q8-Q15= High Z disable X X VCC± X H X High-Z High-Z High-Z 0.3V Output Disable Reset enable H H H X X X High-Z High-Z High-Z X X X L X X X High-Z High-Z High-Z H L VID H X X X X X Sector Group Protect enable (Note 2) Sector Addresses, (Note 4) A7=L,A4=L, A3=L, A2=H,A1=L Chip unprotect enable H L VID H X (Note 2) Sector Addresses, (Note 4) A7=H, A4=L, A3=L, A2=H, A1=L Temporary Sector X X X VID H X AIN (Note 4) (Note 4) High-Z Group Unprotect Legend: L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0±0.5V, VHH=12.0±0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN, DOUT=Data OUT Notes: 1. Address are A23:A1 in word mode; A23:A0 in byte mode. Sector addresses are A23:A16 in both modes. 2. The sector group protect and chip unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Chip Unprotect" section. 3. If WP#=VIL, all the sectors remain protected. If WP#=VIH, all sectors protection depends on whether they were last protected or unprotect using the method described in "Sector/ Sector Block Protection and Unprotect". 4. DIN or DOUT as required by command sequence, Data# polling or sector protect algorithm (see Figure 15). P/N:PM1171 REV. 1.0, FEB. 27, 2006 13 MX29LA129M H/L Table 2. AUTOSELECT CODES (High Voltage Method) A23 A15 Description CEx OE# WE# to to A9 A10 A16 A11 29LA129M H/L Manufacturer ID enable L H X X to A7 A8 VID X L A6 A4 to to A5 A3 X L L L Cycle 1 Cycle 2 enable L H X X VID X L X Cycle 3 Q8 to Q15 A2 A1 Word Byte Mode Mode L 00 X C2h L H 22 X 7Eh H H L 22 X 12h H H H 22 X 00h Sector Group Protection Q7 to Q0 01h (protected), enable L H SA X VID X L X L H L X X Verification 00h (unprotected) Secured Silicon 98h Sector Indicator (factory locked), Bit (Q7), WP# enable L H X X VID X L X L H H X X protects highest 18h address sector (not factory locked) Secured Silicon 88h Sector Indicator (factory locked), Bit (Q7), WP# enable L H X X VID X L X L H H X X protects lowest 08h address sector (not factory locked) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. P/N:PM1171 REV. 1.0, FEB. 27, 2006 14 MX29LA129M H/L consists of the address bits required to uniquely select a sector. The Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CEx and OE# pins to VIL. CEx is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. After the system writes the Automatic Select command sequence, the device enters the Automatic Select mode. The system can then read Automatic Select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Automatic Select Mode and Automatic Select Command Sequence section for more information. PAGE MODE READ ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. The MX29LA129M H/L offers "fast page mode read" function. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A1~A2(Word Mode)/ A0~A2(Byte Mode) This is an asynchronous operation; the microprocessor supplies the specific word location. WRITE BUFFER Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See "Write Buffer" for more information. The system performance could be enhanced by initiating 1 normal read and 3 fast page read (for word mode A1A2) or 7 fast page read (for byte mode A0~A2). When CEx is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses. WRITING COMMANDS/COMMAND QUENCES ACCELERATED PROGRAM OPERATION The device offers accelerated program operations through the ACC function. This is one of two functions provided by the ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. SE- If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. To program data to the device or erase sectors of memory, the system must drive WE# and CEx to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. Table indicates the address space that each sector occupies. A "sector address" P/N:PM1171 REV. 1.0, FEB. 27, 2006 15 MX29LA129M H/L but not within VSS±0.3V, the standby current will be greater. STANDBY MODE When using both pins of CEx and RESET#, the device enter CMOS Standby with both pins held at VCC ± 0.3V. If CEx and RESET# are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, VCC active current (ICC2) is required even CEx = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data. The RESET# pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. AUTOMATIC SLEEP MODE The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when address remain stable for tACC+30ns. The automatic sleep mode is independent of the CEx, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. Refer to the AC Characteristics tables for RESET# parameters and to Figure 3 for the timing diagram. SECTOR GROUP PROTECT OPERATION The MX29LA129M H/L features hardware sector group protection. This feature will disable both program and erase operations for these sector group protected. In this device, a sector group consists of four adjacent sectors which are protected or unprotected at the same time. To activate this mode, the programming equipment must force VID on address pin A10 and control pin OE#, (suggest VID = 12V) A7 = VIL and CEx = VIL. (see Table 2) Programming of the protection circuitry begins on the falling edge of the WE# pulse and is terminated on the rising edge. Please refer to sector group protect algorithm and waveform. OUTPUT DISABLE With the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. RESET# OPERATION MX29LA129M H/L also provides another method. Which requires VID on the RESET# only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity To verify programming of the protection circuitry, the programming equipment must force VID on address pin A10 ( with CEx and OE# at VIL and WE# at VIH). When A2=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A2, are don't care. Address locations with A2 = VIL are reserved to read manufacturer and device codes. (Read Silicon ID) Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL P/N:PM1171 REV. 1.0, FEB. 27, 2006 16 MX29LA129M H/L last protected or unprotect using the method described in "Sector/Sector Group Protection and Chip Unprotect". It is also possible to determine if the group is protected in the system by writing a Read Silicon ID command. Performing a read operation with A2=VIH, it will produce a logical "1" at Q0 for the protected sector. Note that the WP# pin must not be left floating or unconnected; inconsistent behavior of the device may result. CHIP UNPROTECT OPERATION TEMPORARY SECTOR GROUP UNPROTECT OPERATION The MX29LA129M H/L also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. This feature allows temporary unprotect of previously protected sector to change data in-system. The Temporary Sector Unprotect mode is activated by setting the RESET# pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased as unprotect sector. Once VID is remove from the RESET# pin, all the previously protected sectors are protected again. To activate this mode, the programming equipment must force VID on control pin OE# and address pin A10. The CEx pins must be set at VIL. Pins A7 must be set to VIH. (see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotect mechanism begins on the falling edge of the WE# pulse and is terminated on the rising edge. SILICON ID READ OPERATION MX29LA129M H/L also provides another method. Which requires VID on the RESET# only. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A10 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. It is also possible to determine if the chip is unprotect in the system by writing the Read Silicon ID command. Performing a read operation with A2=VIH, it will produce 00H at data outputs (Q0-Q7) for an unprotect sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed. MX29LA129M H/L provides hardware method to access the silicon ID read operation. Which method requires VID on A10 pin, VIL on CEx, OE#, A7, and A2 pins. Which apply VIL on A1 pin, the device will output MXIC's manufacture code of which apply VIH on A1 pin, the device will output MX29LA129M H/L device code. WRITE PROTECT (WP#) The write protect function provides a hardware method to protect all sectors without using VID. VERIFY SECTOR GROUP PROTECT STATUS OPERATION If the system asserts VIL on the WP# pin, the device disables program and erase functions in all sectors independently of whether those sectors were protected or unprotect using the method described in Sector/Sector Group Protection and Chip Unprotect". MX29LA129M H/L provides hardware method for sector group protect status verify. Which method requires VID on A10 pin, VIH on WE# and A2 pins, VIL on CEx, OE#, A7, and A1 pins, and sector address on A16 to A23 pins. Which the identified sector is protected, the device will output 01H. Which the identified sector is not protect, the device will output 00H. If the system asserts VIH on the WP# pin, the device reverts to whether the sectors were last set to be protected or unprotect. That is, sector protection or unprotection for the sectors depends on whether they were P/N:PM1171 REV. 1.0, FEB. 27, 2006 17 MX29LA129M H/L of main sectors is as normally. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending command to sector SA0. DATA PROTECTION The MX29LA129M H/L is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. Secured Silicon ESN factory Customer Sector address locked lockable 000000h-000007h ESN Determined by 000008h-00007Fh Unavailable Customer range SECURED SILICON SECTOR The MX29LA129M H/L features a OTP memory region where the system may access through a command sequence to create a permanent part identification as so called Electronic Serial Number (ESN) in the device. Once this region is programmed, any further modification on the region is impossible. The secured silicon sector is a 128 words in length, and uses a Secured Silicon Sector Indicator Bit (Q7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevent duplication of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. FACTORY LOCKED:Secured Silicon Sector Programmed and Protected At the Factory In device with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. A factory locked device has an 8-word random ESN at address 000000h-000007h. CUSTOMER LOCKABLE:Secured Silicon Sector NOT Programmed or Protected At the Factory The MX29LA129M H/L offers the device with Secured Silicon Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory , and has the Secured Silicon Sector Indicator Bit permanently set to a "1". The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to utilize that sector in any form they prefer. The customer-lockable version has the secured sector Indicator Bit permanently set to a "0". Therefore, the Secured Silicon Sector Indicator Bit prevents customer, lockable device from being used to replace devices that are factory locked. As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-word Secured Silicon Sector. Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotected the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. The Secured Silicon Sector area can be protected using one of the following procedures: The system access the Secured Silicon Sector through a command sequence (refer to "Enter Secured Silicon/ Exit Secured Silicon Sector command Sequence). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the address normally occupied by the first sector SA0. Once entry the Secured Silicon Sector the operation of boot sectors is disabled but the operation Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 15, except that RESET# may be at either VIH or VID. This allows insystem protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that method is only applicable to the Secured Silicon Sector. P/N:PM1171 REV. 1.0, FEB. 27, 2006 18 MX29LA129M H/L Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then alternate method of sector protection described in the :Sector Group Protection and Unprotect" section. POWER SUPPLY DE COUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND. Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. LOW VCC WRITE INHIBIT When VCC is less than VLKO the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional write when VCC is greater than VLKO. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns (typical) on CEx or WE# will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE# = VIL, CEx = VIH or WE# = VIH. To initiate a write cycle CEx and WE# must be a logical zero while OE# is a logical one. POWER-UP SEQUENCE The MX29LA129M H/L powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. POWER-UP WRITE INHIBIT If WE#=CEx=VIL and OE#=VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. P/N:PM1171 REV. 1.0, FEB. 27, 2006 19 MX29LA129M H/L Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device (when applicable). SOFTWARE COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 3 defines the valid register command sequences. Note that the Erase Suspend (B0H) and All addresses are latched on the falling edge of WE# or CEx, whichever happens later. All data are latched on rising edge of WE# or CEx, whichever happens first. TABLE 3. MX29LA129M H/L COMMAND DEFINITIONS First Bus Command Bus Cycle Second Bus Third Bus Cycle Cycles Addr Data Addr Read (Note 5) 1 RA RD Reset (Note 6) 1 XXX F0 Fourth Bus Cycle Cycle Data Addr Data Addr Data Fifth Bus Sixth Bus Cycle Cycle Addr Data Addr Data Automatic Select (Note 7) Manufacturer ID Word 4 555 AA 2AA 55 555 90 X00 C2H Byte 4 AAA AA 555 55 AAA 90 X00 C2H Device ID Word 4 555 AA 2AA 55 555 90 X01 ID1 X0E ID2 X0F ID3 (Note 8) Byte 4 AAA AA 555 55 AAA 90 X02 ID1 X1C ID2 X1E ID3 Secured Sector Fact- Word 4 555 AA 2AA 55 555 90 X03 see ory Protect (Note 9) Byte 4 AAA AA 555 55 AAA 90 X06 note 9 Sector Group Protect Word 4 555 AA 2AA 55 555 90 (SA)X02 XX00/ Verify (Note 10) Byte 4 AAA AA 555 55 AAA 90 (SA)X04 XX01 Enter Secured Silicon Word 3 555 AA 2AA 55 555 Sector Byte 3 AAA AA 555 55 AAA 88 88 Exit Secured Silicon Word 4 555 AA 2AA 55 555 90 XXX 00 Sector Byte 4 AAA AA 555 55 AAA 90 XXX 00 Program Word 4 555 AA 2AA 55 555 A0 PA PD Byte 4 AAA AA 555 55 AAA A0 PA PD Word 6 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD Byte 6 AAA AA 555 55 SA 25 SA BC PA PD WBL PD F0 Write to Buffer (Note 11) Program Buffer to Flash Word 1 SA 29 Byte 1 SA 29 Write to Buffer Abort Word 3 555 AA 2AA 55 555 Reset (Note 12) Byte 3 AAA AA 555 55 AAA F0 Chip Erase Sector Erase Word 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Word 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30 Program/Erase Suspend (Note 13) 1 XXX B0 Program/Erase Resume (Note 14) 1 XXX 30 CFI Query (Note 15) Word 1 55 98 Byte 1 AA 98 P/N:PM1171 REV. 1.0, FEB. 27, 2006 20 MX29LA129M H/L Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CEx pulse, whichever happen later. DDI=Data of device identifier C2H for manufacture code PD=Data to be programmed at location PA. Data is latched on the rising edge of WE# or CEx pulse. SA=Address of the sector to be erase or verified (in autoselect mode). Address bits A23-A16 uniquely select any sector. WBL=Write Buffer Location. Address must be within the same write buffer page as PA. WC=Word Count. Number of write buffer locations to load minus 1. BC=Byte Count. Number of write buffer locations to load minus 1. Notes: 1. See Table 1 for descriptions of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or automatic select data, all bus cycles are write operation. 4. Address bits are don't care for unlock and command cycles, except when PA or SA is required. 5. No unlock or command cycles required when device is in read mode. 6. The Reset command is required to return to the read mode when the device is in the automatic select mode or if Q5 goes high. 7. The fourth cycle of the automatic select command sequence is a read cycle. 8. The device ID must be read in three cycles. The data is 01h for top boot and 00h for bottom boot. 9. If WP# protects the highest address sectors, the data is 98h for factory locked and 18h for not factory locked. If WP# protects the lowest address sectors, the data is 88h for factory locked and 08h for not factor locked. 10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 21(Word Mode) / 37(Byte Mode). 12. Command sequence resets device for next command after aborted write-to-buffer operation. 13. The system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in the erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 14. The Erase Resume command is valid only during the Erase Suspend mode. 15. Command is valid when device is ready to read array data or when device is in automatic select mode. P/N:PM1171 REV. 1.0, FEB. 27, 2006 21 MX29LA129M H/L array data (also applies during Erase Suspend). READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. SILICON ID READ COMMAND SEQUENCE The SILICON ID READ command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 2 shows the address and data requirements. This method is an alternative to that shown in Table 1, which is intended for PROM programmers and requires VID on address bit A10. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if Q5 goes high, or while in the automatic select mode. See the "Reset Command" section, next. The SILICON ID READ command sequence is initiated by writing two unlock cycles, followed by the SILICON ID READ command. The device then enters the SILICON ID READ mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table for valid sector addresses. RESET COMMAND Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The system must write the reset command to exit the automatic select mode and return to reading array data. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. BYTE/WORD PROGRAM COMMAND SEQUENCE The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 3 shows the address and data requirements for the byte program command sequence. The reset command may be written between the sequence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset command must be written to return to reading array data (also applies to SILICON ID READ during Erase Suspend). When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/ BY#. See "Write Operation Status" for information on these status bits. If Q5 goes high during a program or erase operation, writing the reset command returns the device to reading Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hard- P/N:PM1171 REV. 1.0, FEB. 27, 2006 22 MX29LA129M H/L multiple times, the address/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. ware reset immediately terminates the programming operation. The Byte/Word Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. Q7, Q6, Q5, and Q1 should be monitored to determine the device status during Write Buffer Programming. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: • Load a value that is greater than the page buffer size during the Number of Locations to Program step. • Write to an address in a sector different than the one specified during the Write-Buffer-Load command. • Write an Address/Data pair to a different write-bufferpage than the one selected by the Starting Address during the write buffer data loading stage of the operation. • Write data other than the Confirm Command after the specified number of data load cycles. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX-4. All subsequent address/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The abort condition is indicated by Q1 = 1, Q7 = DATA# (for the last address location loaded), Q6 = toggle, and Q5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend com- Note that if a Write Buffer address location is loaded P/N:PM1171 REV. 1.0, FEB. 27, 2006 23 MX29LA129M H/L mand is written during a programming process, the device halts the program operation within 15us maximum (5 us typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. AUTOMATIC CHIP/SECTOR ERASE COMMAND The device does not require the system to preprogram prior to erase. The Automatic Erase algorithm automatically pre-program and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 3 shows the address and data requirements for the chip erase command sequence. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. Any commands written to the chip during the Automatic Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. The system can determine the status of the erase operation by using Q7, Q6, Q2, or RY/BY#. See "Write Operation Status" for information on these status bits. When the Automatic Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. See Write Operation Status for more information. Figure 10 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 9 for timing diagrams. SETUP AUTOMATIC CHIP/SECTOR ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H, or the sector erase command 30H. The MX29LA129M H/L contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A2=VIL,A1=VIL retrieves the manufacturer code. A read cycle with A2=VIL, A1=VIH returns the device code. P/N:PM1171 REV. 1.0, FEB. 27, 2006 24 MX29LA129M H/L device requires a maximum 20us to suspend the sector erase operation. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Erase Resume, program data to, or read data from any sector not selected for erasure. SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended blocks. ERASE RESUME When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE# or CEx, whichever happens later , while the command (data) is latched on the rising edge of WE# or CEx, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE# or CEx, whichever happens later. Each successive sector load cycle started by the falling edge of WE# or CEx, whichever happens later must begin within 50us from the rising edge of the preceding WE# or CEx, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode. This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. ERASE SUSPEND This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is issued during the sector erase operation, the P/N:PM1171 REV. 1.0, FEB. 27, 2006 25 MX29LA129M H/L The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Read ID mode; however, it is ignored otherwise. QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29LA129M H/L is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table 4. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or read ID mode. The command is valid only when the device is in the CFI mode. Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code (none) Address for secondary algorithm extended query table (none) Address h Address h (x16) (x8) 10 20 11 22 12 24 13 26 14 28 15 2A 16 2C 17 2E 18 30 19 32 1A 34 Data h Address h Address h (x16) (x8) 1B 36 1C 38 1D 3A 1E 3C 1F 3E 20 40 21 42 22 44 23 46 24 48 25 4A 26 4C Data h 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000 Table 4-2. CFI Mode: System Interface Data Values Description VCC supply, minimum (2.7V) VCC supply, maximum (3.6V) VPP supply, minimum (none) VPP supply, maximum (none) Typical timeout for single word/byte write (2N us) Typical timeout for maximum size buffer write (2N us) Typical timeout for individual block erase (2N ms) Typical timeout for full chip erase (2N ms) Maximum timeout for single word/byte write times (2N X Typ) Maximum timeout for maximum size buffer write times (2N X Typ) Maximum timeout for individual block erase times (2N X Typ) Maximum timeout for full chip erase times (not supported) P/N:PM1171 0027 0036 0000 0000 0007 0007 000A 0000 0001 0005 0004 0000 REV. 1.0, FEB. 27, 2006 26 MX29LA129M H/L Table 4-3. CFI Mode: Device Geometry Data Values Description Address h Address h (x16) (x8) 27 4E 28 50 29 52 Device size (2n bytes) Flash device interface code Maximum number of bytes in multi-byte write = 2n Number of erase block regions Erase block region 1 information [2E,2D] = # of blocks in region -1 [30, 2F] = size in multiples of 256-bytes Erase Block Region 2 Information (refer to CFI publication 100) Erase Block Region 3 Information (refer to CFI publication 100) Erase Block Region 4 Information (refer to CFI publication 100) P/N:PM1171 2A 2B 2C 2D 2E 2F 30 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 Data h 0018 0002 0000 0005 0000 0001 00FF 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 REV. 1.0, FEB. 27, 2006 27 MX29LA129M H/L Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Address h Address h Data h (x16) (x8) 40 80 0050 41 82 0052 42 84 0049 Major version number, ASCII 43 86 0031 Minor version number, ASCII 44 88 0033 Query-unique ASCII string "PRI" Address sensitive unlock (0=required, 1= not required) 45 8A 0000 Erase suspend (2= to read and write) 46 8C 0002 Sector protect (N= # of sectors/group) 47 8E 0001 Temporary sector unprotect (1=supported) 48 90 0001 Sector protect/unprotect scheme 49 92 0004 Simultaneous R/W operation (0=not supported) 4A 94 0000 Burst mode type (0=not supported) 4B 96 0000 Page mode type (0=not supported) 4C 98 0001 ACC (Acceleration) Supply Minimum 4Dh 9A 00B5 4Eh 9C 00C5 4Fh 9E 0004/ 00h=Not Supported, D7-D4: Volt, D3-D0:100mV ACC (Acceleration) Supply Maximum 00h=Not Supported, D7-D4: Volt, D3-D0:100mV Top/Bottom Boot Sector Flag 02h=Bottom Boot Device, 03h=Top Boot Device 0005 04h=uniform sectors bottom WP# protect, 05h=uniform sectors top WP# protect Program Suspend 50h A0 0001 00h=Not Supported, 01h=Supported P/N:PM1171 REV. 1.0, FEB. 27, 2006 28 MX29LA129M H/L WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY#. Table 5 and the following subsections describe the functions of these bits. Q7, RY/BY#, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 5. Write Operation Status Status Q7 Q6 Q5 Q3 Q2 Q1 RY/BY# Byte/Word Program in Auto Program Algorithm Q7# Toggle 0 N/A No 0 0 Toggle Auto Erase Algorithm Erase Suspend Read Erase (Erase Suspended Sector) Suspended Erase Suspend Read Mode (Non-Erase Suspended Sector) Erase Suspend Program 0 Toggle 0 1 Toggle N/A 0 1 No 0 N/A Toggle N/A 1 Toggle Data Data Data Data Data Data 1 Q7# Toggle 0 N/A N/A N/A 0 Program-Suspended Read Program (Program-Suspended Sector) Suspend Program-Suspended Read Invalid (not allowed) 1 Data 1 (Non-Program-Suspended Sector) Write-to-Buffer Busy Q7# Toggle 0 N/A N/A 0 0 Abort Q7# Toggle 0 N/A N/A 1 0 Notes: 1. Q5 switches to "1" when an Word/Byte Program, Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on Q5 for more information. 2. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. Q1 switches to "1" when the device has aborted the write-to-buffer operation. P/N:PM1171 REV. 1.0, FEB. 27, 2006 29 MX29LA129M H/L happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. Q7: Data# Polling The Data# Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE# or CEx to control the read cycles. When the operation is complete, Q6 stops toggling. During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming during Erase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program address to read valid status information on Q7. If a program address falls within a protected sector, Data# Polling on Q7 is active for approximately 1 us, then the device returns to reading array data. After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles for 100us and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7. During the Automatic Erase algorithm, Data# Polling produces a "0" on Q7. When the Automatic Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on Q7. This is analogous to the complement/true datum output described for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement," or "0". The system must provide an address within any of the sectors selected for erasure to read valid status information on Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 5 shows the outputs for Toggle Bit I on Q6. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output Enable (OE#) is asserted low. Q2:Toggle Bit II Q6:Toggle BIT I The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# or CEx, whichever happens first pulse in the command sequence. Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# or CEx, whichever Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CEx to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- P/N:PM1171 REV. 1.0, FEB. 27, 2006 30 MX29LA129M H/L If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. parison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 5 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the byte/word programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. The Q5 failure condition may appear if the system tries to program a to a "1" location that is previously programmed to "0". Only an erase operation can change a "0" back to a "1". Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, Q5 produces a "1". The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Q3:Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase command sequence. Q5:Program/Erase Timing Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this condition. If Data# Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data# Polling or P/N:PM1171 REV. 1.0, FEB. 27, 2006 31 MX29LA129M H/L Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. If the time between additional erase commands from the system can be less than 50us, the system need not to monitor Q3. Q1: Write-to-Buffer Abort Q1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions Q1 produces a "1". The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer section for more details. RY/BY#:READY/BUSY OUTPUT The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC . If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. P/N:PM1171 REV. 1.0, FEB. 27, 2006 32 MX29LA129M H/L ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC Ambient Temperature with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A10, OE#, and RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Commercial (C) Devices Ambient Temperature (TA ). . . . . . . . . . . . 0° C to +70° C Industrial (I) Devices Ambient Temperature (TA ). . . . . . . . . . -40° C to +85° C VCC Supply Voltages VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V VCC for regulated voltage range. . . . . .. +3.0 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20ns. 2. Minimum DC input voltage on pins A10, OE#, and RESET# is -0.5 V. During voltage transitions, A10, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A10 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. P/N:PM1171 REV. 1.0, FEB. 27, 2006 33 MX29LA129M H/L DC CHARACTERISTICS TA=-40°° C to 85°° C, VCC=2.7V~3.6V (TA=-40°° C to 85°° C, VCC=3.0V~3.6V for 90R) Parameter Description I LI Input Load Current (Note 1) I LIT I LO A10 Input Leakage Current Output Leakage Current ICC1 VCC Initial Read Current (Notes 2,3) ICC2 VCC Intra-Page Read Current (Notes 2,3) ICC3 VCC Active Write Current (Notes 2,4,6) ICC4 VCC Standby Current (Note 2) ICC5 VCC Reset Current (Note 2) ICC6 Automatic Sleep Mode (Notes 2,5) VIL VIH VHH Input Low Voltage Input High Voltage Voltage for ACC Program Acceleration VID Voltage for Autoselect and Temporary Sector Unprotect VOL Output Low Voltage VOH1 Output High Voltage VOH2 VLKO Low VCC Lock-Out Voltage (Note 4) Test Conditions VIN = VSS to VCC , VCC = VCC max VCC=VCC max; A10 = 12.5V VOUT = VSS to VCC , VCC= VCC max CEx= VIL, 10 MHz OE# = VIH 5 MHz 1 MHz CEx= VIL , 10 MHz OE# = VIH 40 MHz CEx= VIL , OE# = VIH WE#=VIL CEx,RESET#=VCC±0.3V WP#=VIH RESET#=VSS±0.3V WP#=VIH VIL = VSS ± 0.3 V, VIH = VCC ± 0.3 V, WP#=VIH Min. Max. ±1.0 Unit uA 35 ±1.0 uA uA 35 18 5 5 10 50 50 25 20 20 40 60 mA mA mA mA mA mA 20 50 uA 20 50 uA 20 50 uA VCC = 2.7V ~ 3.6V -0.5 0.7xVCC 11.5 12.0 0.8 VCC+0.5 12.5 V V V VCC = 3.0 V ± 10% 11.5 12.0 12.5 V 0.45 V V V V IOL= 4.0mA,VCC=VCC min IOH=-2.0mA,VCC=VCC min 0.85VCC IOH=-100uA,VCC=VCC min VCC-0.4 2.3 Typ. 2.5 Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0uA. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC = 3.0V. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 6. Not 100% tested. 7. A9=12.5V when TA=0° C to 85° C, A9=12V when when TA=-40° C to 0° C. P/N:PM1171 REV. 1.0, FEB. 27, 2006 34 MX29LA129M H/L SWITCHING TEST CIRCUITS TEST SPECIFICATIONS Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 2.7K ohm DEVICE UNDER TEST 3.3V CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT All Speeds 1 TTL gate 30 Unit 5 0.0-3.0 1.5 ns V V 1.5 V pF KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State(High Z) SWITCHING TEST WAVEFORMS 3.0V 1.5V Measurement Level 1.5V 0.0V INPUT OUTPUT P/N:PM1171 REV. 1.0, FEB. 27, 2006 35 MX29LA129M H/L AC CHARACTERISTICS Read-Only Operations TA=-40°° C to 85°° C, VCC=2.7V~3.6V (TA=-40°° C to 85°° C, VCC=3.0V~3.6V for 90R) Parameter Speed Options Std. Description Test Setup 90R 100 Unit tRC Read Cycle Time (Note 1) Min 90 100 ns tACC Address to Output Delay CEx, OE#=VIL Max 90 100 ns tCE Chip Enable to Output Delay OE#=VIL Max 90 100 ns tPACC Page Access Time Max 25 ns tOE Output Enable to Output Delay Max 35 ns tDF Chip Enable to Output High Z (Note 1) Max 16 ns tDF Output Enable to Output High Z (Note 1) Max 16 ns tOH Output Hold Time From Address, CEx Min 0 ns Read Min 35 ns Output Enable Hold Time Toggle and Min 10 ns (Note 1) Data# Polling or OE#, whichever Occurs First tOEH Notes: 1. Not 100% tested. 2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE for test specifications. P/N:PM1171 REV. 1.0, FEB. 27, 2006 36 MX29LA129M H/L Figure 1. READ TIMING WAVEFORMS tRC VIH ADD Valid Addresses VIL tCE Disable CEx tRH Enable tRH VIH WE# VIL tDF tOE tOEH VIH OE# VIL VOH Outputs tOH tACC HIGH Z HIGH Z DATA Valid VOL VIH RESET# VIL RY/BY# 0V Figure 2. PAGE READ TIMING WAVEFORMS Same Page A3-A23 (A0), A1~A2 tACC Disable CEx Enable tPACC Output tPACC tPACC OE# Qa Qb P/N:PM1171 Qc Qd REV. 1.0, FEB. 27, 2006 37 MX29LA129M H/L AC CHARACTERISTICS Parameter Description Test Setup All Speed Options Unit tREADY1 RESET# PIN Low (During Automatic Algorithms) MAX 20 us MAX 500 ns to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns tRH RESET# High Time Before Read (See Note) MIN 50 ns tRB RY/BY# Recovery Time(to CEx, OE# go low) MIN 0 ns tRPD RESET# Low to Standby Mode MIN 20 us Note:Not 100% tested Figure 3. RESET# TIMING WAVEFORM RY/BY# CEx, OE# tRH RESET# tRP tReady2 Reset Timing NOT during Automatic Algorithms tReady1 RY/BY# tRB CEx, OE# RESET# tRP Reset Timing during Automatic Algorithms P/N:PM1171 REV. 1.0, FEB. 27, 2006 38 MX29LA129M H/L AC CHARACTERISTICS Erase and Program Operations Parameter Std. tWC tAS tASO tAH tAHT tDS tDH tCEPH tOEPH tGHWL tGHEL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tBUSY tVHH tPOLL TA=-40°° C to 85°° C, VCC=2.7V~3.6V (TA=-40°° C to 85°° C, VCC=3.0V~3.6V for 90R) Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CEx or OE# high during toggle bit polling Data Setup Time Data Hold Time CEx High During Toggle Bit Polling Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) Read Recovery Time Before Write CEx Setup Time CEx Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Notes 2,3) Single Word/Byte Program Byte Operation (Notes 2,5) Word Accelerated Single Word/Byte Byte Programming Operation (Notes 2,5) Word Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay VHH Rise and Fall Time (Note 1) Program Valid Before Status Polling (Note 6) Min Min Min Min Min Speed Options 90R 100 90 100 0 15 45 0 Unit ns ns ns ns ns Min Min Min Min Min 35 0 20 20 0 ns ns ns ns ns Min Min Min Min Min Typ Typ Typ Typ Typ Typ Min Min Min Min Max 0 0 0 35 30 240 60 60 54 54 0.5 50 0 ns ns ns ns ns us us us us us sec us ns ns ns us 90 100 250 4 Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-16 words/1-32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. P/N:PM1171 REV. 1.0, FEB. 27, 2006 39 MX29LA129M H/L ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC PROGRAM TIMING WAVEFORMS Program Command Sequence(last two cycle) tWC XXXh Address Read Status Data (last two cycle) tAS PA PA PA tAH Disable CEx Enable tCH OE# tWP WE# tWHWH1 tCS tWPH tDS tDH A0h Status PD DOUT Data tBUSY tRB RY/BY# tVCS VCC Note : 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address Figure 5. ACCELERATED PROGRAM TIMING DIAGRAM VHH ACC VIL or VIH VIL or VIH tVHH tVHH P/N:PM1171 REV. 1.0, FEB. 27, 2006 40 MX29LA129M H/L Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system Increment Address No Verify Word Ok ? YES No Last Address ? YES Auto Program Completed P/N:PM1171 REV. 1.0, FEB. 27, 2006 41 MX29LA129M H/L Figure 7. WRITE BUFFER PROGRAMMING ALGORITHM FLOWCHART Write "Write to Buffer" command and Sector Address Write number of addresses to program minus 1(WC) and Sector Address Part of "Write to Buffer" Command Sequence Write first address/data Yes WC = 0 ? No Abort Write to Buffer Operation ? Yes Write to a different sector address No Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write next address/data pair (Note 1) WC = WC - 1 Write program buffer to flash sector address Notes: 1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. Q7 may change simultaneously with Q5. Therefore, Q7 should be verified. 3. If this flowchart location was reached because Q5= "1" then the device FAILED. If this flowchart location was reached because Q1="1", then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If Q1=1, write the Write-Buffer-Programming-Abort-Reset command. If Q5=1, write the Reset command. 4. See Table 3 for command sequences required for write buffer programming. Read Q7~Q0 at Last Loaded Address Yes Q7 = Data ? No No No Q5 = 1 ? Q1 = 1 ? Yes Yes Read Q7~Q0 with address = Last Loaded Address (Note 2) Q7 and Q15 = Data ? Yes No (Note 3) FAIL or ABORT PASS P/N:PM1171 REV. 1.0, FEB. 27, 2006 42 MX29LA129M H/L Figure 8. PROGRAM SUSPEND/RESUME FLOWCHART Program Operation or Write-to-Buffer Sequence in Progress Write address/data XXXh/B0h Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations Wait 15us Autoselect and Secured Sector read operations are also allowed Data cannot be read from erase-or program-suspended sectors Read data as required No Done reading ? Yes Write address/data XXXh/30h Write Program Resume Command Sequence Device reverts to operation prior to Program Suspend P/N:PM1171 REV. 1.0, FEB. 27, 2006 43 MX29LA129M H/L Figure 9. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM Erase Command Sequence(last two cycle) tWC 2AAh Address Read Status Data tAS VA SA 555h for chip erase VA tAH Disable CEx Enable tCH OE# tWHWH2 tWP WE# tCS tWPH tDS tDH 55h Data In Progress Complete 30h 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Note : 1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1171 REV. 1.0, FEB. 27, 2006 44 MX29LA129M H/L Figure 10. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data Poll from system YES No DATA = FFh ? YES Auto Erase Completed P/N:PM1171 REV. 1.0, FEB. 27, 2006 45 MX29LA129M H/L Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address NO Last Sector to Erase ? YES Data Poll from System NO Data=FFh? YES Auto Sector Erase Completed P/N:PM1171 REV. 1.0, FEB. 27, 2006 46 MX29LA129M H/L Figure 12. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H NO ERASE SUSPEND Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1171 REV. 1.0, FEB. 27, 2006 47 MX29LA129M H/L AC CHARACTERISTICS Alternate CEx Controlled Erase and Program Operations TA=-40°° C to 85°° C, VCC=2.7V~3.6V (TA=-40°° C to 85°° C, VCC=3.0V~3.6V for 90R) Parameter Speed Options Std. Description tWC Write Cycle Time (Note 1) Min tAS Address Setup Time Min 0 ns tAH Address Hold Time Min 45 ns tDS Data Setup Time Min 35 ns tDH Data Hold Time Min 0 ns Read Recovery Time Before Write Min 0 ns Min 0 ns tGHEL 90R 100 Unit 90 100 ns (OE# High to WE# Low) tWS WE# Setup Time tWH WE# Hold Time Min 0 ns tCP CEx Pulse Width Min 35 ns tCPH CEx Pulse Width High Min 25 ns Write Buffer Program Operation (Notes 2,3) tWHWH1 Typ 240 us Single Word/Byte Program Byte Typ 60 us Operation (Notes 2,5) Word Typ 60 us Accelerated Single Word/Byte Byte Typ 54 us Programming Operation (Notes 2,5) Word Typ 54 us Typ 0.5 sec tWHWH2 Sector Erase Operation (Note 2) tRH RESET HIGH Time Before Write (Note 1) Min 50 ns tPOLL Program Valid Before Status Polling (Note 6) Max 4 us Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-16 words/1-32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. P/N:PM1171 REV. 1.0, FEB. 27, 2006 48 MX29LA129M H/L Figure 13. CEx CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Address PA tWC tAS tAH tWH WE# tGHEL OE# tCP tWHWH1 or 2 Disable CEx tWS Enable tCPH tDS tBUSY tDH Q7 Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence. P/N:PM1171 REV. 1.0, FEB. 27, 2006 49 MX29LA129M H/L SECTOR GROUP PROTECT/CHIP UNPROTECT Figure 14. Sector Group Protect / Chip Unprotect Waveform (RESET# Control) VID VIH RESET# SA, A6 A1, A0 Valid* Valid* Sector Group Protect or Chip Unprotect Data 60h 1us 60h Valid* Verify 40h Status Sector Group Protect:150us Chip Unprotect:15ms Disable CEx Enable WE# OE# Note: For sector group protect A7=0, A2=1, A1=0. For chip unprotect A7=1, A2=1, A1=0 P/N:PM1171 REV. 1.0, FEB. 27, 2006 50 MX29LA129M H/L Figure 15. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH RESET#=VID START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT=1 RESET#=VID Wait 1us PLSCNT=1 RESET#=VID Wait 1us Temporary Sector Unprotect Mode No First Write Cycle=60h? First Write No Cycle=60h? Temporary Sector Unprotect Mode Yes Yes Set up sector address No Sector Protect: Write 60h to sector address with A7=0, A2=1, A1=0 All sectors protected? Yes Set up first sector address Wait 150us Verify Sector Protect: Write 40h to sector address with A7=0, A2=1, A1=0 Sector Unprotect: Write 60h to sector address with A7=1, A2=1, A1=0 Reset PLSCNT=1 Increment PLSCNT Wait 15 ms Read from sector address with A7=0, A2=1, A1=0 Verify Sector Unprotect: Write 40h to sector address with A7=1, A2=1, A1=0 No Increment PLSCNT No PLSCNT=25? Yes Data=01h? Read from sector address with A7=1, A2=1, A1=0 Yes No Device failed Protect another No sector? Sector Protect Algorithm Reset PLSCNT=1 Yes PLSCNT=1000? Data=00h? No Yes Remove VID from RESET# Yes Device failed Last sector Write reset command No verified? Chip Unprotect Algorithm Sector Protect complete Yes Remove VID from RESET# Write reset command Sector Unprotect complete P/N:PM1171 REV. 1.0, FEB. 27, 2006 51 MX29LA129M H/L AC CHARACTERISTICS Parameter Description Test Setup All Speed Options Unit tVLHT Voltage transition time Min. 4 us tWPP1 Write pulse width for sector group protect Min. 100 ns tOESP OE# setup time to WE# active Min. 4 us Figure 16. SECTOR GROUP PROTECT TIMING WAVEFORM (A10, OE# Control) A2 A7 12V 3V A10 tVLHT Verify 12V 3V OE# tVLHT tVLHT tWPP 1 WE# Disable tOESP CEx Enable Data 01H F0H tOE A23-A16 Sector Address P/N:PM1171 REV. 1.0, FEB. 27, 2006 52 MX29LA129M H/L Figure 17. SECTOR GROUP PROTECTION ALGORITHM (A10, OE# Control) START Set Up Sector Addr PLSCNT=1 OE#=VID, A10=VID, CEx=VIL A7=VIL Activate WE# Pulse Time Out 150us Set WE#=VIH, CEx=OE#=VIL A10 should remain VID Read from Sector Addr=SA, A2=1 No PLSCNT=32? No Data=01H? Yes Device Failed Protect Another Sector? Yes Remove VID from A10 Write Reset Command Sector Protection Complete P/N:PM1171 REV. 1.0, FEB. 27, 2006 53 MX29LA129M H/L Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A10, OE# Control) A2 12V 3V A10 tVLHT A7 Verify 12V 3V OE# tVLHT tVLHT tWPP 2 WE# Disable tOESP CEx Enable Data 00H F0H tOE P/N:PM1171 REV. 1.0, FEB. 27, 2006 54 MX29LA129M H/L Figure 19. CHIP UNPROTECT FLOWCHART (A10, OE# Control) START Protect All Sectors PLSCNT=1 Set OE#=A10=VID CEx=VIL, A7=1 Activate WE# Pulse Time Out 15ms Increment PLSCNT Set OE#=CEx=VIL A10=VID, A2=1 Set Up First Sector Addr Read Data from Device No Data=00H? Increment Sector Addr Yes No All sectors have No PLSCNT=1000? Yes Device Failed been verified? Yes Remove VID from A10 Write Reset Command Chip Unprotect Complete * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1171 REV. 1.0, FEB. 27, 2006 55 MX29LA129M H/L AC CHARACTERISTICS Parameter Description Test All Speed Options Unit Setup tVIDR VID Rise and Fall Time (see Note) Min 500 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 us tRRB RESET# Hold Time from RY/BY# High for Temporary Min 4 us Sector Group Unprotect Figure 20. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS 12V RESET# 0 or 3V VIL or VIH tVIDR tVIDR Program or Erase Command Sequence Disable CEx Enable WE# tRSP tRRB RY/BY# P/N:PM1171 REV. 1.0, FEB. 27, 2006 56 MX29LA129M H/L Figure 21. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART Start RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH Temporary Sector Unprotect Completed(Note 2) Notes : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V 2. All previously protected sectors are protected again. P/N:PM1171 REV. 1.0, FEB. 27, 2006 57 MX29LA129M H/L Figure 22. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART START Enter Secured Silicon Sector Wait 1us First Wait Cycle Data=60h Second Wait Cycle Data=60h A7=0, A2=1, A1=0 Wait 300us No Data = 01h ? Yes Device Failed Write Reset Command Secured Sector Protect Complete P/N:PM1171 REV. 1.0, FEB. 27, 2006 58 MX29LA129M H/L Figure 23. SILICON ID READ TIMING WAVEFORM VCC 3V VID VIH VIL ADD A10 ADD A1 VIH VIL tACC A2 tACC tACC tACC VIH VIL A3 VIH VIL VIH ADD VIL Disable CEx Enable WE# tCE VIH VIL VIH tOE OE# tDF VIL tOH tOH tOH tOH VIH DATA Q0-Q15 VIL DATA OUT DATA OUT DATA OUT DATA OUT Manufacturer ID Device ID Cycle 1 Device ID Cycle 2 Device ID Cycle 3 P/N:PM1171 REV. 1.0, FEB. 27, 2006 59 MX29LA129M H/L WRITE OPERATION STATUS Figure 24. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA VA VA tACC tCE Disable CEx Enable tCH tOE OE# tOEH tDF WE# tOH Q7 Status Data Q0-Q6 Status Data Complement Status Data True True Valid Data Valid Data High Z High Z tBUSY RY/BY# Note : VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle. P/N:PM1171 REV. 1.0, FEB. 27, 2006 60 MX29LA129M H/L Figure 25. DATA# POLLING ALGORITHM Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? No No Q5 = 1 ? Yes Read Q7~Q0 Add.=VA Yes Q7 = Data ? (2) No FAIL Pass Notes: 1.VA=valid address for programming. 2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1171 REV. 1.0, FEB. 27, 2006 61 MX29LA129M H/L Figure 26. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA VA VA VA tACC tCE Disable CEx Enable tCH tOE OE# tOEH tDF WE# tDH Q6/Q2 Valid Status tOH Valid Status Valid Data (second read) (stops toggling) Valid Status (first read) Valid Data RY/BY# Note : VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. P/N:PM1171 REV. 1.0, FEB. 27, 2006 62 MX29LA129M H/L Figure 27. TOGGLE BIT ALGORITHM START Read Q7~Q0 Read Q7~Q0 (Note 1) NO Toggle Bit Q6 =Toggle? YES NO Q5=1? YES Read Q7~Q0 Twice (Note 1,2) Toggle Bit Q6= Toggle? YES Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes : 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1171 REV. 1.0, FEB. 27, 2006 63 MX29LA129M H/L Figure 28. Q6 versus Q2 Enter Embedded Erasing Erase Suspend Erase WE# Enter Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Program Erase Suspend Read Erase Erase Complete Q6 Q2 Note : The system can use OE# or CEx to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended P/N:PM1171 REV. 1.0, FEB. 27, 2006 64 MX29LA129M H/L ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Typ (Note 1) Max (Note 2) Unit Comments 0.5 2 sec Excludes 00h programming Chip Erase Time 128 256 sec prior to erasure Note 6 Total Write Buffer Program Time (Note 4) 240 us Excludes Total Accelerated Effective Write Buffer 200 us system level Program Time (Note 4) Chip Program Time overhead 126 sec Note 7 Notes: 1. Typical program and erase times assume the following conditions: 25° C, 3.0V VCC. Programming specifications assume checkboard data pattern. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 3 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V VCC + 1.0V -100mA +100mA Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. DATA RETENTION Parameter Minimum Pattern Data Retention Time P/N:PM1171 Min Unit 20 Years REV. 1.0, FEB. 27, 2006 65 MX29LA129M H/L TSOP PIN AND BGA PACKAGE CAPACITANCE Parameter Symbol Parameter Description CIN Input Capacitance COUT CIN2 Output Capacitance Control Pin Capacitance Test Set VIN=0 VOUT=0 VIN=0 TYP MAX UNIT 6 7.5 pF CSP 4.2 5.0 pF TSOP 8.5 12 pF CSP 5.4 6.5 pF TSOP 7.5 9 pF CSP 3.9 4.7 pF TSOP Notes: 1. Sampled, not 100% tested. 2. Test conditions TA=25° C, f=1.0MHz P/N:PM1171 REV. 1.0, FEB. 27, 2006 66 MX29LA129M H/L ORDERING INFORMATION PLASTIC PACKAGE PART NO. MX29LA129MHTI-90R ACCESS TIME (ns) 90 MX29LA129MLTI-90R 90 MX29LA129MHTI-10 100 MX29LA129MLTI-10 100 MX29LA129MHTI-90Q 90 MX29LA129MLTI-90Q 90 MX29LA129MHTI-10G 100 MX29LA129MLTI-10G 100 PACKAGE 56 Pin TSOP (Normal Type) 56 Pin TSOP (Normal Type) 56 Pin TSOP (Normal Type) 56 Pin TSOP (Normal Type) 56 Pin TSOP (Normal Type) 56 Pin TSOP (Normal Type) 56 Pin TSOP (Normal Type) 56 Pin TSOP (Normal Type) P/N:PM1171 Remark PB-free PB-free PB-free PB-free REV. 1.0, FEB. 27, 2006 67 MX29LA129M H/L PART NAME DESCRIPTION MX 29 LV 640 M T T C 90 G OPTION: G: Lead-free package R: Restricted VCC (3.0V~3.6V) Q: Restricted VCC (3.0V~3.6V) with Lead-free package blank: normal SPEED: 70: 70ns 90: 90ns 10:100ns TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: M: SOP T: TSOP X: FBGA (CSP) XB - 0.3mm Ball XE - 0.4mm Ball XC - 1.0mm Ball BOOT BLOCK TYPE: T: Top Boot B: Bottom Boot H: Uniform with Highest Sector H/W Protect L: Uniform with Lowest Sector H/W Protect U: Uniform Sector REVISION: M: NBit Technology DENSITY & MODE: 033/320/321: 32Mb, Page Mode Flash Device 065/640/641: 64Mb, Page Mode Flash Device 128/129: 128Mb, Page Mode Flash Device TYPE: LV/GL: 3V standard LA: 3V Security DEVICE: 29:Flash P/N:PM1171 REV. 1.0, FEB. 27, 2006 68 MX29LA129M H/L PACKAGE INFORMATION P/N:PM1171 REV. 1.0, FEB. 27, 2006 69 MX29LA129M H/L REVISION HISTORY Revision No. Description 1.0 1. Removed title "Preliminary" 2. To correct content error Page P1 P3 P/N:PM1171 Date FEB/27/2006 REV. 1.0, FEB. 27, 2006 70 MX29LA129M H/L MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.