Numonyx M25PE40-VMP6TG 4 mbit, page-erasable serial flash memory with byte alterability, 75 mhz spi bus, standard pinout Datasheet

M25PE40
4 Mbit, page-erasable serial Flash memory with
byte alterability, 75 MHz SPI bus, standard pinout
Features
■
SPI bus compatible serial interface
■
4 Mbit page-erasable Flash memory
■
Page size: 256 bytes
– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)
■
Subsector Erase (4 Kbytes)
■
Sector Erase (64 Kbytes)
■
Bulk Erase (4 Mbits)
■
2.7 V to 3.6 V single supply voltage
■
75 MHz clock rate (maximum)
■
Deep Power-down mode 1 µA (typical)
■
Electronic signature
– JEDEC standard two-byte signature
(8013h)
■
Software write protection on a 64-Kbyte sector
basis
■
Hardware write protection of the memory area
selected using the BP0, BP1 and BP2 bits
■
More than 100 000 Write cycles
■
More than 20 year data retention
■
Packages
– ECOPACK® (RoHS compliant)
January 2008
VFQFPN8 (MP)
6 × 5 mm (MLP8)
SO8W (MW) 208 mils
SO8N (MN) 150 mils
Rev 9
1/62
www.numonyx.com
1
Contents
M25PE40
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) or Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13
4.5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6
Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13
4.7
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.1
Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.2
Specific hardware and software protections . . . . . . . . . . . . . . . . . . . . . 15
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/62
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
M25PE40
Contents
6.4
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.3
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 29
6.8
Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.9
Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.10
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.11
Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.12
Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.13
Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.14
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.15
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.16
Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.17
Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7
Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3/62
List of tables
M25PE40
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
4/62
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Software protection truth table (Sectors 0 to 7, 64-Kbyte granularity) . . . . . . . . . . . . . . . . 16
Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Identification (RDID) Data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Protection modes (T9HX process only, see Important note on page 6) . . . . . . . . . . . . . . . 27
Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Device status after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DC characteristics (75 MHz operation, T9HX (0.11 µm) process) . . . . . . . . . . . . . . . . . . . 47
AC characteristics (25 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
AC characteristics (33 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
AC characteristics (50 MHz operation, T9HX (0.11µm) process) . . . . . . . . . . . . . . . . . . . . 50
AC characteristics (75 MHz operation, T9HX (0.11µm) process) . . . . . . . . . . . . . . . . . . . . 51
Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . 57
SO8W – 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . 58
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M25PE40
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Logic diagram - previous T7X process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic diagram - new T9HX process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 23
Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 25
Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 28
Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Lock Register (RDLR) instruction sequence and data-out sequence . . . . . . . . . . . . 30
Page Write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Page Erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Subsector Erase (SSE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 41
Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 57
SO8W – 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . . 58
5/62
Description
1
M25PE40
Description
The M25PE40 is a 4 Mbit (512Kbit × 8 bit) serial paged Flash memory accessed by a high
speed SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or
Page Program instruction. The Page Write instruction consists of an integrated Page Erase
cycle followed by a Page Program cycle.
The memory is organized as 8 sectors that are further divided up into 16 subsectors each
(128 subsectors in total). Each sector contains 256 pages and each subsector contains 16
pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting
of 2048 pages, or 524,288 bytes.
The memory can be erased a page at a time, using the Page Erase instruction, a subsector
at a time, using the Subsector Erase instruction, a sector at a time, using the Sector Erase
instruction or as a whole, using the Bulk Erase (BE) instruction.
The memory can be write protected by either hardware or software using a mix of volatile
and non-volatile protection features, depending on the application needs. The protection
granularity is of 64 Kbytes (sector granularity).
Important note
This datasheet details the functionality of the devices, based on the previous T7X process or
based on the current T9HX process (available since July 2007). Delivery of parts operating
with a maximum clock rate of 75 MHz starts from week 8 of 2008.
What are the changes?
The M25PE40 in T9HX process offers the following additional features:
6/62
●
the whole memory array is partitioned into 4-Kbyte subsectors
●
five new instructions: Write Status Register (WRSR), Write to Lock Register (WRLR),
Read Lock Register (RDLR), 4-Kbyte Subsector Erase (SSE) and Bulk Erase (BE)
●
Status Register: 4 bits can be written (BP0, BP1, BP2, SRWD)
●
WP input (pin 3): write protection limits are extended, depending on the value of the
BP0, BP1, BP2, SRWD bits. The WP write protection remains the same if bits (BP2,
BP1, BP0) are set to (0, 0, 1)
●
smaller die size allowing assembly into an SO8N package.
M25PE40
Description
Figure 1.
Logic diagram - previous T7X Figure 2.
process
VCC
VCC
D
D
Q
Q
C
C
S
S
M25PE40
TSL
W
Reset
Reset
VSS
Table 1.
Logic diagram - new T9HX
process
M25PE40
VSS
AI09704C
AI13781
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
D
Serial Data input
Input
Q
Serial Data output
Output
S
Chip Select
Input
TSL or W(1)
Top Sector Lock or Write Protect
Input
Reset
Reset
Input
VCC
Supply voltage
VSS
Ground
1. In the previous T7X process the pin is a Top Sector Lock input whereas in the new T9HX process, the pin
is a Write Protect input (see Figure 1 and Figure 2).
Figure 3.
VFQFPN and SO connections
M25PE40
S
Q
TSL or W
VSS
1
2
3
4
8
7
6
5
VCC
Reset
C
D
AI09703d
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Section 12: Package mechanical for package dimensions, and how to identify pin-1.
7/62
Signal description
2
Signal description
2.1
Serial Data output (Q)
M25PE40
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving
Chip Select (S) Low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory.
When Reset (Reset) is driven High, the memory is in the normal operating mode. When
Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output
is high impedance.
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
8/62
M25PE40
2.6
Signal description
Write Protect (W) or Top Sector Lock (TSL)
●
The Write Protect function is available in the T9HX process only (see Important
note on page 6).
The Write Protect (W) input is used to freeze the size of the area of memory that is
protected against write, program and erase instructions (as specified by the values in
the BP2, BP1 and BP0 bits of the Status Register. See Section 6.4: Read Status
Register (RDSR) for a description of these bits.
●
The Top Sector Lock function is available in the T7X process only (see Important
note on page 6).
The input signal sets the device in the Hardware Protected mode, when Top Sector
Lock (TSL) is connected to VSS, causing the top 256 pages (upper addresses) of the
memory to become read-only (protected from write, program and erase operations).
When Top Sector Lock (TSL) is connected to VCC, the top 256 pages of memory
behave like the other pages of memory.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
9/62
SPI modes
3
M25PE40
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Standby mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
VCC
SPI Bus Master
SPI memory
device
R
CS3
C Q D
VCC
VSS
C Q D
VCC
VSS
SPI memory
device
R
VSS
SPI memory
device
R
CS2 CS1
S
W Reset
or
TSL
S
W Reset
or
TSL
S
Reset
W
or
TSL
AI13558b
1. The Write Protect or Top Sector Lock (W or TSL) signal should be driven, High or Low as appropriate.
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure
that the M25PE40 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the tSHCH requirement is met). The
typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
10/62
M25PE40
SPI modes
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5 µs.
Figure 5.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI01438B
11/62
Operating features
4
Operating features
4.1
Sharing the overhead of modifying data
M25PE40
To write or program one (or more) data bytes, two instructions are required: Write Enable
(WREN), which is one byte, and a Page Write (PW) or Page Program (PP) sequence, which
consists of four bytes plus data. This is followed by the internal cycle (of duration tPW or tPP).
To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to
256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at
a time, provided that they lie in consecutive addresses on the same page of memory.
4.2
An easy way to modify data
The Page Write (PW) instruction provides a convenient way of modifying data (up to 256
contiguous bytes at a time), and simply requires the start address, and the new data in the
instruction sequence.
The Page Write (PW) instruction is entered by driving Chip Select (S) Low, and then
transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte,
and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data
bytes are written to the data buffer, starting at the address given in the third address byte
(A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining,
unchanged, bytes of the data buffer are automatically loaded with the values of the
corresponding bytes of the addressed memory page. The addressed memory page then
automatically put into an erase cycle. Finally, the addressed memory page is programmed
with the contents of the data buffer.
All of this buffer management is handled internally, and is transparent to the user. The user
is given the facility of being able to alter the contents of the memory on a byte-by-byte basis.
For optimized timings, it is recommended to use the Page Write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few bytes (see Section 6.9: Page Write (PW),
Table 21: AC characteristics (50 MHz operation, T9HX (0.11µm) process), and Table 22: AC
characteristics (75 MHz operation, T9HX (0.11µm) process)).
12/62
M25PE40
4.3
Operating features
A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to 0 that had
previously been set to ‘1’.
This might be:
●
when the designer is programming the device for the first time
●
when the designer knows that the page has already been erased by an earlier Page
Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a
fast stream of data, having first performed the erase cycle when time was available
●
when the designer knows that the only changes involve resetting bits to ‘0’ that are still
set to ‘1’. When this method is possible, it has the additional advantage of minimizing
the number of unnecessary erase operations, and the extra stress incurred by each
page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Section 6.10: Page
Program (PP), Table 21: AC characteristics (50 MHz operation, T9HX (0.11µm) process),
and Table 22: AC characteristics (75 MHz operation, T9HX (0.11µm) process)).
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (tPW, tPP, tPE, or tSE). The Write In Progress (WIP) bit is provided in the
Status Register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
4.5
Reset
An internal Power-on Reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the power-on process, and only
driving it High when VCC has reached the correct voltage level, VCC(min).
4.6
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write). The device then goes
in to the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until the Release from Deep Power-down instruction is
executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
13/62
Operating features
4.7
M25PE40
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by using specific instructions. See Section 6.4: Read Status Register (RDSR)
for a detailed description of the Status Register bits.
4.8
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
features the following data protection mechanisms:
4.8.1
Protocol-related protections
●
Power On Reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
●
Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
14/62
Power-up
–
Reset (Reset) driven Low
–
Write Disable (WRDI) instruction completion
–
Page Write (PW) instruction completion
–
Page Program (PP) instruction completion
–
Write to Lock Register (WRLR) instruction completion
–
Page Erase (PE) instruction completion
–
Subsector Erase (SSE) instruction completion
–
Sector Erase (SE) instruction completion
–
Bulk Erase (BE) instruction completion
●
The Reset (Reset) signal can be driven Low to freeze and reset the internal logic. For
the specific cases of Program and Write cycles, the designer should refer to
Section 6.5: Write Status Register (WRSR), Section 6.9: Page Write (PW),
Section 6.10: Page Program (PP), Section 6.12: Page Erase (PE), Section 6.14: Sector
Erase (SE), Section 6.13: Subsector Erase (SSE), and to Table 12: Device status after
a Reset Low pulse.
●
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions while
the device is not in active use.
M25PE40
4.8.2
Operating features
Specific hardware and software protections
The M25PE40 features a Hardware Protected mode, HPM, and two Software Protected
modes, SPM1 and SPM2 that can be combined to protect the memory array as required.
They are described below:
HPM
●
HPM in T7X process (see Important note on page 6):
The Hardware Protected mode (HPM) is entered when Top Sector Lock (TSL) is driven
Low, causing the top 256 pages of memory to become read-only. When Top Sector
Lock (TSL) is driven High, the top 256 pages of memory behave like the other pages of
memory and the protection depends on the Block Protect bits (see SPM2 below).
●
HPM in T9HX process (see Important note on page 6):
The Hardware Protected mode (HPM) is used to write-protect the non-volatile bits of
the Status Register (that is, the Block Protect bits, BP2, BP1 and BP0, and the Status
Register Write Disable bit, SRWD).
HPM is entered by driving the Write Protect (W) signal Low with the SRWD bit set to
High. This additional protection allows the Status Register to be hardware-protected
(see also Section 6.4.4: SRWD bit).
SPM1 and SPM2
●
The first Software Protected mode (SPM1) is managed by specific Lock Registers
assigned to each 64-Kbyte sector.
The Lock Registers can be read and written using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the protection of each sector: the Write Lock bit
and the Lock Down bit.
–
Write Lock bit:
The Write Lock bit determines whether the contents of the sector can be modified
(using the Write, Program or Erase instructions). When the Write Lock bit is set to
‘1’, the sector is write protected – any operations that attempt to change the data
in the sector will fail. When the Write Lock bit is reset to ‘0’, the sector is not write
protected by the Lock Register, and may be modified.
–
Lock Down bit:
The Lock Down bit provides a mechanism for protecting software data from simple
hacking and malicious attack. When the Lock Down bit is set to ‘1’, further
modification to the Write Lock and Lock Down bits cannot be performed. A reset,
or power-up, is required before changes to these bits can be made. When the
Lock Down bit is reset to ‘0’, the Write Lock and Lock Down bits can be changed.
The Write Lock bit and the Lock Down bit are volatile and their value is reset to ‘0’ after
a power-down or a reset.
15/62
Operating features
M25PE40
Table 2.
Software protection truth table (Sectors 0 to 7, 64-Kbyte granularity)
Sector Lock Register
Protection status
Lock
Down bit
Write
Lock bit
0
0
Sector unprotected from Program/Erase/Write operations, protection status
reversible
0
1
Sector protected from Program/Erase/Write operations, protection status
reversible
1
0
Sector unprotected from Program/Erase/Write operations,
sector protection status cannot be changed except by a reset or power-up.
1
1
Sector protected from Program/Erase/Write operations,
sector protection status cannot be changed except by a reset or power-up.
The second Software Protected mode (SPM2) uses the Block Protect bits (BP2,
BP1, BP0, see Section 6.4.3)) to allow part of the memory to be configured as readonly.
●
Table 3.
Protected area sizes
Status Register
content
Memory content
BP2 BP1 BP0
bit
bit
bit
Protected area
Unprotected area
0
0
0
none
All sectors(1) (eight sectors: 0 to 7)
0
0
1
Upper eighth (sector 7)
Lower seven-eighths (seven sectors: 0 to 6)
0
1
0
Upper quarter (two sectors: 6 and
7)
Lower three-quarters (six sectors: 0 to 5)
0
1
1
Upper half (four sectors: 4 to 7)
Lower half (four sectors: 0 to 3)
1
0
0
All sectors (eight sectors: 0 to 7)
none
1
0
1
All sectors (eight sectors: 0 to 7)
none
1
1
0
All sectors (eight sectors: 0 to 7)
none
1
1
1
All sectors (eight sectors: 0 to 7)
none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect bits (BP2, BP1, BP0)
are 0.
16/62
M25PE40
Memory organization
The memory is organized as:
●
2048 pages (256 bytes each)
●
524,288 bytes (8 bits each)
●
128 subsectors (32 Kbits, 4096 bytes each)
●
8 sectors (512 Kbits, 65536 bytes each)
Each page can be individually:
–
programmed (bits are programmed from 1 to 0)
–
erased (bits are erased from 0 to 1)
–
written (bits are changed to either 0 or 1)
The device is page or sector erasable (bits are erased from 0 to 1).
Memory organization
1
4
04000h
04FFFh
3
03000h
03FFFh
02000h
02FFFh
96
60000h
60FFFh
1
01000h
01FFFh
95
5F000h
5FFFFh
0
00000h
00FFFh
...
2
...
...
...
0FFFFh
...
0
0F000h
...
...
...
15
Address range
...
6FFFFh
50FFFh
4F000h
4FFFFh
40000h
40FFFh
63
3F000h
3FFFFh
48
30000h
30FFFh
47
2F000h
2FFFFh
...
...
64
...
...
50000h
79
...
80
32
20000h
20FFFh
31
1F000h
1FFFFh
...
2
70FFFh
6F000h
...
3
70000h
111
...
4
112
...
5
Sector Subsector
7FFFFh
...
6
7F000h
...
7
...
127
Address range
...
Sector Subsector
...
Table 4.
...
5
Memory organization
16
10000h
10FFFh
17/62
Memory organization
Figure 6.
M25PE40
Block diagram
Reset
TSL or W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Status
Register
256 byte
Data Buffer
7FFFFh
Top 256 pages can
be made read-only
by using the TSL pin(1)
6FFFFh
Y Decoder
Whole memory array can
be made read-only
on a 64-Kbyte basis
through the Lock
Registers
00000h
000FFh
256 bytes (page size)
X Decoder
AI13782
1. These features (in gray) are only available in the T7X process.
18/62
M25PE40
6
Instructions
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed inTable 5.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(FAST_READ), Read Status Register (RDSR) or Read to Lock Register (RDLR) instruction,
the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can
be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Page Write (PW), Page Program (PP), Page Erase (PE), Subsector Erase
(SSE), Sector Erase (SE), Bulk Erase (BE), Write Enable (WREN), Write Disable (WRDI),
Write Status Register (WRSR), Write to Lock Register (WRLR), Deep Power-down (DP) or
Release from Deep Power-down (RDP) instruction, Chip Select (S) must be driven High
exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is,
Chip Select (S) must driven High when the number of clock pulses after Chip Select (S)
being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle
are ignored, and the internal Write cycle, Program cycle or Erase cycle continues
unaffected.
19/62
Instructions
M25PE40
Table 5.
Instruction set
Instruction
Description
One-byte
instruction code
Data
bytes
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
RDID
Read Identification
1001 1111
9Fh
0
0
1 to 3
RDSR
Read Status Register
0000 0101
05h
0
0
1 to ∞
WRLR(1)
Write to Lock Register
1110 0101
E5h
3
0
1
WRSR(1)
Write Status Register
0000 0001
01h
0
0
1
RDLR
Read Lock Register
1110 1000
E8h
3
0
1
READ
Read Data Bytes
0000 0011
03h
3
0
1 to ∞
0000 1011
0Bh
3
1
1 to ∞
(1)
FAST_READ Read Data Bytes at Higher Speed
PW
Page Write
0000 1010
0Ah
3
0
1 to 256
PP
Page Program
0000 0010
02h
3
0
1 to 256
PE
Page Erase
1101 1011
DBh
3
0
0
Subsector Erase
0010 0000
20h
3
0
0
Sector Erase
1101 1000
D8h
3
0
0
Bulk Erase
1100 0111
C7h
0
0
0
Deep Power-down
1011 1001
B9h
0
0
0
Release from Deep Power-down
1010 1011
ABh
0
0
0
SSE(1)
SE
BE(1)
DP
RDP
1. Instruction available only in the T9HX process (see Important note on page 6).
20/62
Addr Dummy
bytes bytes
M25PE40
6.1
Instructions
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page
Program (PP), Page Erase (PE), and Sector Erase (SE) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 7.
Write Enable (WREN) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
21/62
Instructions
6.2
M25PE40
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
●
Power-up
●
Write Disable (WRDI) instruction completion
●
Page Write (PW) instruction completion
●
Page Program (PP) instruction completion
●
Write Status Register (WRSR) instruction completion
●
Write to Lock Register (WRLR) instruction completion
●
Page Erase (PE) instruction completion
●
Subsector Erase (SSE) instruction completion
●
Sector Erase (SE) instruction completion
●
Bulk Erase (BE) instruction completion
Figure 8.
Write Disable (WRDI) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
22/62
M25PE40
6.3
Instructions
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be
read, followed by two bytes of device identification. The manufacturer identification is
assigned by JEDEC, and has the value 20h for Numonyx. The device identification is
assigned by the device manufacturer, and indicates the memory type in the first byte (80h),
and the memory capacity of the device in the second byte (13h).
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data output (Q), each bit being shifted out during
the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Table 6.
Read Identification (RDID) Data-out sequence
Device identification
Manufacturer identification
20h
Figure 9.
Memory type
Memory capacity
80h
13h
Read Identification (RDID) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
C
Instruction
D
Manufacturer identification
Device identification
High Impedance
Q
15 14 13
MSB
3
2
1
0
MSB
AI06809b
23/62
Instructions
6.4
M25PE40
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In
Progress (WIP) bit before sending a new instruction to the device. It is also possible to read
the Status Register continuously, as shown in Figure 10.
The status bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program
or Erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is
in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to ‘1’ the internal Write Enable Latch is set, when set to ‘0’ the internal Write
Enable Latch is reset and no Write, Program or Erase instruction is accepted.
6.4.3
BP2, BP1, BP0 bits
The Block Protect bits (BP2, BP1, BP0) are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 3) becomes
protected against Page Program (PP), Page Erase (PE), Sector Erase (SE) and Subsector
Erase (SSE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided
that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is
executed if, and only if:
6.4.4
●
all Block Protect (BP2, BP1, BP0) bits are 0
●
the Lock Register protection bits are not all set (‘1’).
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. When the Status Register Write Disable (SRWD) bit is set to ‘1’, and
Write Protect (W) is driven Low, the non-volatile bits of the Status Register (SRWD, BP2,
BP1, BP0) become read-only bits. In such a state, as the Write Status Register (WRSR)
instruction is no longer accepted for execution, the definition of the size of the Write
Protected area cannot be further modified.
Table 7.
Status Register format(1)(2)(3)
b7
SRWD
b0
0
0
BP2
BP1
BP0
WEL
WIP
1. WEL (Write Enable Latch) and WIP ((Write In Program) are volatile read-only bits (WEL is set and reset by
specific instructions; WIP is automatically set and reset by the internal logic of the device).
2. SRWD = Status Register Write Protect bit; BP0, BP1, BP2 = Block Protect bits.
3. The BP bits and the SRWD bit exist only in the T9HX process.
24/62
M25PE40
Instructions
Figure 10. Read Status Register (RDSR) instruction sequence and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
25/62
Instructions
6.5
M25PE40
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register.
Note:
The Status Register BPi and SRWD bits are available in the M25PE40 in the T9HX process
only. See Important note on page 6 for more details.
Before the Write Status Register (WRSR) instruction can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows
the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal (see Section 6.4.4).
If a Write Status Register (WRSR) instruction is interrupted by a Reset Low pulse, the
internal cycle of the Write Status Register operation (whose duration is tW) is first completed
(provided that the supply voltage VCC remains within the operating range). After that the
device enters the Reset mode (see also Table 12: Device status after a Reset Low pulse
and Table 24: Timings after a Reset Low pulse).
Figure 11. Write Status Register (WRSR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register in
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
26/62
M25PE40
Instructions
Table 8.
Protection modes (T9HX process only, see Important note on page 6)
W
SRWD
signal
bit
1
Write protection of the
Status Register
Second
software
protected
(SPM2)
Status Register is writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
0
0
0
1
1
0
Mode
1
Status Register is
Hardware hardware write protected
protected The values in the SRWD,
(HPM) BP2, BP1 and BP0 bits
cannot be changed
Memory content
Protected area(1)
Unprotected area(1)
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 3.
The protection features of the device are summarized in Table 8.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W):
●
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
●
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction (attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM2) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM2), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
27/62
Instructions
6.6
M25PE40
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence
0
1
2
3
4
5
6
7
8
Instruction
9 10
28 29 30 31 32 33 34 35 36 37 38 39
24-bit address
23 22 21
3
2
1
0
MSB
Data Out 1
High Impedance
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI03748D
1. Address bits A23 to A19 are Don’t care.
28/62
M25PE40
6.7
Instructions
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24-bit address
23 22 21
D
3
2
1
0
High Impedance
Q
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy byte
D
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
Q
7
MSB
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
AI04006
1. Address bits A23 to A19 are Don’t care.
29/62
Instructions
M25PE40
6.8
Read Lock Register (RDLR)
Note:
The Read Lock Register (RDLR) instruction is decoded only in the M25PE40 in the T9HX
process (see Important note on page 6).
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector (or subsector). Each address bit is latched-in during
the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on
Serial Data output (Q), each bit being shifted out, at a maximum frequency fC, during the
falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Table 9.
Bit
Lock Registers
Bit name
Value
Function
b7-b4
b1
b0
Reserved
‘1’
The Write Lock and Lock Down bits cannot be changed. Once a
‘1’ is written to the Lock Down bit it cannot be cleared to ‘0’,
except by a reset or power-up.
‘0’
The Write Lock and Lock Down bits can be changed by writing
new values to them (default value).
‘1’
Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
‘0’
Write, Program and Erase operations in this sector are executed
and will modify the sector contents (default value).
Sector Lock
Down
Sector Write
Lock
Figure 14. Read Lock Register (RDLR) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
23 22 21
D
3
2
1
0
MSB
Lock Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
MSB
AI10783
30/62
M25PE40
6.9
Instructions
Page Write (PW)
The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch
(WEL).
The Page Write (PW) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, three address bytes and at least one data byte on Serial Data input (D).
The rest of the page remains unchanged if no power failure occurs during this write cycle.
The Page Write (PW) instruction performs a page erase cycle even if only one byte is
updated.
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the addressed page boundary roll over, and are written from the start address of the same
page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be written correctly within the same page. If less than
256 Data bytes are sent to device, they are correctly written at the requested addresses
without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few bytes (see Table 21: AC characteristics (50 MHz
operation, T9HX (0.11µm) process) and Table 22: AC characteristics (75 MHz operation,
T9HX (0.11µm) process)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Write (PW) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration
is tPW) is initiated. While the Page Write cycle is in progress, the Status Register may be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Page Write (PW) instruction applied to a page that is hardware protected is not executed.
Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
31/62
Instructions
M25PE40
Figure 15. Page Write (PW) instruction sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
C
Instruction
24-bit address
23 22 21
D
3
2
Data byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data byte 2
D
7
6
MSB
5
4
3
2
Data byte 3
1
0
7
MSB
6
5
4
3
2
Data byte n
1
0
7
6
5
4
3
2
1
0
MSB
AI04045
1. Address bits A23 to A19 are Don’t care.
2. 1 ≤ n ≤ 256.
32/62
M25PE40
6.10
Instructions
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the addressed page boundary roll over, and are programmed from the start address of the
same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select
(S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Table 20: AC
characteristics (33 MHz operation)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page that is hardware protected is not
executed.
Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
33/62
Instructions
M25PE40
Figure 16. Page Program (PP) instruction sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
C
Instruction
24-bit address
23 22 21
D
3
2
Data byte 1
1
0
7
6
5
4
3
2
0
1
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data byte 2
D
7
6
MSB
5
4
3
2
Data byte 3
1
0
7
MSB
6
5
4
3
2
Data byte n
1
0
7
6
5
4
3
2
1
0
MSB
AI04044
1. Address bits A23 to A19 are Don’t care.
2. 1 ≤ n ≤ 256.
34/62
M25PE40
Instructions
6.11
Write to Lock Register (WRLR)
Note:
The Write to Lock Register (WRLR) instruction is decoded only in the M25PE40 in the T9HX
process (see Important note on page 6).
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the targeted
sector and one data byte on Serial Data input (D). The instruction sequence is shown in
Figure 17. Chip Select (S) must be driven High after the eighth bit of the data byte has been
latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value.
Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Write to Lock Register (WRLR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
Lock Register
value
24-bit address
23 22 21
D
MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
AI10784b
Table 10.
Lock Register in(1)
Sector
All sectors
Bit
Value
b7-b2
‘0’
b1
Sector Lock Down bit value
b0
Sector Write Lock bit value
1. The table rows in gray are true for products processed in the T7X process only (see Important note on
page 6).
35/62
Instructions
6.12
M25PE40
Page Erase (PE)
The Page Erase (PE) instruction sets to ‘1’ (FFh) all bits inside the chosen page. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Page Erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (D). Any address inside the
page is a valid address for the Page Erase (PE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 18.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Page Erase cycle (whose duration is tPE) is initiated.
While the Page Erase cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Page Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Page Erase (PE) instruction applied to a page that is hardware protected is not executed.
Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 18. Page Erase (PE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
D
24-bit address
23 22
2
1
0
MSB
AI04046
1. Address bits A23 to A19 are Don’t care.
36/62
M25PE40
Instructions
6.13
Subsector Erase (SSE)
Note:
The Subsector Erase (SSE) instruction is decoded only in the M25PE40 in the T9HX
process (see Important note on page 6).
The Subsector Erase (SSE) instruction sets to ‘1’ (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Subsector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, and three address bytes on Serial Data input (D). Any address inside
the Subsector (see Table 4) is a valid address for the Subsector Erase (SE) instruction. Chip
Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 20.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Subsector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is tSSE) is
initiated. While the Subsector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Subsector Erase (SSE) instruction applied to a subsector that contains a page that is
hardware or software protected is not executed.
Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
If Reset (Reset) is driven Low while a Subsector Erase (SSE) cycle is in progress, the
Subsector Erase cycle is interrupted and data may not be erased correctly (see Table 12:
Device status after a Reset Low pulse). On Reset going Low, the device enters the Reset
mode and a time of tRHSL is then required before the device can be re-selected by driving
Chip Select (S) Low. For the value of tRHSL see Table 24: Timings after a Reset Low pulse in
Section 11: DC and AC parameters.
Figure 19. Subsector Erase (SSE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
D
24-bit address
23 22
2
1
0
MSB
AI12356
1. Address bits A23 to A19 are Don’t care.
37/62
Instructions
6.14
M25PE40
Sector Erase (SE)
The Sector Erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Sector (see Table 4) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 20.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector that contains a page that is hardware
protected is not executed.
Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 20. Sector Erase (SE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
D
24-bit address
23 22
2
1
0
MSB
AI03751D
1. Address bits A23 to A19 are Don’t care.
38/62
M25PE40
Instructions
6.15
Bulk Erase (BE)
Note:
The Bulk Erase (BE) instruction is decoded only in the M25PE40 in the T9HX process (see
Important note on page 6).
The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 21.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
Any Bulk Erase (BE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress. A Bulk Erase (BE)
instruction is ignored if at least one sector or subsector is write-protected (hardware or
software protection).
If Reset (Reset) is driven Low while a Bulk Erase (BE) cycle is in progress, the Bulk Erase
cycle is interrupted and data may not be erased correctly (see Table 12: Device status after
a Reset Low pulse). On Reset going Low, the device enters the Reset mode and a time of
tRHSL is then required before the device can be re-selected by driving Chip Select (S) Low.
For the value of tRHSL see Table 24: Timings after a Reset Low pulse in Section 11: DC and
AC parameters.
Figure 21. Bulk Erase (BE) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
AI03752D
39/62
Instructions
6.16
M25PE40
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power
mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be entered by executing the
Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to
ICC2, as specified in Table 17).
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. This releases the device from
this mode.
The Deep Power-down mode automatically stops at power-down, and the device always
powers-up in the Standby Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 22.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced
to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 22. Deep Power-down (DP) instruction sequence
S
0
1
2
3
4
5
6
7
tDP
C
Instruction
D
Standby mode
Deep Power-down mode
AI03753D
40/62
M25PE40
6.17
Instructions
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 23.
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the
Standby Power mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 23. Release from Deep Power-down (RDP) instruction sequence
S
0
1
2
3
4
5
6
7
tRDP
C
Instruction
D
High Impedance
Q
Deep Power-down mode
Standby mode
AI06807
41/62
Power-up and power-down
7
M25PE40
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
●
VCC(min) at power-up, and then for a further delay of tVSL
●
VSS at power-down.
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of tPUW has
elapsed after the moment that VCC rises above the VWI threshold. However, the correct
operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No
Write, Program or Erase instructions should be sent until the later of:
●
tPUW after VCC passed the VWI threshold
●
tVSL after VCC passed the VCC(min) level.
These values are specified in Table 11.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the power-up and power-down phases.
At power-up, the device is in the following state:
●
The device is in the Standby Power mode (not the Deep Power-down mode)
●
The Write Enable Latch (WEL) bit is reset
●
The Write In Progress (WIP) bit is reset
●
The Lock Registers are reset (Write Lock bit, Lock Down bit) = (0, 0).
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of 100 nF).
At power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.)
42/62
M25PE40
Power-up and power-down
Figure 24. Power-up timing
VCC
VCC(max)
Program, Erase and Write commands are rejected by the device
Chip selection not allowed
VCC(min)
Reset state
of the
device
tVSL
Read access allowed
Device fully
accessible
VWI
tPUW
time
Table 11.
AI04009C
Power-up timing and VWI threshold
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to S low
30
tPUW(1)
Time delay before the first Write, Program or Erase instruction
1
10
ms
VWI(1)
Write Inhibit voltage
1.5
2.5
V
µs
1. These parameters are characterized only, over the temperature range –40 °C to +85 °C.
43/62
Reset
8
M25PE40
Reset
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
All the Lock bits are reset to ‘0’ after a Reset Low pulse.
Table 12 shows the status of the device after a Reset Low pulse.
Table 12.
Device status after a Reset Low pulse
Conditions:
Reset pulse occurred
Lock bits status
Internal logic
status
Addressed data
While decoding an instruction(1): WREN,
WRDI, RDID, RDSR, READ, RDLR,
Fast_Read, WRLR, PW, PP, PE, SE, BE,
SSE, DP, RDP
Reset to ‘0’
Same as POR
Not significant
Under completion of an Erase or Program
cycle of a PW, PP, PE, SSE, SE, BE
operation
Reset to ‘0’
Equivalent to
POR
Addressed data
could be modified
Under completion of a WRSR operation
Reset to ‘0’
Equivalent to
POR (after tW)
Write is correctly
completed
Device deselected (S High) and in Standby
mode
Reset to ‘0’
Same as POR
Not significant
1.
44/62
S remains Low while Reset is Low.
M25PE40
9
Initial delivery state
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). All usable Status Register bits are 0.
10
Maximum rating
Stressing the device above the rating listed in Table 13: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 13.
Absolute maximum ratings
Symbol
Parameter
TSTG
Storage temperature
TLEAD
Lead temperature during soldering
Min.
Max.
Unit
–65
150
°C
See note (1)
°C
VIO
Input and output voltage (with respect to ground)
–0.6
VCC + 0.6
V
VCC
Supply voltage
–0.6
4.0
V
–2000
2000
V
VESD
Electrostatic discharge voltage (human body
model)(2)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous
Substances (RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
45/62
DC and AC parameters
11
M25PE40
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 14.
Operating conditions
Symbol
VCC
TA
Table 15.
Parameter
Min.
Max.
Unit
Supply voltage
2.7
3.6
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Measurement conditions(1)
Symbol
CL
Parameter
Load capacitance
30
Input rise and fall times
pF
5
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 25. AC measurement I/O waveform
Input levels
Input and output
timing reference levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 16.
Symbol
COUT
CIN
Capacitance(1)
Parameter
Output capacitance (Q)
Input capacitance (other pins)
Test condition
Max.
Unit
VOUT = 0 V
8
pF
VIN = 0 V
6
pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 25 MHz.
46/62
Min.
M25PE40
Table 17.
Symbol
DC and AC parameters
DC characteristics
Parameter
Test condition
Min.
(in addition to those in Table 14)
Max.
Unit
ILI
Input Leakage current
±2
µA
ILO
Output Leakage current
±2
µA
ICC1
Standby current
(Standby and Reset modes)
S = VCC, VIN = VSS or VCC
50
µA
ICC2
Deep Power-down current
S = VCC, VIN = VSS or VCC
10
µA
Operating current
(FAST_READ)
C = 0.1VCC/0.9.VCC at 25 MHz, Q = open
6
mA
ICC3
C = 0.1VCC/0.9.VCC at 50 MHz, Q = open
8
mA
ICC4
Operating current (PW)
S = VCC
15
mA
ICC5
Operating current (SE)
S = VCC
15
mA
VIL
Input Low voltage
– 0.5
0.3VCC
V
VIH
Input High voltage
0.7VCC
VCC+0.4
V
VOL
Output Low voltage
IOL = 1.6 mA
0.4
V
VOH
Output High voltage
IOH = –100 µA
Table 18.
Symbol
VCC–0.2
V
DC characteristics (75 MHz operation, T9HX (0.11 µm) process)(1)
Parameter
Test condition
(in addition to those in Table 14)
Min.
Max.
Unit
ILI
Input Leakage current
±2
µA
ILO
Output Leakage current
±2
µA
ICC1
Standby current
(Standby and Reset modes)
S = VCC, VIN = VSS or VCC
50
µA
ICC2
Deep Power-down current
S = VCC, VIN = VSS or VCC
10
µA
Operating current
(FAST_READ)
C = 0.1VCC/0.9.VCC at 33 MHz, Q = open
4
mA
ICC3
C = 0.1VCC/0.9.VCC at 75 MHz, Q = open
12
mA
ICC4
Operating current (PW)
S = VCC
15
mA
ICC5
Operating current (SE)
S = VCC
15
mA
VIL
Input Low voltage
– 0.5
0.3VCC
V
VIH
Input High voltage
0.7VCC
VCC+0.4
V
VOL
Output Low voltage
IOL = 1.6 mA
0.4
V
VOH
Output High voltage
IOH = –100 µA
VCC–0.2
V
1. Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008.
47/62
DC and AC parameters
Table 19.
M25PE40
M
AC characteristics (25 MHz operation)
Test conditions specified in Table 14 and Table 15
Symbol
Alt.
fC
fC
fR
Parameter
Min.
Typ.
Max.
Unit
Clock frequency for the following instructions:
FAST_READ, PW, PP, PE, SE, DP, RDP,
WREN, WRDI, RDSR
D.C.
25
MHz
Clock frequency for READ instructions
D.C.
20
MHz
tCH
(1)
tCLH
Clock High time
18
ns
tCL
(1)
tCLL
Clock Low time
18
ns
Clock Slew rate (peak-to-peak)
0.1
V/ns
S Active Setup time (relative to C)
10
ns
S Not Active Hold time (relative to C)
10
ns
tSLCH
tCSS
tCHSL
tDVCH
tDSU
Data In Setup time
5
ns
tCHDX
tDH
Data In Hold time
5
ns
tCHSH
S Active Hold time (relative to C)
10
ns
tSHCH
S Not Active Setup time (relative to C)
10
ns
100
ns
tSHSL
tCSH
S Deselect time
tSHQZ (2)
tDIS
Output Disable time
15
ns
tCLQV
tV
Clock Low to Output Valid
15
ns
tCLQX
tHO
Output Hold time
0
ns
tTHSL
Top Sector Lock Setup time
50
ns
tSHTL
Top Sector Lock Hold time
100
ns
tDP
(2)
tRDP
(2)
tPW
(3)
S to Deep Power-down
3
µs
S High to Standby Power mode
30
µs
25
ms
0.4+
n*0.8/256
5
ms
Page Write cycle time (256 bytes)
Page Write cycle time (n bytes)
Page Program cycle time (256 bytes)
tPP (3)
Page Program cycle time (n bytes)
11
10.2+
n*0.8/256
1.2
tPE
Page Erase cycle time
10
20
ms
tSE
Sector Erase cycle time
1
5
s
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
48/62
M25PE40
Table 20.
DC and AC parameters
AC characteristics (33 MHz operation)
33 MHz only available for products marked since week 40 of 2005(1)
Test conditions specified in Table 14 and Table 15
Symbol
Alt.
Parameter
Min.
fC
fC
Clock frequency for the following instructions:
FAST_READ, PW, PP, PE, SE, DP, RDP, WREN,
WRDI, RDSR
Clock frequency for READ instructions
fR
Typ.
Max.
Unit
D.C.
33
MHz
D.C.
20
MHz
(2)
tCLH
Clock High time
13
ns
tCL (2)
tCLL
Clock Low time
13
ns
Clock Slew Rate (peak to peak)
0.1
V/ns
S Active Setup time (relative to C)
10
ns
S Not Active Hold time (relative to C)
10
ns
tCH
tSLCH
tCSS
tCHSL
tDVCH
tDSU
Data In Setup time
3
ns
tCHDX
tDH
Data In Hold time
5
ns
tCHSH
S Active Hold time (relative to C)
5
ns
tSHCH
S Not Active Setup time (relative to C)
5
ns
100
ns
tSHSL
tSHQZ
(3)
tCSH
S Deselect time
tDIS
Output Disable time
12
ns
Clock Low to Output Valid
12
ns
tCLQV
tV
tCLQX
tHO
Output Hold time
0
ns
tTHSL
Top Sector Lock Setup time
50
ns
tSHTL
Top Sector Lock Hold time
100
ns
tDP
(3)
tRDP
(3)
S to Deep Power-down
3
µs
S High to Standby Power mode
30
µs
25
ms
0.4+
n*0.8/256
5
ms
Page Write cycle time (256 bytes)
tPW (4)
Page Write cycle time (n bytes)
Page Program cycle time (256 bytes)
tPP (4)
Page Program cycle time (n bytes)
11
10.2+
n*0.8/256
1.2
tPE
Page Erase cycle time
10
20
ms
tSE
Sector Erase cycle time
1
5
s
1. Details of how to find the date of marking are given in application note, AN1995.
2. tCH + tCL must be greater than or equal to 1/ fC.
3. Value guaranteed by characterization, not 100% tested in production.
4. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
49/62
DC and AC parameters
Table 21.
M25PE40
AC characteristics (50 MHz operation, T9HX (0.11µm) process(1))(2)
Test conditions specified in Table 14 and Table 15
Symbol
Alt.
Parameter
Min.
fC
fC
Clock frequency for the following instructions:
FAST_READ, RDLR, PW, PP, WRLR, PE, SE,
SSE, DP, RDP, WREN, WRDI, RDSR, WRSR
Clock frequency for READ instructions
fR
tCH(3)
tCL(3)
Max.
Unit
D.C.
50
MHz
D.C.
33
MHz
tCLH
Clock High time
9
ns
tCLL
Clock Low time
9
ns
0.1
V/ns
S Active Setup time (relative to C)
5
ns
S Not Active Hold time (relative to C)
5
ns
Clock Slew Rate (peak to peak)
tSLCH
Typ.
tCSS
tCHSL
tDVCH
tDSU
Data In Setup time
2
ns
tCHDX
tDH
Data In Hold time
5
ns
tCHSH
S Active Hold time (relative to C)
5
ns
tSHCH
S Not Active Setup time (relative to C)
5
ns
100
ns
tSHSL
tCSH
S Deselect time
tSHQZ(4)
tDIS
Output Disable time
tCLQV
tV
tCLQX
tHO
Clock Low to Output Valid under 30 pF/10 pF
8
ns
8/6
ns
Output Hold time
0
ns
tWHSL
(5)
Write Protect Setup time
50
ns
tSHWL
(5)
Write Protect Hold time
100
ns
tDP(4)
tRDP(4)
tW
tPW(6)
tPP(6)
S to Deep Power-down
3
µs
S High to Standby mode
30
µs
Write Status Register cycle time
3
15
ms
Page Write cycle time (256 bytes)
11
23
ms
Page Program cycle time (256 bytes)
0.8
3
ms
Page Program cycle time (n bytes)
int(n/8) × 0.025(7)
tPE
Page Erase cycle time
10
20
ms
tSE
Sector Erase cycle time
1.5
5
s
tSSE
Subsector Erase cycle time
80
150
ms
tBE
Bulk Erase cycle time
8
10
s
1. See Important note on page 6.
2. Details of how to find the technology process in the marking are given in AN1995, see also Section 13: Ordering
information.
3. tCH + tCL must be greater than or equal to 1/ fC.
4. Value guaranteed by characterization, not 100% tested in production.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
6. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
7. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
50/62
M25PE40
Table 22.
DC and AC parameters
AC characteristics (75 MHz operation, T9HX (0.11µm) process(1))(2)(3)(4)
Test conditions specified in Table 14 and Table 15
Symbol
Alt.
fC
fC
fR
Parameter
Min.
Typ.
Max.
Unit
Clock frequency for the following instructions:
FAST_READ, RDLR, PW, PP, WRLR, PE, SE,
SSE, DP, RDP, WREN, WRDI, RDSR, WRSR
D.C.
75
MHz
Clock frequency for READ instructions
D.C.
33
MHz
(5)
tCLH
Clock High time
6
ns
tCL(5)
tCLL
Clock Low time
6
ns
0.1
V/ns
S Active Setup time (relative to C)
5
ns
S Not Active Hold time (relative to C)
5
ns
tCH
Clock Slew Rate (peak to peak)
tSLCH
tCSS
tCHSL
tDVCH
tDSU
Data In Setup time
2
ns
tCHDX
tDH
Data In Hold time
5
ns
tCHSH
S Active Hold time (relative to C)
5
ns
tSHCH
S Not Active Setup time (relative to C)
5
ns
100
ns
tSHSL
tCSH
S Deselect time
tSHQZ(6)
tDIS
Output Disable time
tCLQV
tV
tCLQX
tHO
Clock Low to Output Valid
8
ns
8/6
ns
Output Hold time
0
ns
tWHSL
(7)
Write Protect Setup time
20
ns
tSHWL
(7)
Write Protect Hold time
100
ns
tDP(6)
tRDP(6)
tW
tPW
(8)
tPP(8)
S to Deep Power-down
3
µs
S High to Standby mode
30
µs
Write Status Register cycle time
3
15
ms
Page Write cycle time (256 bytes)
11
23
ms
Page Program cycle time (256 bytes)
0.8
int(n/8) ×
0.025(9)
3
ms
Page Program cycle time (n bytes)
tPE
Page Erase cycle time
10
20
ms
tSE
Sector Erase cycle time
1.5
5
s
tSSE
Subsector Erase cycle time
80
150
ms
tBE
Bulk Erase cycle time
8
10
s
1. See Important note on page 6.
2. Details of how to find the technology process in the marking are given in AN1995, see also Section 13: Ordering
information.
3. Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008.
4. Preliminary data.
5. tCH + tCL must be greater than or equal to 1/ fC.
6. Value guaranteed by characterization, not 100% tested in production.
7. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
51/62
DC and AC parameters
M25PE40
8. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
9. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Figure 26. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
MSB IN
D
tCLCH
LSB IN
High Impedance
Q
AI01447C
Figure 27. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold
timing
TSL or
W
tTHSL
tSHTL
tWHSL
tSHWL
S
C
D
High Impedance
Q
AI3559
1. For the differences between devices produced in the two processes, see Important note on page 6.
52/62
M25PE40
DC and AC parameters
Figure 28. Output timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D
ADDR.LSB IN
AI01449e
53/62
DC and AC parameters
Table 23.
M25PE40
Reset conditions
Test conditions specified in Table 14 and Table 15
Symbol
Alt.
Parameter
tRLRH(1)
tRST
Conditions
Reset pulse width
Chip Select High to
Reset High
tSHRH
Min.
Chip should have been
deselected before Reset is
de-asserted
Typ.
Max. Unit
10
µs
10
ns
1. Value guaranteed by characterization, not 100% tested in production.
Table 24.
Timings after a Reset Low pulse(1)(2)
Test conditions specified in Table 14 and Table 15
Symbol Alt.
Parameter
Conditions: Reset pulse occurred
Max.
Unit
While decoding an
WREN,
WRDI, RDID, RDSR, READ, RDLR,
Fast_Read, WRLR, PW, PP, PE, SE, BE,
SSE, DP, RDP
30
µs
Under completion of an Erase or Program
cycle of a PW, PP, PE, SE, BE operation
300
µs
3
ms
tW (see
Table 21)
ms
0
µs
instruction(3):
tRHSL
tREC
Reset
recovery time Under completion of an Erase cycle of an
SSE operation
Under completion of a WRSR operation
Device deselected (S High) and in Standby
mode
1. All the values are guaranteed by characterization, and not 100% tested in production.
2. See Table 12 for a description of the device status after a Reset Low pulse.
3.
S remains Low while Reset is Low.
Figure 29. Reset AC waveforms
S
tSHRH
Reset
tRHSL
tRLRH
AI06808
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M25PE40
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of second level interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
Figure 30. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package outline
A
D
aaa C A
R1
D1
E1
E2
e
bbb
E
M C A B
B
2x
b
0.10 C B
aaa C B
12
Package mechanical
D2
θ
0.10 C A
L
A2
ddd
A
C
A1 A3
70-ME
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 25.
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package mechanical data
millimeters
inches
Symbol
A
Typ
Min
Max
Typ
Min
Max
0.85
0.80
1.00
0.033
0.031
0.039
0.00
0.05
0.000
0.002
0.014
0.019
0.126
0.142
A1
A2
0.65
0.026
A3
0.20
b
0.40
D
6.00
0.236
D1
5.75
0.226
D2
3.40
0.008
0.35
3.20
0.48
3.60
0.016
0.134
E
5.00
0.197
E1
4.75
0.187
E2
4.00
3.80
4.30
0.157
0.150
0.169
e
1.27
–
–
0.050
–
–
R1
0.10
0.00
0.004
0.000
55/62
Package mechanical
Table 25.
M25PE40
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead
6 × 5 mm, package mechanical data (continued)
millimeters
inches
Symbol
L
56/62
Typ
Min
Max
Typ
Min
Max
0.60
0.50
0.75
0.024
0.020
0.029
Θ
12°
12°
aaa
0.15
0.006
bbb
0.10
0.004
ddd
0.05
0.002
M25PE40
Package mechanical
Figure 31. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
1. Drawing is not to scale.
Table 26.
SO8N – 8 lead plastic small outline, 150 mils body width, package
mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.75
Max
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.009
ccc
0.25
0.004
0.010
0.049
0.10
0.004
D
4.90
4.80
5.00
0.193
0.189
0.197
E
6.00
5.80
6.20
0.236
0.228
0.244
E1
3.90
3.80
4.00
0.154
0.150
0.157
e
1.27
–
–
0.050
–
–
h
0.25
0.50
0.010
0.020
k
0°
8°
0°
8°
L
0.40
1.27
0.016
0.050
L1
1.04
0.041
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Package mechanical
M25PE40
Figure 32. SO8W – 8 lead plastic small outline, 208 mils body width, package outline
A2
A
c
b
CP
e
D
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 27.
SO8W – 8 lead plastic small outline, 208 mils body width, package
mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
2.50
Max
0.098
A1
0.00
0.25
0.000
0.010
A2
1.51
2.00
0.059
0.079
b
0.40
0.35
0.51
0.016
0.014
0.020
c
0.20
0.10
0.35
0.008
0.004
0.014
CP
0.10
0.004
D
6.05
0.238
E
5.02
6.22
0.198
0.245
E1
7.62
8.89
0.300
0.350
–
–
–
–
k
0°
10°
0°
10°
L
0.50
0.80
0.020
0.031
N
8
e
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Max
1.27
0.050
8
M25PE40
13
Ordering information
Ordering information
Table 28.
Ordering information scheme
Example:
M25PE40
V MP 6
T
G
Device type
M25PE = page-erasable serial Flash memory
Device function
40 = 4 Mbit (512Kbit × 8)
Operating voltage
V = VCC = 2.7 to 3.6 V
Package
MW = SO8W (208 mils width)
MP = VFQFPN8 6 × 5 mm (MLP8)
MN = SO8N (150 mils width)(1)
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
1. Package only available for products in the T9HX process.
Note:
For a list of available options (speed, package, etc.), for further information on any aspect of
this device or when ordering parts operating at 75 MHz (0.11 µm, process digit ‘4’), please
contact your nearest Numonyx Sales Office.
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Revision history
14
M25PE40
Revision history
Table 29.
Document revision history
Date
Revision
01-Apr-2004
0.1
Initial release.
09-Nov-2004
1
Write Protect (W) pin replaced by Top Block Lock (TBL).
Section 2.5: Reset (Reset) description modified. JEDEC signature
modified. Reset timings tRLRH, tRHSL and tSHRH removed from
Table 20: AC characteristics (33 MHz operation) and inserted in
Table 21: Reset timings (tRHSL modified). Document status
promoted from target specification to preliminary data.
01-Dec-2004
2
Top Block Lock (TBL) renamed as Top Sector Lock (TSL). Small text
changes. Deep Power-down mode clarified in Section 4.6: Active
Power, Standby Power and Deep Power-down modes.
11-Jan-2005
3
Notes removed from Table 28: Ordering information scheme.
Wording changes. SO16 package removed, SO8 wide package
added.
4
Added Table 20: AC characteristics (33 MHz operation). Document
status promoted from preliminary data to full datasheet. Table 19:
AC characteristics (25 MHz operation) updated. Section 4.2: An
easy way to modify data, Section 4.3: A fast way to modify data,
Section 6.9: Page Write (PW) and Section 6.10: Page Program (PP)
updated to explain optimal use of Page Write and Page Program
instructions. Clock slew rate changed from 0.03 to 0.1 V/ns.
Updated Table 28: Ordering information scheme. Added
ECOPACK® information.
5
Changed document to new template; amended figure in Feature
summary; replaced Figure 4: Bus master and memory devices on
the SPI bus; amended data in Table 19 and Table 20; amended title
of Figure 30: VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat
package no lead 6 × 5 mm, package outline and added a footnote;
amended name of the MP package in Table 28: Ordering
information scheme.
4-Oct-2005
11-Aug 2006
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Changes
M25PE40
Revision history
Table 29.
Document revision history (continued)
Date
Revision
Changes
6
50 MHz frequency added. SO8N package added, VFQFPN and
SO8W package specifications updated (see Section 12: Package
mechanical).
The sectors are further divided up into subsectors (see Table 4:
Memory organization). Important note on page 6 added. Figure 4:
Bus master and memory devices on the SPI bus updated and
explanatory paragraph added. VCC supply voltage and VSS ground
added. Section 4.8: Protection modes modified. Section 8: Reset
added, reset timings table split into Table 23: Reset conditions and
Table 24: Timings after a Reset Low pulse.
At power-up the WIP bit is reset (see Section 7: Power-up and
power-down).
VIO max changed in Table 13: Absolute maximum ratings. End
timing line of tSHQZ moved in Figure 28: Output timing.
Products processed in T9HX process added to datasheet:
– WP pin replaces TSL (T7X technology), see Section 2.6: Write
Protect (W) or Top Sector Lock (TSL)
– Write Status Register (WRSR) and Subsector Erase (SSE)
instructions added for T9HX process
– subsector protection granularity removed in T9HX process, still
exists in T7X process
– Table 4: Memory organization updated to show subsectors
– Status Register BP2, BP1, BP0 bits and SRWD bit added.
Small text changes.
7
T7X process name corrected.
Write Enable Latch (WEL) bit is reset also on completion of the
Subsector Erase, Bulk Erase, Write to Lock Register and Write
Status Register instructions (see Section 6.2: Write Disable
(WRDI)).
Address bit A20 is not Don’t care (Note 1 modified) in the Sector
Erase (SE) instruction sequence. SO8N package is only available in
products manufactured in the T9HX process.
10-Dec-2007
8
Removed ‘low voltage’ from the title.
Table 18: DC characteristics (75 MHz operation, T9HX (0.11 µm)
process) and Table 22: AC characteristics (75 MHz operation, T9HX
(0.11µm) process) added.
Added ECOPACK® text in Section 12: Package mechanical.
Updated the value for the maximum clock frequency (from 50 to
75 MHz) through the document.
Minor text changes.
03-Jan-2007
9
Applied Numonyx branding.
15-Jan-2007
23-Jan-2007
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M25PE40
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these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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visiting Numonyx's website at http://www.numonyx.com.
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