Intersil ISL78841ASRH High performance industry standard single-ended current mode pwm controller Datasheet

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
The ISL7884xASRH is a high performance, radiation
hardened drop-in replacement for the popular 28C4x and
18C4x PWM controllers suitable for a wide range of
power conversion applications including boost, flyback,
and isolated output configurations. Its fast signal
propagation and output switching characteristics make
this an ideal product for existing and new designs.
Features include up to 13.2V operation, low operating
current, 90µA typ start-up current, adjustable operating
frequency to 1MHz, and high peak current drive
capability with 50ns rise and fall times.
PART NUMBER
RISING UVLO
MAX. DUTY CYCLE
ISL78840ASRH
7.0
100%
ISL78841ASRH
7.0
50%
ISL78843ASRH
8.4V
100%
ISL78845ASRH
8.4V
50%
Features
• Electrically Screened to DSCC SMD # 5962-07249
• QML Qualified Per MIL-PRF-38535 Requirements
• 1A MOSFET Gate Driver
• 90µA Typ Start-up Current, 125µA Max
• 35ns Propagation Delay Current Sense to Output
• Fast Transient Response with Peak Current Mode
Control
• 9V to 13.2V Operation
• Adjustable Switching Frequency to 1MHz
• 50ns Rise and Fall Times with 1nF Output Load
• Trimmed Timing Capacitor Discharge Current for
Accurate Deadtime/Maximum Duty Cycle Control
• 1.5MHz Bandwidth Error Amplifier
• Tight Tolerance Voltage Reference Over Line, Load
and Temperature
Specifications for Rad Hard QML devices are
controlled by the Defense Supply Center in
Columbus (DSCC). The SMD numbers listed in the
ordering information must be used when ordering.
Detailed Electrical Specifications for the
ISL788xASRH are contained in SMD 5962-07249. A
“hot-link” is provided on our website for
downloading.
• ±3% Current Limit Threshold
• Pb-Free Available (RoHS Compliant)
Applications
• Current Mode Switching Power Supplies
• Isolated Buck and Flyback Regulators
• Boost Regulators
• Direction and Speed Control in Motors
• Control of High Current FET Drivers
Pin Configurations
ISL78840ASRH, ISL78841ASRH,
ISL78843ASRH, ISL78845ASRH
(8 LD SBDIP)
TOP VIEW
ISL78840ASRH, ISL78841ASRH,
ISL78843ASRH, ISL78845ASRH
(8 LD FLATPACK)
TOP VIEW
COMP
1
8
VREF
FB
2
7
VDD
CS
3
6
OUT
RTCT
4
5
GND
August 19, 2010
FN6991.1
1
COMP
1
8
VREF
FB
2
7
VDD
CS
3
6
OUT
RTCT
4
5
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL78840ASRH, ISL78841ASRH,
ISL78843ASRH, ISL78845ASRH
Radiation Hardened, High Performance Industry
Standard Single-Ended Current Mode PWM
Controller
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Ordering Information
ORDERING NUMBER
PART NUMBER
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL78840ASRHVX/SAMPLE
ISL78840ASRHVX/SAMPLE
-55 to +125
Die
ISL78840ASRHF/PROTO
ISL78840ASRHF/PROTO (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
5962R0724901QXC
ISL78840ASRHQF (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
5962R0724901VXC
ISL78840ASRHVF (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
ISL78840ASRHD/PROTO
ISL78840ASRHD/PROTO (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
5962R0724901QPC
ISL78840ASRHQD (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
5962R0724901VPC
ISL78840ASRHVD (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
ISL78841ASRHVX/SAMPLE
ISL78841ASRHVX/SAMPLE
-55 to +125
Die
ISL78841ASRHF/PROTO
ISL78841ASRHF/PROTO (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
5962R0724902QXC
ISL78841ASRHQF (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
5962R0724902VXC
ISL78841ASRHVF (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
ISL78841ASRHD/PROTO
ISL78841ASRHD/PROTO (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
5962R0724902QPC
ISL78841ASRHQD (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
5962R0724902VPC
ISL78841ASRHVD (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
ISL78843ASRHVX/SAMPLE
ISL78843ASRHVX/SAMPLE
-55 to +125
Die
ISL78843ASRHF/PROTO
ISL78843ASRHF/PROTO (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
5962R0724903QXC
ISL78843ASRHQF (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
5962R0724903VXC
ISL78843ASRHVF (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
ISL78843ASRHD/PROTO
ISL78843ASRHD/PROTO (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
5962R0724903QPC
ISL78843ASRHQD (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
5962R0724903VPC
ISL78843ASRHVD (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
ISL78845ASRHVX/SAMPLE
ISL78845ASRHVX/SAMPLE
-55 to +125
Die
ISL78845ASRHF/PROTO
ISL78845ASRHF/PROTO (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
5962R0724904QXC
ISL78845ASRHQF (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
5962R0724904VXC
ISL78845ASRHVF (Notes 1, 2)
-55 to +125
8 Ld Flatpack
K8.A
ISL78845ASRHD/PROTO
ISL78845ASRHD/PROTO (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
5962R0724904QPC
ISL78845ASRHQD (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
5962R0724904VPC
ISL78845ASRHVD (Notes 1, 2)
-55 to +125
8 Ld SBDIP
D8.3
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant
and compatible with both SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL78840ASRH, ISL78841ASRH, ISL78843ASRH,
ISL78845ASRH. For more information on MSL please see techbrief TB363.
2
FN6991.1
August 19, 2010
Functional Block Diagram
+
-
VREF
VREF
5V
START/STOP
UV COMPARATOR
ENABLE
VDD OK
VREF FAULT
+-
+
2.5V
A
4.65V
4.80V
+-
3
VREF
UV COMPARATOR
GND
A = 0.5
PWM
COMPARATOR
+-
CS
100mV
2R
1.1V
CLAMP
+
-
FB
VF TOTAL = 1.15V
ERROR
AMPLIFIER
+
-
ONLY
ISL78841A,
ISL78845A
R
Q
T
COMP
Q
OUT
S Q
36k
R Q
RESET
DOMINANT
VREF
100k
2.9V
1.0V
ON
150k
OSCILLATOR
COMPARATOR
<10ns
+
RTCT
8.4mA
FN6991.1
August 19, 2010
ON
CLOCK
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
VDD
Typical Application - 48V Input Dual Output Flyback
CR5
T1
+ C16
R21
VIN+
R3
+ C15
+1.8V
C4
CR4
C2
C17
CR2
4
C5
+
C22
+
C20
C19
RETURN
CR6
R1
36V TO 75V
R16
R17
C6
C1
C3
R18
R19
U2
Q1
C14
R28
R4
R22
C13
R15
U3
VIN-
R27
R20
U4
R26
COMP
VREF
CS
V DD
FB
OUT
RTCT
GND
ISL7884xASRH
R6
R10
CR1
Q3
C12
VR1
C8
R13
C11
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
+3.3V
C21
Typical Application - Boost Converter
R8
C10
VIN+
+VOUT
+
C2
C3
5
RETURN
R4
Q1
R5
R9
C9
C1
R1
R2
U1
FB
CS
C4
RTCT
ISL7884xASRH
COMP
R7
VREF
VIN+
VDD
OUT
GND
R3
C5
C7
VIN-
C6
C8
R6
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
CR1
L1
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and
Typical Application schematic on page 3 and page 4. VDD = 13.2V, RT = 10kΩ, CT = 3.3nF,
TA = -55 to +125°C. Typical values are at TA = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL78840A, ISL78841A
-
7.0
-
V
ISL78843A, ISL78845A
-
8.4
-
V
ISL78840A, ISL78841A
-
6.6
-
V
ISL78843A, ISL78845A
-
7.6
-
V
UNDERVOLTAGE LOCKOUT
START Threshold
STOP Threshold
Hysteresis
ISL78840A, ISL78841A
-
0.4
-
V
ISL78843A, ISL78845A
-
0.8
-
V
VDD < START Threshold
-
90
-
µA
VDD < START Threshold, 100krad
-
300
-
µA
Operating Current, IDD
(Note 3)
-
2.9
-
mA
Operating Supply Current, ID
Includes 1nF GATE loading
-
4.75
-
mA
Overall Accuracy
Over line (VDD = 9V to 13.2V),
load 1mA and 10mA, temperature
-
5.000
-
V
Long Term Stability
TA = +125°C, 1000 hours (Note 4)
Start-up Current, IDD
REFERENCE VOLTAGE
-
5
-
mV
Current Limit, Sourcing
-
-
-
mA
Current Limit, Sinking
-
-
-
mA
-
-
-
µA
-
1.00
-
V
-
3.0
-
V/V
-
35
-
ns
CURRENT SENSE
VCS = 1V
Input Bias Current
Input Signal, Maximum
Gain, ACS = ΔVCOMP/ΔVCS
0 < VCS < 910mV, VFB = 0V
CS to OUT Delay
ERROR AMPLIFIER
Open Loop Voltage Gain
(Note 4)
-
90
-
dB
Unity Gain Bandwidth
(Note 4)
-
1.5
-
MHz
Reference Voltage
VFB = VCOMP
-
2.500
-
V
FB Input Bias Current
VFB = 0V
-
-0.2
-
µA
COMP Sink Current
VCOMP = 1.5V, VFB = 2.7V
-
-
-
mA
COMP Source Current
VCOMP = 1.5V, VFB = 2.3V
-
-
-
mA
COMP VOH
VFB = 2.3V
-
-
-
V
COMP VOL
VFB = 2.7V
-
-
-
V
PSRR
Frequency = 120Hz, VDD = 9V to
13.2V (Note 4)
-
80
-
dB
OSCILLATOR
Frequency Accuracy
Initial, TA = +25°C
-
51
-
kHz
Frequency Variation with VDD
TA= +25°C, (f13.2V - f9V)/f12V
-
0.2
-
%
Temperature Stability
(Note 4)
-
5
-
%
Amplitude, Peak-to-Peak
Static Test
-
1.75
-
V
RTCT Discharge Voltage (Valley Voltage)
Static Test
-
1.0
-
V
Discharge Current
RTCT = 2.0V
-
7.8
-
mA
OUTPUT
6
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Electrical Specifications
PARAMETER
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and
Typical Application schematic on page 3 and page 4. VDD = 13.2V, RT = 10kΩ, CT = 3.3nF,
TA = -55 to +125°C. Typical values are at TA = +25°C.
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Gate VOH
VDD to OUT, IOUT = -100mA
-
1.0
-
V
Gate VOL
OUT to GND, IOUT = 100mA
-
1.0
-
V
Peak Output Current
COUT = 1nF (Note 4)
-
1.0
-
A
Rise Time
COUT = 1nF
-
35
-
ns
Fall Time
COUT = 1nF
-
20
-
ns
OUTPUT OFF state leakage
VDD = 5V
-
-
-
µA
Maximum Duty Cycle
(ISL78840A, ISL78843A)
COMP = VREF
-
96.0
-
%
Maximum Duty Cycle
(ISL78841A, ISL78845A)
COMP = VREF
-
48.0
-
%
Minimum Duty Cycle
COMP = GND
-
-
-
%
PWM
NOTES:
3. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.
4. Limits established by characterization and are not production tested.
5. SEE tests performed with VREF bypass capacitor of 0.22µF and FSW = 200kHz. SEB/L tests done on a standalone open loop
configuration. SET tests done in a closed loop configuration. For SEL no hard latch requiring manual intervention were
observed. For more information see SEE test Report xxxx.
7
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Typical Performance Curves
NORMALIZED FREQUENCY
1.01
1.001
NORMALIZED VREF
1.000
1.00
0.99
0.98
-60 -40 -20
0
20
40
60
80
0.999
0.998
0.997
0.996
0.995
-60
100 120 140
TEMPERATURE (°C)
0
20 40 60 80
TEMPERATURE (°C)
100 120 140
103
FREQUENCY (kHz)
1.001
NORMALIZED EA REFERENCE
-20
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 1. FREQUENCY vs TEMPERATURE
1.000
0.998
0.997
0.996
-60
-40
220pF
330pF
470pF
-20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
FIGURE 3. EA REFERENCE vs TEMPERATURE
Pin Descriptions
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set
by connecting a resistor, RT, between VREF and this pin
and a timing capacitor, CT, from this pin to GND. The
oscillator produces a sawtooth waveform with a
programmable frequency range up to 2.0MHz. The
charge time, tC, the discharge time, tD, the switching
frequency, f, and the maximum duty cycle, DMAX, can be
approximated from the Equations 1 through 4:
1.0nF
10
2.2nF
3.3nF
4.7nF
6.8nF
1
-40
100pF
100
1
10
RT (kΩ)
100
FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES
GIVEN
COMP - COMP is the output of the error amplifier and
the input of the PWM comparator. The control loop
frequency compensation network is connected between
the COMP and FB pins.
FB - The output voltage feedback is connected to the
inverting input of the error amplifier through this pin. The
non-inverting input of the error amplifier is internally tied
to a reference voltage.
t C ≈ 0.533 ⋅ RT ⋅ CT
(EQ. 1)
CS - This is the current sense input to the PWM
comparator. The range of the input signal is nominally 0V
to 1.0V and has an internal offset of 100mV.
0.008 ⋅ RT – 3.83
t D ≈ – RT ⋅ CT ⋅ In ⎛ --------------------------------------------- ⎞
⎝ 0.008 ⋅ RT – 1.71 ⎠
(EQ. 2)
GND - GND is the power and small signal reference
ground for all functions.
f = 1 ⁄ (tC + tD)
(EQ. 3)
D = tC ⋅ f
(EQ. 4)
The formulae have increased error at higher frequencies
due to propagation delays. Figure 4 may be used as a
guideline in selecting the capacitor and resistor values
required for a given switching frequency for the
ISL78841, ISL78845ASRH. The value for the ISL78840,
ISL78843ASRH will be twice that shown in Figure 4.
8
OUT - This is the drive output to the power switching
device. It is a high current output capable of driving the
gate of a power MOSFET with peak currents of 1.0A. This
GATE output is actively held low when VDD is below the
UVLO threshold.
VDD - VDD is the power connection for the device. The
total supply current will depend on the load applied to
OUT. Total IDD current is the sum of the operating
current and the average output current. Knowing the
operating frequency, f, and the MOSFET gate charge, Qg,
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
the average output current can be calculated from
Equation 5:
(EQ. 5)
I OUT = Qg × f
To optimize noise immunity, bypass VDD to GND with a
ceramic capacitor as close to the VDD and GND pins as
possible.
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. The
recommended bypass to GND cap is in the range 0.1µF
to 0.22µF. A typical value of 0.15µF can be used.
Functional Description
Features
The ISL7884xASRH current mode PWM makes an ideal
choice for low-cost flyback and forward topology
applications. With its greatly improved performance over
industry standard parts, it is the obvious choice for new
designs or existing designs which require updating.
Oscillator
The ISL7884xASRH has a sawtooth oscillator with a
programmable frequency range to 2MHz, which can be
programmed with a resistor from VREF and a capacitor to
GND on the RTCT pin. (Please refer to Figure 4 for the
resistor and capacitance required for a given frequency).
Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.
COMP
Q1
GND
C1
ISL7884xASRH
R1
The ISL7884xASRH is capable of sourcing and sinking 1A
peak current. To limit the peak current through the IC, an
optional external resistor may be placed between the
totem-pole output of the IC (OUT pin) and the gate of
the MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance. TID environment of >50krads requires the
use of a bleeder resistor of 10k from OUT pin to GND.
Slope Compensation
For applications where the maximum duty cycle is less
than 50%, slope compensation may be used to improve
noise immunity, particularly at lighter loads. The amount
of slope compensation required for noise immunity is
determined empirically, but is generally about 10% of the
full scale current feedback signal. For applications where
the duty cycle is greater than 50%, slope compensation
is required to prevent instability.
Slope compensation may be accomplished by summing
an external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback
error signal. Adding the external ramp to the current
feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation is calculated in Equation 6:
1
Fm = -------------------SnTsw
1
1
Fm = ------------------------------------- = -------------------------( Sn + Se )tsw
m c Sntsw
FIGURE 5. SOFT-START
The COMP pin is clamped to the voltage on capacitor C1
plus a base-emitter junction by transistor Q1. C1 is
charged from VREF through resistor R1 and the base
current of Q1. At power-up C1 is fully discharged, COMP
is at ~0.7V, and the duty cycle is zero. As C1 charges,
the voltage on COMP increases, and the duty cycle
increases in proportion to the voltage on C1. When COMP
reaches the steady state operating point, the control loop
takes over and soft start is complete. C1 continues to
charge up to VREF and no longer affects COMP. During
power down, diode D1 quickly discharges C1 so that the
soft start circuit is properly initialized prior to the next
power on sequence.
(EQ. 7)
where Se is slope of the external ramp and becomes
Equation 8:
Se
m c = 1 + ------Sn
9
(EQ. 6)
where Sn is the slope of the sawtooth signal and tsw is
the duration of the half-cycle. When an external ramp is
added, the modulator gain becomes Equation 7:
VREF
D1
Gate Drive
(EQ. 8)
The criteria for determining the correct amount of
external ramp can be determined by appropriately
setting the damping factor of the double-pole located at
the switching frequency. The double-pole will be critically
damped if the Q-factor is set to 1, over-damped for Q <
1, and under-damped for Q > 1. An under-damped
condition may result in current loop instability.
1
Q = ------------------------------------------------π ( m c ( 1 – D ) – 0.5 )
(EQ. 9)
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
where D is the percent of on time during a switching
cycle. Setting Q = 1 and solving for Se yields
Equation 10:
1
1
S e = S n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝π
⎠
RTCT signal with the current sense feedback and applies
the result to the CS pin as shown in Figure 6.
(EQ. 10)
VREF
1
1
V e = V n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝π
⎠
R9
RTCT
(EQ. 11)
C4
where Vn is the change in the current feedback signal
(ΔI) during the on time and Ve is the voltage that must
be added by the external ramp.
For a flyback converter, Vn can be solved for in terms of
input voltage, current transducer components, and
primary inductance, yielding Equation 12:
D ⋅ T SW ⋅ V IN ⋅ R CS 1
1
V e = ---------------------------------------------------- ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝π
⎠
Lp
V
(EQ. 12)
where RCS is the current sense resistor, fsw is the
switching frequency, Lp is the primary inductance, VIN is
the minimum input voltage, and D is the maximum duty
cycle.
The current sense signal at the end of the ON time for
CCM operation is Equation 13:
( 1 – D ) ⋅ VO ⋅ f ⎞
N S ⋅ R CS ⎛
sw
V CS = ------------------------ ⎜ I O + --------------------------------------------⎟
2L s
NP
⎝
⎠
V
(EQ. 13)
where VCS is the voltage across the current sense
resistor, Ls is the secondary winding inductance, and IO is
the output current at current limit. Equation 13 assumes
the voltage drop across the output rectifier is negligible.
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage
must sum to this value when the output load is at the
current limit threshold as shown in Equation 14.
(EQ. 14)
V e + V CS = 1
Substituting Equations 12 and 13 into Equation 14 and
solving for RCS yields Equation 15:
1
R CS = ----------------------------------------------------------------------------------------------------------------------------------------------------1
-+
0.5
⎛
⎞
( 1 – D ) ⋅ V O ⋅ f sw⎞
D ⋅ f sw ⋅ V IN π
Ns ⎛
------------------------------⋅ ⎜ ------------------ – 1⎟ + ------- ⋅ ⎜ I O + --------------------------------------------⎟
⎜ 1–D
⎟ N ⎝
Lp
2L s
⎠
p
⎝
⎠
(EQ. 15)
Adding slope compensation is accomplished in the
ISL7884xASRH using an external buffer transistor and
the RTCT signal. A typical application sums the buffered
10
CS
R6
ISL78843ASRH
Since Sn and Se are the on time slopes of the current
ramp and the external ramp, respectively, they can be
multiplied by tON to obtain the voltage change that
occurs during tON.
FIGURE 6. SLOPE COMPENSATION
Assuming the designer has selected values for the RC
filter (R6 and C4) placed on the CS pin, the value of R9
required to add the appropriate external ramp can be
found by superposition.
2.05D ⋅ R 6
V e = ---------------------------R6 + R9
(EQ. 16)
V
The factor of 2.05 in Equation 16 arises from the peak
amplitude of the sawtooth waveform on RTCT minus a
base-emitter junction drop. That voltage multiplied by
the maximum duty cycle is the voltage source for the
slope compensation. Rearranging to solve for R9 yields
Equation 17:
( 2.05D – V e ) ⋅ R 6
R 9 = ---------------------------------------------Ve
(EQ. 17)
Ω
The value of RCS determined in Equation 15 must be
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 13. The divider
created by R6 and R9 makes this necessary.
R6 + R9
R′ CS = --------------------- ⋅ R CS
R9
(EQ. 18)
Example:
VIN = 12V
VO = 48V
Ls = 800µH
Ns/Np = 10
Lp = 8.0µH
IO = 200mA
Switching Frequency, fsw = 200kHz
Duty Cycle, D = 28.6%
R6 = 499Ω
Solve for the current sense resistor, RCS, using
Equation 15.
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
RCS = 295mΩ
Determine the amount of voltage, Ve, that must be
added to the current feedback signal using Equation 12.
Ve = 92.4mV
Using Equation 17, solve for the summing resistor, R9,
from CT to CS.
R9 = 2.67kΩ
Determine the new value of RCS (R’CS) using
Equation 18.
R’CS = 350mΩ
Additional slope compensation may be considered for
design margin. The above discussion determines the
minimum external ramp that is required. The buffer
transistor used to create the external ramp from RTCT
should have a sufficiently high gain (>200) so as to
minimize the required base current. Whatever base
current is required reduces the charging current into
RTCT and will reduce the oscillator frequency.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected OUT is disabled. When VREF exceeds
4.80V, the Fault condition clears, and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of
the device. A good ground plane must be employed. A
unique section of the ground plane must be designated
for high di/dt currents associated with the output stage.
VDD should be bypassed directly to GND with good high
frequency capacitors.
References
[1] Ridley, R., “A New Continuous-Time Model for
Current Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
11
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Die Map
12
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
4/22/10
FN6991.1
Added Electrical Spec Table showing only the typical values. Removed boldface over-temp limit
notes.
4/8/10
12/21/09
Added SBDIP parts, pinout and Flatpack & SBDIP PODs.
FN6991.0
Initial pre-release
Products
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information page on intersil.com: ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
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13
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Package Outline Drawing
K8.A
8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 1, 1/10
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
0.050 (1.27 BSC)
0.005 (0.13)
MIN
4
PIN NO. 1
ID AREA
0.022 (0.56)
0.015 (0.38)
0.115 (2.92)
0.070 (1.18)
0.265 (6.73)
0.245 (6.22)
TOP VIEW
0.026 (0.66) MIN
0.09 (0.23)
0.04 (0.10)
6
0.265 (6.75)
0.245 (6.22)
-D-
-H-
-C0.180 (4.57)
0.170 (4.32)
SEATING AND
BASE PLANE
0.370 (9.40)
0.250 (6.35)
0.03 (0.76) MIN
SIDE VIEW
0.007 (0.18)
0.004 (0.10)
NOTES:
LEAD FINISH
BASE
METAL
0.009 (0.23)
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
0.004 (0.10)
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
4. Measure dimension at all four corners.
3
SECTION A-A
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
14
FN6991.1
August 19, 2010
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
-A-
D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)
LEAD FINISH
8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-DBASE
METAL
E
b1
M
(b)
M
-Bbbb S C A - B S
(c)
SECTION A-A
D S
D
BASE
PLANE
Q
S2
-C-
SEATING
PLANE
A
L
S1
eA
A A
b2
b
e
eA/2
c
aaa M C A - B S D S
ccc M C A - B S D S
NOTES:
INCHES
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
-
E
0.220
0.310
5.59
7.87
-
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
N
8
8
5. Dimension Q shall be measured from the seating plane to the
base plane.
8
Rev. 0 4/94
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
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15
FN6991.1
August 19, 2010
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