STMicroelectronics M48T59VSH 64 kbit 8kb x8 timekeeper sram Datasheet

M48T59
M48T59Y/M48T59V
64 Kbit (8Kb x8) TIMEKEEPER® SRAM
PRELIMINARY DATA
■
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
■
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK SOFTWARE CALIBRATION
■
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T59: 4.5V ≤ VPFD ≤ 4.75V
– M48T59Y: 4.2V ≤ VPFD ≤ 4.5V
– M48T59V: 2.7V ≤ VPFD ≤ 3.0V
■
SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
■
PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT® TOP
(to be Ordered Separately)
■
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
■
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
■
PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACK-UP MODE
■
BATTERY LOW FLAG
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
IRQ/FT
Interrupt / Frequency Test
Output (Open Drain)
RST
Power Fail Reset Output
(Open Drain)
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
SNAPHAT (SH)
Battery/Crytstal
28
1
28
PCDIP28 (PC)
Battery/Crystal
CAPHAT
1
SOH28 (MH)
Figure 1. Logic Diagram
VCC
13
8
A0-A12
W
E
DQ0-DQ7
M48T59
M48T59Y
M48T59V
IRQ/FT
RST
G
VSS
AI01380E
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/21
M48T59, M48T59Y, M48T59V
Figure 2A. DIP Connections
RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 2B. SOIC Connections
28
1
27
2
26
3
25
4
24
5
23
6
7
M48T59 22
8 M48T59Y 21
20
9
19
10
18
11
17
12
13
16
14
15
VCC
W
IRQ/FT
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
27
2
26
3
25
4
24
5
23
6
7 M48T59Y 22
8 M48T59V 21
20
9
19
10
18
11
17
12
16
13
15
14
AI01381D
VCC
W
IRQ/FT
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI01382E
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
TSTG
TSLD (2)
Parameter
Value
Ambient Operating Temperature
Grade 1
0 to 70
Grade 6
–40 to 85
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
Unit
°C
–40 to 85
°C
260
°C
–0.3 to 7
V
VIO
Input or Output Voltages
VCC
Supply Voltage
IO
Output Current
20
mA
PD
Power Dissipation
1
W
M48T59/M48T59Y
–0.3 to 7
M48T59V
–0.3 to 4.6
V
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes (1)
Mode
Deselect
Write
Read
Read
Deselect
Deselect
VCC
E
G
W
DQ7-DQ0
Power
4.75V to 5.5V
or
4.5V to 5.5V
or
3.0V to 3.6V
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS Standby
X
X
X
High Z
Battery Back-up Mode
VSO to VPFD (min)
≤ VSO
(2)
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
2/21
M48T59, M48T59Y, M48T59V
Figure 3. Block Diagram
IRQ/FT
OSCILLATOR AND
CLOCK CHAIN
16 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A12
POWER
DQ0-DQ7
8176 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VCC
W
VPFD
G
RST
VSS
AI01383D
DESCRIPTION
The M48T59/59Y/59V TIMEKEEPER ® RAM is an
8Kb x8 non-volatile static RAM and real time clock.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory and real time clock solution.
The M48T59/59Y/59V is a non-volatile pin and
function equivalent to any JEDEC standard 8Kb x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed.
The 28 pin 600mil DIP CAPHAT™ houses the
M48T59/59Y/59V silicon with a quartz crystal and
a long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to
the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
Table 4. AC Measurement Conditions
≤ 5ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Figure 4. AC Testing Load Circuit
645Ω
DEVICE
UNDER
TEST
CL = 100pF
CL includes JIG capacitance
1.75V
AI02325
Note: Excluding open-drain output pins.
3/21
M48T59, M48T59Y, M48T59V
Table 5. Capacitance (1, 2)
(TA = 25 °C)
Symbol
CIN
CIO (3)
Parameter
Test Condition
Input Capacitance
Input / Output Capacitance
Min
Max
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
M48T59/Y
Symbol
Parameter
M48T59V
Test Condition
Unit
Min
ILI (1)
Input Leakage Current
ILO (1)
Output Leakage Current
Max
Min
Max
0V ≤ VIN ≤ VCC
±1
±1
µA
0V ≤ VOUT ≤ VCC
±1
±1
µA
Outputs open
50
30
mA
ICC
Supply Current
ICC1
Supply Current (Standby)
TTL
E = VIH
3
2
mA
ICC2
Supply Current (Standby)
CMOS
E = VCC – 0.2V
3
1
mA
VIL (2)
Input Low Voltage
–0.3
0.8
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
2
VCC + 0.3
V
VOL
VOH
Output Low Voltage
IOL = 2.1mA
0.4
0.4
V
Output Low Voltage (IRQ/FT
and RST) (3)
IOL = 10mA
0.4
0.4
V
Output High Voltage
IOH = –1mA
2.4
2.4
V
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
3. The IRQ/FT and RST pins are Open Drain.
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C)
Symbol
VPFD
VSO
tDR
Parameter
Power-fail Deselect Voltage
Min
Typ
Max
Unit
M48T59
4.5
4.6
4.75
V
M48T59Y
4.2
4.35
4.5
V
M48T59V
2.7
2.9
3.0
V
M48T59/Y
3.0
V
M48T59V
VPFD –100mV
V
Battery Back-up Switchover Voltage
Grade 1
7
YEARS
Grade 6
10 (2)
YEARS
ExpectedDataRetentionTime(at25°C)
Note: 1. All voltages referenced to VSS.
2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
4/21
M48T59, M48T59Y, M48T59V
Table 8. Power Down/Up AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C)
Symbol
tPD
Parameter
Min
E or W at VIH before Power Down
tF (1)
VPFD (max) to VPFD (min) VCC Fall Time
tFB (2)
VPFD (min) to VSS VCC Fall Time
Max
Unit
0
µs
300
µs
M48T59/Y
10
µs
M48T59V
150
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
VPFD (max) to RST High
40
tREC (3)
200
ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes V PFD (min).
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
3. tREC (min) = 20ms for industrial temperature grade 6 device.
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tPD
tRB
tDR
tREC
RST
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI03258
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number
is "M4T28-BR12SH" or “M4T32-BR12SH”.
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T59/59Y/59V are integrated on one silicon
chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format (except
for the century). Corrections for 28, 29 (leap year),
30, and 31 day months are made automatically.
Byte 1FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
5/21
M48T59, M48T59Y, M48T59V
Table 9. Read Mode AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
M48T59/M48T59Y/M48T59V
Symbol
Parameter
-70
Min
tAVAV
Read Cycle Time
Unit
Max
70
ns
tAVQV (1)
Address Valid to Output Valid
70
ns
tELQV (1)
Chip Enable Low to Output Valid
70
ns
tGLQV (1)
Output Enable Low to Output Valid
35
ns
tELQX (2)
Chip Enable Low to Output Transition
5
ns
tGLQX (2)
Output Enable Low to Output Transition
5
ns
tEHQZ (2)
Chip Enable High to Output Hi-Z
25
ns
tGHQZ (2)
Output Enable High to Output Hi-Z
25
ns
tAXQX (1)
Address Transition to Output Transition
10
ns
Note: 1. CL = 100pF (see Fig 4).
2. CL = 5pF (see Fig 4).
Figure 6. Read Mode AC Waveforms.
tAVAV
A0-A12
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01385
Note: Write Enable (W) = High.
6/21
M48T59, M48T59Y, M48T59V
Table 10. Write Mode AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
M48T59/M48T59Y/M48T59V
Symbol
Parameter
-70
Min
Unit
Max
tAVAV
Write Cycle Time
70
ns
tAVWL
Address Valid to Write Enable Low
0
ns
tAVEL
Address Valid to Chip Enable Low
0
ns
tWLWH
Write Enable Pulse Width
50
ns
tELEH
Chip Enable Low to Chip Enable High
55
ns
tWHAX
Write Enable High to Address Transition
0
ns
tEHAX
Chip Enable High to Address Transition
0
ns
tDVWH
Input Valid to Write Enable High
30
ns
tDVEH
Input Valid to Chip Enable High
30
ns
tWHDX
Write Enable High to Input Transition
5
ns
tEHDX
Chip Enable High to Input Transition
5
ns
tWLQZ (1, 2)
Write Enable Low to Output Hi-Z
25
ns
tAVWH
Address Valid to Write Enable High
60
ns
tAVE1H
Address Valid to Chip Enable High
60
ns
Write Enable High to Output Transition
5
ns
tWHQX (1, 2)
Note: 1. CL = 5pF (see Fig 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ read/write memory cells.
The M48T59/59Y/59V includes a clock control circuit which updates the clock bytes with current information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T59/59Y/59V also has its own Power-fail
Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance
condition. When V CC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operation brought on by low V CC. As VCC falls
below approximately 3V, the control circuitry connects the battery which maintains data and clock
operation until valid power returns.
READ MODE
The M48T59/59Y/59V is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable)
is low. The unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access
time (t AVQV) after the last address input signal is
stable, providing that the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access time (tELQV) or Output
Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated before t AVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
7/21
M48T59, M48T59Y, M48T59V
Figure 7. Write Enable Controlled, Write AC Waveform
tAVAV
VALID
A0-A12
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01386
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01387B
8/21
M48T59, M48T59Y, M48T59V
WRITE MODE
The M48T59/59Y/59V is in the Write Mode whenever W and E are low. The start of a write is referenced from the latter occurring falling edge of W or
E. A write is terminated by the earlier rising edge
of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from Write Enable prior to the initiation of another
read or write cycle. Data-in must be valid tDVWH
prior to the end of write and remain valid for tWHDX
afterward. G should be kept high during write cycles to avoid bus contention; although, if the output
bus has been activated by a low on E and G a low
on W will disable the outputs tWLQZ after W falls.
DATA RETENTION MODE
With valid V CC applied, the M48T59/59Y/59V operates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V CC falls within the VPFD (max), VPFD
(min) window. All outputs become high impedance, and all inputs are treated as "don’t care."
Note: A power failure during a write cycle may corrupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below V PFD (min), the user can be assured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48T59/59Y/59V may respond to transient noise
spikes on VCC that reach into the deselect window
Table 11. Register Map
Data
Address
D7
1FFFh
D6
D5
D4
D3
D2
10 Years
10 M
D0
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Century/Day
00-01/01-07
Hours
Hour
00-23
1FFEh
0
0
1FFDh
0
0
1FFCh
0
FT
1FFBh
0
0
1FFAh
0
10 Minutes
Minutes
Minutes
00-59
1FF9h
ST
10 Seconds
Seconds
Seconds
00-59
1FF8h
W
R
S
1FF7h
WDS
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
Watchdog
1FF6h
AFE
Y
ABE
Y
Y
Y
Y
Y
Interrupts
1FF5h
RPT4
Y
Al. 10 Date
Alarm Date
Alarm Date
01-31
1FF4h
RPT3
Y
Al. 10 Hours
Alarm Hours
Alarm Hours
00-23
1FF3h
RPT2
Alarm 10 Minutes
Alarm Minutes
Alarm Minutes
00-59
1FF2h
RPT1
Alarm 10 Seconds
Alarm Seconds
Alarm Seconds
00-59
1FF1h
Y
Y
Y
Y
Y
Y
Y
Y
Unused
1FF0h
WDF
AF
Z
BL
Z
Z
Z
Z
Flags
Keys:
0
D1
Function/Range
BCD Format
10 Date
CB
CEB
0
Day
10 Hours
S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to zero
Y = ’1’ or ’0’
Z = ’0’ and are Read only
AF = Alarm Flag
BL = Battery Low
Calibration
Control
WDS = Watchdog Steering Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
CEB = Century Enable Bit
CB = Century Bit
9/21
M48T59, M48T59Y, M48T59V
during the time the device is sampling V CC. Therefore, decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which preserves data and powers the clock. The internal
button cell will maintain data in the M48T59/59Y/
59V for an accumulated period of at least 7 years
when VCC is less than V SO. As system power returns and V CC rises above VSO , the battery is disconnected, and the power supply is switched to
external VCC. Deselect continues for tREC after
VCC reaches VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
POWER-ON RESET
The M48T59/59Y/59V continuously monitors VCC.
When V CC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for 40ms to 200ms after V CC passes
VPFD. RST is valid for all VCC conditions. The RST
pin is an open drain output and an appropriate resistor to VCC should be chosen to control rise time.
PROGRAMMABLE INTERRUPTS
The M48T59/59Y/59V provides two programmable interrupts; an alarm and a watchdog. When an
interrupt condition occurs, the M48T59/59Y/59V
sets the appropriate flag bit in the flag register
1FF0h. The interrupt enable bits in (AFE and ABE)
in 1FF6h and the Watchdog Steering (WDS) bit in
1FF7h allow the interrupt to activate the IRQ/FT
pin.
The interrupt flags and the IRQ/FT output are
cleared by a read to the flags register. An interrupt
condition reset will not occur unless the addresses
are stable at the flag location for at least 15ns
while the divice is in the read mode as shown in
Figure 11.
The IRQ/FT pin is an open drain output and requires a pull-up resistor (10kΩ recommended) to
VCC. The pin remains in the high impedance state
unless an interrupt occurs or the frequency test
mode is enabled.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control register (1FF8h). As
long as a ’1’ remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
Setting the Clock
Bit D7 of the Control register (1FF8h) is the
WRITE bit. Setting the WRITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER reg-
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
10/21
M48T59, M48T59Y, M48T59V
isters. The user can then load them with the correct day, date, and time data in 24 hour BCD
format (see Table 12). Resetting the WRITE bit to
a ’0’ then transfers the values of all time registers
(1FF9h-1FFFh) to the actual TIMEKEEPER
counters and allows normal operation to resume.
After the WRITE bit is reset, the next clock update
will occur within approximately one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ‘0’.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T59/59Y/59V in
the
DIP
package,
is
shipped
from
STMicroelectronics with the STOP bit set to a '1'.
When reset to a '0', the M48T59/59Y/59V oscillator starts within one second.
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT), the STOP bit (ST) or the CENTURY ENABLE bit (CEB).
Calibrating the Clock
The M48T59/59Y/59V is driven by a quartz controlled oscillator with a nominal frequency of
32,768Hz. The devices are tested not to exceed
35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes
per month. With the calibration bits properly set,
the accuracy of each M48T59/59Y/59V improves
to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips
compensate for crystal frequency and temperature shift error with cumbersome trim capacitors.
The M48T59/59Y/59V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Figure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five bit Calibration byte found in the
Control Register. Adding counts speeds the clock
up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control register (1FF8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
Figure 10. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
–120
T0 = 25 °C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
11/21
M48T59, M48T59Y, M48T59V
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary ’1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles; for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T59/59Y/59V may
require. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the final product is packaged in a non-user serviceable
enclosure. All the designer has to do is provide a
simple utility that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz when the
Stop bit (D7 of 1FF9h) is '0', the FT bit (D6 of
1FFCh) is '1', the AFE bit (D7 of 1FF6h) is '0', and
the Watchdog Steering bit (D7 of 1FF7h) is '1' or
the Watchdog Register is reset (1FF7h = 0).
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 ppm oscillator frequency
error, requiring a –10 (WR001010) to be loaded
into the Calibration Byte for correction. Note that
setting or changing the Calibration Byte does not
affect the Frequency test output frequency.
The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time. The FT bit is cleared on power-down.
For more information on calibration, see the Application Note AN934 "TIMEKEEPER Calibration".
SETTING ALARM CLOCK
Registers 1FF5h-1FF2h contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific day of the month or
repeat every month, day, hour, minute, or second.
It can also be programmed to go off while the
M48T59 is in the battery back-up mode of operation to serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 12 shows the possible configurations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Table 12. Alarm Repeat Mode
RPT4
RPT3
RPT2
RPT1
Alarm Activated
1
1
1
1
Once per Second
1
1
1
0
Once per Minute
1
1
0
0
Once per Hour
1
0
0
0
Once per Day
0
0
0
0
Once per Month
Figure 11. Interrupt Reset Waveforms
15ns Min
A0-A12
ADDRESS 1FF0h
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI01388B
12/21
M48T59, M48T59Y, M48T59V
Note: User must transition address (or toggle chip
enable) to see Flag bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. To disable alarm,
write ‘0’ to the Alarm Date register and RPT1-4.
The alarm flag and the IRQ/FT output are cleared
by a read to the Flags register.
The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T59 was in the deselect mode during
power-up. Figure 12 illustrates the back-up mode
alarm timing.
WATCHDOG TIMER
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight bit Watchdog Register (Address 1FF7h). The five bits (BMB4-BMB0) store a
binary multiplier and the two lower order bits (RB1RB0) select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4
seconds. The amount of time-out is then determined to be the multiplication of the five bit multiplier value with the resolution. (For example:
writing 00001110 in the Watchdog Register = 3 x 1
or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T59 sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset.
WDF is reset by reading the Flags Register (Address 1FFOh).
Figure 12. Back-up Mode Alarm Waveforms
tREC
VCC
VPFD (max)
VPFD (min)
VSO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI03254B
13/21
M48T59, M48T59Y, M48T59V
power-up sequence or the next scheduled 24-hour
interval.
If a battery low is generated during a power-up sequence, this indicates that the battery voltage is
below 2.5V (approximately), which may be insufficient to maintain data integrity. Data should be
considered suspect and verified as correct. A fresh
battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data has not been
compromised due to the fact that a nominal VCC
is supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, it is
recommended that the battery be replaced. The
SNAPHAT top may be replaced while VCC is applied to the device.
Note: Battery monitoring is a useful technique only
when performed periodically. The M48T59/59Y/
59V only monitors the battery when a nominal
VCC is applied to the device. Thus applications
which require extensive durations in the battery
back-up mode should be powered-up periodically
(at least once every few months) in order for this
technique to be beneficial. Additionally, if a battery
low is indicated, data integrity should be verified
upon power-up via a checksum or other technique.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a ’0’, the
watchdog will activate the IRQ/FT pin when timedout. When WDS is set to a ’1’, the watchdog will
output a negative pulse on the RST pin for a duration of 40ms to 200ms. The Watchdog register and
the FT bit will reset to a ’0’ at the end of a watchdog
time-out when the WDS bit is set to a ’1’.
The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Register.
The time-out period then starts over. The watchdog timer is disabled by writing a value of
00000000 to the eight bits in the Watchdog Register. The watchdog function is automatically disabled upon power-down and the Watchdog
Register is cleared. If the watchdog function is set
to output to the IRQ/FT pin and the frequency test
function is activated, the watchdog or alarm function prevails and the frequency test function is denied.
BATTERY LOW FLAG
The M48T59/59Y/59V automatically performs periodic battery voltage monitoring upon power-up
and at factory-programmed time intervals of 24
hours (at day rollover) as long as the device is
powered and the oscillator is running. The Battery
Low flag (BL), Bit D4 of the flags Register 1FF0h,
will be asserted high if the internal or SNAPHAT
battery is found to be less than approximately
2.5V. The BL flag will remain active until completion of battery replacement and subsequent battery low monitoring tests, either during the next
POWER-ON DEFAULTS
Upon application of power to the device, the following register bits are set to a ’0’ state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT.
(See Table 13).
Table 13. Default Values
W
R
FT
AFE
ABE
WATCHDOG
Register (1)
Initial Power-up
(Battery Attach for SNAPHAT) (2)
0
0
0
0
0
0
Subsequent Power-up / RESET (3)
0
0
0
0
0
0
Power-down (4)
0
0
0
1
1
0
Condition
Note: 1.
2.
3.
4.
14/21
WDS, BMB0-BMB4, RBO, RB1.
State of other control bits undefined.
State of other control bits remains unchanged.
Assuming these bits set to ’1’ prior to power-down.
M48T59, M48T59Y, M48T59V
POWER SUPPLY DECOUPLING and
UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy, which stabilizes the V CC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values
below V SS by as much as one Volt. These negative spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from V CC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount
Figure 13. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
15/21
M48T59, M48T59Y, M48T59V
Table 14. Ordering Information Scheme
Example:
M48T59Y
-70 MH
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
59 (1) = VCC = 4.75V to 5.5V; VPFD = 4.5V to 5.5V
59Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V
59V = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V
Speed
-70 = 70ns
Package
PC = PCDIP28
MH (2) = SOH28
Temperature Range
1 = 0 to 70 °C
6 (3) = –40 to 85 °C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The M48T59 part is offered with the PCDIP28 (i.e. CAPHAT) package only.
2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number
"M4TXX-BR12SH1" in plastic tube or "M4TXX-BR12SH1TR" in Tape & Reel form.
3. Available in SOIC package only.
Caution: Do not place the SNAPHAT battery/crystal package "M4TXX-BR12SH1" in conductive foam since will drain the lithium buttoncell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
16/21
M48T59, M48T59Y, M48T59V
Table 15. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
8.89
A1
Typ
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
29.72
36.32
1.170
1.430
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
28
Figure 14. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline
A2
A1
B1
B
e1
A
L
C
eA
e3
D
N
E
1
PCDIP
Drawing is not to scale.
17/21
M48T59, M48T59Y, M48T59V
Table 16. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
Typ
Min
3.05
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
1.27
0.050
28
CP
0.10
0.004
Figure 15. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
1
SOH-A
Drawing is not to scale.
18/21
Max
α
L
M48T59, M48T59Y, M48T59V
Table 17. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
Max
9.78
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
Figure 16. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A1
eA
A2
A
A3
B
L
eB
D
E
SHTK-A
Drawing is not to scale.
19/21
M48T59, M48T59Y, M48T59V
Table 18. M4T32-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
Max
10.54
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
Figure 17. M4T32-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
eA
A2
A
A3
B
L
eB
D
E
SHTK-A
Drawing is not to scale.
20/21
M48T59, M48T59Y, M48T59V
.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
 1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
21/21