NTD4804N, NVD4804N Power MOSFET 30 V, 117 A, Single N−Channel, DPAK/IPAK Features Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses AEC Q101 Qualified − NVD4804N These Devices are Pb−Free and are RoHS Compliant http://onsemi.com RDS(on) MAX V(BR)DSS D N−Channel MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) G Symbol Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS "20 V ID 19.6 A Continuous Drain Current (RqJA) (Note 1) TA = 25°C Power Dissipation (RqJA) (Note 1) TA = 25°C PD 2.66 W Continuous Drain Current (RqJA) (Note 2) TA = 25°C ID 14.5 A TA = 85°C S 4 15.2 4 1 2 11 TA = 25°C PD 1.43 W Continuous Drain Current (RqJC) (Note 1) TC = 25°C ID 124 A Power Dissipation (RqJC) (Note 1) TC = 25°C PD 107 TA = 25°C IDM 230 TA = 25°C IDmaxPkg 45 A TJ, Tstg −55 to 175 °C IS 78 A Drain to Source dV/dt dV/dt 6.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 1.0 mH, IL(pk) = 30 A, RG = 25 W) EAS 450 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C TC = 85°C tp=10ms Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) CASE 369AA DPAK (Bent Lead) STYLE 2 W A Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2 3 CASE 369AD CASE 369D 3 IPAK IPAK (Straight Lead) (Straight Lead DPAK) MARKING DIAGRAMS & PIN ASSIGNMENTS 96 4 Drain 4 Drain AYWW 48 04NG Steady State TA = 85°C 1 3 4 Drain AYWW 48 04NG Parameter Pulsed Drain Current 117 A 5.5 mW @ 4.5 V • CPU Power Delivery • DC−DC Converters • Low Side Switching Power Dissipation (RqJA) (Note 2) ID MAX 4.0 mW @ 10 V 30 V Applications AYWW 48 04NG • • • • • 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source A = Assembly Location Y = Year WW = Work Week 4804N = Device Code G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2014 May, 2014 − Rev. 9 1 Publication Order Number: NTD4804N/D NTD4804N, NVD4804N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 1.4 °C/W Junction−to−TAB (Drain) RqJC−TAB 3.5 Junction−to−Ambient − Steady State (Note 1) RqJA 56.4 Junction−to−Ambient − Steady State (Note 2) RqJA 105 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 26 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA "100 mA nA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) gFS 2.5 7.6 VGS = 10 to 11.5 V VGS = 4.5 V Forward Transconductance 1.5 ID = 30 A 3.4 ID = 15 A 3.4 ID = 30 A 4.7 ID = 15 A 4.6 VDS = 15 V, ID = 15 A V mV/°C 4.0 mW 5.5 23 S 4490 pF CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Ciss Coss VGS = 0 V, f = 1.0 MHz, VDS = 12 V 952 Crss 556 Total Gate Charge QG(TOT) 30 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 15 V, ID = 30 A 40 nC 5.5 13 13 VGS = 11.5 V, VDS = 15 V, ID = 30 A 73 nC 18 ns SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 20 24 tf 8 td(on) 10 tr td(off) VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 19 35 5 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns NTD4804N, NVD4804N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit TJ = 25°C 0.81 1.2 V TJ = 125°C 0.72 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 30 A 34 VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A ns 19 15 QRR 30 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 0.6 PACKAGE PARASITIC VALUES TA = 25°C http://onsemi.com 3 1.88 W NTD4804N, NVD4804N TYPICAL PERFORMANCE CURVES 240 10 V 6V VDS ≥ 10 V TJ = 25°C 200 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 240 4.5 V 160 4V 120 80 3.6 V 40 200 160 120 80 TJ = 125°C TJ = 25°C 40 3.2 V 1 2 5 4 3 0 2 4 3 5 6 7 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 30 A TJ = 25°C 0.009 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.010 0.01 TJ = 25°C 0.0075 0.008 0.007 0.006 0.005 VGS = 4.5 V 0.005 VGS = 11.5 V 0.0025 0.004 0.003 2 4 8 6 10 0 10 20 30 40 50 60 70 80 90 100 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.7 1.6 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100,000 VGS = 0 V ID = 30 A VGS = 10 V TJ = 175°C 1.5 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = −55°C 0 0 1.4 10,000 1.3 1.2 1.1 1.0 1000 TJ = 125°C 0.9 0.8 0.7 −50 −25 100 0 25 50 75 100 125 150 175 0 5 10 15 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 20 NTD4804N, NVD4804N TYPICAL PERFORMANCE CURVES VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) 6000 TJ = 25°C Ciss C, CAPACITANCE (pF) 5000 4000 Ciss 3000 Crss 2000 Coss 1000 0 15 VDS = 0 V VGS = 0 V 5 5 0 VGS VDS 10 Crss 10 15 20 25 30 5 QT 4 2 1 ID = 30 A TJ = 25°C 0 0 5 15 20 25 10 QG, TOTAL GATE CHARGE (nC) 30 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge Figure 7. Capacitance Variation 30 1000 100 IS, SOURCE CURRENT (AMPS) VDD = 15 V ID = 30 A VGS = 11.5 V tr td(off) tf td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V 25 100 15 10 5 100 100 ms 1 ms 10 ms dc 1 0.1 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.4 0.6 1.0 0.8 Figure 10. Diode Forward Voltage vs. Current 1000 10 0.2 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance VGS = 20 V SINGLE PULSE TC = 25°C TJ = 25°C 20 0 0 1 I D, DRAIN CURRENT (AMPS) Q2 3 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) t, TIME (ns) Q1 500 ID = 30 A 400 300 200 100 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4804N, NVD4804N TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) 100 100°C 125°C 25°C 10 1 1 100 10 PULSE WIDTH (ms) 1000 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 13. Avalanche Characteristics 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 t1 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E-01 1.0E+00 1.0E+01 Figure 14. Thermal Response ORDERING INFORMATION Package Shipping† NTD4804NT4G DPAK (Pb−Free) 2500 / Tape & Reel NTD4804N−35G IPAK Trimmed Lead (3.5 " 0.15 mm) (Pb−Free) 75 Units / Rail NVD4804NT4G DPAK (Pb−Free) 2500 / Tape & Reel Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4804N, NVD4804N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA ISSUE B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C A A E b3 c2 B 4 L3 Z D 1 2 H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z L4 b2 e c b 0.005 (0.13) M C H L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NTD4804N, NVD4804N PACKAGE DIMENSIONS 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD ISSUE B E E3 L2 NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. A E2 A1 D2 D L1 DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 L T SEATING PLANE A1 b1 2X E2 e A2 3X b 0.13 M D2 T MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.57 5.45 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 OPTIONAL CONSTRUCTION IPAK CASE 369D ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN H D G 3 PL 0.13 (0.005) M T DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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