MA2909/11 APRIL 1995 PRELIMINARY INFORMATION DS3577-3.4 MA2909/11 RADIATION HARD MICROPROGRAM SEQUENCER The MA2909/11 Microprogram Sequencer is fully compatible with the industry standard 2909A and 2911A components, and forms part of the GPS 2900 Series of devices. The series offers a building block approach to microcomputer and controller design, with each device in the range being expandable to permit efficient emulation of any microcode machine. The devices have tristate outputs and have an internal address register, with all internal registers changing state on LOW to HIGH clock transition. The 4-bit slice can cascade to any number of microwords. Branch input for N-way branches is supported. Additional features include: FEATURES ■ Fully Compatible with Industry Standard 2909A and 2911A Components ■ Radiation Hard CMOS SOS Technology ■ High SEU Immunity ■ High Speed / Low Power ■ Fully TTL Compatible ■ 4-bit cascadable microprogram counter. ■ 4 x 4 file with stack counter supporting nesting microsubroutines. ■ Zero input for returning to the zero microcode word. ■ Individual OR input for each bit for branching to higher microinstructions (2909 only). The 2909 is a 4-bit wide address controller intended for sequencing through a series of microinstructions contained in a ROM or PROM. Two 2909s may be interconnected to generate an 8-bit address (256 words), and three may be used to generate a 12-bit address (4K words). The 2909 can select an address from any of four sources: 1) A set of external direct inputs (D); 2) External data from the R inputs, stored in an internal register; 3) A four-word push/pop stack; or 4) A program counter register (which usually contains the last address plus one). The push/pop stack includes certain control lines so that it can efficiently execute nested subroutine linkages. Each of the four outputs can be OR’ed with an external input for conditional skip or branch instructions, and a separate line forces the outputs to all zeroes. The outputs are three-state. The 2911 is an identical circuit to the 2909 except the four OR inputs are removed and the D and R inputs are tied together. 1 MA2909/11 STK PTR Figure 1: Microprogram Sequencer Block Diagram 2 MA2909/11 The 2909/2911 are CMOS SOS microprogram sequencers intended for use in high-speed microprocessor applications. The device is a cascadable 4-bit slice such that two devices allow addressing of up to 256 words of microprogram and three devices allow addressing of up to 4K words of microprogram. A detailed logic diagram is shown in figure 1. The device contains a four input multiplexer that is used to select either the address register, direct inputs, microprogram counter, or file as the source of the next microinstruction address. This multiplexer is controlled by the S0 and S1 inputs. The address register consists of four D-type, edge triggered flip-flops with a common clock enable. When the address register enable is LOW, new data is entered into the register on the clock LOW-to-HlGH transition. The address register is available at the multiplexer as a source for the next microinstruction address The direct input is a 4-bit field of inputs to the multiplexer and can be selected as the next microinstruction address. On the 2911 the direct inputs are also used as inputs to the register. This allows an N-way branch where N is any word in the microcode. The 2909/2911 contains a microprogram counter (µPC) that is composed of a 4-bit incrementer followed by a 4bit register. The incrementer has carry-in (Cn) and carry-out (Cn + 4) such that cascading to larger word lengths is straight forward. The µPC can be used in either of two ways. When the least significant carry-in to the incrementer is HIGH, the microprogram register is loaded on the next clock cycle with the current Y output word plus one (Y + 1 ➜ µPC). Thus sequential microinstructions can be executed. If this least significant Cn is LOW, the incrementer passes the Y output word unmodified and the microprgram register is loaded with the same Y word on the next clock cycle (Y ➜ µPC). Thus, the same microinstruction can be executed any number of times by using the 4x4 file (stack). The file is used to provide return address linkage when executing microsubroutines. The file contains a built-in stack pointer (SP) which always points to the last file word written. This allows stack reference operations (looping) to be performed without a push or pop. The stack pointer operates as an up/down counter with separate push/pop and file enable inputs. When the file enable input is LOW and the push/pop input is HIGH, the PUSH operation is enabled. This causes the stack pointer to increment and the file to be written with the required return linkage - the next microinstruction address following the subroutine jump which initiated the PUSH. If the file enable input is LOW and the push/pop control is LOW, a POP operation occurs. This implies the usage of the return linkage during this cycle and thus a return from subroutine. The next LOW-to-HlGH clock transition causes the stack pointer to decrement. If the file enable is HIGH, no action is taken by the stack pointer regardless of any other input. The stack pointer linkage is such that any combination of push, pop or stack references can be achieved. One microinstruction subroutine can be performed. Since the stack is 4 words deep, up to four microsubroutines can be nested. The ZERO input is used to force the four outputs to the binary zero state. When the ZERO input is LOW all Y outputs are LOW regardless of any other inputs (except OE). Each Y output bit also has a separate OR input such that a conditional logic one can be forced at each Y output. This allows jumping to different microinstructions on programmed conditions. The 2909/2911 feature three-state Y outputs. These can be particularly useful in designs requiring external equipment to provide automatic checkout of the microprocessor. The internal control can be placed in the high impedance state and preprogrammed. MULTIPLEXER SELECT CODES Table 1 lists the select codes for the multiplexer. The two bits applied from the microword register (and additional combinational logic for branching) determine which data source contains the address for the next microinstruction. The contents of the selected source will appear on the Y outputs. Table 1 also shows the truth table for the output control and for the control of the push/pop stack. Table 2 shows in detail the effect of S 0, S1, FE and PUP on the 2909. These four signals define the address that apears on the Y outputs and what the state of all the internal registers will be following the clock LOW-to-HlGH edge. In this illustration, the microprogram counter is assumed to contain initially some word J, the address register some word K, and the four words in the push/ pop stack contain Ra through Rd. OR1 ZERO OE Y1 X X H L X L H H H L L L Z L H Source selected by S0S1 H = High, L = Low, Z = High Impedance Table 1a: Output Control FE ZERO H L X H PUSH-POP stack change No change Increment stack pointer, then push current PC on to STK0 Pop stack (decrement stack pointer) L L H = High, L = Low, X = Irrelevant Table 1b: Synchronous Stack Control S1 S2 L L H H L H L H Source for Y outputs Microprogram counter Address/Holding register Push-Pop stack Direct inputs Symbol µPC AR STKO D1 Table 1c: Address Selection 3 MA2909/11 Cycle S1 S0 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 L L FE PUP L L L H H X L L L H H X L L L H H X L L L H H X L L - L L - L H - L H - L H - H L - H L - H L - H H - H H - H H - µPC J J+1 J J+1 J J+1 J K+1 J K+1 J K+1 J Ra + 1 J Ra + 1 J Ra + 1 J D+1 J D+1 J D+1 REG STK0 STK1 STK2 STK3 YOUT K K K K K K K K K K K K K K K K K K K K K K K K Ra Rb Ra J Ra Ra Ra Rb Ra J Ra Ra Ra Rb Ra J Ra Ra Ra Rb Ra J Ra Ra Rb Rc Rb Ra Rb Rb Rb Rc Rb Ra Rb Rb Rb Rc Rb Ra Rb Rb Rb Rc Rb Ra Rb Rb Rc Rd Rc Rb Rc Rc Rc Rd Rc Rb Rc Rc Rc Rd Rc Rb Rc Rc Rc Rd Rc Rb Rc Rc Rd Ra Rd Rc Rd Rd Rd Ra Rd Rc Rd Rd Rd Ra Rd Rc Rd Rd Rd Ra Rd Rc Rd Rd J J J K K K Ra Ra Ra D D D - Comment Principal Use Pop Stack End Loop Push µPC Set-up Loop Continue Continue Pop Stack; Use AR for Address Push µPC; Jump to Address in AR Jump to Address in AR End Loop Jump to Address in STK0; Pop Stack Jump to Address in STK0; Push µPC RTS Jump to Address in STK0 Pop Stack; Jump to Address on D Jump to Address on D; Push µPC Jump to Address on D Stack Ref (Loop) End Loop 1 = High, 0 = Low, X = Irrelevant, Assume Cn = High Note: STK0 is the location addressed by the stack pointer Table 2: Output and Internal Next-Cycle Register States for 2909/2911 Table 3 (Page 5) illustrates the execution of a subroutine using the 2909. The configuration of Figure 2 is assumed. The instruction being executed at any given time is the one contained in the microword register (µWR). The contents of the µWR also control (indirectly, perhaps) the four signals S0, S1, FE, and PUP. The starting address of the subroutine is applied to the D inputs of the 2909 at the appropriate time. In the column on the left is the sequence of microinstructions to be executed. At address J+2, the sequence control portion of the microinstruction contains the command “Jump to subroutine at A”. At the time T2, this instruction is in the µWR, and the 2909 inputs are set-up to execute the jump and save the return address. The subroutine address A is applied to the D inputs from the µWR and appears on the Y outputs. The first instruction of the subroutine, I(A), is accessed and is at the inputs of the µWR. On the next clock transition, l(A) is loaded into the µWR for execution, and the return address J + 3 is pushed on to the stack. The return instruction is executed at T5. Table 4 is a similar timing chart showing one subroutine linking to a second, the latter consisting of only one microinstruction. 4 JSR AR JMP AR JSR D JMP D MA2909/11 Execute Cycle 2909 inputs (from µWR) Internal Registers 2909 Output ROM Output Contents of µWR (instruction being executed) T0 S1, S0 FE PUP D µPC STK0 STK1 STK2 STK3 Y (Y) µWR T1 0 0 H H X X X X J+1 J+2 J+1 J+2 I(J + 1) JSR A I(J) I(J + 1) T2 T3 T4 T5 3 L H A J+3 A I(A) 0 H X X A+1 J+3 A+1 I(A + 1) 0 H X X A+2 J+3 A+2 RTS 2 L L X A+3 J+3 J+3 I(J + 3) 0 0 H H X X X X J+4 J+5 J+4 J+5 I(J + 4) I(J + 5) JSR A I(A) I(A + 1) RTS I(J + 3) I(J + 4) T6 T7 T8 T9 Table 3: Subroutine Execution CONTROL MEMORY Microprogram Execute Cycle T0 T1 T2 T6 T7 T3 T4 T5 Address Sequencer Instruction J-1 J J+1 J+2 J+3 J+4 A A+1 A+2 - JSR A I(A) RTS - 5 MA2909/11 T0 Execute Cycle 2909 inputs (from µWR) Internal Registers 2909 Output ROM Output Contents of µWR (instruction being executed) S1, S0 FE PUP D µPC STK0 STK1 STK2 STK3 Y (Y) µWR T1 0 0 H H X X X X J+1 J+2 J+1 J+2 I(J + 1) JSR A I(J) I(J + 1) T2 T3 T4 T5 T6 T7 T8 T9 3 L H A J+3 A I(A) 0 H X X A+1 J+3 A+1 I(A + 1) 0 H X X A+2 J+3 A+2 JSR B 2 L L X A+3 J+3 B RTS 0 H X X B+1 A+3 J+3 A+ 3 I(A + 3) 0 H X X A+4 J+3 A+4 RTS 2 L L X A+5 J+3 J+3 I(J + 3) 0 H X X J+4 J+4 I(J + 4) JSR A I(A) I(A + 1) JRS B RTS I(A + 3) RTS I(J + 3) Table 4: Two Nested Subroutines CONTROL MEMORY Microprogram Execute Cycle T0 T1 T2 T9 T3 T4 T5 T7 T8 T6 6 Address Sequencer Instruction J-1 J J+1 J+2 J+3 A A+1 A+2 A+3 A+4 B - JSR A JSR B RTS RTS - MA2909/11 DC CHARACTERISTICS AND RATINGS Parameter Min Max Units Supply Voltage -0.5 7 V Input Voltage -0.3 VDD+0.3 V - 20 mA Operating Temperature -55 125 °C Storage Temperature -65 150 °C Current Through Any Pin Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5: Absolute Maximum Ratings Subgroup 1 2 3 7 8a 8b 9 10 11 Definition Static characteristics specified in Table 7 at +25°C Static characteristics specified in Table 7 at +125°C Static characteristics specified in Table 7 at -55°C Functional characteristics at +25°C Functional characteristics at +125°C Functional characteristics at -55°C Switching characteristics specified in Tables 8, 9 and 10 at +25°C Switching characteristics specified in Tables 8, 9 and 10 at +125°C Switching characteristics specified in Tables 8, 9 and 10 at -55°C Table 6: Definition of Subgroups Symbol Parameter Conditions VOH VOL VIH VIL IIH IIL IOZH IOZL IDD Output high voltage Output low voltage Input high level (Note 1) Input low level (Note 1) Input high current Input low current Tristate high current Tristate low current Power supply current VDD = Min., IOH = -2.6mA, VIN = VIH or VIL VDD = Max., IOL = 16 mA, VIN = VIH or VIL Guaranteed input logical high voltage for all inputs Guaranteed input logical low voltage for all inputs VIN = VDD (Note 3) VIN = VSS (Note 3) VO = VDD (Note 3) VO = VSS (Note 3) Min. Max. Units VDD -0.5 VDD/2 - 0.5 0.8 10 -10 50 -50 10 V V V V µA µA µA µA mA NOTES: Mil-Std-883, Method 5005, Subgroups 1, 2, 3. 1. These input levels provide no guaranteed noise immunity and should only be static tested in a noise-free environment. 2. VDD = 5V ±10%, over full operating temperature range. 3. Guaranteed but not tested at low temperatures. Table 7: DC Operating Characteristics 7 MA2909/11 Time Minimum clock low time Minimum clock high time 15 15 Table 8: Cycle Time and Clock Charcteristics From input Y Cn + 4 From input Set-up time Hold Time D1 S0, S1 ORI Cn ZERO OE LOW (enable) (Note 2) OE HIGH (disable) (Note 3) Clock: S1S0 = LH Clock: S1S0 = LL Clock: S1S0 = HL 35 30 20 35 25 25 40 40 50 40 35 30 25 40 45 45 45 RE RI PUP FE Cn DI ORI S0, S1 ZERO 10 10 20 20 15 20 20 20 25 10 7 5 10 5 0 0 0 0 Notes: 1. CL < 50pF 2. RL ≥ 680Ω 3. RL ≥ 680Ω, measured 0.5V change in output level Table 10: Guaranteed Set-up and Hold Times (all in ns) All times in ns across full voltage and temperature range. MIL-STD-883, method 5005, subgroups 9, 10 and 11. Table 9: Maximum Combinational Propogation Delays Figure 2 8 MA2909/11 PACKAGE OUTLINES Millimetres Ref Inches Min. Nom. Max. Min. Nom. Max. A - - 5.715 - - 0.225 A1 0.38 - 1.53 0.015 - 0.060 b 0.35 - 0.59 0.014 - 0.023 c 0.20 - 0.36 0.008 - 0.014 D - - 36.02 - - 1.418 e - 2.54 Typ. - - 0.100 Typ. - e1 - 15.24 Typ. - - 0.600 Typ. - H 4.71 - 5.38 0.185 - 0.212 Me - - 15.90 - - 0.626 Z - - 1.27 - - 0.050 W - - 1.53 - - 0.060 XG404 D 14 1 15 28 REN 1 28 VCC R3 2 27 CP R2 3 26 PUP R1 4 25 FEN 24 Cn+4 R0 5 OR3 6 D3 7 OR2 8 D2 9 20 Y2 OR1 10 19 Y1 23 Cn Top View 22 OEN 21 Y3 D1 11 18 Y0 OR0 12 17 S1 D0 13 16 S0 GND 14 15 ZERON W ME Seating Plane A1 A C H e b Z e1 15° Figure 3: 28-Lead Ceramic DIL (Solder Seal) - Package Style C 9 MA2909/11 Millimetres Ref Inches Min. Nom. Max. Min. Nom. Max. A - - 2.97 - - 0.117 b 0.381 - 0.482 0.015 - 0.019 c 0.076 - 0.152 0.003 - 0.006 D 18.08 - 18.49 0.712 - 0.728 E 12.50 - 12.9 0.492 - 0.508 E2 9.45 - 9.85 0.372 - 0.388 e 1.143 - 1.40 0.045 - 0.055 L 8.00 - 9.27 0.315 - 0.365 Q 0.66 - - 0.026 - - S - - 1.14 - - 0.045 XG543 E b D S e L A c E2 Q Pin 1 Figure 3: 28-Lead Dual Flatpack (Solder Seal) - Package Style C 10 MA2909/11 RADIATION TOLERANCE Total Dose (Function to specification)* 3x105 Rad(Si) Total Dose Radiation Testing Transient Upset (Stored data loss) 5x1010 Rad(Si)/sec Transient Upset (Survivability) >1x1012 Rad(Si)/sec Neutron Hardness (Function to specification) >1x1015 n/cm2 Single Event Upset** 1x10-10 Errors/bit day Latch Up Not possible For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. GEC Plessey Semiconductors can provide radiation testing compliant with MIL-STD-883 test method 1019, Ionizing Radiation (Total Dose). * Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit Table 11: Radiation Hardness Parameters ORDERING INFORMATION Unique Circuit Designator Radiation Tolerance S R Q MAx2909xxxxx MAx2911xxxxx Radiation Hard Processing 100 kRads (Si) Guaranteed 300 kRads (Si) Guaranteed Package Type C N F Ceramic DIL (Solder Seal) Naked Die Flatpack (Solder Seal) QA/QCI Process (See Section 9 Part 4) Test Process (See Section 9 Part 3) Assembly Process (See Section 9 Part 2) Reliability Level For details of reliability, QA/QC, test and assembly options, see ‘Manufacturing Capability and Quality Assurance Standards’ Section 9. L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S 11 MA2909/11 HEADQUARTERS OPERATIONS CUSTOMER SERVICE CENTRES GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire, SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 • FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07 • GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55 • ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 • JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 • NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023 • SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 • SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 • TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260 • UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK GEC PLESSEY SEMICONDUCTORS P.O. Box 660017, 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576 Tel: (01793) 518527/518566 Fax: (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. © GEC Plessey Semiconductors 1995 Publication No. DS3577-3.3 March 1995 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM. This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. 12 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’ s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’ s conditions of sale which are available on request. Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE