Product Folder Order Now Support & Community Tools & Software Technical Documents LF356-MIL SNOSD55 – JUNE 2017 LF356-MIL JFET Input Operational Amplifier 1 Features 2 Applications • • • • • • • • 1 • • Advantages – Replace Expensive Hybrid and Module FET Op Amps – Rugged JFETs Allow Blow-Out Free Handling Compared With MOSFET Input Devices – Excellent for Low Noise Applications Using Either High or Low Source Impedance—Very Low 1/f Corner – Offset Adjust Does Not Degrade Drift or Common-Mode Rejection as in Most Monolithic Amplifiers – New Output Stage Allows Use of Large Capacitive Loads (5,000 pF) Without Stability Problems – Internal Compensation and Large Differential Input Voltage Capability Common Features – Low Input Bias Current: 30 pA – Low Input Offset Current: 3 pA – High Input Impedance: 1012 Ω – Low Input Noise Current: 0.01 pA/√Hz – High Common-Mode Rejection Ratio: 100 dB – Large DC Voltage Gain: 106 dB Uncommon Features – Extremely Fast Settling Time to 0.01%: 1.5 μs – Fast Slew Rate: 12 V/µs – Wide Gain Bandwidth: 5 MHz – Low Input Noise Voltage: 12 nV/√Hz Precision High-Speed Integrators Fast D/A and A/D Converters High Impedance Buffers Wideband, Low Noise, Low Drift Amplifiers Logarithmic Amplifiers Photocell Amplifiers Sample and Hold Circuits 3 Description The LF356-MIL device are the first monolithic JFET input operational amplifiers to incorporate wellmatched, high-voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust, which does not degrade drift or common-mode rejection. The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner. Device Information(1) PART NUMBER LF356-MIL PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm TO-CAN (8) 9.08 mm × 9.08 mm PDIP (8) 9.81 mm × 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic 3 pF in LF357 series 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LF356-MIL SNOSD55 – JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 1 1 1 2 3 3 8 6.1 6.2 6.3 6.4 6.5 3 4 4 4 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 22 4 11 Device and Documentation Support ................. 24 6.6 6.7 6.8 6.9 7 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 12 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. AC Electrical Characteristics, TA = TJ = 25°C, VS = ±15 V.......................................................................... DC Electrical Characteristics, TA = TJ = 25°C, VS = ±15 V.......................................................................... DC Electrical Characteristics .................................... Power Dissipation Ratings ........................................ Typical Characteristics .............................................. Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application .................................................. 14 8.3 System Examples ................................................... 15 10.1 Layout Guidelines ................................................. 22 10.2 Layout Example .................................................... 23 11.1 11.2 11.3 11.4 11.5 4 5 5 6 Detailed Description ............................................ 10 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 24 7.1 Overview ................................................................. 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES June 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 5 Pin Configuration and Functions LMC Package 8-Pin TO-99 Top View D or P Package 8-Pin SOIC or PDIP Top View Available per JM38510/11401 or JM38510/11402 Pin Functions PIN NAME NO. BALANCE I/O DESCRIPTION 1, 5 I Balance for input offset voltage +INPUT 3 I Noninverting input –INPUT 2 I Inverting input NC 8 — No connection OUTPUT 6 O Output V+ 7 — Positive power supply V– 4 — Negative power supply 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MAX UNIT Supply voltage MIN ±18 V Differential input voltage ±30 V Input voltage (4) ±16 V Output short circuit duration TJMAX Soldering information (lead temp.) Continuous LMC package 115 P package 100 D package 100 TO-99 package Soldering (10 sec.) 300 PDIP package Soldering (10 sec.) 260 Vapor phase (60 sec.) 215 SOIC package Infrared (15 sec.) (1) (2) (3) (4) °C °C 220 −65 Storage temperature, Tstg — 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is PD = (TJMAX − TA) / θJA or the 25°C PdMAX, whichever is less. If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 3 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2) VALUE UNIT ±1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 100 pF discharged through 1.5-kΩ resistor 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM Supply voltage, VS TA 0 MAX UNIT ±15 V 70 °C TA 6.4 Thermal Information LF356-MIL THERMAL METRIC (1) D (SOIC) P (PDIP) 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 112.5 55.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58.8 44.5 °C/W RθJB Junction-to-board thermal resistance 52.8 32.4 °C/W ψJT Junction-to-top characterization parameter 12.8 21.7 °C/W ψJB Junction-to-board characterization parameter 52.3 32.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 AC Electrical Characteristics, TA = TJ = 25°C, VS = ±15 V PARAMETER SR Slew Rate GBW TEST CONDITIONS MIN TYP MAX UNIT 12 V/μs Gain Bandwidth Product 5 MHz ts Settling Time to 0.01% (1) 1.5 μs en Equivalent Input Noise Voltage f = 100 Hz 15 nV/√Hz f = 1000 Hz 12 nV/√Hz f = 100 Hz 0.01 pA/√Hz f = 1000 Hz 0.01 pA/√Hz in Equivalent Input Current Noise CIN Input Capacitance (1) AV = 1 RS = 100 Ω 3 pF Settling time is defined here, for a unity gain inverter connection using 2-kΩ resistors for the LF15x. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10-V step input is applied to the inverter. For the LF357, AV = −5, the feedback resistor from output to input is 2 kΩ and the output step is 10 V (See Settling Time Test Circuit). 6.6 DC Electrical Characteristics, TA = TJ = 25°C, VS = ±15 V PARAMETER TEST CONDITIONS MIN Supply current 4 Submit Documentation Feedback TYP MAX 5 10 UNIT mA Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 6.7 DC Electrical Characteristics See (1) PARAMETER TEST CONDITIONS VOS Input offset voltage RS = 50 Ω ΔVOS/ΔT Average TC of input offset voltage RS = 50 Ω ΔTC/ΔVOS Change in average TC with VOS adjust RS = 50 Ω (2) IOS Input offset current IB TJ = 25°C (1) TYP MAX 3 10 Over temperature TJ = 25°C (1) UNIT mV 13 5 μV/°C μV/°C per mV 0.5 (3) 3 TJ ≤ THIGH Input bias current RIN MIN TA = 25°C (3) 30 TJ ≤ THIGH 50 pA 2 nA 200 pA 8 nA 12 Input resistance TJ = 25°C AVOL Large signal voltage gain VS = ±15 V, VO = ±10 V, RL = 2 kΩ VO Output voltage swing VCM Input common-mode voltage range CMRR Common-mode rejection ratio 80 100 dB PSRR Supply voltage rejection ratio (1) 80 100 dB (1) (2) (3) (1) Ω 10 TA = 25°C 25 Over temperature 15 200 V/mV VS = ±15 V, RL = 10 kΩ ±12 ±13 VS = ±15 V, RL= 2 kΩ ±10 ±12 10 15.1 VCM, High VS = ±15 V −12 VCM, Low V V –10 Unless otherwise stated, these test conditions apply: Supply Voltage, VS VS = ±15 V TA 0°C ≤ TA ≤ +70°C THIGH +70°C and VOS, IB and IOS are measured at VCM = 0. The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5 μV/°C typically) for each mV of adjustment from its original unadjusted value. Common-mode rejection and open-loop voltage gain are also unaffected by offset adjustment. The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ = TA + θJA Pd where θJA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice. 6.8 Power Dissipation Ratings MIN LMC Package (Still Air) Power Dissipation at TA = 25°C (1) (2) (1) (2) LMC Package (400 LF/Min Air Flow) MAX UNIT 400 1000 P Package 670 D Package 380 mW The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is PD = (TJMAX − TA) / θJA or the 25°C PdMAX, whichever is less. Maximum power dissipation is defined by the package characteristics. Operating the part near the maximum power dissipation may cause the part to operate outside specified limits. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 5 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com 6.9 Typical Characteristics 6.9.1 Typical AC Performance Characteristics 6 Figure 1. Gain Bandwidth Figure 2. Gain Bandwidth Figure 3. Normalized Slew Rate Figure 4. Output Impedance Figure 5. Output Impedance Figure 6. LF155 Small Signal Pulse Response, AV = +1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 Typical AC Performance Characteristics (continued) Figure 7. LF156 Small Signal Pulse Response, AV = +1 Figure 8. LF155 Large Signal Pulse Response, AV = +1 Figure 9. LF156 Large Signal Puls Response, AV = +1 Figure 10. Inverter Settling Time Figure 11. Inverter Settling Time Figure 12. Open-Loop Frequency Response Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 7 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com Typical AC Performance Characteristics (continued) 8 Figure 13. Bode Plot Figure 14. Bode Plot Figure 15. Bode Plot Figure 16. Common-Mode Rejection Ratio Figure 17. Power Supply Rejection Ratio Figure 18. Power Supply Rejection Ratio Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 Typical AC Performance Characteristics (continued) Figure 19. Undistorted Output Voltage Swing Figure 20. Equivalent Input Noise Voltage Figure 21. Equivalent Input Noise Voltage (Expanded Scale) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 9 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com 7 Detailed Description 7.1 Overview These are the first monolithic JFET input operational amplifiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET Technology). These amplifiers feature low input bias and offset currents, as well as low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. These devices can replace expensive hybrid and module FET operational amplifiers. Designed for low voltage and current noise and a low 1/f noise corner, these devices are excellent for low noise applications using either high or low source impedance. 10 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 7.2 Functional Block Diagram *C = 3 pF in LF357 series. Figure 22. Detailed Schematic Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 11 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com 7.3 Feature Description 7.3.1 Large Differential Input Voltage These are operational amplifiers with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. 7.3.2 Large Common-Mode Input Voltage These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter. 7.4 Device Functional Modes The LF356-MIL has a single functional mode and operates according to the conditions listed in the Recommended Operating Conditions. 12 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information These are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize pick-up and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3-dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3-dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 13 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com 8.2 Typical Application Figure 23. Settling Time Test Circuit 8.2.1 Design Requirements Settling time is tested with the LF35x connected as unity gain inverter and LF357 connected for AV = −5 8.2.2 Detailed Design Procedure Connect the circuit components as shown in Figure 23. In particular, use FET to isolate the probe capacitance. Apply a 10-V step function to the input. Use an oscilloscope to probe the circuit as shown in Figure 23. 8.2.3 Application Curve Figure 24. Large Signal Inverter Output, VOUT (from Settling Time Circuit) 14 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 8.3 System Examples Figure 25. Fast Logarithmic Converter • • • • • Dynamic range: 100 μA ≤ Ii ≤ 1 mA (5 decades), |VO| = 1 V/decade Transient response: 3 μs for ΔIi = 1 decade C1, C2, R2, R3: added dynamic compensation VOS adjust the LF156 to minimize quiescent error RT: Tel Labs type Q81 + 0.3%/°C (1) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 15 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com System Examples (continued) Figure 26. 8-Bit D/A Converter With Symmetrical Offset Binary Operation • • R1, R2 should be matched within ±0.05% Full-scale response time: 3 μs Table 1. Bit Illustration of the 8-Bit D/A Converter EO B1 B2 B3 B4 B5 B6 B7 B8 COMMENTS +9.920 1 1 1 1 1 1 1 1 Positive Full-Scale +0.040 1 0 0 0 0 0 0 0 (+) Zero-Scale −0.040 0 1 1 1 1 1 1 1 (−) Zero-Scale −9.920 0 0 0 0 0 0 0 0 Negative Full-Scale Figure 27. Wide BW Low Noise, Low Drift Amplifier (2) 16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 Parasitic input capacitance C1 ≃ (3 pF for LF155, LF156 and LF357 plus any additional layout capacitance) interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 ≃ R1 C1. Figure 28. Boosting the LF156 With a Current Amplifier • IOUT(MAX) ≃ 150 mA (will drive RL ≥ 100 Ω) • No additional phase shift added by the current amplifier (3) Figure 29. Decades VCO Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 17 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com R1, R4 matched. Linearity 0.1% over 2 decades. (4) Figure 30. Isolating Large Capacitive Loads • • • Overshoot 6% ts 10 μs When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX): (5) 18 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 Figure 31. Fast Sample and Hold • • Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible) Acquisition time TA, estimated by: (6) • • • LF156 develops full Sr output capability for VIN ≥ 1 V Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 19 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com Figure 32. High Accuracy Sample and Hold • • • • • By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1. – No VOS adjust required for A2. TA can be estimated by same considerations as previously but, because of the added – propagation delay in the feedback loop (A2) the overshoot is not negligible. Overall system slower than fast sample and hold R1, CC: additional compensation Use LF156 for – Fast settling time – Low VOS Figure 33. VOS Adjustment • • • • 20 VOS is adjusted with a 25-k potentiometer The potentiometer wiper is connected to V+ For potentiometers with temperature coefficient of 100 ppm/°C or less the additional drift with adjust is ≈ 0.5 μV/°C/mV of adjustment Typical overall drift: 5 μV/°C ±(0.5 μV/°C/mV of adj.) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 Figure 34. Driving Capacitive Loads • • • * LF15x R = 5k, LF357 R = 1.25 k Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. CL(MAX) ≃ 0.01 μF. Overshoot ≤ 20%, Settling time (ts) ≃ 5 μs Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 21 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com 9 Power Supply Recommendations See the Recommended Operating Conditions for the minimum and maximum values for the supply input voltage and operating junction temperature. 10 Layout 10.1 Layout Guidelines 10.1.1 Printed-Circuit-Board Layout For High-Impedance Work It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PCB. When one wishes to take advantage of the low input bias current of the LF356-MIL, typically less than 30 pA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PCB, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the inputs of the LF356-MIL and the terminals of capacitors, diodes, conductors, resistors, relay terminals, and so forth, connected to the inputs of the op amp, as in Figure 39. To have a significant effect, guard rings must be placed on both the top and bottom of the PCB. This PC foil must then be connected to a voltage that is at the same voltage as the amplifier inputs, because no leakage current can flow between two points at the same potential. For example, a PCB trace-to-pad resistance of 10 TΩ, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5-V bus adjacent to the pad of the input. If a guard ring is used and held close to the potential of the amplifier inputs, it will significantly reduce this leakage current. Figure 35. Inverting Amplifier Figure 36. Noninverting Amplifier 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL LF356-MIL www.ti.com SNOSD55 – JUNE 2017 Layout Guidelines (continued) Figure 37. Typical Connections Of Guard Rings The designer should be aware that when it is inappropriate to lay out a PCB for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PCB: Do not insert the input pin of the amplifier into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PCB construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 38. (Input pins are lifted out of PCB and soldered directly to components. All other pins connected to PCB). Figure 38. Air Wiring Another potential source of leakage that might be overlooked is the device package. When the LF356-MIL is manufactured, the device is always handled with conductive finger cots. This is to assure that salts and skin oils do not cause leakage paths on the surface of the package. We recommend that these same precautions be adhered to, during all phases of inspection, test and assembly. 10.2 Layout Example Figure 39. Examples Of Guard Ring In PCB Layout Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL 23 LF356-MIL SNOSD55 – JUNE 2017 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks BI-FET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LF356-MIL PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LF356 MWC ACTIVE WAFERSALE YS 0 1 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85 LF356H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI 0 to 70 ( LF356H ~ LF356H) LF356H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM 0 to 70 ( LF356H ~ LF356H) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated