Microchip MCP2003 Lin j2602 transceiver Datasheet

MCP2003/4
LIN J2602 Transceiver
Features
Description
• The MCP2003 and MCP2004 are compliant with
LIN Bus Specifications 1.3, 2.0 and 2.1 and are
compliant to SAE J2602
• Support Baud Rates up to 20 Kbaudwith
LIN-compatible output driver
• 43V load dump protected
• Very low EMI meets stringent OEM requirements
• Very high ESD immunity:
- >20kV on VBB (IEC 61000-4-2)
- >14kV on LBUS (IEC 61000-4-2)
• Very high immunity to RF disturbances meets
stringent OEM requirements
• Wide supply voltage, 6.0V-27.0V continuous
• Extended Temperature Range: -40 to +125°C
• Interface to PIC® MCU EUSART and standard
USARTs
• Local Interconnect Network (LIN) bus pin:
- Internal pull-up resistor and diode
- Protected against battery shorts
- Protected against loss of ground
- High current drive
• Automatic thermal shutdown
• Low-power mode:
- Receiver monitoring bus and transmitter off,
( 5 µA)
This device provides a bidirectional, half-duplex
communication physical interface to automotive and
industrial LIN systems to meet the LIN bus specification
Revision 2.1 and SAE J2602. The device is short circuit
and overtemperature protected by internal circuitry.
The device has been specifically designed to operate in
the automotive operating environment and will survive
all specified transient conditions while meeting all of the
stringent quiescent current requirements.
MCP200X family members:
• 8-pin PDIP, DFN and SOIC packages:
- MCP2003, LIN-compatible driver, with WAKE
pins
- MCP2004, LIN-compatible driver, with
FAULT/TXE pins
Package Types
MCP2003
PDIP, SOIC
MCP2004
PDIP, SOIC
RXD 1
8 VREN
RXD 1
8 VREN
CS 2
7 VBB
CS 2
7 VBB
WAKE 3
6 LBUS FAULT/TXE 3
5 VSS
TXD 4
TXD 4
MCP2003
4x4 DFN*
8 VREN
RXD 1
CS 2
7 VBB
CS 2
WAKE 3
TXD 4
6 LBUS
5 VSS
5 VSS
MCP2004
4x4 DFN*
RXD 1
EP
9
6 LBUS
FAULT/TXE 3
TXD 4
8 VREN
EP
9
7 VBB
6 LBUS
5 VSS
* Includes Exposed Thermal Pad (EP); see Table 1-1.
 2010 Microchip Technology Inc.
DS22230A-page 1
MCP2003/4
MCP2003 Block Diagram
VREN
VBB
Ratiometric
Reference
WAKE
Wake-Up
Logic and
Power Control
RXD
CS
TXD
~30 k
LBUS
OC
VSS
Thermal
Protection
Short Circuit
Protection
MCP2004 Block Diagram
VREN
VBB
Ratiometric
Reference
Wake-Up
Logic and
Power Control
RXD
CS
~30 k
TXD
LBUS
OC
FAULT/TXE
VSS
Thermal
Protection
DS22230A-page 2
Short Circuit
Protection
 2010 Microchip Technology Inc.
MCP2003/4
1.0
DEVICE OVERVIEW
1.2.3
THERMAL PROTECTION
The MCP2003/4 provides a physical interface between
a microcontroller and a LIN bus. This device will
translate the CMOS/TTL logic levels to LIN logic level,
and vice versa. It is intended for automotive and
industrial applications with serial bus speeds up to
20 Kbaud.
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter.
LIN specification 2.1 requires that the transceiver of all
nodes in the system is connected via the LIN pin, referenced to ground and with a maximum external
termination resistance of 510 from LIN bus to battery
supply. The 510 corresponds to 1 master and
15 slave nodes.
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
The VREN pin can be used to drive the logic input of an
external voltage regulator. This pin is high in all modes
except for Power Down mode.
1.1
1.1.1
There are two causes for a thermal overload. A thermal
shut down can be triggered by either, or both, of the
following thermal overload conditions.
Driving the TXD and checking the RXD pin makes it possible to determine whether there is a bus contention
(Rx = low, Tx = high) or a thermal overload condition
(Rx = high, Tx = low). After a thermal overload event,
the device will automatically recover once the die temperature has fallen below the recovery temperature
threshold. See Figure 1-1.
External Protection
REVERSE BATTERY PROTECTION
FIGURE 1-1:
THERMAL SHUTDOWN
STATE DIAGRAM
An external reverse-battery-blocking diode should be
used to provide polarity protection (see Example 1-1).
1.1.2
TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 43V transient suppressor (TVS) diode,
between VBB and ground, with a 50 transient
protection resistor (RTP) in series with the battery
supply and the VBB pin serve to protect the device from
power transients (see Example 1-1) and ESD events.
While this protection is optional, it is considered good
engineering practice.
1.2
1.2.1
LIN bus
Shorted
to VBB
Operation
Transmitter
Mode
Shutdown
Temp < SHUTDOWNTEMP
Internal Protection
ESD PROTECTION
For component-level ESD ratings, please refer to the
maximum operation specifications.
1.2.2
GROUND LOSS PROTECTION
The LIN Bus specification states that the LIN pin must
transition to the recessive state when ground is
disconnected. Therefore, a loss of ground effectively
forces the LIN line to a high-impedance level.
 2010 Microchip Technology Inc.
DS22230A-page 3
MCP2003/4
1.3
Modes of Operation
the TXD pin is held low when CS goes high, the device
will transition to Transmitter Off mode instead of
Operation mode.
For an overview of all operational modes, refer to
Table 1-1.
1.3.1
1.3.3
POWER-DOWN MODE
In Power Down mode, the transmitter and VREN are
both off. Only the receiver section and the wake-up
circuits are operational. This is the lowest power
mode.
The MCP2003/4 will go into the Power Down mode on
the falling edge of CS. The MCP2003/4 will enter
Transmitter Off mode in the event of a Fault condition.
These include: thermal overload, bus contention and
TXD timer expiration.
On bus activity (e.g. a BREAK character), CS going to
a high level, or on a falling edge on WAKE, the device
will immediately enter Ready mode. If CS is held high
as the device transitions from Power Down to Ready
mode, the device will transition to Operation mode as
soon as internal voltages stabilize.
Note:
1.3.2
OPERATION MODE
In this mode, all internal modules are operational.
The MCP2004 device can also enter Transmitter Off
mode if the FAULT/TXE pin is pulled low
1.3.4
TRANSMITTER OFF MODE
Transmitter Off mode is reached whenever the
transmitter is disabled either due to a Fault condition or
pulling the nFAULT/TXE pin low on the MCP2004. The
fault conditions include: thermal overload, bus
contention or TXD timer expiration.
Bus activity is defined as LBUS dropping
below VIL(LBUS) for longer than the Bus
Activity Debounce time (tBDB).
READY MODE
The MCP2003/4 will go into Power Down mode on
falling edge of CS, or return to Operation mode if all
faults are resolved and the FAULT/TXE pin on the
MCP2004 is high.
Upon entering the Ready mode, VREN is enabled and
the receiver detect circuit is powered up. The transmitter remains disabled and the device is ready to receive
data but not to transmit.
Upon VBB supply pin power-on, the device will remain
in Ready mode as long as CS is low. If CS transitions
high, the device will enter Operation mode. However, if
FIGURE 1-2:
OPERATIONAL MODES STATE DIAGRAM – MCP2003
POR
VREN OFF
RX OFF
TX OFF
VBB > 5.5V
Ready
Mode
VREN ON
RX ON
TX OFF
CS = 1 and TXD = 1
CS = 1 and TXD = 0
Falling edge
on LIN
or CS = 1
TOFF
Mode
VREN ON
RX ON
TX OFF
CS = 1 and
TXD = 1
and No Fault
Fault
(Thermal or Timer)
Operation
Mode
VREN ON
RX ON
TX ON
CS=0
CS=0
Sleep Mode
VREN OFF
RX OFF
TX OFF
DS22230A-page 4
 2010 Microchip Technology Inc.
MCP2003/4
FIGURE 1-3:
OPERATIONAL MODES STATE DIAGRAM – MCP2004
Ready
Mode
POR
VREN OFF
RX OFF
TX OFF
VBB > 5.5V
VREN ON
RX ON
TX OFF
CS = 1 and (TXE = 0 or TXD = 0)
TOFF
Mode
Falling edge on LIN
or
CS = 1
VREN ON
RX ON
TX OFF
CS = 1 and
TXD = 1 and
TXE = 1
CS = 1and TXE = 1
and TXD = 1
and No Fault
Fault
(Thermal or Timer)
or TXE=0
Operation
Mode
VREN ON
RX ON
TX ON
CS = 0
CS = 0
Sleep Mode
VREN OFF
RX OFF
TX OFF
Note:
While the MCP2003/4 is in thermal shutdown, TXD should not be actively driven high or it may power
internal logic through the ESD diodes and may damage the device.
TABLE 1-1:
State
OVERVIEW OF OPERATIONAL MODES
Transmitter Receiver
Vren
Operation
Comments
POR
OFF
OFF
OFF
Read CS, if low, then Ready;
if high, Operational mode
Ready
OFF
ON
ON
If CS high level, then Operation mode
Operation
ON
ON
ON
If CS low level, then Power Down;
Normal Operation
If FAULT/TXE low level, then Transmitter Off mode
mode
Power Down
OFF
Activity
Detect
OFF
On LIN bus falling, go to Ready mode. On CS Low Power mode
high level, go to Operation mode
Transmitter Off
OFF
ON
ON
If CS low level, then Power Down;
FAULT/TXE only
If FAULT/TXE and TXD high, then Operation available on
mode
MCP2004
 2010 Microchip Technology Inc.
Bus Off state
DS22230A-page 5
MCP2003/4
1.4
Typical Applications
EXAMPLE 1-1:
TYPICAL MCP2003 APPLICATION
+12
+12
50
43V
1.0 µF
(See Note)
Master Node Only
+12
220 K
VOLTAGE REG
VDD
VBB
VREN
TXD
TXD
RXD
RXD
I/O
CS
1 K
LIN Bus
LBUS
27V
WAKE
Wake-up
100 nF
Note:
VSS
For applications with current requirements of less than 20 mA, the connection to +12V can be deleted,
and voltage to the regulator supplied directly from the VREN pin.
EXAMPLE 1-2:
TYPICAL MCP2004 APPLICATION
+12
+12
50
43V
Wake-up
1.0 µF
Master Node Only
+12
220 K
VDD
VOLTAGE REG
TXD
TXD
RXD
RXD
I/O
CS
I/O
FAULT/TXE
100 nF
DS22230A-page 6
VREN
VBB
1 K
LIN Bus
LBUS
27V
VSS
 2010 Microchip Technology Inc.
MCP2003/4
EXAMPLE 1-3:
TYPICAL LIN NETWORK CONFIGURATION
40m
+ Return
LIN bus
1 k
VBB
LIN bus
MCP200X
LIN bus
MCP200X
Slave 1
µC
LIN bus
MCP200X
LIN bus
MCP200X
Slave 2
µC
Slave n <23
µC
Master
µC
 2010 Microchip Technology Inc.
DS22230A-page 7
MCP2003/4
1.5
Pin Descriptions
TABLE 1-1:
PINOUT DESCRIPTIONS
MCP2003
MCP2004
Normal Operation
Normal Operation
1
Receive Data Output (OD)
Receive Data Output (OD)
2
2
Chip Select (TTL)
Chip Select/Local WAKE (TTL)
WAKE (MCP2003 only)
FAULT/TXE (MCP2004
only)
3
3
Wake up, HV tolerant
Fault Detect Output (OD)
Transmitter Enable (TTL)
TXD
4
4
Transmit Data Input (TTL)
Transmit Data Input (TTL)
VSS
5
5
Ground
Ground
LBUS
6
6
LIN bus (bidirectional)
LIN bus (bidirectional)
VBB
7
7
Battery positive
Battery positive
VREN
8
8
Voltage Regulator Enable Output Voltage Regulator Enable Output
EP
—
9
Exposed Thermal Pad. Do not
electrically connect or connect to
Vss
8-Pin
PDIP,
SOIC
8-Pin
DFN
RXD
1
CS
Pin Name
Exposed Thermal Pad. Do not
electrically connect or connect to
Vss
Legend: TTL = TTL Input Buffer; OD = Open-Drain Output
1.5.1
RECEIVE DATA OUTPUT (RXD)
The Receive Data Output pin is a open drain (OD)
output and follows the state of the LIN pin.
1.5.2
CS (CHIP SELECT)
Chip Select Input pin. An internal pull-down resistor will
keep the CS pin low. This is done to ensure that no
disruptive data will be present on the bus while the
microcontroller is executing a Power-on Reset and an
I/O initialization sequence. The pin must detect a high
level to activate the transmitter.
If CS = 0 when the VBB supply is turned on, the device
stays in Ready mode. In Ready mode, the receiver is
on and the LIN transmitter driver is off.
If CS = 1 when the VBB supply is turned on, the device
will proceed to the Operation mode as soon as internal
voltages stabilize.
This pin may also be used as a local wake-up input
(Refer to Example 1-1). In this implementation, the
microcontroller I/O controlling the CS should be
converted to a high-impedance input allowing the
internal pull-down resistor will keep CS low. An external
switch, or other source, can then wake-up both the
transceiver and the microcontroller (if powered).
Note:
1.5.3
WAKE UP INPUT (WAKE)
This pin is only available on the MCP2003.
The WAKE pin has an internal 800K pull up to VBB. A
falling edge on the WAKE pin causes the device to
wake from Power Down mode. Upon waking, the
MCP2003 will enter Ready mode
1.5.4
FAULT/TXE
This pin is only available on the MCP2004. This pin is
bidirectional and allows disabling of the transmitter, as
well as fault reporting related to disabling the
transmitter. This pin is an open-drain output with states
as defined in Table 1-2. The transmitter is disabled
whenever this pin is low (‘0’), either from an internal
Fault condition or by an external drive. While the
transmitter is disabled, the internal 30 k pull-up
resistor on the LBUS pin is also disconnected to reduce
current.
Note:
The FAULT/TXE pin is true (‘0’) whenever
the internal circuits have detected a short
or thermal excursion and have disabled
the LBUS output driver.
It is not recommended to tie CS high as
this can result the MCP2003/4 entering
Operation mode before the microcontroller is initialized and may result in
unintentional LIN traffic.
DS22230A-page 8
 2010 Microchip Technology Inc.
MCP2003/4
TABLE 1-2:
FAULT/TXE TRUTH TABLE
FAULT/TXE
TXD
In
RXD
Out
LINBUS
I/O
Thermal
Override
L
H
VBB
H
H
L
External
Input
Driven
Output
Definition
OFF
H
L
FAULT, TXD driven low, LINBUS shorted to VBB
(Note 1)
VBB
OFF
H
H
OK
L
GND
OFF
H
H
OK
H
L
GND
OFF
H
H
OK, data is being received from the LINBUS
x
x
VBB
ON
H
L
FAULT, Transceiver in thermal shutdown
x
x
VBB
x
L
x
NO FAULT, the CPU is commanding the
transceiver to turn off the transmitter driver
Legend: x = don’t care
Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault
reporting during bus propagation delays.
1.5.5
TRANSMIT DATA INPUT (TXD)
The Transmit Data Input pin has an internal pull-up.
The LIN pin is low (dominant) when TXD is low, and high
(recessive) when TXD is high.
For extra bus security, TXD is internally forced to ‘1’
whenever the transmitter is disabled regardless of
external TXD voltage.
1.5.5.1
TXD Dominant Timeout
If TXD is driven low longer than approximately 10 ms,
the LBUS pin is switched to Recessive mode and the
part enters TOFF mode. This is to prevent the LIN node
from permanently driving the LIN Bus dominant. The
transmitter is re-enabled on the TXD rising edge.
1.5.6
GROUND (VSS)
1.5.7.1
The Bus Dominant Timer is an internal timer that deactivates the LBUS transmitter after approximately
25 milliseconds of dominant state on the LBUS pin. The
timer is reset on any recessive LBUS state.
The LIN bus transmitter will be re-enabled after a
recessive state on the LBUS pin as long as CS is high.
Disabling can be caused by the LIN bus being externally held dominant, or by TXD being driven low. Additionally, on the MCP2004, the FAULT pin will be driven
low to indicate the Transmitter Off state.
1.5.8
LIN BUS (LBUS)
The bidirectional LIN Bus pin (LBUS) is controlled by the
TXD input. LBUS has a current limited open collector
output. To reduce EMI, the edges during the signal
changes are slope controlled and include corner
rounding control for both falling and rising edges.
BATTERY (VBB)
This is the Battery Positive Supply Voltage pin.
1.5.9
This is the Ground pin.
1.5.7
Bus Dominant Timer
VOLTAGE REGULATOR ENABLE
OUTPUT (VREN)
This is the External Voltage Regulator Enable pin.
Open source output is pulled high to VBB in all modes,
except Power Down.
1.5.10
EXPOSED THERMAL PAD (EP)
Do not electrically connect, or connect to Vss.
The internal LIN receiver observes the activities on the
LIN bus, and matches the output signal RXD to follow
the state of the LBUS pin.
 2010 Microchip Technology Inc.
DS22230A-page 9
MCP2003/4
NOTES:
DS22230A-page 10
 2010 Microchip Technology Inc.
MCP2003/4
2.0
ELECTRICAL CHARACTERISTICS
2.1
Absolute Maximum Ratings†
VIN DC Voltage on RXD, TXD, FAULT/TXE .....................................................................................................-0.3 to +30V
VIN DC Voltage on CS, WAKE and VREN .......................................................................................................-0.3 to +30V
VBB Battery Voltage, continuous ....................................................................................................................-0.3 to +30V
VBB Battery Voltage, non-operating (LIN bus recessive, t < 60s) ..................................................................-0.3 to +43V
VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-200V
VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V
VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-300V
VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V
VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V
VLBUS Bus Voltage, transient (Note 1)............................................................................................................-27 to +43V
ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA
ESD protection on LIN, VBB (IEC 61000-4-2) (Note 2) ........................................................................................... ±8 KV
ESD protection on LIN, VBB (Human Body Model) (Note 3)................................................................................... ±8 KV
ESD protection on all other pins (Human Body Model) (Note 3) ............................................................................ ±4 KV
ESD protection on all pins (Charge Device Model) (Note 4) .................................................................................. ±2 KV
ESD protection on all pins (Machine Model) (Note 5).............................................................................................±200V
Maximum Junction Temperature ............................................................................................................................. 150C
Storage Temperature .................................................................................................................................. -65 to +150C
Note 1: ISO 7637/1 load dump compliant (t < 500 ms).
2: According to IEC 61000-4-2, 330 ohm, 150 pF and Tranceiver EMC Test Specifications [2] to [4].
3: According to AEC-Q100-002/JESD22-A114.
4: According to AEC-Q100-011B.
5: According to AEC-Q100-003/JESD22-A115.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
 2010 Microchip Technology Inc.
DS22230A-page 11
MCP2003/4
2.2
DC Specifications
DC Specifications
Parameter
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 27.0V
TA = -40°C to +125°C
Sym
Min.
Typ.
Max.
Units
Conditions
90
150
µA
Operating Mode,
bus recessive (Note 1)
Power
VBB Quiescent Operating
Current
IBBQ
VBB Transmitter-off Current
IBBTO
—
75
120
µA
Transmitter off,
bus recessive (Note 1)
VBB Power Down Current
IBBPD
—
5
15
µA
Transmitter off,
bus recessive (Note 1)
IBBNOGND
-1
—
1
mA
VBB = 12V, GND to VBB,
VLIN = 0-18V
High Level Input Voltage
(TXD, FAULT/TXE)
VIH
2.0
—
5.3
V
Low Level Input Voltage
(TXD, FAULT/TXE)
VIL
-0.3
—
0.8
V
High Level Input Current
(TXD, FAULT/TXE)
IIH
-2.5
—
—
µA
Input voltage = 4.0V
Low Level Input Current
(TXD, FAULT/TXE)
High Level Voltage (VREN)
IIL
-10
—
—
µA
Input voltage = 0.5V
VHVREN
-0.3
—
VBB+0.3
IHVREN
-20
—
-10
mA
Output voltage = VBB0.5V
High Level Input Voltage
(CS)
VIH
2.0
—
VBB
V
Low Level Input Voltage
(CS)
VIL
-0.3
—
0.8
V
High Level Input Current
(CS)
IIH
-10.0
—
10.0
µA
Input voltage = 4.0V
Low Level Input Current
(CS)
IIL
-5.0
—
5.0
µA
Input voltage = 0.5V
Low Level Input Voltage
(WAKE)
VIL
VBB – 4.0V
—
—
V
Low Level Output Voltage
(RXD)
VOL
—
—
0.4
V
IIN = 2 mA
High Level Output Current
(RXD)
IOH
-1
—
-1
µA
VLIN - VBB, VRXD = 5.5V
VBB Current
with VSS Floating
Microcontroller Interface
High Level Output Current
(VREN)
Note 1:
2:
Through a current limiting
resistor
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB).
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
DS22230A-page 12
 2010 Microchip Technology Inc.
MCP2003/4
2.2
DC Specifications (Continued)
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 27.0V
TA = -40°C to +125°C
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
High Level Input Voltage
VIH(LBUS)
0.6 VBB
—
18
V
Recessive state
Low Level Input Voltage
VIL(LBUS)
-8
—
0.4 VBB
V
Dominant state
VHYS
—
—
0.175 VBB
V
Low Level Output Current
IOL(LBUS)
40
—
200
mA
Output voltage = 0.1 VBB,
VBB = 12V
Pull-up Current on Input
IPU(LBUS)
5
—
180
µA
~30 k internal pull-up
@ VIH (LBUS) = 0.7 VBB
Short Circuit Current Limit
ISC
50
—
200
mA
(Note 1)
High Level Output Voltage
VOH(LBUS)
0.9 VBB
—
VBB
V
V_LOSUP
—
—
1.2
V
VBB = 7V, RLOAD = 500
Bus Interface
Input Hysteresis
Driver Dominant Voltage
VIH(LBUS) – VIL(LBUS)
Driver Dominant Voltage
V_HISUP
—
—
2.0
V
VBB = 18V, RLOAD = 500
Driver Dominant Voltage
V_LOSUP-1K
0.6
—
—
V
VBB = 7V, RLOAD = 1 k
Driver Dominant Voltage
V_HISUP-1K
0.8
—
—
V
VBB = 18V, RLOAD = 1 k
Input Leakage Current
(at the receiver during
dominant bus level)
IBUS_PAS_DOM
-1
-0.4
—
mA
Driver off,
VBUS = 0V,
VBB = 12V
Input Leakage Current
(at the receiver during
recessive bus level)
IBUS_PAS_REC
—
12
20
µA
Driver off,
8V < VBB < 18V
8V < VBUs < 18V
VBUS  VBB
Leakage Current
(disconnected from ground)
IBUS_NO_GND
-10
1.0
+10
µA
GNDDEVICE = VBB,
0V < VBUS < 18V,
VBB = 12V
Leakage Current
(disconnected from VBB)
IBUS
—
—
10
µA
VBB = GND,
0 < VBUS < 18V,
TA = -40°C to +85°C
(Note 2)
Receiver Center Voltage
VBUS_CNT
0.475 VBB
0.5
VBB
0.525 VBB
V
VBUS_CNT = (VIL (LBUS) +
VIH (LBUS))/2
RSLAVE
20
30
47
k
Slave Termination
Note 1:
2:
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB).
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
 2010 Microchip Technology Inc.
DS22230A-page 13
MCP2003/4
2.3
AC Specifications
AC CHARACTERISTICS
Parameter
VBB = 6.0V to 27.0V; TA = -40°C to +125°C
Sym
Min.
Typ.
Max.
Units
Test Conditions
Bus Interface – Constant Slope Time Parameters
tslope
3.5
—
22.5
µs
7.3V <= VBB <= 18V
Propagation Delay of
Transmitter
ttranspd
—
—
4.0
µs
ttranspd = max (ttranspdr or ttranspdf)
Propagation Delay of
Receiver
trecpd
—
—
6.0
µs
trecpd = max (trecpdr or trecpdf)
Symmetry of Propagation
Delay of Receiver rising
edge w.r.t. falling edge
trecsym
-2.0
—
2.0
µs
trecsym = max (trecpdf – trecpdr)
Symmetry of Propagation
Delay of Transmitter rising
edge w.r.t. falling edge
ttranssym
-2.0
—
2.0
µs
ttranssym = max (ttranspdf - ttranspdr)
tfault
—
—
32.5
µs
tfault = max (ttranspd + tslope + trecpd)
Duty Cycle 1 @20.0 kbit/sec
39.6
—
—
%tbit Cbus;Rbus conditions:
1 nF; 1 kW | 6.8 nF; 660W | 10 nF; 500W
THrec(max) = 0.744 x VBB,
THdom(max) = 0.581 x VBB,
VBB =7.0V-18V; tbit = 50 µs
D1 = tbus_rec(min) / 2 x tbit)
Duty Cycle 2 @20.0 kbit/sec
—
—
58.1
%tbit Cbus;Rbus conditions:
1 nF; 1 kW | 6.8 nF; 660W | 10 nF; 500W
THrec(max) = 0.284 x VBB,
THdom(max) = 0.422 x VBB,
VBB =7.6V-18V; tbit = 50 µs
D2 = tbus_rec(max) / 2 x tbit)
Duty Cycle 3 @10.4 kbit/sec
41.7
—
—
%tbit Cbus;Rbus conditions:
1 nF; 1 kW | 6.8 nF; 660W | 10 nF; 500W
THrec(max) = 0.778 x VBB,
THdom(max) = 0.616 x VBB,
VBB =7.0V-18V; tbit = 96 µs
D3 = tbus_rec(min) / 2 x tbit)
Duty Cycle 4 @10.4 kbit/sec
—
—
59.0
%tbit Cbus;Rbus conditions:
1 nF; 1 kW | 6.8 nF; 660W | 10 nF; 500W
THrec(max) = 0.251 x VBB,
THdom(max) = 0.389 x VBB,
VBB =7.6V-18V; tbit = 96 µs
D4 = tbus_rec(max) / 2 x tbit)
Slope rising and falling
edges
Time to sample of FAULT/
TXE for bus conflict reporting
Wake-up Timing
Bus Activity Debounce time
Bus Activity to Vren on
tBDB
5
tBACTVE
35
WAKE to Vren on
tWAKE
Chip Select to Vren on
tCSOR
Chip Select to Vren off
tCSPD
DS22230A-page 14
20
µs
Bus debounce time, 10 µs typical
After Bus debounce time, 52 µs typical
150
µs
150
µs
—
150
µs
Vren floating
—
80
µs
Vren floating
 2010 Microchip Technology Inc.
MCP2003/4
2.4
Thermal Specifications
THERMAL CHARACTERISTICS
Parameter
Symbol
Typ
Max
Units
Recovery Temperature
RECOVERY
+140
—
C
Shutdown Temperature
SHUTDOWN
+150
—
C
tTHERM
1.5
5.0
ms
Short Circuit Recovery Time
Test Conditions
Thermal Package Resistances
Thermal Resistance, 8L-DFN
JA
35.7
—
C/W
Thermal Resistance, 8L-PDIP
JA
89.3
—
C/W
Thermal Resistance, 8L-SOIC
JA
149.5
—
C/W
Note 1:
The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum
allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)JA. If this dissipation is
exceeded, the die temperature will rise above 150C and the MCP2003/4 will go into thermal shutdown.
 2010 Microchip Technology Inc.
DS22230A-page 15
MCP2003/4
2.5
Typical Performance Curves
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VBB = 6.0V to 18.0V, TA = -40°C to +125°C.
TYPICAL IBBQ
FIGURE 2-3:
0.14
0.12
0.12
0.1
0.1
-40C
25C
85C
125C
0.08
0.06
0.04
Current (mA)
Current (mA)
FIGURE 2-1:
TYPICAL IBBTO
0.08
-40C
25C
85C
125C
0.06
0.04
0.02
0.02
0
0
6
7.3
12
14.4
18
6V
VBB (V)
FIGURE 2-2:
7.3V
12V
14.4V
18V
VBB (V)
TYPICAL IBBPD
0.008
0.007
Current (mA)
0.006
0.005
-40C
25C
85C
125C
0.004
0.003
0.002
0.001
0
6
7.3
12
14.4
18
VBB (V)
DS22230A-page 16
 2010 Microchip Technology Inc.
MCP2003/4
2.6
Timing Diagrams and Specifications
FIGURE 2-4:
BUS TIMING DIAGRAM
TXD
50%
50%
LBUS
.95VLBUS
.50VBB
0.5VLBUS
TTRANSPDR
TTRANSPDF
TRECPDF
0.0V
TRECPDR
RXD
50%
Internal TXD/RXD
Compare
Match
50%
Match
Match
Match
Match
FAULT Sampling
TFAULT
TFAULT
FAULT/TXE Output Stable
FIGURE 2-5:
Hold
Value
Stable
Hold
Value
Stable
CS TO VREN TIMING DIAGRAM
CS
TCSOR
VBB
VREN
OFF
TCSPD
FIGURE 2-6:
BUS TO VREN WAKE TIMING DIAGRAM
LBUS
.4VBB
TBDB + TBACTVE
VBB
VREN
 2010 Microchip Technology Inc.
DS22230A-page 17
MCP2003/4
NOTES:
DS22230A-page 18
 2010 Microchip Technology Inc.
MCP2003/4
3.0
PACKAGING INFORMATION
3.1
Package Marking Information
8-Lead DFN (4x4)
XXXXXX
XXXXXX
YYWW
NNN
2004
e3
E/MD^^
0948
256
8-Lead PDIP (300 mil)
8-Lead SOIC (150 mil)
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
MCP2003
e3
E/P^^256
0948
XXXXXXXX
XXXXXNNN
YYWW
XXXXXXXX
XXXXYYWW
NNN
Example:
Example:
MCP2003E
e3
SN^^0948
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2010 Microchip Technology Inc.
DS22230A-page 19
MCP2003/4
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
DS22230A-page 20
 2010 Microchip Technology Inc.
MCP2003/4
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
 2010 Microchip Technology Inc.
DS22230A-page 21
MCP2003/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22230A-page 22
 2010 Microchip Technology Inc.
MCP2003/4
3 & ' !&" & 4# *!( !!& 4 %& &#&
&& 255***' '5 4
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
6&!
'! 9'&!
7"') %!
7,8.
7
7
&
;
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& &
7:
1,
=
=
-
1!& &
=
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.
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=
& &
9#
6
4!!
9#>#&
9 * 9#>#&
: * +
-
!"#$%&" ' ()"&'"!&) &#*& & & # +%&, & !&
- '! !#.# &"#' #%! & "! ! #%! & "! !! &$#/ !#
'! #& .0
1,21!'! &$& "! **& "&& !
 2010 Microchip Technology Inc.
* ,<1
DS22230A-page 23
MCP2003/4
! ""#$%& !'
3 & ' !&" & 4# *!( !!& 4 %& &#&
&& 255***' '5 4
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
A2
A
c
φ
L
A1
β
L1
6&!
'! 9'&!
7"') %!
99. .
7
7
7:
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: 8 &
=
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=
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=
##4
4!!
&# %%+
1,
: >#&
.
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.
-1,
: 9&
1,
, '% @
3
& A
&9&
9
3
& &
9
3
&
?1,
=
=
.3
I
B
=
<B
=
9#>#&
)
-
=
# %&
D
B
=
B
# %&1 && '
E
B
=
9#
4!!
B
!"#$%&" ' ()"&'"!&) &#*& & & # +%&, & !&
- '! !#.# &"#' #%! & "! ! #%! & "! !! &$#'' !#
'! #& .0
1,2 1!'! &$& "! **& "&& !
.32 % '! ("!"*& "&& (% % '& " !! DS22230A-page 24
* ,1
 2010 Microchip Technology Inc.
MCP2003/4
! ""#$%& !'
3 & ' !&" & 4# *!( !!& 4 %& &#&
&& 255***' '5 4
 2010 Microchip Technology Inc.
DS22230A-page 25
MCP2003/4
NOTES:
DS22230A-page 26
 2010 Microchip Technology Inc.
MCP2003/4
APPENDIX A:
REVISION HISTORY
Revision A (March 2010)
• Original Release of this Document.
 2010 Microchip Technology Inc.
DS22230A-page 27
MCP2003/4
NOTES:
DS22230A-page 28
 2010 Microchip Technology Inc.
MCP2003/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Device:
MCP2003: LIN Transceiver with Voltage Regulator
MCP2003T: LIN Transceiver with Voltage Regulator
(Tape and Reel) (DFN and SOIC)
MCP2004: LIN Transceiver with Voltage Regulator
MCP2004T: LIN Transceiver with Voltage Regulator
(Tape and Reel) (DFN and SOIC)
Temperature Range: E
Package:
Examples:
a)
b)
c)
d)
e)
= -40°C to +125°C
MD = Plastic Micro Small Outline (4x4), 8-lead
P
= Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
a)
b)
c)
d)
e)
 2010 Microchip Technology Inc.
MCP2003-E/MD:
Extended Temperature,
8L-DFN pkg.
MCP2003-E/P:
Extended Temperature,
8L-PDIP pkg.
MCP2003-E/SN:
Extended Temperature,
8L-SOIC pkg.
MCP2003T-E/MD: Tape and Reel,
Extended Temperature,
8L-DFN pkg.
MCP2003T-E/SN: Tape and Reel,
Extended Temperature,
8L-SOIC pkg.
MCP2004-E/MD:
Extended Temperature,
8L-DFN pkg.
MCP2004-E/P:
Extended Temperature,
8L-PDIP pkg.
MCP2004-E/SN:
Extended Temperature,
8L-SOIC pkg.
MCP2004T-E/MD: Tape and Reel,
Extended Temperature,
8L-DFN pkg.
MCP2004T-E/SN: Tape and Reel,
Extended Temperature,
8L-SOIC pkg.
DS22230A-page 29
MCP2003/4
NOTES:
DS22230A-page 30
 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-080-5
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2010 Microchip Technology Inc.
DS22230A-page 31
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Technical Support:
http://support.microchip.com
Web Address:
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01/05/10
DS22230A-page 32
 2010 Microchip Technology Inc.