NTB6412AN, NTP6412AN N-Channel Power MOSFET 100 V, 58 A, 18.2 mW Features • • • • Low RDS(on) High Current Capability 100% Avalanche Tested These are Pb−Free Devices http://onsemi.com V(BR)DSS MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 100 V Gate−to−Source Voltage − Continuous VGS $20 V ID 58 A Continuous Drain Current RqJC Steady State Power Dissipation RqJC Steady State TC = 25°C TC = 100°C 167 IDM 240 A TJ, Tstg −55 to +175 °C IS 58 A Single Pulse Drain−to−Source Avalanche Energy (VDD = 50 Vdc, VGS = 10 Vdc, IL(pk) = 44.7 A, L = 0.3 mH, RG = 25 W) EAS 300 mJ Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds TL tp = 10 ms Operating Junction and Storage Temperature Range Source Current (Body Diode) 58 A 18.2 mW @ 10 V N−Channel D W G S 4 4 1 260 1 Symbol Max Unit Junction−to−Case (Drain) Steady State RqJC 0.9 °C/W Junction−to−Ambient (Note 1) RqJA 33 2 3 °C THERMAL RESISTANCE RATINGS Parameter 100 V 41 PD Pulsed Drain Current TC = 25°C ID MAX (Note 1) RDS(ON) MAX 2 3 4 Drain Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface mounted on FR4 board using 1 sq in pad size, (Cu Area 1.127 sq in [2 oz] including traces). D2PAK CASE 418B STYLE 2 TO−220AB CASE 221A STYLE 5 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain NTB 6412ANG AYWW NTP 6412ANG AYWW 1 Gate 3 Source 2 Drain 1 Gate 2 Drain 3 Source 6412AN = Specific Device Code G = Pb−Free Device A = Assembly Location Y = Year WW = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 0 1 Publication Order Number: NTB6412AN/D NTB6412AN, NTP6412AN ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified) Characteristics Symbol Test Condition Min V(BR)DSS VGS = 0 V, ID = 250 mA 100 Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 103 VGS = 0 V, VDS = 100 V mV/°C TJ = 25°C 1.0 TJ = 125°C 100 IGSS VDS = 0 V, VGS = $20 V VGS(th) VGS = VDS, ID = 250 mA $100 mA nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On−Resistance VGS(th)/TJ 4.0 9.2 RDS(on) Forward Transconductance 2.0 gFS V mV/°C VGS = 10 V, ID = 58 A 16.8 18.2 VGS = 10 V, ID = 20 A 15.6 18.2 VDS = 5 V, ID = 20 A 31 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 150 Total Gate Charge QG(TOT) 73 Threshold Gate Charge QG(TH) VDS = 25 V, VGS = 0 V, f = 1 MHz 2700 3500 400 500 100 pF nC 2.5 VGS = 10 V, VDS = 80 V, ID = 58 A Gate−to−Source Charge QGS 13.5 Gate−to−Drain Charge QGD Plateau Voltage VGP 5.6 V Gate Resistance RG 2.2 W 16 ns 35 SWITCHING CHARACTERISTICS, VGS = 10 V (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 10 V, VDD = 80 V, ID = 58 A, RG = 6.2 W tf 140 70 126 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time trr Charge Time ta Discharge Time Reverse Recovery Charge IS = 58 A TJ = 25°C 0.96 TJ = 125°C 0.89 85 VGS = 0 V, IS = 58 A, dISD/dt = 100 A/ms tb QRR http://onsemi.com 2 V ns 60 25 270 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperatures. 1.3 nC NTB6412AN, NTP6412AN 120 120 7.5 V 100 6.5 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) TJ = 25°C 10 V 80 6.0 V 60 5.4 V 40 5.0 V 20 VDS w 10 V 100 80 60 40 20 VGS = 4.4 V 1 2 3 TJ = −55°C 4 0 5 2 6 7 Figure 2. Transfer Characteristics 0.03 0.02 0.01 5 6 7 8 9 10 VGS, GATE−TO−SOURCE VOLTAGE (V) VGS = 10 V 0.05 TJ = 175°C 0.04 TJ = 125°C 0.03 0.02 TJ = 25°C TJ = −55°C 0.01 0 10 100000 IDSS, LEAKAGE (nA) 1 −25 0 25 50 75 100 125 150 30 40 50 60 ID, DRAIN CURRENT (A) VGS = 0 V ID = 58 A VGS = 10 V 1.5 20 Figure 4. On−Resistance versus Drain Current and Gate Voltage 3 2 8 0.06 Figure 3. On−Region versus Gate Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) ID = 58 A TJ = 25°C 0.5 −50 4 Figure 1. On−Region Characteristics 0.04 2.5 3 VGS, GATE−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 0 TJ = 25°C TJ = 125°C 175 10000 TJ = 150°C TJ = 125°C 1000 100 10 TJ, JUNCTION TEMPERATURE (°C) 20 30 40 50 60 70 80 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature 90 100 Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 10 VGS, GATE−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 5000 TJ = 25°C VGS = 0 V 4000 3000 Ciss 2000 1000 0 Coss Crss 0 10 20 30 40 50 60 70 80 90 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 100 4 tf td(on) 1 40 2 0 VDS = 80 V ID = 58 A TJ = 25°C 0 10 60 td(off) 1 60 20 30 40 50 60 Qg, TOTAL GATE CHARGE (nC) 70 20 0 Figure 8. Gate−to−Source Voltage and Drain−to−Source Voltage versus Total Charge tr 10 80 Qgd Qgs 6 IS, SOURCE CURRENT (A) t, TIME (ns) VDS = 80 V ID = 58 A VGS = 10 V VGS VDS Figure 7. Capacitance Variation 1000 100 QT 8 VDS, DRAIN−TO−SOURCE VOLTAGE (V) NTB6412AN, NTP6412AN 10 RG, GATE RESISTANCE (W) 100 TJ = 25°C VGS = 0 V 50 40 30 20 10 0 0.5 Figure 9. Resistive Switching Time Variation versus Gate Resistance 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 1.0 Figure 10. Diode Forward Voltage versus Current 1000 300 100 10 ms 100 ms 10 1 ms 10 ms dc 1 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 VGS = 10 V SINGLE PULSE TC = 25°C 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (A) ID = 44.7 A 1000 200 100 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE 175 Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 4 NTB6412AN, NTP6412AN 1 D = 0.5 0.2 R(t) (°C/W) 0.1 0.1 0.05 0.02 0.01 0.01 0.001 0.000001 SINGLE PULSE 0.00001 0.0001 0.001 0.01 0.1 t, PULSE TIME (s) 1 10 100 1000 Figure 13. Thermal Response ORDERING INFORMATION Package Shipping† NTB6412ANG D2PAK (Pb−Free) 50 Units / Rail NTB6412ANT4G D2PAK (Pb−Free) 800 / Tape & Reel NTP6412ANG TO−220 (Pb−Free) 50 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTB6412AN, NTP6412AN PACKAGE DIMENSIONS D2PAK 3 CASE 418B−04 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. C E V W −B− 4 1 2 A S 3 −T− SEATING PLANE K W J G D 3 PL 0.13 (0.005) VARIABLE CONFIGURATION ZONE H M T B M N R L L M M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 SOLDERING FOOTPRINT* 10.49 8.38 16.155 2X 3.504 2X 1.016 5.080 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN P U L M DIM A B C D E F G H J K L M N P R S V MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 NTB6412AN, NTP6412AN PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AF −T− B F T SEATING PLANE C S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q U 1 2 3 H K Z L R V J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.161 0.095 0.105 0.110 0.155 0.014 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 STYLE 5: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 4.09 2.42 2.66 2.80 3.93 0.36 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04 GATE DRAIN SOURCE DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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