MC10H123 Triple 4‐3‐3‐Input Bus Driver Description The MC10H123 is a triple 4-3-3-Input Bus Driver. The MC10H123 consists of three NOR gates designed for bus driving applications on card or between cards. Output low logic levels are specified with VOL = −2.1 Vdc so that the bus may be terminated to −2.0 Vdc. The gate output, when low, appears as a high impedance to the bus, because the output emitter-followers of the MC10H123 are “turned-off.” This eliminates discontinuities in the characteristic impedance of the bus. The VOH level is specified when driving a 25 W load terminated to −2.0 Vdc, the equivalent of a 50 W bus terminated at both ends. Although 25 W is the lowest characteristic impedance that can be driven by the MC10H123, higher impedance values may be used with this part. A typical 50 W bus is shown in Figure 3. www.onsemi.com 16 PDIP−16 P SUFFIX CASE 648−08 Features PLLC−20 FN SUFFIX CASE 775−02 MARKING DIAGRAMS* • Propagation Delay, 1.5 ns Typical • Improved Noise Margin 150 mV • • • 20 1 1 1 20 (Over Operating Voltage and Temperature Range) Voltage Compensated MECL 10K™ Compatible These Devices are Pb-Free, Halogen Free and are RoHS Compliant 16 MC10H123P AWLYYWWG 10H123G AWLYYWW 1 PDIP−16 A WL, L YY, Y WW, W G PLLC−20 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping† MC10H123FNG PLLC−20 (Pb-Free) 46 Units / Tube MC10H123FNR2G PLLC−20 (Pb-Free) 500 Tape & Reel MC10H123PG PDIP−16 (Pb-Free) 25 Units / Tube †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 August, 2016 − Rev. 8 1 Publication Order Number: MC10H123/D MC10H123 4 5 3 6 7 VCC1 1 16 VCC2 BOUT 2 15 COUT AOUT 3 14 CIN AIN 4 13 CIN AIN 5 12 CIN AIN 6 11 BIN AIN 7 10 BIN VEE 8 9 BIN 9 10 2 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 11 12 13 15 14 Pin assignment is for Dual-in-Line Package. Figure 1. LOGIC DIAGRAM Figure 2. Dip Pin Assignment Table 1. MAXIMUM RATINGS Symbol Characteristic Rating Unit VEE Power Supply (VCC = 0) −8.0 to 0 Vdc VI Input Voltage (VCC = 0) 0 to VEE Vdc Iout Output Current Continuous Surge TA Operating Temperature Range Tstg Storage Temperature Range Plastic Ceramic mA 50 100 0 to +75 °C °C °C −55 to +150 −55 to +165 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 2. ELECTRICAL CHARACTERISTICS (VEE = −5.2 V ±5%) (Note 1) 0° Symbol IE Characteristic Min 25° Max Min 75° Max Min Max Unit Power Supply Current 60 56 60 mA IinH Input Current High 495 310 310 mA IinL Input Current Low VOH High Output Voltage VOL VIH VIL 0.5 0.5 −1.02 −0.84 Low Output Voltage −2.1 High Input Voltage −1.17 Low Input Voltage −1.95 0.3 −0.98 −0.81 −0.92 −2.03 −2.1 −2.03 −0.84 −1.13 −0.81 −1.48 −1.95 −1.48 −1.95 mA −0.735 Vdc −2.1 −2.03 Vdc −1.07 −0.735 Vdc −1.45 Vdc 1. Each MECL 10H™ series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Outputs are terminated through a 50 W resistor to −2.1 V. www.onsemi.com 2 MC10H123 Table 3. AC CHARACTERISTICS 0° Symbol 25° 75° Min Max Min Max Min Max Unit Propagation Delay 0.7 1.5 0.7 1.6 0.7 1.7 ns tr Rise Time 0.7 1.6 0.7 1.7 0.7 1.8 ns tf Fall Time 0.7 1.6 0.7 1.7 0.7 1.8 ns tpd Characteristic NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1/3 MC10H123 1/3 MC10H123 1/3 MC10H123 ZO = 50 W 50 W −2.0 VDC 50 W RECEIVERS (MECL GATES) Figure 3. 50 W Bus Driver (25 W Load) www.onsemi.com 3 −2.0 VDC MC10H123 PACKAGE DIMENSIONS 20 LEAD PLLC FN SUFFIX CASE 775−02 ISSUE F B 0.007 (0.180) Y BRK −N− M T L-M 0.007 (0.180) U M N S T L-M S G1 0.010 (0.250) S N S D −L− −M− Z W 20 D 1 X V S T L-M S N S VIEW D−D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S Z C H −T− VIEW S G1 0.010 (0.250) S T L-M SEATING PLANE F 0.007 (0.180) VIEW S S N T L-M S N S K 0.004 (0.100) J M K1 E G 0.007 (0.180) S NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSIONS IN INCHES. 3. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 4. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 5. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 6. DIMENSIONS IN THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). www.onsemi.com 4 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.021 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10 _ 0.310 0.330 0.040 −−− MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.53 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10 _ 7.88 8.38 1.02 −−− M T L-M S N S MC10H123 PACKAGE DIMENSIONS PDIP−16 P SUFFIX CASE 648−08 ISSUE V D A 16 9 E H E1 1 NOTE 8 b2 8 c B TOP VIEW END VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L A1 C D1 e SEATING PLANE M eB END VIEW 16X b SIDE VIEW 0.010 M C A M B M NOTE 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.735 0.775 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° STYLE 1: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. CATHODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE 15. ANODE 16. ANODE MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 18.67 19.69 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° STYLE 2: PIN 1. COMMON DRAIN 2. COMMON DRAIN 3. COMMON DRAIN 4. COMMON DRAIN 5. COMMON DRAIN 6. COMMON DRAIN 7. COMMON DRAIN 8. COMMON DRAIN 9. GATE 10. SOURCE 11. GATE 12. SOURCE 13. GATE 14. SOURCE 15. GATE 16. SOURCE MECL is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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